; --------------------------------------------------------------------------------
; @Title: M46x On-Chip Peripherals
; @Props: Released
; @Author: KRZ, NEJ
; @Changelog: 2023-07-20 KRZ
;             2023-11-08 NEJ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: Generated (TRACE32, build: 164352.), based on:
;       M460.svd (Ver. 1.0)
; @Core: Cortex-M4F
; @Chip: M463KGCAE, M463LGCAE, M463SGCAE, M463YGCAE,
;        M467HJHAN, M467JJHAN, M467KJHAN, M467SJHAN
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perm46x.per 16971 2023-11-09 16:09:22Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACMP (Analog Comparator Controller)"
base ad:0x0
tree "ACMP01"
base ad:0x40045000
group.long 0x0++0x13
line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
bitfld.long 0x0 28.--29. "MODESEL,Comparator Power Mode Selection\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Low power mode comparator AVDD current 1uA,1: Low power mode comparator AVDD current 2uA,?,?"
bitfld.long 0x0 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?,?,?,?,?"
newline
bitfld.long 0x0 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,?,?"
bitfld.long 0x0 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
newline
bitfld.long 0x0 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
newline
bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
bitfld.long 0x0 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is unfiltered..,1: Comparator 0 output to ACMP0_O pin is from.."
newline
bitfld.long 0x0 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
bitfld.long 0x0 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,?,?"
newline
bitfld.long 0x0 4.--5. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV0),?,?"
bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
newline
bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled. If WKEN.."
bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
bitfld.long 0x4 28.--29. "MODESEL,Comparator Power Mode Selection\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Low power mode comparator AVDD current 1uA,1: Low power mode comparator AVDD current 2uA,?,?"
bitfld.long 0x4 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?,?,?,?,?"
newline
bitfld.long 0x4 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,?,?"
bitfld.long 0x4 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
newline
bitfld.long 0x4 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
bitfld.long 0x4 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
newline
bitfld.long 0x4 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
bitfld.long 0x4 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is unfiltered..,1: Comparator 1 output to ACMP1_O pin is from.."
newline
bitfld.long 0x4 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
bitfld.long 0x4 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,?,?"
newline
bitfld.long 0x4 4.--5. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV1),?,?"
bitfld.long 0x4 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
newline
bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled. If WKEN.."
bitfld.long 0x4 0. "ACMPEN,Comparator Enable Bit\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
line.long 0x8 "ACMP_STATUS,Analog Comparator Status Register"
bitfld.long 0x8 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the window,1: The positive input voltage is in the window"
bitfld.long 0x8 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled  i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
newline
bitfld.long 0x8 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled  i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
bitfld.long 0x8 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
newline
bitfld.long 0x8 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
bitfld.long 0x8 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled  i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
newline
bitfld.long 0x8 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled  i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
bitfld.long 0x8 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear.." "0,1"
newline
bitfld.long 0x8 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to clear.." "0,1"
line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
bitfld.long 0xC 31. "CLAMPEN,Current Level Control Selection under Speed Up Function" "0: ACMP run on high SPEED mode with high quiescent..,1: ACMP run on low SPEED mode with high quiescent.."
bitfld.long 0xC 24. "CRV1EN,CRV1 Enable Bit" "0: CRV1 Disabled,1: CRV1 Enabled"
newline
bitfld.long 0xC 22. "CRV1SSEL,CRV1 Source Voltage Selection" "0: AVDD is selected as CRV1 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
hexmask.long.byte 0xC 16.--21. 1. "CRV1SEL,Comparator1 Reference Voltage Setting"
newline
bitfld.long 0xC 8. "CRV0EN,CRV0 Enable Bit" "0: CRV0 Disabled,1: CRV0 Enabled"
bitfld.long 0xC 6. "CRV0SSEL,CRV0 Source Voltage Selection" "0: AVDD is selected as CRV0 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
newline
hexmask.long.byte 0xC 0.--5. 1. "CRV0SEL,Comparator0 Reference Voltage Setting"
line.long 0x10 "ACMP_CALCTL,Analog Comparator Calibration Control Register"
bitfld.long 0x10 1. "CALTRG1,Comparator1 Calibration Trigger Bit\nNote 1: Before this bit is enabled  ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will automatically clear this bit when.." "0: Calibration is stopped,1: Before this bit is enabled"
bitfld.long 0x10 0. "CALTRG0,Comparator0 Calibration Trigger Bit\nNote 1: Before this bit is enabled  ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will automatically clear this bit when.." "0: Calibration is stopped,1: Before this bit is enabled"
rgroup.long 0x14++0x3
line.long 0x0 "ACMP_CALSR,Analog Comparator Calibration Status Register"
bitfld.long 0x0 4. "DONE1,Comparator1 Calibration Done Status\nNote: Write 1 to clear this bit to 0." "0: Calibrating,1: Calibration done"
bitfld.long 0x0 0. "DONE0,Comparator0 Calibration Done Status\nNote: Write 1 to clear this bit to 0." "0: Calibrating,1: Calibration done"
tree.end
tree "ACMP23"
base ad:0x400C9000
group.long 0x0++0x13
line.long 0x0 "ACMP_CTL2,Analog Comparator 2 Control Register"
bitfld.long 0x0 28.--29. "MODESEL,Comparator Power Mode Selection\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Low power mode comparator AVDD current 1uA,1: Low power mode comparator AVDD current 2uA,?,?"
bitfld.long 0x0 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,?,?,?,?,?,?"
newline
bitfld.long 0x0 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,?,?"
bitfld.long 0x0 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
newline
bitfld.long 0x0 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
newline
bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP2 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
bitfld.long 0x0 12. "OUTSEL,Comparator Output Select" "0: Comparator 2 output to ACMP2_O pin is unfiltered..,1: Comparator 2 output to ACMP2_O pin is from.."
newline
bitfld.long 0x0 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF2 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
bitfld.long 0x0 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP2_P0,1: Input from ACMP2_P1,?,?"
newline
bitfld.long 0x0 4.--5. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP2_N pin,1: Internal comparator reference voltage (CRV2),?,?"
bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 2 output inverse Disabled,1: Comparator 2 output inverse Enabled"
newline
bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 2 interrupt Disabled,1: Comparator 2 interrupt Enabled. If WKEN.."
bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Comparator 2 Disabled,1: Comparator 2 Enabled"
line.long 0x4 "ACMP_CTL3,Analog Comparator 3 Control Register"
bitfld.long 0x4 28.--29. "MODESEL,Comparator Power Mode Selection\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Low power mode comparator AVDD current 1uA,1: Low power mode comparator AVDD current 2uA,?,?"
bitfld.long 0x4 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,?,?,?,?,?,?"
newline
bitfld.long 0x4 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,?,?"
bitfld.long 0x4 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
newline
bitfld.long 0x4 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
bitfld.long 0x4 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
newline
bitfld.long 0x4 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP3 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
bitfld.long 0x4 12. "OUTSEL,Comparator Output Select" "0: Comparator 3 output to ACMP3_O pin is unfiltered..,1: Comparator 3 output to ACMP3_O pin is from.."
newline
bitfld.long 0x4 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF3 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
bitfld.long 0x4 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP3_P0,1: Input from ACMP3_P1,?,?"
newline
bitfld.long 0x4 4.--5. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP3_N pin,1: Internal comparator reference voltage (CRV3),?,?"
bitfld.long 0x4 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 3 output inverse Disabled,1: Comparator 3 output inverse Enabled"
newline
bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 3 interrupt Disabled,1: Comparator 3 interrupt Enabled. If WKEN.."
bitfld.long 0x4 0. "ACMPEN,Comparator Enable Bit\nNote: There is a setup time TSetup after comparator is enabled or MODESEL is changed. User should wait this TSetup to make comparator working normally  or user may get unstable comparator output value." "0: Comparator 3 Disabled,1: Comparator 3 Enabled"
line.long 0x8 "ACMP_STATUS2,Analog Comparator Status Register 2"
bitfld.long 0x8 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the window,1: The positive input voltage is in the window"
bitfld.long 0x8 13. "ACMPS3,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 3 is disabled  i.e. ACMPEN (ACMP_CTL3[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 12. "ACMPS2,Comparator 2 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 2 is disabled  i.e. ACMPEN (ACMP_CTL2[0]) is cleared to 0." "0,1"
bitfld.long 0x8 9. "WKIF3,Comparator 3 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP3 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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bitfld.long 0x8 8. "WKIF2,Comparator 2 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP2 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
bitfld.long 0x8 5. "ACMPO3,Comparator 3 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 3 is disabled  i.e. ACMPEN (ACMP_CTL3[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 4. "ACMPO2,Comparator 2 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 2 is disabled  i.e. ACMPEN (ACMP_CTL2[0]) is cleared to 0." "0,1"
bitfld.long 0x8 1. "ACMPIF3,Comparator 3 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL3[9:8]) is detected on comparator 3 output. This will cause an interrupt if ACMPIE (ACMP_CTL3[1]) is set to 1.\nNote: Write 1 to clear.." "0,1"
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bitfld.long 0x8 0. "ACMPIF2,Comparator 2 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL2[9:8]) is detected on comparator 2 output. This will generate an interrupt if ACMPIE (ACMP_CTL2[1]) is set to 1.\nNote: Write 1 to clear.." "0,1"
line.long 0xC "ACMP_VREF2,Analog Comparator Reference Voltage Control Register 2"
bitfld.long 0xC 31. "CLAMPEN,Current Level Control Selection under Speed Up Function" "0: ACMP run on high SPEED mode with high quiescent..,1: ACMP run on low SPEED mode with high quiescent.."
bitfld.long 0xC 24. "CRV3EN,CRV3 Enable Bit" "0: CRV3 Disabled,1: CRV3 Enabled"
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bitfld.long 0xC 22. "CRV3SSEL,CRV3 Source Voltage Selection" "0: AVDD is selected as CRV3 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
hexmask.long.byte 0xC 16.--21. 1. "CRV3SEL,Comparator3 Reference Voltage Setting"
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bitfld.long 0xC 8. "CRV2EN,CRV2 Enable Bit" "0: CRV2 Disabled,1: CRV2 Enabled"
bitfld.long 0xC 6. "CRV2SSEL,CRV2 Source Voltage Selection" "0: AVDD is selected as CRV2 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
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hexmask.long.byte 0xC 0.--5. 1. "CRV2SEL,Comparator2 Reference Voltage Setting"
line.long 0x10 "ACMP_CALCTL2,Analog Comparator Calibration Control Register 2"
bitfld.long 0x10 1. "CALTRG3,Comparator3 Calibration Trigger Bit\nNote 1: Before this bit is enabled  ACMPEN(ACMP_CTL3[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will automatically clear this bit when.." "0: Calibration is stopped,1: Before this bit is enabled"
bitfld.long 0x10 0. "CALTRG2,Comparator2 Calibration Trigger Bit\nNote 1: Before this bit is enabled  ACMPEN(ACMP_CTL2[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will automatically clear this bit when.." "0: Calibration is stopped,1: Before this bit is enabled"
rgroup.long 0x14++0x3
line.long 0x0 "ACMP_CALSR2,Analog Comparator Calibration Status Register 2"
bitfld.long 0x0 4. "DONE3,Comparator3 Calibration Done Status\nNote: Write 1 to clear this bit to 0." "0: Calibrating,1: Calibration done"
bitfld.long 0x0 0. "DONE2,Comparator2 Calibration Done Status\nNote: Write 1 to clear this bit to 0." "0: Calibrating,1: Calibration done"
tree.end
tree.end
tree "BPWM (Basic PWM Generator and Capture Timer)"
base ad:0x0
tree "BPWM0"
base ad:0x4005A000
group.long 0x0++0x7
line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled  BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
group.long 0x10++0x7
line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
group.long 0x20++0x7
line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
group.long 0x30++0x3
line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode  BPWM counter counts from 0 to PERIOD  and restarts from 0.\nDown-Count mode: In this mode  BPWM counter counts from PERIOD to 0  and restarts from PERIOD."
group.long 0x50++0x17
line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
rgroup.long 0x90++0x3
line.long 0x0 "BPWM_CNT,BPWM Counter Register"
bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
group.long 0xB0++0xF
line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
group.long 0xD4++0x7
line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
group.long 0xE0++0x3
line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: Up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
group.long 0xE8++0x3
line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. \nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0. \nNote: This bit is cleared by writing 1 to it." "0,1"
group.long 0xF8++0x7
line.long 0x0 "BPWM_EADCTS0,BPWM Trigger EADC0/1/2 Source Select Register 0"
bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger EADC0/1/2 Source Select\nOthers reserved."
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger EADC0/1/2 Source Select\nOthers reserved"
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger EADC0/1/2 Source Select\nOthers reserved"
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger EADC0/1/2 Source Select\nOthers reserved"
line.long 0x4 "BPWM_EADCTS1,BPWM Trigger EADC0/1/2 Source Select Register 1"
bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger EADC0/1/2 Source Select\nOthers reserved"
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger EADC0/1/2 Source Select\nOthers reserved"
group.long 0x110++0x3
line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled  the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
wgroup.long 0x114++0x3
line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only)\nBPMW counter synchronous enable function is used to make EPWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
group.long 0x120++0x3
line.long 0x0 "BPWM_STATUS,BPWM Status Register"
bitfld.long 0x0 21. "EADCTRG5,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
bitfld.long 0x0 20. "EADCTRG4,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
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bitfld.long 0x0 19. "EADCTRG3,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
bitfld.long 0x0 18. "EADCTRG2,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
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bitfld.long 0x0 17. "EADCTRG1,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
bitfld.long 0x0 16. "EADCTRG0,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit is cleared by writing 1 to it." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
group.long 0x200++0x7
line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
rgroup.long 0x208++0x33
line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
group.long 0x250++0x7
line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n."
hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n."
line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
rgroup.long 0x304++0x3
line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register."
rgroup.long 0x31C++0x17
line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
tree.end
tree "BPWM1"
base ad:0x4005B000
group.long 0x0++0x7
line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled  BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled  CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
group.long 0x10++0x7
line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
group.long 0x20++0x7
line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
group.long 0x30++0x3
line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode  BPWM counter counts from 0 to PERIOD  and restarts from 0.\nDown-Count mode: In this mode  BPWM counter counts from PERIOD to 0  and restarts from PERIOD."
group.long 0x50++0x17
line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform  interrupt and trigger EADC0/1/2.\nIn independent mode  CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point."
rgroup.long 0x90++0x3
line.long 0x0 "BPWM_CNT,BPWM Counter Register"
bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
group.long 0xB0++0xF
line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to zero." "0: Do nothing,1: BPWM zero point output Low,?,?"
line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin  if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
group.long 0xD4++0x7
line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n." "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM pin at tri-state,1: BPWM pin in output mode"
group.long 0xE0++0x3
line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: Up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
group.long 0xE8++0x3
line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. \nNote: If CMPDAT is equal to PERIOD  this flag does not work in down.." "0,1"
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT is equal to PERIOD  this flag does not work in up counter.." "0,1"
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. \nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0. \nNote: This bit is cleared by writing 1 to it." "0,1"
group.long 0xF8++0x7
line.long 0x0 "BPWM_EADCTS0,BPWM Trigger EADC0/1/2 Source Select Register 0"
bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger EADC0/1/2 Source Select\nOthers reserved."
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger EADC0/1/2 Source Select\nOthers reserved"
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger EADC0/1/2 Source Select\nOthers reserved"
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger EADC0/1/2 Source Select\nOthers reserved"
line.long 0x4 "BPWM_EADCTS1,BPWM Trigger EADC0/1/2 Source Select Register 1"
bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger EADC0/1/2 Source Select\nOthers reserved"
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger EADC0/1/2 Enable Bit" "0,1"
hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger EADC0/1/2 Source Select\nOthers reserved"
group.long 0x110++0x3
line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled  the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
wgroup.long 0x114++0x3
line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only)\nBPMW counter synchronous enable function is used to make EPWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
group.long 0x120++0x3
line.long 0x0 "BPWM_STATUS,BPWM Status Register"
bitfld.long 0x0 21. "EADCTRG5,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
bitfld.long 0x0 20. "EADCTRG4,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
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bitfld.long 0x0 19. "EADCTRG3,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
bitfld.long 0x0 18. "EADCTRG2,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
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bitfld.long 0x0 17. "EADCTRG1,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
bitfld.long 0x0 16. "EADCTRG0,EADC0 EADC1 EADC2 Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No EADC0/1/2 start of conversion trigger event..,1: An EADC0/1/2 start of conversion trigger event.."
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit is cleared by writing 1 to it." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
group.long 0x200++0x7
line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
rgroup.long 0x208++0x33
line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when.." "0,1"
line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened  the BPWM counter value will be saved in this register."
line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened  the BPWM counter value will be saved in this register."
group.long 0x250++0x7
line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n."
hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n."
line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
rgroup.long 0x304++0x3
line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register."
rgroup.long 0x31C++0x17
line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register."
tree.end
tree.end
tree "CANFD (Controller Area Network with Feasibility Data Rate)"
base ad:0x0
tree "CANFD0"
base ad:0x40020000
rgroup.long 0xC++0xB
line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
line.long 0x4 "CANFD_TEST,Test Register (P*)"
bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (refer to 6.38.5.1.."
line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Conguration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
group.long 0x18++0x3
line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set  the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set  the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 6.38.5.5)." "0: Transmit pause disabled,1: Transmit pause enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled  the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x0 1. "CCE,Conguration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains  there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
rgroup.long 0x1C++0x13
line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time segment after sample point\nNote: With a CAN Core clock (cclk) of 8 MHz  the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
line.long 0x4 "CANFD_TSCC,Timestamp Counter Conguration (P*)"
hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV."
line.long 0xC "CANFD_TOCC,Timeout Counter Conguration (P*)"
hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode  a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs  an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to 6.38.5.3." "0: Timeout Counter disabled,1: Timeout Counter enabled"
line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the conguration of TCP (CANFD_TSCC[19:16]). When decremented to zero  interrupt ag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and.."
rgroup.long 0x40++0xB
line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter  values between 0 and 127."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter  values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set  the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected  but CEL is still.."
line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point  dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]). The SSP position is  in the data phase  the number of minimum time quata.."
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RFDF  reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF ag set has.."
bitfld.long 0x4 12. "RBRS,BRS ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RBRS  reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS ag set"
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bitfld.long 0x4 11. "RESI,ESI ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI ag set"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS ag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS ag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position  dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
group.long 0x50++0xF
line.long 0x0 "CANFD_IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
bitfld.long 0x0 22. "ELO,Error Logging Overow" "0: CAN Error Logging Counter did not overow,1: Overow of CAN Error Logging Counter occurred"
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe ag is set  when the Rx Handler\n- Has not completed acceptance ltering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance ltering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
line.long 0x4 "CANFD_IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 22. "ELOE,Error Logging Overow Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x8 22. "ELOL,Error Logging Overow Interrupt Line" "0,1"
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
line.long 0xC "CANFD_ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_can_int1 disabled,1: Interrupt line m_can_int1 enabled"
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_can_int0 disabled,1: Interrupt line m_can_int0 enabled"
rgroup.long 0x80++0xB
line.long 0x0 "CANFD_GFC,Global Filter Conguration (P*)"
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
line.long 0x4 "CANFD_SIDFC,Standard ID Filter Conguration (P*)"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID lter list (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_XIDFC,Extended ID Filter Conguration (P*)"
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID lter list (32-bit word address  refer to Figure 6.3811)"
rgroup.long 0x90++0x7
line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance ltering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
line.long 0x4 "CANFD_HPMS,High Priority Message Status"
bitfld.long 0x4 15. "FLST,Filter List\nIndicates the lter list of the matching lter element." "0: Standard Filter List,1: Extended Filter List"
hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0x7
line.long 0x0 "CANFD_NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 0 to 31. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
line.long 0x4 "CANFD_NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 32 to 63. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
rgroup.long 0xA0++0x7
line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Conguration (P*)"
bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer  range 0 to 63."
hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer  range 0 to 63."
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0  range 0 to 64"
group.long 0xA8++0x3
line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
rgroup.long 0xAC++0xB
line.long 0x0 "CANFD_RXBC,Rx Buffer Conguration (P*)"
hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Conguration (P*)"
bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64."
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer  range 0 to 63."
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hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64"
group.long 0xB8++0x3
line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
rgroup.long 0xBC++0x13
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Conguration (P*)"
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO  only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x4 "CANFD_TXBC,Tx Buffer Conguration (P*)"
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address  refer to Figure 6.3811).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers.."
line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue is not full,1: Tx FIFO/Queue is full"
hexmask.long.byte 0x8 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer  range 0 to 31."
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hexmask.long.byte 0x8 8.--12. 1. "TFG,Tx FIFO Get Index"
hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue  the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Conguration (P*)"
bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0])  the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
group.long 0xD0++0x7
line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
rgroup.long 0xD8++0x7
line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
group.long 0xE0++0x7
line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt enable bit."
line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
rgroup.long 0xF0++0x7
line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Conguration (P*)"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt ag TEFL (CANFD_IR[15]). When TEFL is reset  this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer  range 0 to 31"
hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer  range 0 to 31"
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hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO  range 0 to 32"
group.long 0xF8++0x3
line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
tree.end
tree "CANFD1"
base ad:0x40024000
rgroup.long 0xC++0xB
line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
line.long 0x4 "CANFD_TEST,Test Register (P*)"
bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (refer to 6.38.5.1.."
line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Conguration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
group.long 0x18++0x3
line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set  the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set  the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 6.38.5.5)." "0: Transmit pause disabled,1: Transmit pause enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled  the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x0 1. "CCE,Conguration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains  there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
rgroup.long 0x1C++0x13
line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time segment after sample point\nNote: With a CAN Core clock (cclk) of 8 MHz  the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
line.long 0x4 "CANFD_TSCC,Timestamp Counter Conguration (P*)"
hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV."
line.long 0xC "CANFD_TOCC,Timeout Counter Conguration (P*)"
hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode  a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs  an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to 6.38.5.3." "0: Timeout Counter disabled,1: Timeout Counter enabled"
line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the conguration of TCP (CANFD_TSCC[19:16]). When decremented to zero  interrupt ag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and.."
rgroup.long 0x40++0xB
line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter  values between 0 and 127."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter  values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set  the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected  but CEL is still.."
line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point  dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]). The SSP position is  in the data phase  the number of minimum time quata.."
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RFDF  reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF ag set has.."
bitfld.long 0x4 12. "RBRS,BRS ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RBRS  reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS ag set"
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bitfld.long 0x4 11. "RESI,ESI ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI ag set"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS ag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS ag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position  dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
group.long 0x50++0xF
line.long 0x0 "CANFD_IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
bitfld.long 0x0 22. "ELO,Error Logging Overow" "0: CAN Error Logging Counter did not overow,1: Overow of CAN Error Logging Counter occurred"
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe ag is set  when the Rx Handler\n- Has not completed acceptance ltering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance ltering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
line.long 0x4 "CANFD_IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 22. "ELOE,Error Logging Overow Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x8 22. "ELOL,Error Logging Overow Interrupt Line" "0,1"
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
line.long 0xC "CANFD_ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_can_int1 disabled,1: Interrupt line m_can_int1 enabled"
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_can_int0 disabled,1: Interrupt line m_can_int0 enabled"
rgroup.long 0x80++0xB
line.long 0x0 "CANFD_GFC,Global Filter Conguration (P*)"
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
line.long 0x4 "CANFD_SIDFC,Standard ID Filter Conguration (P*)"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID lter list (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_XIDFC,Extended ID Filter Conguration (P*)"
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID lter list (32-bit word address  refer to Figure 6.3811)"
rgroup.long 0x90++0x7
line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance ltering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
line.long 0x4 "CANFD_HPMS,High Priority Message Status"
bitfld.long 0x4 15. "FLST,Filter List\nIndicates the lter list of the matching lter element." "0: Standard Filter List,1: Extended Filter List"
hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0x7
line.long 0x0 "CANFD_NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 0 to 31. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
line.long 0x4 "CANFD_NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 32 to 63. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
rgroup.long 0xA0++0x7
line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Conguration (P*)"
bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer  range 0 to 63."
hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer  range 0 to 63."
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0  range 0 to 64"
group.long 0xA8++0x3
line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
rgroup.long 0xAC++0xB
line.long 0x0 "CANFD_RXBC,Rx Buffer Conguration (P*)"
hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Conguration (P*)"
bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64."
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer  range 0 to 63."
newline
hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64"
group.long 0xB8++0x3
line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
rgroup.long 0xBC++0x13
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Conguration (P*)"
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
newline
bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO  only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x4 "CANFD_TXBC,Tx Buffer Conguration (P*)"
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address  refer to Figure 6.3811).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers.."
line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue is not full,1: Tx FIFO/Queue is full"
hexmask.long.byte 0x8 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer  range 0 to 31."
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hexmask.long.byte 0x8 8.--12. 1. "TFG,Tx FIFO Get Index"
hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue  the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Conguration (P*)"
bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0])  the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
group.long 0xD0++0x7
line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
rgroup.long 0xD8++0x7
line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
group.long 0xE0++0x7
line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt enable bit."
line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
rgroup.long 0xF0++0x7
line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Conguration (P*)"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt ag TEFL (CANFD_IR[15]). When TEFL is reset  this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
newline
hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer  range 0 to 31"
hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer  range 0 to 31"
newline
hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO  range 0 to 32"
group.long 0xF8++0x3
line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
tree.end
tree "CANFD2"
base ad:0x40028000
rgroup.long 0xC++0xB
line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
newline
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
newline
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
line.long 0x4 "CANFD_TEST,Test Register (P*)"
bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
newline
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (refer to 6.38.5.1.."
line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Conguration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
group.long 0x18++0x3
line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set  the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set  the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 6.38.5.5)." "0: Transmit pause disabled,1: Transmit pause enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled  the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
newline
bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x0 1. "CCE,Conguration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains  there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
rgroup.long 0x1C++0x13
line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time segment after sample point\nNote: With a CAN Core clock (cclk) of 8 MHz  the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
line.long 0x4 "CANFD_TSCC,Timestamp Counter Conguration (P*)"
hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV."
line.long 0xC "CANFD_TOCC,Timeout Counter Conguration (P*)"
hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode  a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs  an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to 6.38.5.3." "0: Timeout Counter disabled,1: Timeout Counter enabled"
line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the conguration of TCP (CANFD_TSCC[19:16]). When decremented to zero  interrupt ag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and.."
rgroup.long 0x40++0xB
line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter  values between 0 and 127."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter  values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set  the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected  but CEL is still.."
line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point  dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]). The SSP position is  in the data phase  the number of minimum time quata.."
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RFDF  reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF ag set has.."
bitfld.long 0x4 12. "RBRS,BRS ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RBRS  reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS ag set"
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bitfld.long 0x4 11. "RESI,ESI ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI ag set"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS ag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS ag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position  dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
group.long 0x50++0xF
line.long 0x0 "CANFD_IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
bitfld.long 0x0 22. "ELO,Error Logging Overow" "0: CAN Error Logging Counter did not overow,1: Overow of CAN Error Logging Counter occurred"
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe ag is set  when the Rx Handler\n- Has not completed acceptance ltering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance ltering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
line.long 0x4 "CANFD_IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 22. "ELOE,Error Logging Overow Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x8 22. "ELOL,Error Logging Overow Interrupt Line" "0,1"
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
line.long 0xC "CANFD_ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_can_int1 disabled,1: Interrupt line m_can_int1 enabled"
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_can_int0 disabled,1: Interrupt line m_can_int0 enabled"
rgroup.long 0x80++0xB
line.long 0x0 "CANFD_GFC,Global Filter Conguration (P*)"
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
line.long 0x4 "CANFD_SIDFC,Standard ID Filter Conguration (P*)"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID lter list (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_XIDFC,Extended ID Filter Conguration (P*)"
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID lter list (32-bit word address  refer to Figure 6.3811)"
rgroup.long 0x90++0x7
line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance ltering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
line.long 0x4 "CANFD_HPMS,High Priority Message Status"
bitfld.long 0x4 15. "FLST,Filter List\nIndicates the lter list of the matching lter element." "0: Standard Filter List,1: Extended Filter List"
hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0x7
line.long 0x0 "CANFD_NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 0 to 31. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
line.long 0x4 "CANFD_NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 32 to 63. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
rgroup.long 0xA0++0x7
line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Conguration (P*)"
bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer  range 0 to 63."
hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer  range 0 to 63."
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0  range 0 to 64"
group.long 0xA8++0x3
line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
rgroup.long 0xAC++0xB
line.long 0x0 "CANFD_RXBC,Rx Buffer Conguration (P*)"
hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Conguration (P*)"
bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64."
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer  range 0 to 63."
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hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64"
group.long 0xB8++0x3
line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
rgroup.long 0xBC++0x13
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Conguration (P*)"
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO  only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x4 "CANFD_TXBC,Tx Buffer Conguration (P*)"
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address  refer to Figure 6.3811).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers.."
line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue is not full,1: Tx FIFO/Queue is full"
hexmask.long.byte 0x8 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer  range 0 to 31."
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hexmask.long.byte 0x8 8.--12. 1. "TFG,Tx FIFO Get Index"
hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue  the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Conguration (P*)"
bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0])  the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
group.long 0xD0++0x7
line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
rgroup.long 0xD8++0x7
line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
group.long 0xE0++0x7
line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt enable bit."
line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
rgroup.long 0xF0++0x7
line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Conguration (P*)"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt ag TEFL (CANFD_IR[15]). When TEFL is reset  this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer  range 0 to 31"
hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer  range 0 to 31"
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hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO  range 0 to 32"
group.long 0xF8++0x3
line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
tree.end
tree "CANFD3"
base ad:0x4002C000
rgroup.long 0xC++0xB
line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
line.long 0x4 "CANFD_TEST,Test Register (P*)"
bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (refer to 6.38.5.1.."
line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Conguration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
group.long 0x18++0x3
line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set  the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set  the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 6.38.5.5)." "0: Transmit pause disabled,1: Transmit pause enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled  the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x0 1. "CCE,Conguration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains  there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
rgroup.long 0x1C++0x13
line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time segment after sample point\nNote: With a CAN Core clock (cclk) of 8 MHz  the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
line.long 0x4 "CANFD_TSCC,Timestamp Counter Conguration (P*)"
hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV."
line.long 0xC "CANFD_TOCC,Timeout Counter Conguration (P*)"
hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode  a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs  an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to 6.38.5.3." "0: Timeout Counter disabled,1: Timeout Counter enabled"
line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the conguration of TCP (CANFD_TSCC[19:16]). When decremented to zero  interrupt ag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and.."
rgroup.long 0x40++0xB
line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter  values between 0 and 127."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter  values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set  the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected  but CEL is still.."
line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point  dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]). The SSP position is  in the data phase  the number of minimum time quata.."
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RFDF  reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF ag set has.."
bitfld.long 0x4 12. "RBRS,BRS ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RBRS  reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS ag set"
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bitfld.long 0x4 11. "RESI,ESI ag of last received CAN FD Message\nThis bit is set together with RFDF  independent of acceptance ltering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI ag set"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS ag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS ag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position  dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
group.long 0x50++0xF
line.long 0x0 "CANFD_IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
bitfld.long 0x0 22. "ELO,Error Logging Overow" "0: CAN Error Logging Counter did not overow,1: Overow of CAN Error Logging Counter occurred"
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe ag is set  when the Rx Handler\n- Has not completed acceptance ltering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance ltering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
line.long 0x4 "CANFD_IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 22. "ELOE,Error Logging Overow Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x8 22. "ELOL,Error Logging Overow Interrupt Line" "0,1"
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
line.long 0xC "CANFD_ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_can_int1 disabled,1: Interrupt line m_can_int1 enabled"
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_can_int0 disabled,1: Interrupt line m_can_int0 enabled"
rgroup.long 0x80++0xB
line.long 0x0 "CANFD_GFC,Global Filter Conguration (P*)"
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
line.long 0x4 "CANFD_SIDFC,Standard ID Filter Conguration (P*)"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID lter list (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_XIDFC,Extended ID Filter Conguration (P*)"
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID lter list (32-bit word address  refer to Figure 6.3811)"
rgroup.long 0x90++0x7
line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance ltering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
line.long 0x4 "CANFD_HPMS,High Priority Message Status"
bitfld.long 0x4 15. "FLST,Filter List\nIndicates the lter list of the matching lter element." "0: Standard Filter List,1: Extended Filter List"
hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0x7
line.long 0x0 "CANFD_NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 0 to 31. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
line.long 0x4 "CANFD_NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 32 to 63. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
rgroup.long 0xA0++0x7
line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Conguration (P*)"
bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer  range 0 to 63."
hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer  range 0 to 63."
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0  range 0 to 64"
group.long 0xA8++0x3
line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
rgroup.long 0xAC++0xB
line.long 0x0 "CANFD_RXBC,Rx Buffer Conguration (P*)"
hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Conguration (P*)"
bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64."
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer  range 0 to 63."
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hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1  range 0 to 64"
group.long 0xB8++0x3
line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
rgroup.long 0xBC++0x13
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Conguration (P*)"
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO  only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x4 "CANFD_TXBC,Tx Buffer Conguration (P*)"
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address  refer to Figure 6.3811).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers.."
line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue is not full,1: Tx FIFO/Queue is full"
hexmask.long.byte 0x8 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer  range 0 to 31."
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hexmask.long.byte 0x8 8.--12. 1. "TFG,Tx FIFO Get Index"
hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue  the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Conguration (P*)"
bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0])  the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
group.long 0xD0++0x7
line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
rgroup.long 0xD8++0x7
line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
group.long 0xE0++0x7
line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt enable bit."
line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
rgroup.long 0xF0++0x7
line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Conguration (P*)"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address  refer to Figure 6.3811)."
line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt ag TEFL (CANFD_IR[15]). When TEFL is reset  this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer  range 0 to 31"
hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer  range 0 to 31"
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hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO  range 0 to 32"
group.long 0xF8++0x3
line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
tree.end
tree.end
tree "CCAP (Camera Capture Interface)"
base ad:0x40030000
group.long 0x0++0xB
line.long 0x0 "CCAP_CTL,Camera Capture Interface Control Register"
bitfld.long 0x0 24. "VPRST,Capture Interface Reset" "0: Capture interface reset Disabled,1: Capture interface reset Enabled"
bitfld.long 0x0 20. "UPDATE,Update Register at New Frame" "0: Update register at new frame Disabled,1: Update register at new frame Enabled (auto.."
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bitfld.long 0x0 19. "Luma_Y_One,Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion\nNote: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled." "0: Color/Monochrome CMOS sensor Luma-Y-One bit..,1: Color/Monochrome CMOS sensor Luma-Y-One bit.."
bitfld.long 0x0 18. "MY8_MY4,Monochrome CMOS Sensor Data I/O Interface" "0: Monochrome CMOS sensor is by the 4-bit data I/O..,1: Monochrome CMOS sensor is by the 8-bit data I/O.."
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bitfld.long 0x0 17. "MY4_SWAP,Monochrome CMOS Sensor 4-bit Data Nibble Swap" "0: The 4-bit data input sequence: 1st Pixel is for..,1: The 4-bit data input sequence: 1st Pixel is for.."
bitfld.long 0x0 16. "SHUTTER,Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured" "0: Shutter Disabled,1: Shutter Enabled"
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bitfld.long 0x0 7. "MONO,Monochrome CMOS Sensor Select" "0: Color CMOS Sensor,1: Monochrome CMOS Sensor. The U/V components are.."
bitfld.long 0x0 6. "PKTEN,Packet Output Enable Bit" "0: Packet output Disabled,1: Packet output Enabled"
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bitfld.long 0x0 0. "CCAPEN,Camera Capture Interface Enable Bit" "0: Camera Capture Interface Disabled,1: Camera Capture Interface Enabled"
line.long 0x4 "CCAP_PAR,Camera Capture Interface Parameter Register"
bitfld.long 0x4 18. "FBB,Field by Blank \nField by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not." "0: Field by blank Disabled. (blank pixel data will..,1: Field by blank Enabled. (only active data will.."
bitfld.long 0x4 10. "VSP,Sensor Vsync Polarity" "0: Sync Low,1: Sync High"
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bitfld.long 0x4 9. "HSP,Sensor Hsync Polarity" "0: Sync Low,1: Sync High"
bitfld.long 0x4 8. "PCLKP,Sensor Pixel Clock Polarity" "0: Input video data and signals are latched by..,1: Input video data and signals are latched by.."
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bitfld.long 0x4 6. "RANGE,Scale Input YUV CCIR601 Color Range to Full Range" "0: Default,1: Scale to full range"
bitfld.long 0x4 4.--5. "OUTFMT,Image Data Format Output to System Memory" "0: YCbCr422,1: Only output Y. (Select this format when CCAP_CTL..,?,?"
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bitfld.long 0x4 2.--3. "INDATORD,Sensor Input Data Order\nSensor input data (Byte 1) is {B[4:0]  G[5:3]}." "0: Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1..,1: Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1..,?,?"
bitfld.long 0x4 1. "SENTYPE,Sensor Input Type" "0: CCIR601,1: CCIR656 Vsync Hsync embedded in the data signal"
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bitfld.long 0x4 0. "INFMT,Sensor Input Data Format" "0: YCbCr422,1: RGB565"
line.long 0x8 "CCAP_INT,Camera Capture Interface Interrupt Register"
bitfld.long 0x8 19. "ADDRMIEN,Address Match Interrupt Enable Bit" "0: Address match interrupt Disabled,1: Address match interrupt Enabled"
bitfld.long 0x8 17. "MEIEN,Bus Master Transfer Error Interrupt Enable Bit" "0: Bus Master Transfer error interrupt Disabled,1: Bus Master Transfer error interrupt Enabled"
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bitfld.long 0x8 16. "VIEN,Video Frame End Interrupt Enable Bit" "0: Video frame end interrupt Disabled,1: Video frame end interrupt Enabled"
bitfld.long 0x8 3. "ADDRMINTF,Memory Address Match Interrupt\nNote: This bit is cleared by writing 1 to it." "0: Memory Address Match Interrupt did not occur,1: Memory Address Match Interrupt occurred"
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bitfld.long 0x8 1. "MEINTF,Bus Master Transfer Error Interrupt\nNote: This bit is cleared by writing 1 to it." "0: Transfer Error did not occur,1: Transfer Error occurred"
bitfld.long 0x8 0. "VINTF,Video Frame End Interrupt\nNote: This bit is cleared by writing 1 to it." "0: Did not receive a frame completely,1: Received a frame completely"
group.long 0x20++0xB
line.long 0x0 "CCAP_CWSP,Cropping Window Starting Address Register"
hexmask.long.word 0x0 16.--26. 1. "CWSADDRV,Cropping Window Vertical Starting Address\nSpecify the value of the cropping window vertical start address."
hexmask.long.word 0x0 0.--11. 1. "CWSADDRH,Cropping Window Horizontal Starting Address\nSpecify the value of the cropping window horizontal start address."
line.long 0x4 "CCAP_CWS,Cropping Window Size Register"
hexmask.long.word 0x4 16.--26. 1. "CWH,Cropping Window Height\nSpecify the size of the cropping window height."
hexmask.long.word 0x4 0.--11. 1. "CWW,Cropping Window Width\nSpecify the size of the cropping window width."
line.long 0x8 "CCAP_PKTSL,Packet Scaling Vertical/Horizontal Factor Register (LSB)"
hexmask.long.byte 0x8 24.--31. 1. "PKTSVNL,Packet Scaling Vertical Factor N\nSpecify the lower 8-bit of numerator part (N) of the vertical scaling factor. \nThe lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor."
hexmask.long.byte 0x8 16.--23. 1. "PKTSVML,Packet Scaling Vertical Factor M\nSpecify the lower 8-bit of denominator part (M) of the vertical scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.\nThe output image.."
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hexmask.long.byte 0x8 8.--15. 1. "PKTSHNL,Packet Scaling Horizontal Factor N\nSpecify the lower 8-bit of numerator part (N) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor."
hexmask.long.byte 0x8 0.--7. 1. "PKTSHML,Packet Scaling Horizontal Factor M\nSpecify the lower 8-bit of denominator part (M) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.\nThe output.."
group.long 0x30++0x7
line.long 0x0 "CCAP_FRCTL,Scaling Frame Rate Factor Register"
hexmask.long.byte 0x0 8.--13. 1. "FRN,Scaling Frame Rate Factor N\nSpecify the numerator part (N) of the frame rate scaling factor."
hexmask.long.byte 0x0 0.--5. 1. "FRM,Scaling Frame Rate Factor M\nSpecify the denominator part (M) of the frame rate scaling factor.\nThe output image frame rate will be equal to input image frame rate * (N/M).\nNote: The value of N must be equal to or less than M."
line.long 0x4 "CCAP_STRIDE,Frame Output Pixel Stride Width Register"
hexmask.long.word 0x4 0.--13. 1. "PKTSTRIDE,Packet Frame Output Pixel Stride Width\nThe output pixel stride size of the packet pipe.\nIt is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or.."
group.long 0x3C++0xF
line.long 0x0 "CCAP_FIFOTH,FIFO Threshold Register"
bitfld.long 0x0 31. "OVF,FIFO Overflow Flag\nIndicate the FIFO overflow flag." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "PKTFTH,Packet FIFO Threshold\nSpecify the 5-bit value of the packet FIFO threshold."
line.long 0x4 "CCAP_CMPADDR,Compare Memory Base Address Register"
hexmask.long 0x4 0.--31. 1. "CMPADDR,Compare Memory Base Address\nIt is a word alignment address  that is  the address is aligned by ignoring the 2 LSB bits [1:0]."
line.long 0x8 "CCAP_LUMA_Y1_THD,Luminance Y8 to Y1 Threshold Value Register"
hexmask.long.byte 0x8 0.--7. 1. "LUMA_Y1_THRESH,Luminance Y8 to Y1 Threshold Value\nSpecify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion."
line.long 0xC "CCAP_PKTSM,Packet Scaling Vertical/Horizontal Factor Register (MSB)"
hexmask.long.byte 0xC 24.--31. 1. "PKTSVNH,Packet Scaling Vertical Factor N\nSpecify the higher 8-bit of numerator part (N) of the vertical scaling factor. \nPlease refer to the register 'CCAP_PKTSL' to check the cooperation between these two registers."
hexmask.long.byte 0xC 16.--23. 1. "PKTSVMH,Packet Scaling Vertical Factor M\nSpecify the higher 8-bit of denominator part (M) of the vertical scaling factor.\nPlease refer to the register 'CCAP_PKTSL' to check the cooperation between these two registers."
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hexmask.long.byte 0xC 8.--15. 1. "PKTSHNH,Packet Scaling Horizontal Factor N\nSpecify the higher 8-bit of numerator part (N) of the horizontal scaling factor.\nPlease refer to the register 'CCAP_PKTSL' for the detailed operation."
hexmask.long.byte 0xC 0.--7. 1. "PKTSHMH,Packet Scaling Horizontal Factor M\nSpecify the higher 8-bit of denominator part (M) of the horizontal scaling factor.\nPlease refer to the register 'CCAP_PKTSL' for the detailed operation."
rgroup.long 0x50++0x3
line.long 0x0 "CCAP_CURADDRP,Current Packet System Memory Address Register"
hexmask.long 0x0 0.--31. 1. "CURADDR,Current Packet Output Memory Address\nSpecify the 32-bit value of the current packet output memory address."
group.long 0x60++0x3
line.long 0x0 "CCAP_PKTBA0,System Memory Packet Base Address 0 Register"
hexmask.long 0x0 0.--31. 1. "BASEADDR,System Memory Packet Base Address 0\nIt is a word alignment address  that is  the address is aligned by ignoring the 2 LSB bits [1:0]."
tree.end
tree "CLK (Clock Controller)"
base ad:0x40000200
group.long 0x0++0x43
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
bitfld.long 0x0 31. "HXTMD,HXT Mode Selection (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGCTL register.\nNote 2: When external clock mode enable  HXTSELTYP(CLK_PWRCTL[12]) must be set as GM type." "0: HXT work as crystal mode. PF.2 and PF.3 are..,1: This bit is write protected"
bitfld.long 0x0 18. "HIRC48MEN,HIRC48M Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x0 16.--17. "HIRCSTBS,HIRC Stable Count Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: HIRC stable count is 64 clocks,1: HIRC stable count is 24 clocks,?,?"
bitfld.long 0x0 12. "HXTSELTYP,HXT Crystal Type Select Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Select INV type,1: Select GM type"
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bitfld.long 0x0 10.--11. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: HXT frequency is lower than from 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?"
bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1  Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode  this bit.." "0: Chip will not enter Power-down mode after CPU..,1: This bit is write protected"
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bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event'  it indicates that resume from Power-down mode. \nThe flag is set if any wake-up source occurred. Refer Power Modes and Wake-up Sources chapter.\nNote 1: Write 1 to clear.." "?,1: Write 1 to clear the bit to 0"
bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
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bitfld.long 0x0 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode  the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 12 MHz internal high speed RC oscillator (HIRC)..,1: 12 MHz internal high speed RC oscillator (HIRC).."
bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal (LXT)..,1: 32.768 kHz external low speed crystal (LXT).."
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bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal (HXT)..,1: 4~24 MHz external high speed crystal (HXT) Enabled"
line.long 0x4 "CLK_AHBCLK0,AHB Devices Clock Enable Control Register 0"
bitfld.long 0x4 31. "GPHCKEN,GPIOH Clock Enable Bit" "0: GPIOH clock Disabled,1: GPIOH clock Enabled"
bitfld.long 0x4 30. "GPGCKEN,GPIOG Clock Enable Bit" "0: GPIOG clock Disabled,1: GPIOG clock Enabled"
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bitfld.long 0x4 29. "GPFCKEN,GPIOF Clock Enable Bit" "0: GPIOF clock Disabled,1: GPIOF clock Enabled"
bitfld.long 0x4 28. "GPECKEN,GPIOE Clock Enable Bit" "0: GPIOE clock Disabled,1: GPIOE clock Enabled"
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bitfld.long 0x4 27. "GPDCKEN,GPIOD Clock Enable Bit" "0: GPIOD clock Disabled,1: GPIOD clock Enabled"
bitfld.long 0x4 26. "GPCCKEN,GPIOC Clock Enable Bit" "0: GPIOC clock Disabled,1: GPIOC clock Enabled"
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bitfld.long 0x4 25. "GPBCKEN,GPIOB Clock Enable Bit" "0: GPIOB clock Disabled,1: GPIOB clock Enabled"
bitfld.long 0x4 24. "GPACKEN,GPIOA Clock Enable Bit" "0: GPIOA clock Disabled,1: GPIOA clock Enabled"
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bitfld.long 0x4 19. "TRACECKEN,TRACE Clock Enable Bit" "0: TRACE clock Disabled,1: TRACE clock Enabled"
bitfld.long 0x4 18. "PDMA1CKEN,PDMA1 Clock Enable Bit" "0: PDMA1 clock Disabled,1: PDMA1 clock Enabled"
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bitfld.long 0x4 17. "SDH1CKEN,SDH1 Controller Clock Enable Bit" "0: SDH1 clock Disabled,1: SDH1 clock Enabled"
bitfld.long 0x4 16. "USBHCKEN,USB HOST Controller Clock Enable Bit" "0: USB HOST peripheral clock Disabled,1: USB HOST peripheral clock Enabled"
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bitfld.long 0x4 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC clock Disabled when chip is under IDLE mode,1: FMC clock Enabled when chip is under IDLE mode"
bitfld.long 0x4 14. "SPIMCKEN,SPIM Controller Clock Enable Bit" "0: SPIM controller clock Disabled,1: SPIM controller clock Enabled"
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bitfld.long 0x4 13. "KSCKEN,Key Store Clock Enable Bit" "0: Key Store clock Disabled,1: Key Store clock Enabled"
bitfld.long 0x4 12. "CRPTCKEN,Cryptographic Accelerator Clock Enable Bit" "0: Cryptographic Accelerator clock Disabled,1: Cryptographic Accelerator clock Enabled"
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bitfld.long 0x4 11. "HBICKEN,HyperBus Interface Clock Enable Bit" "0: HBI clock Disabled,1: HBI clock Enabled"
bitfld.long 0x4 10. "HSUSBDCKEN,HSUSB Device Clock Enable Bit" "0: HSUSB device controller clock Disabled,1: HSUSB device controller clock Enabled"
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bitfld.long 0x4 9. "SENCKEN,CCAP Sensor Clock Enable Control" "0: CCAP Sensor clock Disabled,1: CCAP Sensor clock Enabled"
bitfld.long 0x4 8. "CCAPCKEN,Camera Capture Interface Controller Clock Enable Control" "0: CCAP controller clock Disabled,1: CCAP controller clock Enabled"
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bitfld.long 0x4 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
bitfld.long 0x4 6. "SDH0CKEN,SDH0 Controller Clock Enable Bit" "0: SDH0 clock Disabled,1: SDH0 clock Enabled"
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bitfld.long 0x4 5. "EMAC0CKEN,EMAC0 Controller Clock Enable Bit" "0: EMAC0 controller clock Disabled,1: EMAC0 controller clock Enabled"
bitfld.long 0x4 4. "STCKEN,System Tick Clock Enable Bit" "0: System tick clock Disabled,1: System tick clock Enabled"
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bitfld.long 0x4 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled"
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x4 1. "PDMA0CKEN,PDMA0 Controller Clock Enable Bit" "0: PDMA0 peripheral clock Disabled,1: PDMA0 peripheral clock Enabled"
line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
bitfld.long 0x8 30. "HSOTGCKEN,HSUSB OTG Clock Enable Bit" "0: HSUSB OTG clock Disabled,1: HSUSB OTG clock Enabled"
bitfld.long 0x8 29. "I2S0CKEN,I2S0 Clock Enable Bit" "0: I2S0 clock Disabled,1: I2S0 clock Enabled"
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bitfld.long 0x8 28. "EADC0CKEN,EADC0 Clock Enable Bit" "0: EADC0 clock Disabled,1: EADC0 clock Enabled"
bitfld.long 0x8 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB device clock Disabled,1: USB device clock Enabled"
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bitfld.long 0x8 26. "OTGCKEN,USB OTG Clock Enable Bit" "0: USB OTG clock Disabled,1: USB OTG clock Enabled"
bitfld.long 0x8 23. "UART7CKEN,UART7 Clock Enable Bit" "0: UART7 clock Disabled,1: UART7 clock Enabled"
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bitfld.long 0x8 22. "UART6CKEN,UART6 Clock Enable Bit" "0: UART6 clock Disabled,1: UART6 clock Enabled"
bitfld.long 0x8 21. "UART5CKEN,UART5 Clock Enable Bit" "0: UART5 clock Disabled,1: UART5 clock Enabled"
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bitfld.long 0x8 20. "UART4CKEN,UART4 Clock Enable Bit" "0: UART4 clock Disabled,1: UART4 clock Enabled"
bitfld.long 0x8 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
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bitfld.long 0x8 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
bitfld.long 0x8 15. "SPI2CKEN,SPI2 Clock Enable Bit" "0: SPI2 clock Disabled,1: SPI2 clock Enabled"
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bitfld.long 0x8 14. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
bitfld.long 0x8 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
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bitfld.long 0x8 12. "QSPI0CKEN,QSPI0 Clock Enable Bit" "0: QSPI0 clock Disabled,1: QSPI0 clock Enabled"
bitfld.long 0x8 11. "I2C3CKEN,I2C3 Clock Enable Bit" "0: I2C3 clock Disabled,1: I2C3 clock Enabled"
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bitfld.long 0x8 10. "I2C2CKEN,I2C2 Clock Enable Bit" "0: I2C2 clock Disabled,1: I2C2 clock Enabled"
bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
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bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
bitfld.long 0x8 7. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled"
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bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
bitfld.long 0x8 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). It can be selected to 32.768 kHz external low speed crystal (LXT) or 10.." "0: RTC clock Disabled,1: RTC clock Enabled"
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bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
line.long 0xC "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
bitfld.long 0xC 31. "EADC1CKEN,EADC1 Clock Enable Bit" "0: EADC1 clock Disabled,1: EADC1 clock Enabled"
bitfld.long 0xC 29. "I2S1CKEN,I2S1 Clock Enable Bit" "0: I2S1 clock Disabled,1: I2S1 clock Enabled"
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bitfld.long 0xC 27. "ECAP1CKEN,ECAP1 Clock Enable Bit" "0: ECAP1 clock Disabled,1: ECAP1 clock Enabled"
bitfld.long 0xC 26. "ECAP0CKEN,ECAP0 Clock Enable Bit" "0: ECAP0 clock Disabled,1: ECAP0 clock Enabled"
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bitfld.long 0xC 25. "TRNGCKEN,TRNG Clock Enable Bit" "0: TRNG clock Disabled,1: TRNG clock Enabled"
bitfld.long 0xC 23. "EQEI1CKEN,EQEI1 Clock Enable Bit" "0: EQEI1 clock Disabled,1: EQEI1 clock Enabled"
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bitfld.long 0xC 22. "EQEI0CKEN,EQEI0 Clock Enable Bit" "0: EQEI0 clock Disabled,1: EQEI0 clock Enabled"
bitfld.long 0xC 21. "EQEI3CKEN,EQEI3 Clock Enable Bit" "0: QEI3 clock Disabled,1: QEI3 clock Enabled"
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bitfld.long 0xC 20. "EQEI2CKEN,EQEI2 Clock Enable Bit" "0: EQEI2 clock Disabled,1: EQEI2 clock Enabled"
bitfld.long 0xC 19. "BPWM1CKEN,BPWM1 Clock Enable Bit" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled"
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bitfld.long 0xC 18. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
bitfld.long 0xC 17. "EPWM1CKEN,EPWM1 Clock Enable Bit" "0: EPWM1 clock Disabled,1: EPWM1 clock Enabled"
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bitfld.long 0xC 16. "EPWM0CKEN,EPWM0 Clock Enable Bit" "0: EPWM0 clock Disabled,1: EPWM0 clock Enabled"
bitfld.long 0xC 14. "ECAP3CKEN,ECAP3 Clock Enable Bit" "0: ECAP3 clock Disabled,1: ECAP3 clock Enabled"
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bitfld.long 0xC 13. "ECAP2CKEN,ECAP2 Clock Enable Bit" "0: ECAP2 clock Disabled,1: ECAP2 clock Enabled"
bitfld.long 0xC 12. "DACCKEN,DAC Clock Enable Bit" "0: DAC clock Disabled,1: DAC clock Enabled"
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bitfld.long 0xC 10. "PSIOCKEN,PSIO Clock Enable Bit" "0: PSIO clock Disabled,1: PSIO clock Enabled"
bitfld.long 0xC 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
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bitfld.long 0xC 7. "SPI4CKEN,SPI4 Clock Enable Bit" "0: SPI4 clock Disabled,1: SPI4 clock Enabled"
bitfld.long 0xC 6. "SPI3CKEN,SPI3 Clock Enable Bit" "0: SPI3 clock Disabled,1: SPI3 clock Enabled"
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bitfld.long 0xC 4. "QSPI1CKEN,QSPI1 Clock Enable Bit" "0: QSPI1 clock Disabled,1: QSPI1 clock Enabled"
bitfld.long 0xC 3. "I2C4CKEN,I2C4 Clock Enable Bit" "0: I2C4 clock Disabled,1: I2C4 clock Enabled"
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bitfld.long 0xC 2. "SC2CKEN,SC2 Clock Enable Bit" "0: SC2 clock Disabled,1: SC2 clock Enabled"
bitfld.long 0xC 1. "SC1CKEN,SC1 Clock Enable Bit" "0: SC1 clock Disabled,1: SC1 clock Enabled"
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bitfld.long 0xC 0. "SC0CKEN,SC0 Clock Enable Bit" "0: SC0 clock Disabled,1: SC0 clock Enabled"
line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x10 30.--31. "CANFD3SEL,CANFD3 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
bitfld.long 0x10 28.--29. "CANFD2SEL,CANFD2 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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bitfld.long 0x10 26.--27. "CANFD1SEL,CANFD1 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
bitfld.long 0x10 24.--25. "CANFD0SEL,CANFD0 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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bitfld.long 0x10 22.--23. "SDH1SEL,SDH1 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
bitfld.long 0x10 20.--21. "SDH0SEL,SDH0 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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bitfld.long 0x10 16.--17. "CCAPSEL,CCAP Sensor Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x10 14.--15. "EADC2SEL,EADC2 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from PLLFN/2,1: Clock source from PLL/2,?,?"
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bitfld.long 0x10 12.--13. "EADC1SEL,EADC1 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from PLLFN/2,1: Clock source from PLL/2,?,?"
bitfld.long 0x10 10.--11. "EADC0SEL,EADC0 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from PLLFN/2,1: Clock source from PLL/2,?,?"
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bitfld.long 0x10 8. "USBSEL,USB Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 48 MHz internal high speed RC..,1: Clock source from PLL/2"
bitfld.long 0x10 3.--5. "STCLKSEL,Cortex-M4 SysTick Clock Source Selection (Write Protect)\nNote 2: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,2: These bits are write protected,?,?,?,?,?"
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bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching  the related clock sources (both pre-select and new-select) must be turned on.\nNote: Theses bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x14 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "?,?,?,?"
bitfld.long 0x14 26.--27. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x14 24.--25. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x14 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
bitfld.long 0x14 4.--6. "CLKOSEL,Clock Output Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Reserved.,1: Clock source from 32.768 kHz external low speed..,?,?"
line.long 0x18 "CLK_CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x18 28.--30. "PSIOSEL,PSIO Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
bitfld.long 0x18 27. "TRNGSEL,TRNG Clock Source Selection" "0: Clock source from 32.768 kHz external low speed..,1: Clock source from 10 kHz internal low speed RC.."
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bitfld.long 0x18 22.--23. "UART9SEL,UART9 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x18 20.--21. "UART8SEL,UART8 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x18 16.--18. "I2S1SEL,I2S1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
bitfld.long 0x18 12.--14. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
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bitfld.long 0x18 10.--11. "QSPI1SEL,QSPI1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x18 9. "BPWM1SEL,BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL." "0: Clock source from HCLK,1: Clock source from PCLK1"
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bitfld.long 0x18 8. "BPWM0SEL,BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL." "0: Clock source from HCLK,1: Clock source from PCLK0"
bitfld.long 0x18 4.--6. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
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bitfld.long 0x18 2.--3. "QSPI0SEL,QSPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x18 1. "EPWM1SEL,EPWM1 Clock Source Selection\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL." "0: Clock source from HCLK,1: Clock source from PCLK1"
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bitfld.long 0x18 0. "EPWM0SEL,EPWM0 Clock Source Selection\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL." "0: Clock source from HCLK,1: Clock source from PCLK0"
line.long 0x1C "CLK_CLKSEL3,Clock Source Select Control Register 3"
bitfld.long 0x1C 30.--31. "UART5SEL,UART5 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x1C 28.--29. "UART4SEL,UART4 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x1C 26.--27. "UART3SEL,UART3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x1C 24.--25. "UART2SEL,UART2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x1C 22.--23. "UART7SEL,UART7 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x1C 20.--21. "UART6SEL,UART6 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x1C 16.--18. "I2S0SEL,I2S0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
bitfld.long 0x1C 12.--14. "SPI3SEL,SPI3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
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bitfld.long 0x1C 9.--11. "SPI2SEL,SPI2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
bitfld.long 0x1C 6.--7. "KPISEL,KPI Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 10 kHz internal low speed RC..,?,?"
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bitfld.long 0x1C 4.--5. "SC2SEL,SC2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
bitfld.long 0x1C 2.--3. "SC1SEL,SC0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x1C 0.--1. "SC0SEL,SC0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?"
line.long 0x20 "CLK_CLKDIV0,Clock Divider Number Register 0"
hexmask.long.byte 0x20 24.--31. 1. "SDH0DIV,SDH0 Clock Divide Number from SDH0 Clock Source"
hexmask.long.byte 0x20 16.--23. 1. "EADC0DIV,EADC0 Clock Divide Number from EADC0 Clock Source"
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hexmask.long.byte 0x20 12.--15. 1. "UART1DIV,UART1 Clock Divide Number from UART1 Clock Source"
hexmask.long.byte 0x20 8.--11. 1. "UART0DIV,UART0 Clock Divide Number from UART0 Clock Source"
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hexmask.long.byte 0x20 4.--7. 1. "USBDIV,USB Clock Divide Number from PLL/2 Clock"
hexmask.long.byte 0x20 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number from HCLK Clock Source"
line.long 0x24 "CLK_CLKDIV1,Clock Divider Number Register 1"
hexmask.long.byte 0x24 24.--31. 1. "PSIODIV,PSIO Clock Divide Number from PSIO Clock Source"
hexmask.long.byte 0x24 16.--23. 1. "SC2DIV,SC2 Clock Divide Number from SC2 Clock Source"
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hexmask.long.byte 0x24 8.--15. 1. "SC1DIV,SC1 Clock Divide Number from SC1 Clock Source"
hexmask.long.byte 0x24 0.--7. 1. "SC0DIV,SC0 Clock Divide Number from SC0 Clock Source"
line.long 0x28 "CLK_CLKDIV2,Clock Divider Number Register 2"
hexmask.long.byte 0x28 24.--31. 1. "EADC1DIV,EADC1 Clock Divide Number from EADC1 Clock Source"
hexmask.long.byte 0x28 8.--15. 1. "KPIDIV,KPI Clock Divide Number from KPI Clock Source"
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hexmask.long.byte 0x28 4.--7. 1. "I2S1DIV,I2S1 Clock Divide Number from I2S1 Clock Source"
hexmask.long.byte 0x28 0.--3. 1. "I2S0DIV,I2S0 Clock Divide Number from I2S0 Clock Source"
line.long 0x2C "CLK_CLKDIV3,Clock Divider Number Register 3"
hexmask.long.byte 0x2C 24.--31. 1. "SDH1DIV,SDH1 Clock Divide Number from SDH1 Clock Source"
hexmask.long.byte 0x2C 8.--15. 1. "VSENSEDIV,Video Pixel Clock Divide Number from CCAP Sensor Clock Source"
line.long 0x30 "CLK_CLKDIV4,Clock Divider Number Register 4"
hexmask.long.byte 0x30 20.--23. 1. "UART7DIV,UART7 Clock Divide Number from UART7 Clock Source"
hexmask.long.byte 0x30 16.--19. 1. "UART6DIV,UART6 Clock Divide Number from UART6 Clock Source"
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hexmask.long.byte 0x30 12.--15. 1. "UART5DIV,UART5 Clock Divide Number from UART5 Clock Source"
hexmask.long.byte 0x30 8.--11. 1. "UART4DIV,UART4 Clock Divide Number from UART4 Clock Source"
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hexmask.long.byte 0x30 4.--7. 1. "UART3DIV,UART3 Clock Divide Number from UART3 Clock Source"
hexmask.long.byte 0x30 0.--3. 1. "UART2DIV,UART2 Clock Divide Number from UART2 Clock Source"
line.long 0x34 "CLK_PCLKDIV,APB Clock Divider Register"
bitfld.long 0x34 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK." "0: PCLK1 frequency is HCLK,1: PCLK1 frequency is HCLK/2,?,?,?,?,?,?"
bitfld.long 0x34 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK." "0: PCLK0 frequency is HCLK,1: PCLK0 frequency is HCLK/2,?,?,?,?,?,?"
line.long 0x38 "CLK_APBCLK2,APB Devices Clock Enable Control Register 2"
bitfld.long 0x38 17. "UART9CKEN,UART9 Clock Enable Bit" "0: UART9 clock Disabled,1: UART9 clock Enabled"
bitfld.long 0x38 16. "UART8CKEN,UART8 Clock Enable Bit" "0: UART8 clock Disabled,1: UART8 clock Enabled"
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bitfld.long 0x38 13. "SPI10CKEN,SPI10 Clock Enable Bit" "0: SPI10 clock Disabled,1: SPI10 clock Enabled"
bitfld.long 0x38 12. "SPI9CKEN,SPI9 Clock Enable Bit" "0: SPI9 clock Disabled,1: SPI9 clock Enabled"
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bitfld.long 0x38 11. "SPI8CKEN,SPI8 Clock Enable Bit" "0: SPI8 clock Disabled,1: SPI8 clock Enabled"
bitfld.long 0x38 10. "SPI7CKEN,SPI7 Clock Enable Bit" "0: SPI7 clock Disabled,1: SPI7 clock Enabled"
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bitfld.long 0x38 9. "SPI6CKEN,SPI6 Clock Enable Bit" "0: SPI6 clock Disabled,1: SPI6 clock Enabled"
bitfld.long 0x38 8. "SPI5CKEN,SPI5 Clock Enable Bit" "0: SPI5 clock Disabled,1: SPI5 clock Enabled"
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bitfld.long 0x38 7. "ACMP23CKEN,Analog Comparator 2/3 Clock Enable Bit" "0: Analog comparator 2/3 clock Disabled,1: Analog comparator 2/3 clock Enabled"
bitfld.long 0x38 6. "EADC2CKEN,EADC2 Clock Enable Bit" "0: EADC2 clock Disabled,1: EADC2 clock Enabled"
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bitfld.long 0x38 0. "KPICKEN,KPI Clock Enable Bit" "0: KPI clock Disabled,1: KPI clock Enabled"
line.long 0x3C "CLK_CLKDIV5,Clock Divider Number Register 5"
hexmask.long.byte 0x3C 24.--31. 1. "EADC2DIV,EADC2 Clock Divide Number from EADC2 Clock Source"
hexmask.long.byte 0x3C 20.--23. 1. "UART9DIV,UART9 Clock Divide Number from UART9 Clock Source"
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hexmask.long.byte 0x3C 16.--19. 1. "UART8DIV,UART8 Clock Divide Number from UART8 Clock Source"
hexmask.long.byte 0x3C 12.--15. 1. "CANFD3DIV,CANFD3 Clock Divide Number from CANFD3 Clock Source"
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hexmask.long.byte 0x3C 8.--11. 1. "CANFD2DIV,CANFD2 Clock Divide Number from CANFD2 Clock Source"
hexmask.long.byte 0x3C 4.--7. 1. "CANFD1DIV,CANFD1 Clock Divide Number from CANFD1 Clock Source"
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hexmask.long.byte 0x3C 0.--3. 1. "CANFD0DIV,CANFD0 Clock Divide Number from CANFD0 Clock Source"
line.long 0x40 "CLK_PLLCTL,PLL Control Register"
bitfld.long 0x40 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL stable time is 1200 PLL source clock..,1: PLL stable time is 2400 PLL source clock.."
bitfld.long 0x40 19. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL source clock from 4~24 MHz external..,1: PLL source clock from 12 MHz internal high-speed.."
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bitfld.long 0x40 18. "OE,PLL FOUT Enable Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
bitfld.long 0x40 17. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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bitfld.long 0x40 16. "PD,Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register  the PLL will enter Power-down mode  too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
bitfld.long 0x40 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
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hexmask.long.byte 0x40 9.--13. 1. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
hexmask.long.word 0x40 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
group.long 0x48++0x7
line.long 0x0 "CLK_PLLFNCTL0,PLLFN Control Register 0"
hexmask.long.word 0x0 16.--27. 1. "FRDIV,PLL Fractional Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
bitfld.long 0x0 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
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hexmask.long.byte 0x0 9.--13. 1. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
hexmask.long.word 0x0 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
line.long 0x4 "CLK_PLLFNCTL1,PLLFN Control Register 1"
bitfld.long 0x4 31. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL source clock from 4~32 MHz external..,1: PLL source clock from 12 MHz internal high-speed.."
bitfld.long 0x4 30. "OE,PLL FOUT Enable Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x4 29. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
bitfld.long 0x4 28. "PD,Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register  the PLL will enter Power-down mode  too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
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bitfld.long 0x4 27. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL stable time is 1200 PLL source clock..,1: PLL stable time is 2400 PLL source clock.."
rgroup.long 0x50++0x3
line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
bitfld.long 0x0 10. "PLLFNSTB,Internal PLLFN Clock Source Stable Flag (Read Only)" "0: Internal PLLFN clock is not stable or disabled,1: Internal PLLFN clock is stable"
bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable  this bit will be set to 0. If switch target clock is not stable  this bit will be set to 1.\nNote: This bit.." "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x0 6. "HIRC48MSTB,HIRC48M Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 12 MHz internal high speed RC oscillator (HIRC)..,1: 12 MHz internal high speed RC oscillator (HIRC).."
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bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0x0 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
bitfld.long 0x0 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
group.long 0x58++0xB
line.long 0x0 "CLK_AHBCLK1,AHB Devices Clock Enable Control Register 1"
bitfld.long 0x0 25. "GPJCKEN,GPIOJ Clock Enable Bit" "0: GPIOJ clock Disabled,1: GPIOJ clock Enabled"
bitfld.long 0x0 24. "GPICKEN,GPIOI Clock Enable Bit" "0: GPIOI clock Disabled,1: GPIOI clock Enabled"
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bitfld.long 0x0 23. "CANFD3CKEN,CANFD3 Clock Enable Bit" "0: CANFD3 clock Disabled,1: CANFD3 clock Enabled"
bitfld.long 0x0 22. "CANFD2CKEN,CANFD2 Clock Enable Bit" "0: CANFD2 clock Disabled,1: CANFD2 clock Enabled"
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bitfld.long 0x0 21. "CANFD1CKEN,CANFD1 Clock Enable Bit" "0: CANFD1 clock Disabled,1: CANFD1 clock Enabled"
bitfld.long 0x0 20. "CANFD0CKEN,CANFD0 Clock Enable Bit" "0: CANFD0 clock Disabled,1: CANFD0 clock Enabled"
line.long 0x4 "CLK_CLKSEL4,Clock Source Select Control Register 4"
bitfld.long 0x4 24.--26. "SPI10SEL,SPI10 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
bitfld.long 0x4 20.--22. "SPI9SEL,SPI9 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
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bitfld.long 0x4 16.--18. "SPI8SEL,SPI8 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
bitfld.long 0x4 12.--14. "SPI7SEL,SPI7 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
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bitfld.long 0x4 8.--10. "SPI6SEL,SPI6 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
bitfld.long 0x4 4.--6. "SPI5SEL,SPI5 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
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bitfld.long 0x4 0.--2. "SPI4SEL,SPI4 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2,?,?,?,?,?,?"
line.long 0x8 "CLK_CLKOCTL,Clock Output Control Register"
bitfld.long 0x8 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz frequency..,1: 1 Hz clock output for 32.768 kHz frequency.."
bitfld.long 0x8 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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bitfld.long 0x8 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
hexmask.long.byte 0x8 0.--3. 1. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]."
group.long 0x70++0x13
line.long 0x0 "CLK_CLKDCTL,Clock Fail Detector Control Register"
bitfld.long 0x0 18. "HXTFQASW,HXT Clock Frequency Range Detector Event Auto Switch Enable Bit\nNote: This bit should be set before HXTFQDEN(CLK_CLKDCTL[16])." "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Range Detector Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Range Detector Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
bitfld.long 0x0 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
line.long 0x4 "CLK_CLKDSTS,Clock Fail Detector Status Register"
bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote 1: Write 1 to clear the bit to 0.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: Write 1 to clear the bit to 0"
bitfld.long 0x4 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote 1: Write 1 to clear the bit to 0. \nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal oscillator..,1: Write 1 to clear the bit to 0"
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bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote 1: Write 1 to clear the bit to 0.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: Write 1 to clear the bit to 0"
line.long 0x8 "CLK_CDUPB,Clock Frequency Range Detector Upper Boundary Register"
hexmask.long.word 0x8 0.--9. 1. "UPERBD,HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value  the HXT Clock Frequency Range Detector Interrupt Flag will.."
line.long 0xC "CLK_CDLOWB,Clock Frequency Range Detector Lower Boundary Register"
hexmask.long.word 0xC 0.--9. 1. "LOWERBD,HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value  the HXT Clock Frequency Range Detector Interrupt Flag will.."
line.long 0x10 "CLK_STOPREQ,Clock Stop Request Register"
bitfld.long 0x10 3. "CANFD3STR,CANFD3 Clock Stop Request\nThis bit is used to stop CANFD3 clock." "0: CANFD3 clock is not stopped by this bit. (default),1: Set this bit and check the.."
bitfld.long 0x10 2. "CANFD2STR,CANFD2 Clock Stop Request\nThis bit is used to stop CANFD2 clock." "0: CANFD2 clock is not stopped by this bit. (default),1: Set this bit and check the.."
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bitfld.long 0x10 1. "CANFD1STR,CANFD1 Clock Stop Request\nThis bit is used to stop CANFD1 clock." "0: CANFD1 clock is not stopped by this bit. (default),1: Set this bit and check the.."
bitfld.long 0x10 0. "CANFD0STR,CANFD0 Clock Stop Request\nThis bit is used to stop CANFD0 clock." "0: CANFD0 clock is not stopped by this bit. (default),1: Set this bit and check the.."
rgroup.long 0x84++0x3
line.long 0x0 "CLK_STOPACK,Clock Stop Acknowledge Register"
bitfld.long 0x0 3. "CANFD3STA,CANFD3 Clock Stop Acknowledge (Read Only)\nThis bit is used to check CANFD3 clock stop by setting CANFD3STR(CLK_STOPREQ[3])." "0: CANFD3 clock not stopped,1: CANFD3 clock stopped"
bitfld.long 0x0 2. "CANFD2STA,CANFD2 Clock Stop Acknowledge (Read Only)\nThis bit is used to check CANFD2 clock stop by setting CANFD2STR(CLK_STOPREQ[2])." "0: CANFD2 clock not stopped,1: CANFD2 clock stopped"
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bitfld.long 0x0 1. "CANFD1STA,CANFD1 Clock Stop Acknowledge (Read Only)\nThis bit is used to check CANFD1 clock stop by setting CANFD1STR(CLK_STOPREQ[1])." "0: CANFD1 clock not stopped,1: CANFD1 clock stopped"
bitfld.long 0x0 0. "CANFD0STA,CANFD0 Clock Stop Acknowledge (Read Only)\nThis bit is used to check CANFD0 clock stop by setting CANFD0STR(CLK_STOPREQ[0])." "0: CANFD0 clock not stopped,1: CANFD0 clock stopped"
group.long 0x90++0x7
line.long 0x0 "CLK_PMUCTL,Power Manager Control Register"
bitfld.long 0x0 30.--31. "WKPINEN4,Wake-up Pin4 Enable Bit (Write Protect)\nThis is control register for GPF.6 to wake-up pin.\nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: Setting IOCTLSEL(RTC_LXTCTL[8]) to avoid GPF.6 unexpected falling.." "0: Wake-up pin disabled at Deep Power-down mode,1: These bits are write protected,2: Setting IOCTLSEL,?"
bitfld.long 0x0 28.--29. "WKPINEN3,Wake-up Pin3 Enable Bit (Write Protect)\nThis is control register for GPB.12 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disabled at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x0 26.--27. "WKPINEN2,Wake-up Pin2 Enable Bit (Write Protect)\nThis is control register for GPB.2 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disabled at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
bitfld.long 0x0 24.--25. "WKPINEN1,Wake-up Pin1 Enable Bit (Write Protect)\nThis is control register for GPB.0 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disabled at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x0 23. "RTCWKEN,RTC Wake-up Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: RTC wake-up disabled at Deep Power-down mode or..,1: RTC wake-up enabled at Deep Power-down mode or.."
bitfld.long 0x0 22. "VBUSWKEN,VBUS Wake-up Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: VBUS transition wake-up disabled at Deep..,1: VBUS transition wake-up enabled at Deep.."
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bitfld.long 0x0 18. "ACMPSPWK,ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: Set FILTSEL(ACMP_CTLx[15:13]) for comparator output filter count selection  the filter clock is.." "0: ACMP wake-up disabled at Standby Power-down mode,1: This bit is write protected"
bitfld.long 0x0 16.--17. "WKPINEN0,Wake-up Pin0 Enable Bit (Write Protect)\nThis is control register for GPC.0 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disabled at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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hexmask.long.byte 0x0 9.--12. 1. "WKTMRIS,Wake-up Timer Time-out Interval Select (Write Protect)\nThese bits control wake-up timer time-out interval when chip at DPD/SPD mode.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
bitfld.long 0x0 8. "WKTMREN,Wake-up Timer Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Wake-up timer disabled at DPD/SPD mode,1: Wake-up timer enabled at DPD/SPD mode"
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bitfld.long 0x0 4.--6. "SRETSEL,SRAM Retention Range Select Bit (Write Protect)\nSelect SRAM retention range when chip enter SPD mode.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: No SRAM retention,1: 16K SRAM retention when chip enter SPD mode,?,?,?,?,?,?"
bitfld.long 0x0 3. "DPDHOLDEN,Deep-Power-Down Mode GPIO Hold Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: When GPIO enters deep power-down mode all I/O..,1: When GPIO enters deep power-down mode all I/O.."
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bitfld.long 0x0 0.--2. "PDMSEL,Power-down Mode Selection (Write Protect)\nThese bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Normal Power-down mode is selected (NPD),1: Low leakage Power-down mode is selected (LLPD),?,?,?,?,?,?"
line.long 0x4 "CLK_PMUSTS,Power Manager Status Register"
bitfld.long 0x4 31. "CLRWK,Clear Wake-up Flag\nNote: This bit is auto cleared by hardware." "0: No clear,1: Clear all wake-up flag"
rbitfld.long 0x4 19. "ACMPWK3,ACMP3 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP3 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode." "0,1"
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rbitfld.long 0x4 18. "ACMPWK2,ACMP2 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP2 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode." "0,1"
rbitfld.long 0x4 17. "ACMPWK1,ACMP1 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP1 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode." "0,1"
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rbitfld.long 0x4 16. "ACMPWK0,ACMP0 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP0 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode." "0,1"
rbitfld.long 0x4 15. "RSTWK,RST pin Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RST pin trigger happened. \nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 13. "BODWK,BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode." "0,1"
rbitfld.long 0x4 12. "LVRWK,LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode." "0,1"
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rbitfld.long 0x4 11. "GPDWK,GPD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
rbitfld.long 0x4 10. "GPCWK,GPC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
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rbitfld.long 0x4 9. "GPBWK,GPB Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD.." "0,1"
rbitfld.long 0x4 8. "GPAWK,GPA Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
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rbitfld.long 0x4 7. "VBUSWK,VBUS Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.12). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode." "0,1"
rbitfld.long 0x4 6. "PINWK4,Pin4 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode." "0,1"
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rbitfld.long 0x4 5. "PINWK3,Pin3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode." "0,1"
rbitfld.long 0x4 4. "PINWK2,Pin2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode." "0,1"
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rbitfld.long 0x4 3. "PINWK1,Pin1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode." "0,1"
rbitfld.long 0x4 2. "RTCWK,RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm  tick time or tamper happened. \nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 1. "TMRWK,Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31].." "0,1"
rbitfld.long 0x4 0. "PINWK0,Pin0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode." "0,1"
group.long 0x9C++0x17
line.long 0x0 "CLK_SWKDBCTL,GPIO Standby Power-down Wake-up De-bounce Control Register"
hexmask.long.byte 0x0 0.--3. 1. "SWKDBCLKSEL,Standby Power-down Wake-up De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC)."
line.long 0x4 "CLK_PASWKCTL,GPA Standby Power-down Wake-up Control Register"
bitfld.long 0x4 8. "DBEN,GPA Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal transition is seen.." "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
hexmask.long.byte 0x4 4.--7. 1. "WKPSEL,GPA Standby Power-down Wake-up Pin Select"
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bitfld.long 0x4 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPA group pin falling edge wake-up function..,1: GPA group pin falling edge wake-up function.."
bitfld.long 0x4 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPA group pin rising edge wake-up function..,1: GPA group pin rising edge wake-up function Enabled"
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bitfld.long 0x4 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPA group pin wake-up function Disabled,1: GPA group pin wake-up function Enabled"
line.long 0x8 "CLK_PBSWKCTL,GPB Standby Power-down Wake-up Control Register"
bitfld.long 0x8 8. "DBEN,GPB Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal transition is seen.." "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
hexmask.long.byte 0x8 4.--7. 1. "WKPSEL,GPB Standby Power-down Wake-up Pin Select"
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bitfld.long 0x8 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPB group pin falling edge wake-up function..,1: GPB group pin falling edge wake-up function.."
bitfld.long 0x8 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPB group pin rising edge wake-up function..,1: GPB group pin rising edge wake-up function Enabled"
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bitfld.long 0x8 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPB group pin wake-up function Disabled,1: GPB group pin wake-up function Enabled"
line.long 0xC "CLK_PCSWKCTL,GPC Standby Power-down Wake-up Control Register"
bitfld.long 0xC 8. "DBEN,GPC Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal transition is seen.." "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
hexmask.long.byte 0xC 4.--7. 1. "WKPSEL,GPC Standby Power-down Wake-up Pin Select"
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bitfld.long 0xC 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPC group pin falling edge wake-up function..,1: GPC group pin falling edge wake-up function.."
bitfld.long 0xC 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPC group pin rising edge wake-up function..,1: GPC group pin rising edge wake-up function Enabled"
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bitfld.long 0xC 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPC group pin wake-up function Disabled,1: GPC group pin wake-up function Enabled"
line.long 0x10 "CLK_PDSWKCTL,GPD Standby Power-down Wake-up Control Register"
bitfld.long 0x10 8. "DBEN,GPD Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal transition is seen.." "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
hexmask.long.byte 0x10 4.--7. 1. "WKPSEL,GPD Standby Power-down Wake-up Pin Select"
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bitfld.long 0x10 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPD group pin falling edge wake-up function..,1: GPD group pin falling edge wake-up function.."
bitfld.long 0x10 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPD group pin rising edge wake-up function..,1: GPD group pin rising edge wake-up function Enabled"
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bitfld.long 0x10 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPD group pin wake-up function Disabled,1: GPD group pin wake-up function Enabled"
line.long 0x14 "CLK_IOPDCTL,GPIO Standby Power-down Control Register"
bitfld.long 0x14 0. "IOHR,GPIO Hold Release\nWhen GPIO enters deep power-down mode or standby power-down mode  all I/O status are hold to keep normal operating status. After chip is woken up from deep power-down mode or standby power-down mode  the I/O are still keep hold.." "0,1"
tree.end
tree "CRC (Cyclic Redundancy Check)"
base ad:0x40031000
group.long 0x0++0xB
line.long 0x0 "CRC_CTL,CRC Control Register"
bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode. \nNote: User must program the polynomial value in CRC_POLYNOMIAL register to specify the polynomial used for CRC calculation." "0: CRC-16 Polynomial mode,1: CRC-8 Polynomial mode,?,?"
bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode  the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode  the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode,?,?"
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bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register." "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register." "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
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bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E  the bit order reverse for CRC checksum is 0x74F0DEBB." "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD  the bit order reverse for CRC write data in is 0x55DD33BB." "0: Bit order reversed for CRC write data in Disabled,1: Bit order reversed for CRC write data in Enabled.."
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bitfld.long 0x0 1. "CHKSINIT,Checksum Initialization (Write Only)\nNote: This bit will be cleared automatically." "0: No effect,1: Initial checksum value by auto reload CRC_SEED.."
bitfld.long 0x0 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
line.long 0x4 "CRC_DAT,CRC Write Data Register"
hexmask.long 0x4 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode  the valid data in CRC_DAT register is only DATA[7:0] bits; if.."
line.long 0x8 "CRC_SEED,CRC Seed Register"
hexmask.long 0x8 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after performing CHKSINIT (CRC_CTL[1])."
rgroup.long 0xC++0x3
line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register"
hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result."
group.long 0x10++0x3
line.long 0x0 "CRC_POLYNOMIAL,CRC Polynomial Register"
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC Polynomial Value\nThis field indicates the value of CRC polynomial."
tree.end
tree "CRYPTO (Cryptographic Accelerator)"
base ad:0x0
tree "AES"
base ad:0x40032050
rgroup.long 0x0++0xF
line.long 0x0 "CRYPTO_AES_FDBCK0,AES Engine Output Feedback Data After Cryptographic Operation"
hexmask.long 0x0 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
line.long 0x4 "CRYPTO_AES_FDBCK1,AES Engine Output Feedback Data After Cryptographic Operation"
hexmask.long 0x4 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
line.long 0x8 "CRYPTO_AES_FDBCK2,AES Engine Output Feedback Data After Cryptographic Operation"
hexmask.long 0x8 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
line.long 0xC "CRYPTO_AES_FDBCK3,AES Engine Output Feedback Data After Cryptographic Operation"
hexmask.long 0xC 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
group.long 0x30++0x17
line.long 0x0 "CRYPTO_AES_GCM_IVCNT0,AES GCM IV Byte Count Register 0"
hexmask.long 0x0 0.--31. 1. "CNT,AES GCM IV Byte Count\nThe bit length of IV is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_IVCNT0 keeps the low weight byte count of initial vector (i.e.  len(IV)[34:3]) of AES GCM mode and can be read and written."
line.long 0x4 "CRYPTO_AES_GCM_IVCNT1,AES GCM IV Byte Count Register 1"
hexmask.long 0x4 0.--28. 1. "CNT,AES GCM IV Byte Count\nThe bit length of IV is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_IVCNT1 keeps the high weight byte count of initial vector (i.e.  len(IV)[64:35]) of AES GCM mode and can be read and written."
line.long 0x8 "CRYPTO_AES_GCM_ACNT0,AES GCM A Byte Count Register 0"
hexmask.long 0x8 0.--31. 1. "CNT,AES GCM a Byte Count\nThe bit length of A is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_ACNT0 keeps the low weight byte count of the additional authenticated data (i.e.  len(A)[34:3]) of AES GCM mode and can be read and written."
line.long 0xC "CRYPTO_AES_GCM_ACNT1,AES GCM A Byte Count Register 1"
hexmask.long 0xC 0.--28. 1. "CNT,AES GCM a Byte Count\nThe bit length of A is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_ACNT0 keeps the high weight byte count of the additional authenticated data (i.e.  len(A)[63:35]) of AES GCM mode and can be read and written."
line.long 0x10 "CRYPTO_AES_GCM_PCNT0,AES GCM P Byte Count Register 0"
hexmask.long 0x10 0.--31. 1. "CNT,AES GCM P Byte Count\nThe bit length of Por C is 39 bits for AES GCM mode. The CRYPTO_AES_GCM_PCNT0 keeps the low weight byte count of the plaintext or ciphertext (i.e.  len(P)[34:3] or len(C)[34:3]) of AES GCM mode and can be read and written."
line.long 0x14 "CRYPTO_AES_GCM_PCNT1,AES GCM P Byte Count Register 1"
hexmask.long 0x14 0.--28. 1. "CNT,AES GCM P Byte Count\nThe bit length of Por C is 39 bits for AES GCM mode. The CRYPTO_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e.  len(P)[38:35] or len(C)[38:35]) of AES GCM mode and can be read and.."
group.long 0x50++0x3
line.long 0x0 "CRYPTO_AES_FBADDR,AES DMA Feedback Address Register"
hexmask.long 0x0 0.--31. 1. "FBADDR,AES DMA Feedback Address\nIn DMA cascade mode  software can update DMA feedback address register for automatically reading and writing feedback values via DMA. The FBADDR keeps the feedback address of the feedback data for the next cascade.."
group.long 0xB0++0x3
line.long 0x0 "CRYPTO_AES_CTL,AES Control Register"
bitfld.long 0x0 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT." "0: No effect,1: Protect the content of the AES key from reading."
hexmask.long.byte 0x0 26.--30. 1. "KEYUNPRT,Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating  BUSY flag is 1  there would be no effect.."
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bitfld.long 0x0 25. "KINSWAP,AES Engine Input Key and Initial Vector Swap" "0: Keep the original order,1: The order that CPU feeds key and initial vector.."
bitfld.long 0x0 24. "KOUTSWAP,AES Engine Output Key  Initial Vector and Feedback Swap" "0: Keep the original order,1: The order that CPU reads key initial vector and.."
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bitfld.long 0x0 23. "INSWAP,AES Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the accelerator.."
bitfld.long 0x0 22. "OUTSWAP,AES Engine Output Data Swap" "0: Keep the original order,1: The order that CPU reads data from the.."
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bitfld.long 0x0 21. "FBOUT,Feedback Output From AES Via DMA Automatically" "0: DMA automatic feedback output function Disabled,1: DMA automatic feedback output function Enabled.."
bitfld.long 0x0 20. "FBIN,Feedback Input to AES Via DMA Automatically" "0: DMA automatic feedback input function Disabled,1: DMA automatic feedback input function Enabled.."
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bitfld.long 0x0 16. "ENCRYPTO,AES Encryption/Decryption" "0: AES engine executes decryption operation,1: AES engine executes encryption operation"
hexmask.long.byte 0x0 8.--15. 1. "OPMODE,AES Engine Operation Modes"
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bitfld.long 0x0 7. "DMAEN,AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode  and data movement from/to the engine is done by DMA logic." "0: AES DMA engine Disabled,1: AES_DMA engine Enabled"
bitfld.long 0x0 6. "DMACSCAD,AES Engine DMA with Cascade Mode\nNote: The last two blocks of AES-CBC-CS1/2/3 must be in the last cascade operation." "0: DMA cascade function Disabled,1: In DMA cascade mode software can update DMA.."
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bitfld.long 0x0 5. "DMALAST,AES Last Block\nIn DMA mode  this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode  this bit must be set when feeding in the last block of data in ECB  CBC  CTR  OFB  and CFB mode  and feeding in the (last-1) block of.." "0,1"
bitfld.long 0x0 2.--3. "KEYSZ,AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1  updating this register has no effect." "0,1,2,3"
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bitfld.long 0x0 1. "STOP,AES Engine Stop\nNote: This bit is always 0 when it is read back." "0: No effect,1: Stop AES engine"
bitfld.long 0x0 0. "START,AES Engine Start\nNote: This bit is always 0 when it is read back." "0: No effect,1: Start AES engine. BUSY flag will be set"
rgroup.long 0xB4++0x3
line.long 0x0 "CRYPTO_AES_STS,AES Engine Flag"
bitfld.long 0x0 21. "KSERR,AES Engine Access Key Store Error Flag" "0: No error,1: Key store access error will stop AES engine"
bitfld.long 0x0 20. "BUSERR,AES DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and AES engine"
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bitfld.long 0x0 18. "OUTBUFERR,AES Out Buffer Error Flag" "0: No error,1: Error happened during getting the result from.."
bitfld.long 0x0 17. "OUTBUFFULL,AES Out Buffer Full Flag" "0: AES output buffer is not full,1: AES output buffer is full and software needs to.."
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bitfld.long 0x0 16. "OUTBUFEMPTY,AES Out Buffer Empty" "0: AES output buffer is not empty. There are some..,1: AES output buffer is empty. Software cannot get.."
bitfld.long 0x0 12. "CNTERR,CRYPTO_AES_CNT Setting Error" "0: No error in CRYPTO_AES_CNT setting,1: CRYPTO_AES_CNT is 0 if DMAEN (CRYPTO_AES_CTL[7]).."
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bitfld.long 0x0 10. "INBUFERR,AES Input Buffer Error Flag" "0: No error,1: Error happened during feeding data to the AES.."
bitfld.long 0x0 9. "INBUFFULL,AES Input Buffer Full Flag" "0: AES input buffer is not full. Software can feed..,1: AES input buffer is full. Software cannot feed.."
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bitfld.long 0x0 8. "INBUFEMPTY,AES Input Buffer Empty" "0: There are some data in input buffer waiting for..,1: AES input buffer is empty. Software needs to.."
bitfld.long 0x0 0. "BUSY,AES Engine Busy" "0: The AES engine is idle or finished,1: The AES engine is under processing"
group.long 0xB8++0x3
line.long 0x0 "CRYPTO_AES_DATIN,AES Engine Data Input Port Register"
hexmask.long 0x0 0.--31. 1. "DATIN,AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0."
rgroup.long 0xBC++0x3
line.long 0x0 "CRYPTO_AES_DATOUT,AES Engine Data Output Port Register"
hexmask.long 0x0 0.--31. 1. "DATOUT,AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0."
group.long 0xC0++0x3B
line.long 0x0 "CRYPTO_AES_KEY0,AES Key Word 0 Register"
hexmask.long 0x0 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x4 "CRYPTO_AES_KEY1,AES Key Word 1 Register"
hexmask.long 0x4 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x8 "CRYPTO_AES_KEY2,AES Key Word 2 Register"
hexmask.long 0x8 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0xC "CRYPTO_AES_KEY3,AES Key Word 3 Register"
hexmask.long 0xC 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x10 "CRYPTO_AES_KEY4,AES Key Word 4 Register"
hexmask.long 0x10 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x14 "CRYPTO_AES_KEY5,AES Key Word 5 Register"
hexmask.long 0x14 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x18 "CRYPTO_AES_KEY6,AES Key Word 6 Register"
hexmask.long 0x18 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x1C "CRYPTO_AES_KEY7,AES Key Word 7 Register"
hexmask.long 0x1C 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128  192  or 256 bits and four  six  or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3  CRYPTO_AES_KEY2 .."
line.long 0x20 "CRYPTO_AES_IV0,AES Initial Vector Word 0 Register"
hexmask.long 0x20 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) are for AES operating in CBC  CFB  and OFB mode. Four registers (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) act as.."
line.long 0x24 "CRYPTO_AES_IV1,AES Initial Vector Word 1 Register"
hexmask.long 0x24 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) are for AES operating in CBC  CFB  and OFB mode. Four registers (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) act as.."
line.long 0x28 "CRYPTO_AES_IV2,AES Initial Vector Word 2 Register"
hexmask.long 0x28 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) are for AES operating in CBC  CFB  and OFB mode. Four registers (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) act as.."
line.long 0x2C "CRYPTO_AES_IV3,AES Initial Vector Word 3 Register"
hexmask.long 0x2C 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) are for AES operating in CBC  CFB  and OFB mode. Four registers (CRYPTO_AES_IV0  CRYPTO_AES_IV1  CRYPTO_AES_IV2  and CRYPTO_AES_IV3) act as.."
line.long 0x30 "CRYPTO_AES_SADDR,AES DMA Source Address Register"
hexmask.long 0x30 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source.."
line.long 0x34 "CRYPTO_AES_DADDR,AES DMA Destination Address Register"
hexmask.long 0x34 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be.."
line.long 0x38 "CRYPTO_AES_CNT,AES Byte Count Register"
hexmask.long 0x38 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AES_CNT can be read and written. Writing to.."
wgroup.long 0xEC0++0x3
line.long 0x0 "CRYPTO_AES_KSCTL,AES Key Control Register"
bitfld.long 0x0 6.--7. "RSSRC,Read Key Store Source" "0: Key is read from the SRAM of key store,1: Key is read from the Flash of key store,?,?"
bitfld.long 0x0 5. "RSRC,Read Key Source" "0: Key is read from registers CRYPTO_AESx_KEYx,1: Key is read from key store"
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hexmask.long.byte 0x0 0.--4. 1. "NUM,Read Key Number\nThe key number is sent to key store"
tree.end
tree "CRYPTO"
base ad:0x40032000
group.long 0x0++0x7
line.long 0x0 "CRYPTO_INTEN,Crypto Interrupt Enable Control Register"
bitfld.long 0x0 31. "RSAEIEN,RSA Error Interrupt Enable Bit" "0: RSA error interrupt flag Disabled,1: RSA error interrupt flag Enabled"
bitfld.long 0x0 30. "RSAIEN,RSA Interrupt Enable Bit" "0: RSA interrupt Disabled,1: RSA interrupt Enabled"
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bitfld.long 0x0 25. "HMACEIEN,SHA/HMAC Error Interrupt Enable Bit" "0: SHA/HMAC error interrupt flag Disabled,1: HMAC error interrupt flag Enabled"
bitfld.long 0x0 24. "HMACIEN,SHA/HMAC Interrupt Enable Bit\nNote: In DMA mode  an interrupt will be triggered when an amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine. In Non-DMA mode  an interrupt will be triggered when the SHA/HMAC engine finishes the.." "0: SHA/HMAC interrupt Disabled,1: SHA/HMAC interrupt Enabled"
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bitfld.long 0x0 23. "ECCEIEN,ECC Error Interrupt Enable Bit" "0: ECC error interrupt flag Disabled,1: ECC error interrupt flag Enabled"
bitfld.long 0x0 22. "ECCIEN,ECC Interrupt Enable Bit\nNote: In DMA mode  an interrupt will be triggered when an amount of data set in ECC_DMA_CNT is fed into the ECC engine. In Non-DMA mode  an interrupt will be triggered when the ECC engine finishes the operation." "0: ECC interrupt Disabled,1: ECC interrupt Enabled"
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bitfld.long 0x0 17. "PRNGEIEN,PRNG Error Flag Enable Bit" "0: PRNG error interrupt flag Disabled,1: PRNG error interrupt flag Enabled"
bitfld.long 0x0 16. "PRNGIEN,PRNG Interrupt Enable Bit" "0: PRNG interrupt Disabled,1: PRNG interrupt Enabled"
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bitfld.long 0x0 1. "AESEIEN,AES Error Flag Enable Bit" "0: AES error interrupt flag Disabled,1: AES error interrupt flag Enabled"
bitfld.long 0x0 0. "AESIEN,AES Interrupt Enable Bit\nNote: In DMA mode  an interrupt will be triggered when an amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode  an interrupt will be triggered when the AES engine finishes the operation." "0: AES interrupt Disabled,1: AES interrupt Enabled"
line.long 0x4 "CRYPTO_INTSTS,Crypto Interrupt Flag"
bitfld.long 0x4 31. "RSAEIF,RSA Error Interrupt Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_RSA_STS register.\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No RSA error,1: RSA error interrupt"
bitfld.long 0x4 30. "RSAIF,RSA Finish Interrupt Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No RSA interrupt,1: RSA operation done interrupt"
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bitfld.long 0x4 25. "HMACEIF,SHA/HMAC Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_HMAC_STS register.\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No SHA/HMAC error,1: SHA/HMAC error interrupt"
bitfld.long 0x4 24. "HMACIF,SHA/HMAC Finish Interrupt Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No SHA/HMAC interrupt,1: SHA/HMAC operation done interrupt"
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bitfld.long 0x4 23. "ECCEIF,ECC Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_ECC_STS register.\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No ECC error,1: ECC error interrupt"
bitfld.long 0x4 22. "ECCIF,ECC Finish Interrupt Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No ECC interrupt,1: ECC operation done interrupt"
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bitfld.long 0x4 17. "PRNGEIF,PRNG Error Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No PRNG error,1: PRNG key generation error interrupt"
bitfld.long 0x4 16. "PRNGIF,PRNG Finish Interrupt Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No PRNG interrupt,1: PRNG key generation done interrupt"
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bitfld.long 0x4 1. "AESEIF,AES Error Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No AES error,1: AES encryption/decryption error interrupt"
bitfld.long 0x4 0. "AESIF,AES Finish Interrupt Flag\nNote: This bit is cleared by writing 1  and it has no effect by writing 0." "0: No AES interrupt,1: AES encryption/decryption done interrupt"
tree.end
tree "ECC"
base ad:0x40032800
group.long 0x0++0x3
line.long 0x0 "CRYPTO_ECC_CTL,ECC Control Register"
hexmask.long.word 0x0 22.--31. 1. "CURVEM,The key length of elliptic curve."
bitfld.long 0x0 21. "LDK,The Control Signal of Register for SCALARK" "0: The register for SCALARK is not modified by DMA..,1: The register for SCALARK is modified by DMA or.."
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bitfld.long 0x0 20. "LDN,The Control Signal of Register for the Parameter CURVEN of Elliptic Curve" "0: The register for CURVEN is not modified by DMA..,1: The register for CURVEN is modified by DMA or user"
bitfld.long 0x0 19. "LDB,The Control Signal of Register for the Parameter CURVEB of Elliptic Curve" "0: The register for CURVEB is not modified by DMA..,1: The register for CURVEB is modified by DMA or user"
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bitfld.long 0x0 18. "LDA,The Control Signal of Register for the Parameter CURVEA of Elliptic Curve" "0: The register for CURVEA is not modified by DMA..,1: The register for CURVEA is modified by DMA or user"
bitfld.long 0x0 17. "LDP2,The Control Signal of Register POINTX2 and POINTY2 for the x and Y Coordinate of the Second Point" "0: The register for POINTX2 and POINTY2 is not..,1: The register for POINTX2 and POINTY2 is modified.."
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bitfld.long 0x0 16. "LDP1,The Control Signal of Register POINTX1 and POINTY1 for the x and Y Coordinate of the First Point" "0: The register for POINTX1 and POINTY1 is not..,1: The register for POINTX1 and POINTY1 is modified.."
bitfld.long 0x0 14. "SCAP,Side-channel Attack Protection" "0: Full speed without side-channel protection,1: Less speed with side-channel protection"
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bitfld.long 0x0 13. "CSEL,Curve Selection" "0: NIST suggested curve,1: Montgomery curve"
bitfld.long 0x0 11.--12. "MODOP,Modulus Operation for PF" "0: Division:,1: Multiplication:,?,?"
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bitfld.long 0x0 9.--10. "ECCOP,Point Operation for BF and PF\nBesides above three input data  point operations still need the parameters of elliptic curve (CURVEA  CURVEB  CURVEN and CURVEM) as shown in Figure 6.27-11." "0: Point multiplication:,1: Modulus operation: choose by MODOP..,?,?"
bitfld.long 0x0 8. "FSEL,Field Selection" "0: Binary Field (GF(2m )),1: Prime Field (GF(p))"
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bitfld.long 0x0 7. "DMAEN,ECC Accelerator DMA Enable Bit\nOnly when START and DMAEN are 1  ECC DMA engine will be active." "0: ECC DMA engine Disabled,1: ECC DMA engine Enabled"
bitfld.long 0x0 6. "DFAP,Differential Fault Attack Protection" "0: Differential fault attack protection Disabled,1: Differential fault attack protection Enabled"
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bitfld.long 0x0 5. "ECDSAR,Generate R in ECDSA Signature Generation" "0: No effect,1: Formula for generating R"
bitfld.long 0x0 4. "ECDSAS,Generate S in ECDSA Signature Generation" "0: No effect,1: Formula for generating S"
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bitfld.long 0x0 1. "STOP,ECC Accelerator Stop\nThis bit is always 0 when it is read back.\nRemember to clear ECC interrupt flag after stopping ECC accelerator." "0: No effect,1: Abort ECC accelerator and make it into idle state"
bitfld.long 0x0 0. "START,ECC Accelerator Start\nThis bit is always 0 when it is read back.\nECC accelerator will ignore this START signal when BUSY flag is 1." "0: No effect,1: Start ECC accelerator. BUSY flag will be set"
rgroup.long 0x4++0x3
line.long 0x0 "CRYPTO_ECC_STS,ECC Status Register"
bitfld.long 0x0 18. "DFAERR,ECC Engine Differential Fault Attack Error Flag" "0: No error,1: Differential Fault Attack happened in ECC.."
bitfld.long 0x0 17. "KSERR,ECC Engine Access Key Store Error Flag" "0: No error,1: Access error will stop ECC engine"
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bitfld.long 0x0 16. "BUSERR,ECC DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and ECC.."
bitfld.long 0x0 1. "DMABUSY,ECC DMA Busy Flag" "0: ECC DMA is idle or finished,1: ECC DMA is busy"
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bitfld.long 0x0 0. "BUSY,ECC Accelerator Busy Flag\nNote: Remember to clear ECC interrupt flag after ECC accelerator is finished" "0: The ECC accelerator is idle or finished,1: The ECC accelerator is under processing and.."
group.long 0x8++0x1F7
line.long 0x0 "CRYPTO_ECC_X1_00,ECC the X-coordinate Word0 of the First Point"
hexmask.long 0x0 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x4 "CRYPTO_ECC_X1_01,ECC the X-coordinate Word1 of the First Point"
hexmask.long 0x4 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x8 "CRYPTO_ECC_X1_02,ECC the X-coordinate Word2 of the First Point"
hexmask.long 0x8 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0xC "CRYPTO_ECC_X1_03,ECC the X-coordinate Word3 of the First Point"
hexmask.long 0xC 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x10 "CRYPTO_ECC_X1_04,ECC the X-coordinate Word4 of the First Point"
hexmask.long 0x10 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x14 "CRYPTO_ECC_X1_05,ECC the X-coordinate Word5 of the First Point"
hexmask.long 0x14 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x18 "CRYPTO_ECC_X1_06,ECC the X-coordinate Word6 of the First Point"
hexmask.long 0x18 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x1C "CRYPTO_ECC_X1_07,ECC the X-coordinate Word7 of the First Point"
hexmask.long 0x1C 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x20 "CRYPTO_ECC_X1_08,ECC the X-coordinate Word8 of the First Point"
hexmask.long 0x20 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x24 "CRYPTO_ECC_X1_09,ECC the X-coordinate Word9 of the First Point"
hexmask.long 0x24 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x28 "CRYPTO_ECC_X1_10,ECC the X-coordinate Word10 of the First Point"
hexmask.long 0x28 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x2C "CRYPTO_ECC_X1_11,ECC the X-coordinate Word11 of the First Point"
hexmask.long 0x2C 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x30 "CRYPTO_ECC_X1_12,ECC the X-coordinate Word12 of the First Point"
hexmask.long 0x30 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x34 "CRYPTO_ECC_X1_13,ECC the X-coordinate Word13 of the First Point"
hexmask.long 0x34 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x38 "CRYPTO_ECC_X1_14,ECC the X-coordinate Word14 of the First Point"
hexmask.long 0x38 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x3C "CRYPTO_ECC_X1_15,ECC the X-coordinate Word15 of the First Point"
hexmask.long 0x3C 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x40 "CRYPTO_ECC_X1_16,ECC the X-coordinate Word16 of the First Point"
hexmask.long 0x40 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x44 "CRYPTO_ECC_X1_17,ECC the X-coordinate Word17 of the First Point"
hexmask.long 0x44 0.--31. 1. "POINTX1,ECC the X-coordinate Value of the First Point \nFor B-163 or K-163  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233  POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283  POINTX1 is stored in.."
line.long 0x48 "CRYPTO_ECC_Y1_00,ECC the Y-coordinate Word0 of the First Point"
hexmask.long 0x48 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x4C "CRYPTO_ECC_Y1_01,ECC the Y-coordinate Word1 of the First Point"
hexmask.long 0x4C 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x50 "CRYPTO_ECC_Y1_02,ECC the Y-coordinate Word2 of the First Point"
hexmask.long 0x50 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x54 "CRYPTO_ECC_Y1_03,ECC the Y-coordinate Word3 of the First Point"
hexmask.long 0x54 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x58 "CRYPTO_ECC_Y1_04,ECC the Y-coordinate Word4 of the First Point"
hexmask.long 0x58 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x5C "CRYPTO_ECC_Y1_05,ECC the Y-coordinate Word5 of the First Point"
hexmask.long 0x5C 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x60 "CRYPTO_ECC_Y1_06,ECC the Y-coordinate Word6 of the First Point"
hexmask.long 0x60 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x64 "CRYPTO_ECC_Y1_07,ECC the Y-coordinate Word7 of the First Point"
hexmask.long 0x64 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x68 "CRYPTO_ECC_Y1_08,ECC the Y-coordinate Word8 of the First Point"
hexmask.long 0x68 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x6C "CRYPTO_ECC_Y1_09,ECC the Y-coordinate Word9 of the First Point"
hexmask.long 0x6C 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x70 "CRYPTO_ECC_Y1_10,ECC the Y-coordinate Word10 of the First Point"
hexmask.long 0x70 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x74 "CRYPTO_ECC_Y1_11,ECC the Y-coordinate Word11 of the First Point"
hexmask.long 0x74 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x78 "CRYPTO_ECC_Y1_12,ECC the Y-coordinate Word12 of the First Point"
hexmask.long 0x78 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x7C "CRYPTO_ECC_Y1_13,ECC the Y-coordinate Word13 of the First Point"
hexmask.long 0x7C 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x80 "CRYPTO_ECC_Y1_14,ECC the Y-coordinate Word14 of the First Point"
hexmask.long 0x80 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x84 "CRYPTO_ECC_Y1_15,ECC the Y-coordinate Word15 of the First Point"
hexmask.long 0x84 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x88 "CRYPTO_ECC_Y1_16,ECC the Y-coordinate Word16 of the First Point"
hexmask.long 0x88 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x8C "CRYPTO_ECC_Y1_17,ECC the Y-coordinate Word17 of the First Point"
hexmask.long 0x8C 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point \nFor B-163 or K-163  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233  POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283  POINTY1 is stored in.."
line.long 0x90 "CRYPTO_ECC_X2_00,ECC the X-coordinate Word0 of the Second Point"
hexmask.long 0x90 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0x94 "CRYPTO_ECC_X2_01,ECC the X-coordinate Word1 of the Second Point"
hexmask.long 0x94 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0x98 "CRYPTO_ECC_X2_02,ECC the X-coordinate Word2 of the Second Point"
hexmask.long 0x98 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0x9C "CRYPTO_ECC_X2_03,ECC the X-coordinate Word3 of the Second Point"
hexmask.long 0x9C 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xA0 "CRYPTO_ECC_X2_04,ECC the X-coordinate Word4 of the Second Point"
hexmask.long 0xA0 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xA4 "CRYPTO_ECC_X2_05,ECC the X-coordinate Word5 of the Second Point"
hexmask.long 0xA4 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xA8 "CRYPTO_ECC_X2_06,ECC the X-coordinate Word6 of the Second Point"
hexmask.long 0xA8 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xAC "CRYPTO_ECC_X2_07,ECC the X-coordinate Word7 of the Second Point"
hexmask.long 0xAC 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xB0 "CRYPTO_ECC_X2_08,ECC the X-coordinate Word8 of the Second Point"
hexmask.long 0xB0 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xB4 "CRYPTO_ECC_X2_09,ECC the X-coordinate Word9 of the Second Point"
hexmask.long 0xB4 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xB8 "CRYPTO_ECC_X2_10,ECC the X-coordinate Word10 of the Second Point"
hexmask.long 0xB8 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xBC "CRYPTO_ECC_X2_11,ECC the X-coordinate Word11 of the Second Point"
hexmask.long 0xBC 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xC0 "CRYPTO_ECC_X2_12,ECC the X-coordinate Word12 of the Second Point"
hexmask.long 0xC0 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xC4 "CRYPTO_ECC_X2_13,ECC the X-coordinate Word13 of the Second Point"
hexmask.long 0xC4 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xC8 "CRYPTO_ECC_X2_14,ECC the X-coordinate Word14 of the Second Point"
hexmask.long 0xC8 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xCC "CRYPTO_ECC_X2_15,ECC the X-coordinate Word15 of the Second Point"
hexmask.long 0xCC 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xD0 "CRYPTO_ECC_X2_16,ECC the X-coordinate Word16 of the Second Point"
hexmask.long 0xD0 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xD4 "CRYPTO_ECC_X2_17,ECC the X-coordinate Word17 of the Second Point"
hexmask.long 0xD4 0.--31. 1. "POINTX2,ECC the X-coordinate Value of the Second Point \nFor B-163 or K-163  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233  POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283  POINTX2 is stored in.."
line.long 0xD8 "CRYPTO_ECC_Y2_00,ECC the Y-coordinate Word0 of the Second Point"
hexmask.long 0xD8 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xDC "CRYPTO_ECC_Y2_01,ECC the Y-coordinate Word1 of the Second Point"
hexmask.long 0xDC 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xE0 "CRYPTO_ECC_Y2_02,ECC the Y-coordinate Word2 of the Second Point"
hexmask.long 0xE0 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xE4 "CRYPTO_ECC_Y2_03,ECC the Y-coordinate Word3 of the Second Point"
hexmask.long 0xE4 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xE8 "CRYPTO_ECC_Y2_04,ECC the Y-coordinate Word4 of the Second Point"
hexmask.long 0xE8 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xEC "CRYPTO_ECC_Y2_05,ECC the Y-coordinate Word5 of the Second Point"
hexmask.long 0xEC 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xF0 "CRYPTO_ECC_Y2_06,ECC the Y-coordinate Word6 of the Second Point"
hexmask.long 0xF0 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xF4 "CRYPTO_ECC_Y2_07,ECC the Y-coordinate Word7 of the Second Point"
hexmask.long 0xF4 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xF8 "CRYPTO_ECC_Y2_08,ECC the Y-coordinate Word8 of the Second Point"
hexmask.long 0xF8 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0xFC "CRYPTO_ECC_Y2_09,ECC the Y-coordinate Word9 of the Second Point"
hexmask.long 0xFC 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x100 "CRYPTO_ECC_Y2_10,ECC the Y-coordinate Word10 of the Second Point"
hexmask.long 0x100 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x104 "CRYPTO_ECC_Y2_11,ECC the Y-coordinate Word11 of the Second Point"
hexmask.long 0x104 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x108 "CRYPTO_ECC_Y2_12,ECC the Y-coordinate Word12 of the Second Point"
hexmask.long 0x108 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x10C "CRYPTO_ECC_Y2_13,ECC the Y-coordinate Word13 of the Second Point"
hexmask.long 0x10C 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x110 "CRYPTO_ECC_Y2_14,ECC the Y-coordinate Word14 of the Second Point"
hexmask.long 0x110 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x114 "CRYPTO_ECC_Y2_15,ECC the Y-coordinate Word15 of the Second Point"
hexmask.long 0x114 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x118 "CRYPTO_ECC_Y2_16,ECC the Y-coordinate Word16 of the Second Point"
hexmask.long 0x118 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x11C "CRYPTO_ECC_Y2_17,ECC the Y-coordinate Word17 of the Second Point"
hexmask.long 0x11C 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point \nFor B-163 or K-163  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233  POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283  POINTY2 is stored in.."
line.long 0x120 "CRYPTO_ECC_A_00,ECC the Parameter CURVEA Word0 of Elliptic Curve"
hexmask.long 0x120 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x124 "CRYPTO_ECC_A_01,ECC the Parameter CURVEA Word1 of Elliptic Curve"
hexmask.long 0x124 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x128 "CRYPTO_ECC_A_02,ECC the Parameter CURVEA Word2 of Elliptic Curve"
hexmask.long 0x128 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x12C "CRYPTO_ECC_A_03,ECC the Parameter CURVEA Word3 of Elliptic Curve"
hexmask.long 0x12C 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x130 "CRYPTO_ECC_A_04,ECC the Parameter CURVEA Word4 of Elliptic Curve"
hexmask.long 0x130 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x134 "CRYPTO_ECC_A_05,ECC the Parameter CURVEA Word5 of Elliptic Curve"
hexmask.long 0x134 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x138 "CRYPTO_ECC_A_06,ECC the Parameter CURVEA Word6 of Elliptic Curve"
hexmask.long 0x138 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x13C "CRYPTO_ECC_A_07,ECC the Parameter CURVEA Word7 of Elliptic Curve"
hexmask.long 0x13C 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x140 "CRYPTO_ECC_A_08,ECC the Parameter CURVEA Word8 of Elliptic Curve"
hexmask.long 0x140 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x144 "CRYPTO_ECC_A_09,ECC the Parameter CURVEA Word9 of Elliptic Curve"
hexmask.long 0x144 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x148 "CRYPTO_ECC_A_10,ECC the Parameter CURVEA Word10 of Elliptic Curve"
hexmask.long 0x148 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x14C "CRYPTO_ECC_A_11,ECC the Parameter CURVEA Word11 of Elliptic Curve"
hexmask.long 0x14C 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x150 "CRYPTO_ECC_A_12,ECC the Parameter CURVEA Word12 of Elliptic Curve"
hexmask.long 0x150 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x154 "CRYPTO_ECC_A_13,ECC the Parameter CURVEA Word13 of Elliptic Curve"
hexmask.long 0x154 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x158 "CRYPTO_ECC_A_14,ECC the Parameter CURVEA Word14 of Elliptic Curve"
hexmask.long 0x158 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x15C "CRYPTO_ECC_A_15,ECC the Parameter CURVEA Word15 of Elliptic Curve"
hexmask.long 0x15C 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x160 "CRYPTO_ECC_A_16,ECC the Parameter CURVEA Word16 of Elliptic Curve"
hexmask.long 0x160 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x164 "CRYPTO_ECC_A_17,ECC the Parameter CURVEA Word17 of Elliptic Curve"
hexmask.long 0x164 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve \nFor B-163 or K-163  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233  CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283  CURVEA is stored in.."
line.long 0x168 "CRYPTO_ECC_B_00,ECC the Parameter CURVEB Word0 of Elliptic Curve"
hexmask.long 0x168 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x16C "CRYPTO_ECC_B_01,ECC the Parameter CURVEB Word1 of Elliptic Curve"
hexmask.long 0x16C 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x170 "CRYPTO_ECC_B_02,ECC the Parameter CURVEB Word2 of Elliptic Curve"
hexmask.long 0x170 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x174 "CRYPTO_ECC_B_03,ECC the Parameter CURVEB Word3 of Elliptic Curve"
hexmask.long 0x174 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x178 "CRYPTO_ECC_B_04,ECC the Parameter CURVEB Word4 of Elliptic Curve"
hexmask.long 0x178 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x17C "CRYPTO_ECC_B_05,ECC the Parameter CURVEB Word5 of Elliptic Curve"
hexmask.long 0x17C 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x180 "CRYPTO_ECC_B_06,ECC the Parameter CURVEB Word6 of Elliptic Curve"
hexmask.long 0x180 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x184 "CRYPTO_ECC_B_07,ECC the Parameter CURVEB Word7 of Elliptic Curve"
hexmask.long 0x184 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x188 "CRYPTO_ECC_B_08,ECC the Parameter CURVEB Word8 of Elliptic Curve"
hexmask.long 0x188 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x18C "CRYPTO_ECC_B_09,ECC the Parameter CURVEB Word9 of Elliptic Curve"
hexmask.long 0x18C 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x190 "CRYPTO_ECC_B_10,ECC the Parameter CURVEB Word10 of Elliptic Curve"
hexmask.long 0x190 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x194 "CRYPTO_ECC_B_11,ECC the Parameter CURVEB Word11 of Elliptic Curve"
hexmask.long 0x194 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x198 "CRYPTO_ECC_B_12,ECC the Parameter CURVEB Word12 of Elliptic Curve"
hexmask.long 0x198 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x19C "CRYPTO_ECC_B_13,ECC the Parameter CURVEB Word13 of Elliptic Curve"
hexmask.long 0x19C 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x1A0 "CRYPTO_ECC_B_14,ECC the Parameter CURVEB Word14 of Elliptic Curve"
hexmask.long 0x1A0 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x1A4 "CRYPTO_ECC_B_15,ECC the Parameter CURVEB Word15 of Elliptic Curve"
hexmask.long 0x1A4 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x1A8 "CRYPTO_ECC_B_16,ECC the Parameter CURVEB Word16 of Elliptic Curve"
hexmask.long 0x1A8 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x1AC "CRYPTO_ECC_B_17,ECC the Parameter CURVEB Word17 of Elliptic Curve"
hexmask.long 0x1AC 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve \nFor B-163 or K-163  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233  CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283  CURVEB is stored in.."
line.long 0x1B0 "CRYPTO_ECC_N_00,ECC the Parameter CURVEN Word0 of Elliptic Curve"
hexmask.long 0x1B0 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1B4 "CRYPTO_ECC_N_01,ECC the Parameter CURVEN Word1 of Elliptic Curve"
hexmask.long 0x1B4 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1B8 "CRYPTO_ECC_N_02,ECC the Parameter CURVEN Word2 of Elliptic Curve"
hexmask.long 0x1B8 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1BC "CRYPTO_ECC_N_03,ECC the Parameter CURVEN Word3 of Elliptic Curve"
hexmask.long 0x1BC 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1C0 "CRYPTO_ECC_N_04,ECC the Parameter CURVEN Word4 of Elliptic Curve"
hexmask.long 0x1C0 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1C4 "CRYPTO_ECC_N_05,ECC the Parameter CURVEN Word5 of Elliptic Curve"
hexmask.long 0x1C4 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1C8 "CRYPTO_ECC_N_06,ECC the Parameter CURVEN Word6 of Elliptic Curve"
hexmask.long 0x1C8 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1CC "CRYPTO_ECC_N_07,ECC the Parameter CURVEN Word7 of Elliptic Curve"
hexmask.long 0x1CC 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1D0 "CRYPTO_ECC_N_08,ECC the Parameter CURVEN Word8 of Elliptic Curve"
hexmask.long 0x1D0 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1D4 "CRYPTO_ECC_N_09,ECC the Parameter CURVEN Word9 of Elliptic Curve"
hexmask.long 0x1D4 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1D8 "CRYPTO_ECC_N_10,ECC the Parameter CURVEN Word10 of Elliptic Curve"
hexmask.long 0x1D8 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1DC "CRYPTO_ECC_N_11,ECC the Parameter CURVEN Word11 of Elliptic Curve"
hexmask.long 0x1DC 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1E0 "CRYPTO_ECC_N_12,ECC the Parameter CURVEN Word12 of Elliptic Curve"
hexmask.long 0x1E0 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1E4 "CRYPTO_ECC_N_13,ECC the Parameter CURVEN Word13 of Elliptic Curve"
hexmask.long 0x1E4 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1E8 "CRYPTO_ECC_N_14,ECC the Parameter CURVEN Word14 of Elliptic Curve"
hexmask.long 0x1E8 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1EC "CRYPTO_ECC_N_15,ECC the Parameter CURVEN Word15 of Elliptic Curve"
hexmask.long 0x1EC 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1F0 "CRYPTO_ECC_N_16,ECC the Parameter CURVEN Word16 of Elliptic Curve"
hexmask.long 0x1F0 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
line.long 0x1F4 "CRYPTO_ECC_N_17,ECC the Parameter CURVEN Word17 of Elliptic Curve"
hexmask.long 0x1F4 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve \nIn GF(p)  CURVEN is the prime p.\nIn GF(2m)  CURVEN is the irreducible polynomial.\nFor B-163 or K-163  CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233  CURVEN is stored.."
wgroup.long 0x200++0x47
line.long 0x0 "CRYPTO_ECC_K_00,ECC the Scalar SCALARK Word0 of Point Multiplication"
hexmask.long 0x0 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x4 "CRYPTO_ECC_K_01,ECC the Scalar SCALARK Word1 of Point Multiplication"
hexmask.long 0x4 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x8 "CRYPTO_ECC_K_02,ECC the Scalar SCALARK Word2 of Point Multiplication"
hexmask.long 0x8 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0xC "CRYPTO_ECC_K_03,ECC the Scalar SCALARK Word3 of Point Multiplication"
hexmask.long 0xC 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x10 "CRYPTO_ECC_K_04,ECC the Scalar SCALARK Word4 of Point Multiplication"
hexmask.long 0x10 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x14 "CRYPTO_ECC_K_05,ECC the Scalar SCALARK Word5 of Point Multiplication"
hexmask.long 0x14 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x18 "CRYPTO_ECC_K_06,ECC the Scalar SCALARK Word6 of Point Multiplication"
hexmask.long 0x18 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x1C "CRYPTO_ECC_K_07,ECC the Scalar SCALARK Word7 of Point Multiplication"
hexmask.long 0x1C 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x20 "CRYPTO_ECC_K_08,ECC the Scalar SCALARK Word8 of Point Multiplication"
hexmask.long 0x20 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x24 "CRYPTO_ECC_K_09,ECC the Scalar SCALARK Word9 of Point Multiplication"
hexmask.long 0x24 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x28 "CRYPTO_ECC_K_10,ECC the Scalar SCALARK Word10 of Point Multiplication"
hexmask.long 0x28 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x2C "CRYPTO_ECC_K_11,ECC the Scalar SCALARK Word11 of Point Multiplication"
hexmask.long 0x2C 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x30 "CRYPTO_ECC_K_12,ECC the Scalar SCALARK Word12 of Point Multiplication"
hexmask.long 0x30 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x34 "CRYPTO_ECC_K_13,ECC the Scalar SCALARK Word13 of Point Multiplication"
hexmask.long 0x34 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x38 "CRYPTO_ECC_K_14,ECC the Scalar SCALARK Word14 of Point Multiplication"
hexmask.long 0x38 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x3C "CRYPTO_ECC_K_15,ECC the Scalar SCALARK Word15 of Point Multiplication"
hexmask.long 0x3C 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x40 "CRYPTO_ECC_K_16,ECC the Scalar SCALARK Word16 of Point Multiplication"
hexmask.long 0x40 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
line.long 0x44 "CRYPTO_ECC_K_17,ECC the Scalar SCALARK Word17 of Point Multiplication"
hexmask.long 0x44 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication\nBecause the SCALARK usually stores the private key  ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163  SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor.."
group.long 0x248++0xF
line.long 0x0 "CRYPTO_ECC_SADDR,ECC DMA Source Address Register"
line.long 0x4 "CRYPTO_ECC_DADDR,ECC DMA Destination Address Register"
hexmask.long 0x4 0.--31. 1. "DADDR,ECC DMA Destination Address \nThe ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator. The DADDR keeps the destination address of the data buffer where output data of ECC engine will be.."
line.long 0x8 "CRYPTO_ECC_STARTREG,ECC Starting Address of Updated Registers"
hexmask.long 0x8 0.--31. 1. "STARTREG,ECC Starting Address of Updated Registers\nThe address of the updated registers that DMA feeds the first data or parameter to ECC engine. When ECC engine is active  ECC accelerator does not allow users to modify STARTRE.G. For example  to update.."
line.long 0xC "CRYPTO_ECC_WORDCNT,ECC DMA Word Count"
hexmask.long 0xC 0.--31. 1. "WORDCNT,ECC DMA Word Count \nThe CRYPTO_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode. Although CRYPTO_ECC_WORDCNT is 32-bit  the maximum of word count in ECC.."
wgroup.long 0x740++0x3
line.long 0x0 "CRYPTO_ECC_KSCTL,ECC Key Control Register"
bitfld.long 0x0 24.--26. "OWNER,Write Key Owner Selection Bits" "0: The ECDH written key is only for AES used,1: The ECDH written key is only for HMAC engine used,?,?,?,?,?,?"
bitfld.long 0x0 22.--23. "WSDST,Write Key Store Destination" "0: The ECDH written key is written to the SRAM of..,1: The ECDH written key is written to the Flash of..,?,?"
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bitfld.long 0x0 21. "WDST,Write Key Destination" "0: The ECDH written key is in registers..,1: The ECDH written key is written to key store"
bitfld.long 0x0 20. "XY,ECDH Output Select Bit" "0: The ECDH written key is from X-coordinate Value,1: The ECDH written key is from Y-coordinate Value"
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bitfld.long 0x0 16. "TRUST,Write Key Trust Selection Bit" "0: Set ECDH written key as the non-secure key,1: Set ECDH written key as the secure key"
bitfld.long 0x0 14. "ECDH,ECDH Control Bit" "0: Reserved.,1: Set ECC operation is in ECDH. When this bit and.."
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bitfld.long 0x0 6.--7. "RSSRCK,Read Key Store Source for Key Number K" "0: Key is read from the SRAM of key store,1: Key is read from the Flash of key store,?,?"
bitfld.long 0x0 5. "RSRCK,Read Key Source for Key Number K" "0: Key is read from ECC registers,1: Key is read from key store"
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hexmask.long.byte 0x0 0.--4. 1. "NUMK,Read Key Number K"
rgroup.long 0x744++0x3
line.long 0x0 "CRYPTO_ECC_KSSTS,ECC Key Status Register"
hexmask.long.byte 0x0 0.--4. 1. "NUM,Key Number\nThe key number is generated by key store after ECDH."
wgroup.long 0x748++0x3
line.long 0x0 "CRYPTO_ECC_KSXY,ECC XY Number Register"
bitfld.long 0x0 14.--15. "RSSRCY,Read Key Store Source for Key Number Y" "0: Key is read from the SRAM of key store,1: Key is read from the Flash of key store,?,?"
hexmask.long.byte 0x0 8.--12. 1. "NUMY,Read Key Number Y"
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bitfld.long 0x0 6.--7. "RSSRCX,Read Key Store Source for Key Number X" "0: Key is read from the SRAM of key store,1: Key is read from the Flash of key store,?,?"
bitfld.long 0x0 5. "RSRCXY,Read Key Source for Key Number x and Y" "0: Key is read from ECC registers,1: Key is read from key store"
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hexmask.long.byte 0x0 0.--4. 1. "NUMX,Read Key Number X"
tree.end
tree "HMAC"
base ad:0x40032300
group.long 0x0++0x3
line.long 0x0 "CRYPTO_HMAC_CTL,SHA/HMAC Control Register"
bitfld.long 0x0 25. "FINISHDGST,SHAKE128/256 Next Digest Finish" "0: No effect,1: finish generating the next digest"
bitfld.long 0x0 24. "NEXTDGST,SHAKE128/256 Next Digest Start" "0: No effect,1: Start SHAKE engine to generate the next digest.."
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bitfld.long 0x0 23. "INSWAP,SHA/HMAC Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the accelerator.."
bitfld.long 0x0 22. "OUTSWAP,SHA/HMAC Engine Output Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the accelerator.."
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bitfld.long 0x0 21. "FBOUT,Feedback Output From SHA/HMAC Via DMA Automatically" "0: DMA automatic feedback output function Disabled,1: DMA automatic feedback output function Enabled.."
bitfld.long 0x0 20. "FBIN,Feedback Input to SHA/HMAC Via DMA Automatically" "0: DMA automatic feedback input function Disabled,1: DMA automatic feedback input function Enabled.."
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bitfld.long 0x0 12. "SHA3EN,SHA3 Engine Enable Bit" "0: Execute other function,1: Execute SHA3 function"
bitfld.long 0x0 11. "HMACEN,HMAC_SHA Engine Operating Mode" "0: Execute SHA function,1: Execute HMAC function"
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bitfld.long 0x0 8.--10. "OPMODE,SHA/HMAC Engine Operation Modes\n0x100: SHA3-256\n0x101: SHA3-224\n0x110: SHA3-512\n0x111: SHA3-384\n0x000: SHAKE128\n0x001: SHAKE256\nNote: These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "DMAEN,SHA/HMAC Engine DMA Enable Bit\nSHA/HMAC engine operates in DMA mode  and data movement from/to the engine is done by DMA logic." "0: SHA/HMAC DMA engine Disabled,1: SHA/HMAC DMA engine Enabled"
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bitfld.long 0x0 6. "DMACSCAD,SHA/HMAC Engine DMA with Cascade Mode" "0: DMA cascade function Disabled,1: In DMA cascade mode software can update DMA.."
bitfld.long 0x0 5. "DMALAST,SHA/HMAC Last Block\nThis bit must be set as feeding in last byte of data." "0,1"
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bitfld.long 0x0 4. "DMAFIRST,SHA/HMAC First Block in Cascade function\nThis bit must be set as feeding in first byte of data." "0,1"
bitfld.long 0x0 1. "STOP,SHA/HMAC Engine Stop\nNote: This bit is always 0 when it is read back." "0: No effect,1: Stop SHA/HMAC engine"
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bitfld.long 0x0 0. "START,SHA/HMAC Engine Start\nNote: This bit is always 0 when it is read back." "0: No effect,1: Start SHA/HMAC engine. BUSY flag will be set"
rgroup.long 0x4++0x43
line.long 0x0 "CRYPTO_HMAC_STS,SHA/HMAC Status Flag"
bitfld.long 0x0 16. "DATINREQ,SHA/HMAC Non-DMA Mode Data Input Request" "0: No effect,1: Request SHA/HMAC Non-DMA mode data input"
bitfld.long 0x0 9. "KSERR,HMAC Engine Access Key Store Error Flag" "0: No error,1: Access error will stop HMAC engine"
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bitfld.long 0x0 8. "DMAERR,SHA/HMAC Engine DMA Error Flag" "0: Show the SHA/HMAC engine access normal,1: Show the SHA/HMAC engine access error"
bitfld.long 0x0 2. "SHAKEBUSY,SHAKE Engine Busy Flag" "0: SHAKE engine is idle or finished,1: SHAKE engine is busy"
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bitfld.long 0x0 1. "DMABUSY,SHA/HMAC Engine DMA Busy Flag" "0: SHA/HMAC DMA engine is idle or finished,1: SHA/HMAC DMA engine is busy"
bitfld.long 0x0 0. "BUSY,SHA/HMAC Engine Busy" "0: SHA/HMAC engine is idle or finished,1: SHA/HMAC engine is busy"
line.long 0x4 "CRYPTO_HMAC_DGST0,SHA/HMAC Output Feedback Data 0"
hexmask.long 0x4 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x8 "CRYPTO_HMAC_DGST1,SHA/HMAC Output Feedback Data 1"
hexmask.long 0x8 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0xC "CRYPTO_HMAC_DGST2,SHA/HMAC Output Feedback Data 2"
hexmask.long 0xC 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x10 "CRYPTO_HMAC_DGST3,SHA/HMAC Output Feedback Data 3"
hexmask.long 0x10 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x14 "CRYPTO_HMAC_DGST4,SHA/HMAC Output Feedback Data 4"
hexmask.long 0x14 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x18 "CRYPTO_HMAC_DGST5,SHA/HMAC Output Feedback Data 5"
hexmask.long 0x18 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x1C "CRYPTO_HMAC_DGST6,SHA/HMAC Output Feedback Data 6"
hexmask.long 0x1C 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x20 "CRYPTO_HMAC_DGST7,SHA/HMAC Output Feedback Data 7"
hexmask.long 0x20 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x24 "CRYPTO_HMAC_DGST8,SHA/HMAC Output Feedback Data 8"
hexmask.long 0x24 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x28 "CRYPTO_HMAC_DGST9,SHA/HMAC Output Feedback Data 9"
hexmask.long 0x28 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x2C "CRYPTO_HMAC_DGST10,SHA/HMAC Output Feedback Data 10"
hexmask.long 0x2C 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x30 "CRYPTO_HMAC_DGST11,SHA/HMAC Output Feedback Data 11"
hexmask.long 0x30 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x34 "CRYPTO_HMAC_DGST12,SHA/HMAC Output Feedback Data 12"
hexmask.long 0x34 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x38 "CRYPTO_HMAC_DGST13,SHA/HMAC Output Feedback Data 13"
hexmask.long 0x38 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x3C "CRYPTO_HMAC_DGST14,SHA/HMAC Output Feedback Data 14"
hexmask.long 0x3C 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
line.long 0x40 "CRYPTO_HMAC_DGST15,SHA/HMAC Output Feedback Data 15"
hexmask.long 0x40 0.--31. 1. "DGST,SHA/HMAC Output Feedback Data Output Register\nFor SHA-160  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224  the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256  the digest is stored in.."
group.long 0x48++0x16F
line.long 0x0 "CRYPTO_HMAC_KEYCNT,SHA/HMAC Key Byte Count Register"
hexmask.long 0x0 0.--31. 1. "KEYCNT,SHA/HMAC Key Byte Count\nThe CRYPTO_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRYPTO_HMAC_KEYCNT as.."
line.long 0x4 "CRYPTO_HMAC_SADDR,SHA/HMAC DMA Source Address Register"
hexmask.long 0x4 0.--31. 1. "SADDR,SHA/HMAC DMA Source Address\nThe SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_HMAC_SADDR keeps the source address of the data buffer where the source text is stored."
line.long 0x8 "CRYPTO_HMAC_DMACNT,SHA/HMAC Byte Count Register"
hexmask.long 0x8 0.--31. 1. "DMACNT,SHA/HMAC Operation Byte Count\nThe CRYPTO_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode. The CRYPTO_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_HMAC_DMACNT can be.."
line.long 0xC "CRYPTO_HMAC_DATIN,SHA/HMAC Engine Non-DMA Mode Data Input Port Register"
hexmask.long 0xC 0.--31. 1. "DATIN,SHA/HMAC Engine Input Port\nCPU feeds data to SHA/HMAC engine through this port by checking CRYPTO_HMAC_STS. Feed data as DATINREQ is 1."
line.long 0x10 "CRYPTO_HMAC_FDBCK0,SHA/HMAC Output Feedback Data 0 After SHA/HMAC Operation"
hexmask.long 0x10 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x14 "CRYPTO_HMAC_FDBCK1,SHA/HMAC Output Feedback Data 1 After SHA/HMAC Operation"
hexmask.long 0x14 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x18 "CRYPTO_HMAC_FDBCK2,SHA/HMAC Output Feedback Data 2 After SHA/HMAC Operation"
hexmask.long 0x18 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x1C "CRYPTO_HMAC_FDBCK3,SHA/HMAC Output Feedback Data 3 After SHA/HMAC Operation"
hexmask.long 0x1C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x20 "CRYPTO_HMAC_FDBCK4,SHA/HMAC Output Feedback Data 4 After SHA/HMAC Operation"
hexmask.long 0x20 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x24 "CRYPTO_HMAC_FDBCK5,SHA/HMAC Output Feedback Data 5 After SHA/HMAC Operation"
hexmask.long 0x24 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x28 "CRYPTO_HMAC_FDBCK6,SHA/HMAC Output Feedback Data 6 After SHA/HMAC Operation"
hexmask.long 0x28 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x2C "CRYPTO_HMAC_FDBCK7,SHA/HMAC Output Feedback Data 7 After SHA/HMAC Operation"
hexmask.long 0x2C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x30 "CRYPTO_HMAC_FDBCK8,SHA/HMAC Output Feedback Data 8 After SHA/HMAC Operation"
hexmask.long 0x30 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x34 "CRYPTO_HMAC_FDBCK9,SHA/HMAC Output Feedback Data 9 After SHA/HMAC Operation"
hexmask.long 0x34 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x38 "CRYPTO_HMAC_FDBCK10,SHA/HMAC Output Feedback Data 10 After SHA/HMAC Operation"
hexmask.long 0x38 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x3C "CRYPTO_HMAC_FDBCK11,SHA/HMAC Output Feedback Data 11 After SHA/HMAC Operation"
hexmask.long 0x3C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x40 "CRYPTO_HMAC_FDBCK12,SHA/HMAC Output Feedback Data 12 After SHA/HMAC Operation"
hexmask.long 0x40 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x44 "CRYPTO_HMAC_FDBCK13,SHA/HMAC Output Feedback Data 13 After SHA/HMAC Operation"
hexmask.long 0x44 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x48 "CRYPTO_HMAC_FDBCK14,SHA/HMAC Output Feedback Data 14 After SHA/HMAC Operation"
hexmask.long 0x48 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x4C "CRYPTO_HMAC_FDBCK15,SHA/HMAC Output Feedback Data 15 After SHA/HMAC Operation"
hexmask.long 0x4C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x50 "CRYPTO_HMAC_FDBCK16,SHA/HMAC Output Feedback Data 16 After SHA/HMAC Operation"
hexmask.long 0x50 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x54 "CRYPTO_HMAC_FDBCK17,SHA/HMAC Output Feedback Data 17 After SHA/HMAC Operation"
hexmask.long 0x54 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x58 "CRYPTO_HMAC_FDBCK18,SHA/HMAC Output Feedback Data 18 After SHA/HMAC Operation"
hexmask.long 0x58 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x5C "CRYPTO_HMAC_FDBCK19,SHA/HMAC Output Feedback Data 19 After SHA/HMAC Operation"
hexmask.long 0x5C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x60 "CRYPTO_HMAC_FDBCK20,SHA/HMAC Output Feedback Data 20 After SHA/HMAC Operation"
hexmask.long 0x60 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x64 "CRYPTO_HMAC_FDBCK21,SHA/HMAC Output Feedback Data 21 After SHA/HMAC Operation"
hexmask.long 0x64 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x68 "CRYPTO_HMAC_FDBCK22,SHA/HMAC Output Feedback Data 22 After SHA/HMAC Operation"
hexmask.long 0x68 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x6C "CRYPTO_HMAC_FDBCK23,SHA/HMAC Output Feedback Data 23 After SHA/HMAC Operation"
hexmask.long 0x6C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x70 "CRYPTO_HMAC_FDBCK24,SHA/HMAC Output Feedback Data 24 After SHA/HMAC Operation"
hexmask.long 0x70 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x74 "CRYPTO_HMAC_FDBCK25,SHA/HMAC Output Feedback Data 25 After SHA/HMAC Operation"
hexmask.long 0x74 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x78 "CRYPTO_HMAC_FDBCK26,SHA/HMAC Output Feedback Data 26 After SHA/HMAC Operation"
hexmask.long 0x78 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x7C "CRYPTO_HMAC_FDBCK27,SHA/HMAC Output Feedback Data 27 After SHA/HMAC Operation"
hexmask.long 0x7C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x80 "CRYPTO_HMAC_FDBCK28,SHA/HMAC Output Feedback Data 28 After SHA/HMAC Operation"
hexmask.long 0x80 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x84 "CRYPTO_HMAC_FDBCK29,SHA/HMAC Output Feedback Data 29 After SHA/HMAC Operation"
hexmask.long 0x84 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x88 "CRYPTO_HMAC_FDBCK30,SHA/HMAC Output Feedback Data 30 After SHA/HMAC Operation"
hexmask.long 0x88 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x8C "CRYPTO_HMAC_FDBCK31,SHA/HMAC Output Feedback Data 31 After SHA/HMAC Operation"
hexmask.long 0x8C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x90 "CRYPTO_HMAC_FDBCK32,SHA/HMAC Output Feedback Data 32 After SHA/HMAC Operation"
hexmask.long 0x90 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x94 "CRYPTO_HMAC_FDBCK33,SHA/HMAC Output Feedback Data 33 After SHA/HMAC Operation"
hexmask.long 0x94 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x98 "CRYPTO_HMAC_FDBCK34,SHA/HMAC Output Feedback Data 34 After SHA/HMAC Operation"
hexmask.long 0x98 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x9C "CRYPTO_HMAC_FDBCK35,SHA/HMAC Output Feedback Data 35 After SHA/HMAC Operation"
hexmask.long 0x9C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xA0 "CRYPTO_HMAC_FDBCK36,SHA/HMAC Output Feedback Data 36 After SHA/HMAC Operation"
hexmask.long 0xA0 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xA4 "CRYPTO_HMAC_FDBCK37,SHA/HMAC Output Feedback Data 37 After SHA/HMAC Operation"
hexmask.long 0xA4 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xA8 "CRYPTO_HMAC_FDBCK38,SHA/HMAC Output Feedback Data 38 After SHA/HMAC Operation"
hexmask.long 0xA8 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xAC "CRYPTO_HMAC_FDBCK39,SHA/HMAC Output Feedback Data 39 After SHA/HMAC Operation"
hexmask.long 0xAC 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xB0 "CRYPTO_HMAC_FDBCK40,SHA/HMAC Output Feedback Data 40 After SHA/HMAC Operation"
hexmask.long 0xB0 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xB4 "CRYPTO_HMAC_FDBCK41,SHA/HMAC Output Feedback Data 41 After SHA/HMAC Operation"
hexmask.long 0xB4 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xB8 "CRYPTO_HMAC_FDBCK42,SHA/HMAC Output Feedback Data 42 After SHA/HMAC Operation"
hexmask.long 0xB8 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xBC "CRYPTO_HMAC_FDBCK43,SHA/HMAC Output Feedback Data 43 After SHA/HMAC Operation"
hexmask.long 0xBC 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xC0 "CRYPTO_HMAC_FDBCK44,SHA/HMAC Output Feedback Data 44 After SHA/HMAC Operation"
hexmask.long 0xC0 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xC4 "CRYPTO_HMAC_FDBCK45,SHA/HMAC Output Feedback Data 45 After SHA/HMAC Operation"
hexmask.long 0xC4 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xC8 "CRYPTO_HMAC_FDBCK46,SHA/HMAC Output Feedback Data 46 After SHA/HMAC Operation"
hexmask.long 0xC8 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xCC "CRYPTO_HMAC_FDBCK47,SHA/HMAC Output Feedback Data 47 After SHA/HMAC Operation"
hexmask.long 0xCC 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xD0 "CRYPTO_HMAC_FDBCK48,SHA/HMAC Output Feedback Data 48 After SHA/HMAC Operation"
hexmask.long 0xD0 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xD4 "CRYPTO_HMAC_FDBCK49,SHA/HMAC Output Feedback Data 49 After SHA/HMAC Operation"
hexmask.long 0xD4 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xD8 "CRYPTO_HMAC_FDBCK50,SHA/HMAC Output Feedback Data 50 After SHA/HMAC Operation"
hexmask.long 0xD8 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xDC "CRYPTO_HMAC_FDBCK51,SHA/HMAC Output Feedback Data 51 After SHA/HMAC Operation"
hexmask.long 0xDC 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xE0 "CRYPTO_HMAC_FDBCK52,SHA/HMAC Output Feedback Data 52 After SHA/HMAC Operation"
hexmask.long 0xE0 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xE4 "CRYPTO_HMAC_FDBCK53,SHA/HMAC Output Feedback Data 53 After SHA/HMAC Operation"
hexmask.long 0xE4 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xE8 "CRYPTO_HMAC_FDBCK54,SHA/HMAC Output Feedback Data 54 After SHA/HMAC Operation"
hexmask.long 0xE8 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xEC "CRYPTO_HMAC_FDBCK55,SHA/HMAC Output Feedback Data 55 After SHA/HMAC Operation"
hexmask.long 0xEC 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xF0 "CRYPTO_HMAC_FDBCK56,SHA/HMAC Output Feedback Data 56 After SHA/HMAC Operation"
hexmask.long 0xF0 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xF4 "CRYPTO_HMAC_FDBCK57,SHA/HMAC Output Feedback Data 57 After SHA/HMAC Operation"
hexmask.long 0xF4 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xF8 "CRYPTO_HMAC_FDBCK58,SHA/HMAC Output Feedback Data 58 After SHA/HMAC Operation"
hexmask.long 0xF8 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0xFC "CRYPTO_HMAC_FDBCK59,SHA/HMAC Output Feedback Data 59 After SHA/HMAC Operation"
hexmask.long 0xFC 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x100 "CRYPTO_HMAC_FDBCK60,SHA/HMAC Output Feedback Data 60 After SHA/HMAC Operation"
hexmask.long 0x100 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x104 "CRYPTO_HMAC_FDBCK61,SHA/HMAC Output Feedback Data 61 After SHA/HMAC Operation"
hexmask.long 0x104 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x108 "CRYPTO_HMAC_FDBCK62,SHA/HMAC Output Feedback Data 62 After SHA/HMAC Operation"
hexmask.long 0x108 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x10C "CRYPTO_HMAC_FDBCK63,SHA/HMAC Output Feedback Data 63 After SHA/HMAC Operation"
hexmask.long 0x10C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x110 "CRYPTO_HMAC_FDBCK64,SHA/HMAC Output Feedback Data 64 After SHA/HMAC Operation"
hexmask.long 0x110 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x114 "CRYPTO_HMAC_FDBCK65,SHA/HMAC Output Feedback Data 65 After SHA/HMAC Operation"
hexmask.long 0x114 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x118 "CRYPTO_HMAC_FDBCK66,SHA/HMAC Output Feedback Data 66 After SHA/HMAC Operation"
hexmask.long 0x118 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x11C "CRYPTO_HMAC_FDBCK67,SHA/HMAC Output Feedback Data 67 After SHA/HMAC Operation"
hexmask.long 0x11C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x120 "CRYPTO_HMAC_FDBCK68,SHA/HMAC Output Feedback Data 68 After SHA/HMAC Operation"
hexmask.long 0x120 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x124 "CRYPTO_HMAC_FDBCK69,SHA/HMAC Output Feedback Data 69 After SHA/HMAC Operation"
hexmask.long 0x124 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x128 "CRYPTO_HMAC_FDBCK70,SHA/HMAC Output Feedback Data 70 After SHA/HMAC Operation"
hexmask.long 0x128 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x12C "CRYPTO_HMAC_FDBCK71,SHA/HMAC Output Feedback Data 71 After SHA/HMAC Operation"
hexmask.long 0x12C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x130 "CRYPTO_HMAC_FDBCK72,SHA/HMAC Output Feedback Data 72 After SHA/HMAC Operation"
hexmask.long 0x130 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x134 "CRYPTO_HMAC_FDBCK73,SHA/HMAC Output Feedback Data 73 After SHA/HMAC Operation"
hexmask.long 0x134 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x138 "CRYPTO_HMAC_FDBCK74,SHA/HMAC Output Feedback Data 74 After SHA/HMAC Operation"
hexmask.long 0x138 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x13C "CRYPTO_HMAC_FDBCK75,SHA/HMAC Output Feedback Data 75 After SHA/HMAC Operation"
hexmask.long 0x13C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x140 "CRYPTO_HMAC_FDBCK76,SHA/HMAC Output Feedback Data 76 After SHA/HMAC Operation"
hexmask.long 0x140 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x144 "CRYPTO_HMAC_FDBCK77,SHA/HMAC Output Feedback Data 77 After SHA/HMAC Operation"
hexmask.long 0x144 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x148 "CRYPTO_HMAC_FDBCK78,SHA/HMAC Output Feedback Data 78 After SHA/HMAC Operation"
hexmask.long 0x148 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x14C "CRYPTO_HMAC_FDBCK79,SHA/HMAC Output Feedback Data 79 After SHA/HMAC Operation"
hexmask.long 0x14C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x150 "CRYPTO_HMAC_FDBCK80,SHA/HMAC Output Feedback Data 80 After SHA/HMAC Operation"
hexmask.long 0x150 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x154 "CRYPTO_HMAC_FDBCK81,SHA/HMAC Output Feedback Data 81 After SHA/HMAC Operation"
hexmask.long 0x154 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x158 "CRYPTO_HMAC_FDBCK82,SHA/HMAC Output Feedback Data 82 After SHA/HMAC Operation"
hexmask.long 0x158 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x15C "CRYPTO_HMAC_FDBCK83,SHA/HMAC Output Feedback Data 83 After SHA/HMAC Operation"
hexmask.long 0x15C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x160 "CRYPTO_HMAC_FDBCK84,SHA/HMAC Output Feedback Data 84 After SHA/HMAC Operation"
hexmask.long 0x160 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x164 "CRYPTO_HMAC_FDBCK85,SHA/HMAC Output Feedback Data 85 After SHA/HMAC Operation"
hexmask.long 0x164 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x168 "CRYPTO_HMAC_FDBCK86,SHA/HMAC Output Feedback Data 86 After SHA/HMAC Operation"
hexmask.long 0x168 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
line.long 0x16C "CRYPTO_HMAC_FDBCK87,SHA/HMAC Output Feedback Data 87 After SHA/HMAC Operation"
hexmask.long 0x16C 0.--31. 1. "FDBCK,SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA.."
group.long 0x1F8++0x7
line.long 0x0 "CRYPTO_HMAC_SHA512T,SHA/HMAC SHA512/t Control Register"
hexmask.long.word 0x0 8.--16. 1. "TLEN,SHA512/t output digest length\nThe TLEN is equal to value t of SHA512/t. It also means the output digest length of SHA512 /t.\nNote: TLEN 512  and TLEN is not 384."
bitfld.long 0x0 0. "SHA512TEN,SHA512/t Engine Enable Bit" "0: Execute other function,1: Execute SHA512/t function if SHA3EN=0"
line.long 0x4 "CRYPTO_HMAC_FBADDR,SHA/HMAC DMA Feedback Address Register"
hexmask.long 0x4 0.--31. 1. "FBADDR,SHA/HMAC DMA Feedback Address\nIn DMA cascade mode  software can update DMA feedback address register for automatically reading and writing feedback values via DMA. The FBADDR keeps the feedback address of the feedback data for the next cascade.."
rgroup.long 0x200++0xA7
line.long 0x0 "CRYPTO_HMAC_SHAKEDGST0,SHA/HMAC SHAKE Digest Message 0"
hexmask.long 0x0 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x4 "CRYPTO_HMAC_SHAKEDGST1,SHA/HMAC SHAKE Digest Message 1"
hexmask.long 0x4 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x8 "CRYPTO_HMAC_SHAKEDGST2,SHA/HMAC SHAKE Digest Message 2"
hexmask.long 0x8 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0xC "CRYPTO_HMAC_SHAKEDGST3,SHA/HMAC SHAKE Digest Message 3"
hexmask.long 0xC 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x10 "CRYPTO_HMAC_SHAKEDGST4,SHA/HMAC SHAKE Digest Message 4"
hexmask.long 0x10 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x14 "CRYPTO_HMAC_SHAKEDGST5,SHA/HMAC SHAKE Digest Message 5"
hexmask.long 0x14 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x18 "CRYPTO_HMAC_SHAKEDGST6,SHA/HMAC SHAKE Digest Message 6"
hexmask.long 0x18 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x1C "CRYPTO_HMAC_SHAKEDGST7,SHA/HMAC SHAKE Digest Message 7"
hexmask.long 0x1C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x20 "CRYPTO_HMAC_SHAKEDGST8,SHA/HMAC SHAKE Digest Message 8"
hexmask.long 0x20 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x24 "CRYPTO_HMAC_SHAKEDGST9,SHA/HMAC SHAKE Digest Message 9"
hexmask.long 0x24 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x28 "CRYPTO_HMAC_SHAKEDGST10,SHA/HMAC SHAKE Digest Message 10"
hexmask.long 0x28 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x2C "CRYPTO_HMAC_SHAKEDGST11,SHA/HMAC SHAKE Digest Message 11"
hexmask.long 0x2C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x30 "CRYPTO_HMAC_SHAKEDGST12,SHA/HMAC SHAKE Digest Message 12"
hexmask.long 0x30 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x34 "CRYPTO_HMAC_SHAKEDGST13,SHA/HMAC SHAKE Digest Message 13"
hexmask.long 0x34 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x38 "CRYPTO_HMAC_SHAKEDGST14,SHA/HMAC SHAKE Digest Message 14"
hexmask.long 0x38 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x3C "CRYPTO_HMAC_SHAKEDGST15,SHA/HMAC SHAKE Digest Message 15"
hexmask.long 0x3C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x40 "CRYPTO_HMAC_SHAKEDGST16,SHA/HMAC SHAKE Digest Message 16"
hexmask.long 0x40 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x44 "CRYPTO_HMAC_SHAKEDGST17,SHA/HMAC SHAKE Digest Message 17"
hexmask.long 0x44 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x48 "CRYPTO_HMAC_SHAKEDGST18,SHA/HMAC SHAKE Digest Message 18"
hexmask.long 0x48 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x4C "CRYPTO_HMAC_SHAKEDGST19,SHA/HMAC SHAKE Digest Message 19"
hexmask.long 0x4C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x50 "CRYPTO_HMAC_SHAKEDGST20,SHA/HMAC SHAKE Digest Message 20"
hexmask.long 0x50 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x54 "CRYPTO_HMAC_SHAKEDGST21,SHA/HMAC SHAKE Digest Message 21"
hexmask.long 0x54 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x58 "CRYPTO_HMAC_SHAKEDGST22,SHA/HMAC SHAKE Digest Message 22"
hexmask.long 0x58 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x5C "CRYPTO_HMAC_SHAKEDGST23,SHA/HMAC SHAKE Digest Message 23"
hexmask.long 0x5C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x60 "CRYPTO_HMAC_SHAKEDGST24,SHA/HMAC SHAKE Digest Message 24"
hexmask.long 0x60 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x64 "CRYPTO_HMAC_SHAKEDGST25,SHA/HMAC SHAKE Digest Message 25"
hexmask.long 0x64 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x68 "CRYPTO_HMAC_SHAKEDGST26,SHA/HMAC SHAKE Digest Message 26"
hexmask.long 0x68 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x6C "CRYPTO_HMAC_SHAKEDGST27,SHA/HMAC SHAKE Digest Message 27"
hexmask.long 0x6C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x70 "CRYPTO_HMAC_SHAKEDGST28,SHA/HMAC SHAKE Digest Message 28"
hexmask.long 0x70 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x74 "CRYPTO_HMAC_SHAKEDGST29,SHA/HMAC SHAKE Digest Message 29"
hexmask.long 0x74 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x78 "CRYPTO_HMAC_SHAKEDGST30,SHA/HMAC SHAKE Digest Message 30"
hexmask.long 0x78 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x7C "CRYPTO_HMAC_SHAKEDGST31,SHA/HMAC SHAKE Digest Message 31"
hexmask.long 0x7C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x80 "CRYPTO_HMAC_SHAKEDGST32,SHA/HMAC SHAKE Digest Message 32"
hexmask.long 0x80 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x84 "CRYPTO_HMAC_SHAKEDGST33,SHA/HMAC SHAKE Digest Message 33"
hexmask.long 0x84 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x88 "CRYPTO_HMAC_SHAKEDGST34,SHA/HMAC SHAKE Digest Message 34"
hexmask.long 0x88 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x8C "CRYPTO_HMAC_SHAKEDGST35,SHA/HMAC SHAKE Digest Message 35"
hexmask.long 0x8C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x90 "CRYPTO_HMAC_SHAKEDGST36,SHA/HMAC SHAKE Digest Message 36"
hexmask.long 0x90 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x94 "CRYPTO_HMAC_SHAKEDGST37,SHA/HMAC SHAKE Digest Message 37"
hexmask.long 0x94 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x98 "CRYPTO_HMAC_SHAKEDGST38,SHA/HMAC SHAKE Digest Message 38"
hexmask.long 0x98 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0x9C "CRYPTO_HMAC_SHAKEDGST39,SHA/HMAC SHAKE Digest Message 39"
hexmask.long 0x9C 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0xA0 "CRYPTO_HMAC_SHAKEDGST40,SHA/HMAC SHAKE Digest Message 40"
hexmask.long 0xA0 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
line.long 0xA4 "CRYPTO_HMAC_SHAKEDGST41,SHA/HMAC SHAKE Digest Message 41"
hexmask.long 0xA4 0.--31. 1. "DGST,SHA/HMAC SHAKE Digest Message Register\nFor SHAKE-128  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41.\nFor SHAKE-256  the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33."
wgroup.long 0xC30++0x3
line.long 0x0 "CRYPTO_HMAC_KSCTL,HMAC Key Control Register"
bitfld.long 0x0 6.--7. "RSSRC,Read Key Store Source" "0: Key is read from the SRAM of key store,1: Key is read from the Flash of key store,?,?"
bitfld.long 0x0 5. "RSRC,Read Key Source" "0: Key is read from HMAC registers,1: Key is read from key store"
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hexmask.long.byte 0x0 0.--4. 1. "NUM,Read Key Number\nThe key number is sent to key store"
tree.end
tree "PRNG"
base ad:0x40032008
group.long 0x0++0x3
line.long 0x0 "CRYPTO_PRNG_CTL,PRNG Control Register"
bitfld.long 0x0 16. "SEEDSRC,Seed Source\nNote: When SEEDRLD is set to 0  this bit (SEEDSRC) is meaningless." "0: Seed is from TRNG,1: Seed is from PRNG seed register"
rbitfld.long 0x0 8. "BUSY,PRNG Busy (Read Only)" "0: PRNG engine is idle,1: PRNG engine is generating CRYPTO_PRNG_KEYx"
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hexmask.long.byte 0x0 2.--5. 1. "KEYSZ,PRNG Generate Key Size\nNote: 283~571 bits are only generated for key store."
bitfld.long 0x0 1. "SEEDRLD,Reload New Seed for PRNG Engine" "0: Generating key based on the current seed,1: Reload new seed"
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bitfld.long 0x0 0. "START,Start PRNG Engine" "0: Stop PRNG engine,1: Generate new key and store the new key to.."
wgroup.long 0x4++0x3
line.long 0x0 "CRYPTO_PRNG_SEED,Seed for PRNG"
hexmask.long 0x0 0.--31. 1. "SEED,Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine.\nNote: In TRNG+PRNG mode  the seed is from TRNG engine  and it will not be stored in this register."
rgroup.long 0x8++0x23
line.long 0x0 "CRYPTO_PRNG_KEY0,PRNG Generated Key0"
hexmask.long 0x0 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x4 "CRYPTO_PRNG_KEY1,PRNG Generated Key1"
hexmask.long 0x4 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x8 "CRYPTO_PRNG_KEY2,PRNG Generated Key2"
hexmask.long 0x8 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0xC "CRYPTO_PRNG_KEY3,PRNG Generated Key3"
hexmask.long 0xC 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x10 "CRYPTO_PRNG_KEY4,PRNG Generated Key4"
hexmask.long 0x10 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x14 "CRYPTO_PRNG_KEY5,PRNG Generated Key5"
hexmask.long 0x14 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x18 "CRYPTO_PRNG_KEY6,PRNG Generated Key6"
hexmask.long 0x18 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x1C "CRYPTO_PRNG_KEY7,PRNG Generated Key7"
hexmask.long 0x1C 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
line.long 0x20 "CRYPTO_PRNG_STS,PRNG Status Register"
bitfld.long 0x20 17. "KSERR,PRNG Access Key Store Error Flag" "0: No error,1: Access key store failed"
bitfld.long 0x20 16. "KCTLERR,PRNG Key Control Register Error Flag" "0: No error,1: PRNG key control error. When PRNG execute ECDSA.."
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bitfld.long 0x20 0. "BUSY,PRNG Busy Flag" "0: PRNG engine is idle,1: PRNG engine is generating CRYPTO_PRNG_KEYx"
wgroup.long 0xEF8++0x3
line.long 0x0 "CRYPTO_PRNG_KSCTL,PRNG Key Control Register"
bitfld.long 0x0 24.--26. "OWNER,Write Key Owner Selection Bits" "0: Only for AES use,1: Only for HMAC engine use,?,?,?,?,?,?"
bitfld.long 0x0 22.--23. "WSDST,Write Key Store Destination" "0: Key is written to the SRAM of key store,1: Key is written to the Flash of key store,?,?"
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bitfld.long 0x0 21. "WDST,Write Key Destination" "0: Key is written to registers CRYPTO_PRNG_KEYx,1: Key is written to key store"
bitfld.long 0x0 20. "ECDSA,ECDSA Control Bit\nNote: When ECDSA was set to '1'  1. PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST  CRYPTO_PRNG_KSCTL[23:22] must set to '00'). Otherwise  KCTLERR will become '1'(CRYPTO_PRNG_KSSTS[16]). 2. Key.." "0: Reserved.,1: Key is written to key store and used in ECDSA"
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bitfld.long 0x0 19. "ECDH,ECDH Control Bit\nNote: When ECDH was set to '1'  1. PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST  CRYPTO_PRNG_KSCTL[23:22] must set to '00'). Otherwise  KCTLERR will become '1'(CRYPTO_PRNG_KSSTS[16]).2. Key must.." "0: Reserved.,1: Key is written to key store and used in ECDH"
bitfld.long 0x0 16. "TRUST,Write Key Trust Selection Bit" "0: Set written key as the non-secure key,1: Set written key as the secure key"
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hexmask.long.byte 0x0 0.--4. 1. "NUM,Write Key Number \nThe key number is sent to key store \nNote: Only for destination Is OTP of key store."
rgroup.long 0xEFC++0x3
line.long 0x0 "CRYPTO_PRNG_KSSTS,PRNG Key Status Register"
hexmask.long.byte 0x0 0.--4. 1. "NUM,Key Number\nThe key number is generated by key store"
tree.end
tree "RSA"
base ad:0x40032B00
group.long 0x0++0x3
line.long 0x0 "CRYPTO_RSA_CTL,RSA Control Register"
bitfld.long 0x0 8. "SCAP,Side Channel Attack Protection Enable Control" "0: Side Channel Attack Protection Disabled,1: Side Channel Attack Protection Enabled"
bitfld.long 0x0 4.--5. "KEYLENG,The Key Length of RSA Operation" "0: 1024-bits,1: 2048-bits,?,?"
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bitfld.long 0x0 3. "CRTBYP,CRT Bypass Enable Control\nCRT bypass is only used in CRT decryption with the same key.\nNote: If users want to decrypt repeatedly with the same key  they can execute CRT bypass mode after the first time CRT decryption (means the second time to.." "0: CRT Bypass Disabled,1: CRT Bypass Enabled"
bitfld.long 0x0 2. "CRT,CRT Enable Control\nCRT is only used in decryption with key length 2048  3072 4096 bits." "0: CRT Disabled,1: CRT Enabled"
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bitfld.long 0x0 1. "STOP,RSA Accelerator Stop\nThis bit is always 0 when it is read back.\nRemember to clear RSA interrupt flag after stopping RSA accelerator." "0: No effect,1: Abort RSA accelerator and make it into initial.."
bitfld.long 0x0 0. "START,RSA Accelerator Start\nThis bit is always 0 when it is read back.\nRSA accelerator will ignore this START signal when BUSY flag is 1." "0: No effect,1: Start RSA accelerator. BUSY flag will be set"
rgroup.long 0x4++0x3
line.long 0x0 "CRYPTO_RSA_STS,RSA Status Register"
bitfld.long 0x0 18. "KSERR,RSA Engine Access Key Store Error Flag" "0: No error,1: Access error will stop RSA engine"
bitfld.long 0x0 17. "CTLERR,RSA Control Register Error Flag\nNote: If users use the error combination of control  even though they don't set START(CRYPTO_RSA_CTL[0]) to 1  CTLERR will still be set to 1." "0: No error,1: RSA control error. RSA will not start in the.."
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bitfld.long 0x0 16. "BUSERR,RSA DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and RSA.."
bitfld.long 0x0 1. "DMABUSY,RSA DMA Busy Flag" "0: RSA DMA is idle or finished,1: RSA DMA is busy"
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bitfld.long 0x0 0. "BUSY,RSA Accelerator Busy Flag\nRemember to clear RSA interrupt flag after RSA accelerator finished." "0: The RSA accelerator is idle or finished,1: The RSA accelerator is under processing and.."
group.long 0x8++0x33
line.long 0x0 "CRYPTO_RSA_SADDR0,RSA DMA Source Address Register0"
hexmask.long 0x0 0.--31. 1. "SADDR0,RSA DMA Source Address Register0\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.\nThis register is stored the address of RSA the Base of Exponentiation (M)."
line.long 0x4 "CRYPTO_RSA_SADDR1,RSA DMA Source Address Register1"
hexmask.long 0x4 0.--31. 1. "SADDR1,RSA DMA Source Address Register1\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.\nThis register is stored the address of RSA the Base of Modulus Operation (N)."
line.long 0x8 "CRYPTO_RSA_SADDR2,RSA DMA Source Address Register2"
hexmask.long 0x8 0.--31. 1. "SADDR2,RSA DMA Source Address Register2\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.\nThis register is stored the address of RSA the Exponent of Exponentiation (E)."
line.long 0xC "CRYPTO_RSA_SADDR3,RSA DMA Source Address Register3"
hexmask.long 0xC 0.--31. 1. "SADDR3,RSA DMA Source Address Register3\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.\nThis register is stored the address of RSA the Factor of Modulus Operation (p)."
line.long 0x10 "CRYPTO_RSA_SADDR4,RSA DMA Source Address Register4"
hexmask.long 0x10 0.--31. 1. "SADDR4,RSA DMA Source Address Register4\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.\nThis register is stored the address of RSA the Factor of Modulus Operation (q)."
line.long 0x14 "CRYPTO_RSA_DADDR,RSA DMA Destination Address Register"
hexmask.long 0x14 0.--31. 1. "DADDR,RSA DMA Destination Address Register\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.\nThis register is stored the address of RSA DMA Destination Address Register (Ans)."
line.long 0x18 "CRYPTO_RSA_MADDR0,RSA DMA Middle Address Register0"
hexmask.long 0x18 0.--31. 1. "MADDR0,RSA DMA Middle Address Register0\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
line.long 0x1C "CRYPTO_RSA_MADDR1,RSA DMA Middle Address Register1"
hexmask.long 0x1C 0.--31. 1. "MADDR1,RSA DMA Middle Address Register1\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
line.long 0x20 "CRYPTO_RSA_MADDR2,RSA DMA Middle Address Register2"
hexmask.long 0x20 0.--31. 1. "MADDR2,RSA DMA Middle Address Register2\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
line.long 0x24 "CRYPTO_RSA_MADDR3,RSA DMA Middle Address Register3"
hexmask.long 0x24 0.--31. 1. "MADDR3,RSA DMA Middle Address Register3\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
line.long 0x28 "CRYPTO_RSA_MADDR4,RSA DMA Middle Address Register4"
hexmask.long 0x28 0.--31. 1. "MADDR4,RSA DMA Middle Address Register4\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
line.long 0x2C "CRYPTO_RSA_MADDR5,RSA DMA Middle Address Register5"
hexmask.long 0x2C 0.--31. 1. "MADDR5,RSA DMA Middle Address Register5\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
line.long 0x30 "CRYPTO_RSA_MADDR6,RSA DMA Middle Address Register6"
hexmask.long 0x30 0.--31. 1. "MADDR6,RSA DMA Middle Address Register6\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator."
wgroup.long 0x450++0x3
line.long 0x0 "CRYPTO_RSA_KSCTL,RSA Key Control Register"
hexmask.long.byte 0x0 8.--12. 1. "BKNUM,Read Exponent Blind Key Number\nThe key number is sent to key store  and its destination always be the SRAM of key store. CPU cannot read the exponent blind key.\nNote: Use this key number  only when executing SCA protection but no-CRT mode. When.."
bitfld.long 0x0 6.--7. "RSSRC,Read Key Store Source" "0: Key is read from the SRAM of key store,1: Key is read from the Flash of key store,?,?"
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bitfld.long 0x0 5. "RSRC,Read Key Source" "0: Key is read from RSA engine,1: Key is read from key store"
hexmask.long.byte 0x0 0.--4. 1. "NUM,Read Key Number\nThe key number is sent to key store"
group.long 0x454++0x7
line.long 0x0 "CRYPTO_RSA_KSSTS0,RSA Key Status Register 0"
hexmask.long.byte 0x0 24.--28. 1. "NUM3,Key Number3\nThe key number is generated by key store  RSA can get or store the intermediate temporary value by key number in the key store while operating. \nNote: The size of this key as key length."
hexmask.long.byte 0x0 16.--20. 1. "NUM2,Key Number2\nThe key number is generated by key store  RSA can get or store the intermediate temporary value by key number in the key store while operating. \nNote: The size of this key as key length."
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hexmask.long.byte 0x0 8.--12. 1. "NUM1,Key Number1\nThe key number is generated by key store  RSA can get complete q by key number in Key Store while operating. \nNote: The size of this key as half key length."
hexmask.long.byte 0x0 0.--4. 1. "NUM0,Key Number0\nThe key number is generated by key store  RSA can get complete p by key number in key store while operating. \nNote: The size of this key as half key length."
line.long 0x4 "CRYPTO_RSA_KSSTS1,RSA Key Status Register 1"
hexmask.long.byte 0x4 24.--28. 1. "NUM7,Key Number7\nThe key number is generated by key store  RSA can get or store the intermediate temporary value by key number in key store while operating. \nNote: The size of this key as key length."
hexmask.long.byte 0x4 16.--20. 1. "NUM6,Key Number6\nThe key number is generated by key store  RSA can get or store the intermediate temporary value by key number in key store while operating. \nNote: The size of this key as key length."
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hexmask.long.byte 0x4 8.--12. 1. "NUM5,Key Number5\nThe key number is generated by key store  RSA can get or store the intermediate temporary value by key number in key store while operating. \nNote: The size of this key as half key length."
hexmask.long.byte 0x4 0.--4. 1. "NUM4,Key Number4\nThe key number is generated by key store  RSA can get or store the intermediate temporary value by key number in key store while operating. \nNote: The size of this key as half key length."
tree.end
tree.end
tree "DAC (Digital to Analog Controller)"
base ad:0x40047000
group.long 0x0++0xB
line.long 0x0 "DAC0_CTL,DAC0 Control Register"
bitfld.long 0x0 16. "GRPEN,DAC Group Mode Enable Bit" "0: DAC0 and DAC1 are not grouped,1: DAC0 and DAC1 are grouped"
bitfld.long 0x0 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: data is 12 bits,1: data is 8 bits,?,?"
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bitfld.long 0x0 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,?,?"
bitfld.long 0x0 10. "LALIGN,DAC Data Left-aligned Enabled Bit" "0: Right alignment,1: Left alignment"
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bitfld.long 0x0 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
bitfld.long 0x0 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC0_ST trigger,?,?,?,?,?,?"
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bitfld.long 0x0 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
bitfld.long 0x0 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
newline
bitfld.long 0x0 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
bitfld.long 0x0 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
newline
bitfld.long 0x0 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
line.long 0x4 "DAC0_SWTRG,DAC0 Software Trigger Control Register"
bitfld.long 0x4 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; reading this bit will always get 0." "0: Software trigger Disabled,1: Software trigger Enabled"
line.long 0x8 "DAC0_DAT,DAC0 Data Holding Register"
hexmask.long.word 0x8 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC0_DAT[3:0] in left-alignment mode and DAC0_DAT[15:12] in right alignment mode) are ignored by DAC.."
rgroup.long 0xC++0x3
line.long 0x0 "DAC0_DATOUT,DAC0 Data Output Register"
hexmask.long.word 0x0 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC0_DAT register and user cannot write it directly."
group.long 0x10++0x7
line.long 0x0 "DAC0_STATUS,DAC0 Status Register"
rbitfld.long 0x0 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
bitfld.long 0x0 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit." "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
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bitfld.long 0x0 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0." "0: DAC is in conversion state,1: DAC conversion finish"
line.long 0x4 "DAC0_TCTL,DAC0 Timing Control Register"
hexmask.long.word 0x4 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example  DAC controller clock speed is 80 MHz and DAC conversion settling time is 1.."
group.long 0x30++0x3
line.long 0x0 "DAC_GRPDAT,DAC Group Mode Data Holding Register"
hexmask.long.word 0x0 16.--31. 1. "DAC1DAT,DAC1 12-bit Holding Data\nIn group mode  user can write these bits for DAC1 12-bit conversion data. The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\n12.."
hexmask.long.word 0x0 0.--15. 1. "DAC0DAT,DAC0 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC.."
group.long 0x40++0xB
line.long 0x0 "DAC1_CTL,DAC1 Control Register"
bitfld.long 0x0 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?,?"
bitfld.long 0x0 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,?,?"
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bitfld.long 0x0 10. "LALIGN,DAC Data Left-aligned Enable Control" "0: Right alignment,1: Left alignment"
bitfld.long 0x0 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
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bitfld.long 0x0 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC1_ST trigger,?,?,?,?,?,?"
bitfld.long 0x0 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
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bitfld.long 0x0 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
bitfld.long 0x0 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
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bitfld.long 0x0 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
bitfld.long 0x0 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
line.long 0x4 "DAC1_SWTRG,DAC1 Software Trigger Control Register"
bitfld.long 0x4 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0." "0: Software trigger Disabled,1: Software trigger Enabled"
line.long 0x8 "DAC1_DAT,DAC1 Data Holding Register"
hexmask.long.word 0x8 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC1_DAT[3:0] in left-alignment mode and DAC1_DAT[15:12] in right alignment mode) are ignored by DAC.."
rgroup.long 0x4C++0x3
line.long 0x0 "DAC1_DATOUT,DAC1 Data Output Register"
hexmask.long.word 0x0 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC1_DAT register and user cannot write it directly."
group.long 0x50++0x7
line.long 0x0 "DAC1_STATUS,DAC1 Status Register"
rbitfld.long 0x0 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
bitfld.long 0x0 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit." "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
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bitfld.long 0x0 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0." "0: DAC is in conversion state,1: DAC conversion finished"
line.long 0x4 "DAC1_TCTL,DAC1 Timing Control Register"
hexmask.long.word 0x4 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example  DAC controller clock speed is 80 MHz and DAC conversion settling time is 1.."
tree.end
tree "EADC (Enhanced 12-bit Analog to Digital Converter)"
base ad:0x0
tree "EADC0"
base ad:0x40043000
rgroup.long 0x0++0x4F
line.long 0x0 "EADC_DAT0,EADC Data Register 0 for Sample Module 0"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x0 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x0 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x4 "EADC_DAT1,EADC Data Register 1 for Sample Module 1"
bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x8 "EADC_DAT2,EADC Data Register 2 for Sample Module 2"
bitfld.long 0x8 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0xC "EADC_DAT3,EADC Data Register 3 for Sample Module 3"
bitfld.long 0xC 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x10 "EADC_DAT4,EADC Data Register 4 for Sample Module 4"
bitfld.long 0x10 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x14 "EADC_DAT5,EADC Data Register 5 for Sample Module 5"
bitfld.long 0x14 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x14 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x14 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x18 "EADC_DAT6,EADC Data Register 6 for Sample Module 6"
bitfld.long 0x18 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x18 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x18 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x1C "EADC_DAT7,EADC Data Register 7 for Sample Module 7"
bitfld.long 0x1C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x1C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x1C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x20 "EADC_DAT8,EADC Data Register 8 for Sample Module 8"
bitfld.long 0x20 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x20 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x20 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x24 "EADC_DAT9,EADC Data Register 9 for Sample Module 9"
bitfld.long 0x24 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x24 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x24 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x28 "EADC_DAT10,EADC Data Register 10 for Sample Module 10"
bitfld.long 0x28 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x28 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x28 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x2C "EADC_DAT11,EADC Data Register 11 for Sample Module 11"
bitfld.long 0x2C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x2C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x2C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x30 "EADC_DAT12,EADC Data Register 12 for Sample Module 12"
bitfld.long 0x30 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x30 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x30 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x34 "EADC_DAT13,EADC Data Register 13 for Sample Module 13"
bitfld.long 0x34 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x34 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x34 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x38 "EADC_DAT14,EADC Data Register 14 for Sample Module 14"
bitfld.long 0x38 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x38 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x38 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x3C "EADC_DAT15,EADC Data Register 15 for Sample Module 15"
bitfld.long 0x3C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x3C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x3C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x40 "EADC_DAT16,EADC Data Register 16 for Sample Module 16"
bitfld.long 0x40 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x40 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x40 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x44 "EADC_DAT17,EADC Data Register 17 for Sample Module 17"
bitfld.long 0x44 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x44 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x44 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x48 "EADC_DAT18,EADC Data Register 18 for Sample Module 18"
bitfld.long 0x48 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x48 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x48 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x4C "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
hexmask.long.tbyte 0x4C 0.--18. 1. "CURDAT,EADC PDMA Current Transfer Data (Read Only)"
group.long 0x50++0x3
line.long 0x0 "EADC_CTL,EADC Control Register"
hexmask.long.byte 0x0 28.--31. 1. "INTDELAY3,ADC Start Of Conversion ADINT3 Delay Cycle Selection\nStart of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
hexmask.long.byte 0x0 24.--27. 1. "INTDELAY2,ADC Start Of Conversion ADINT2 Delay Cycle Selection\nStart of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
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hexmask.long.byte 0x0 20.--23. 1. "INTDELAY1,ADC Start Of Conversion ADINT1 Delay Cycle Selection\nStart of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
hexmask.long.byte 0x0 16.--19. 1. "INTDELAY0,ADC Start Of Conversion ADINT0 Delay Cycle Selection\nStart of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
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bitfld.long 0x0 9. "DMOF,ADC Differential Input Mode Output Format" "0: ADC conversion result will be filled in RESULT..,1: ADC conversion result will be filled in RESULT.."
bitfld.long 0x0 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 5. "ADCIEN3,Specific Sample Module EADC ADINT3 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT3 interrupt..,1: Specific sample module EADC ADINT3 interrupt.."
bitfld.long 0x0 4. "ADCIEN2,Specific Sample Module EADC ADINT2 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT2 interrupt..,1: Specific sample module EADC ADINT2 interrupt.."
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bitfld.long 0x0 3. "ADCIEN1,Specific Sample Module EADC ADINT1 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT1 interrupt..,1: Specific sample module EADC ADINT1 interrupt.."
bitfld.long 0x0 2. "ADCIEN0,Specific Sample Module EADC ADINT0 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If ADCIEN0 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT0 interrupt..,1: Specific sample module EADC ADINT0 interrupt.."
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bitfld.long 0x0 1. "ADCRST,EADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset  when EADC reset end  the EADCRST bit is automatically cleared to 0." "0: No effect,1: Cause EADC control circuits reset to initial.."
bitfld.long 0x0 0. "ADCEN,EADC Converter Enable Bit\nNote: Before starting EADC conversion function  this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption." "0: EADC Disabled,1: EADC Enabled"
wgroup.long 0x54++0x3
line.long 0x0 "EADC_SWTRG,EADC Sample Module Software Start Register"
hexmask.long.tbyte 0x0 0.--18. 1. "SWTRG,EADC Sample Module 0~18 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion  the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the.."
group.long 0x58++0xB
line.long 0x0 "EADC_PENDSTS,EADC Start of Conversion Pending Flag Register"
hexmask.long.tbyte 0x0 0.--18. 1. "STPF,EADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation:"
line.long 0x4 "EADC_OVSTS,EADC Sample Module Start of Conversion Overrun Flag Register"
hexmask.long.tbyte 0x4 0.--18. 1. "SPOVF,EADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it."
line.long 0x8 "EADC_CTL1,EADC Control1 Register"
bitfld.long 0x8 23. "CMP3TRG,ADC Comparator 3 Trigger EPWM Brake Enable Bit" "0: Comparator 3 trigger EPWM brake Disabled,1: Comparator 3 trigger EPWM brake Enabled"
bitfld.long 0x8 22. "CMP2TRG,ADC Comparator 2 Trigger EPWM Brake Enable Bit" "0: Comparator 2 trigger EPWM brake Disabled,1: Comparator 2 trigger EPWM brake Enabled"
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bitfld.long 0x8 21. "CMP1TRG,ADC Comparator 1 Trigger EPWM Brake Enable Bit" "0: Comparator 1 trigger EPWM brake Disabled,1: Comparator 1 trigger EPWM brake Enabled"
bitfld.long 0x8 20. "CMP0TRG,ADC Comparator 0 Trigger EPWM Brake Enable Bit" "0: Comparator 0 trigger EPWM brake Disabled,1: Comparator 0 trigger EPWM brake Enabled"
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bitfld.long 0x8 4.--5. "RESSEL,Resolution Select Bits" "0: ADC resolution 12 bits,1: ADC resolution 10 bits,?,?"
group.long 0x80++0x4B
line.long 0x0 "EADC_SCTL0,EADC Sample Module 0 Control Register"
hexmask.long.byte 0x0 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x0 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x0 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x0 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x0 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x0 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x0 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x0 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x0 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x4 "EADC_SCTL1,EADC Sample Module 1 Control Register"
hexmask.long.byte 0x4 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x4 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x4 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x4 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x4 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x4 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x4 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x4 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x4 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x8 "EADC_SCTL2,EADC Sample Module 2 Control Register"
hexmask.long.byte 0x8 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x8 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x8 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x8 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x8 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x8 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x8 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x8 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x8 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0xC "EADC_SCTL3,EADC Sample Module 3 Control Register"
hexmask.long.byte 0xC 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0xC 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0xC 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0xC 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0xC 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0xC 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0xC 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0xC 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0xC 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x10 "EADC_SCTL4,EADC Sample Module 4 Control Register"
hexmask.long.byte 0x10 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x10 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x10 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x10 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x10 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x10 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x10 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x10 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x14 "EADC_SCTL5,EADC Sample Module 5 Control Register"
hexmask.long.byte 0x14 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x14 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x14 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x14 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x14 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x14 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x14 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x14 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x18 "EADC_SCTL6,EADC Sample Module 6 Control Register"
hexmask.long.byte 0x18 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x18 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x18 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x18 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x18 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x18 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x18 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x18 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x1C "EADC_SCTL7,EADC Sample Module 7 Control Register"
hexmask.long.byte 0x1C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x1C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x1C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x1C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x1C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x1C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x1C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x1C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x20 "EADC_SCTL8,EADC Sample Module 8 Control Register"
hexmask.long.byte 0x20 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x20 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x20 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x20 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x20 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x20 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x20 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x20 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x24 "EADC_SCTL9,EADC Sample Module 9 Control Register"
hexmask.long.byte 0x24 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x24 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x24 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x24 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x24 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x24 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x24 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x24 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x28 "EADC_SCTL10,EADC Sample Module 10 Control Register"
hexmask.long.byte 0x28 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x28 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x28 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x28 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x28 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x28 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
newline
bitfld.long 0x28 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x28 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x2C "EADC_SCTL11,EADC Sample Module 11 Control Register"
hexmask.long.byte 0x2C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x2C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x2C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x2C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x2C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x2C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x2C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x2C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x30 "EADC_SCTL12,EADC Sample Module 12 Control Register"
hexmask.long.byte 0x30 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x30 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x30 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x30 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x30 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x30 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
newline
bitfld.long 0x30 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x30 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x34 "EADC_SCTL13,EADC Sample Module 13 Control Register"
hexmask.long.byte 0x34 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x34 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x34 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x34 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x34 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x34 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
newline
bitfld.long 0x34 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x34 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x38 "EADC_SCTL14,EADC Sample Module 14 Control Register"
hexmask.long.byte 0x38 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x38 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x38 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x38 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x38 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x38 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x38 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x38 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x3C "EADC_SCTL15,EADC Sample Module 15 Control Register"
hexmask.long.byte 0x3C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x3C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x3C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x3C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x3C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x3C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x3C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x3C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x40 "EADC_SCTL16,EADC Sample Module 16 Control Register"
hexmask.long.byte 0x40 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
line.long 0x44 "EADC_SCTL17,EADC Sample Module 17 Control Register"
hexmask.long.byte 0x44 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
line.long 0x48 "EADC_SCTL18,EADC Sample Module 18 Control Register"
hexmask.long.byte 0x48 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
group.long 0xD0++0x1F
line.long 0x0 "EADC_INTSRC0,EADC Interrupt 0 Source Enable Control Register."
bitfld.long 0x0 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x0 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x0 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x0 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x0 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x0 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x0 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x0 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x0 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x0 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x0 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x0 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x0 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x0 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x0 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x0 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x0 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x0 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x0 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x4 "EADC_INTSRC1,EADC Interrupt 1 Source Enable Control Register."
bitfld.long 0x4 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x4 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x4 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x4 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x4 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x4 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x4 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x4 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x4 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x4 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x4 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x4 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x4 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x4 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x4 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x4 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x4 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x4 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x4 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x8 "EADC_INTSRC2,EADC Interrupt 2 Source Enable Control Register."
bitfld.long 0x8 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x8 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x8 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x8 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x8 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x8 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x8 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x8 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x8 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x8 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x8 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x8 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x8 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x8 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x8 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x8 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x8 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x8 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x8 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0xC "EADC_INTSRC3,EADC Interrupt 3 Source Enable Control Register."
bitfld.long 0xC 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0xC 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0xC 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0xC 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0xC 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0xC 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0xC 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0xC 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0xC 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0xC 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0xC 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0xC 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0xC 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0xC 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0xC 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0xC 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0xC 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0xC 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0xC 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x10 "EADC_CMP0,EADC Result Compare Register 0"
hexmask.long.word 0x10 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x10 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x10 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x10 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x10 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x10 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x10 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x14 "EADC_CMP1,EADC Result Compare Register 1"
hexmask.long.word 0x14 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x14 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x14 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x14 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x14 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x14 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x14 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x18 "EADC_CMP2,EADC Result Compare Register 2"
hexmask.long.word 0x18 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x18 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x18 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x18 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x18 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x18 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x18 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x1C "EADC_CMP3,EADC Result Compare Register 3"
hexmask.long.word 0x1C 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x1C 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x1C 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x1C 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x1C 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x1C 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x1C 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
rgroup.long 0xF0++0x7
line.long 0x0 "EADC_STATUS0,EADC Status Register 0"
hexmask.long.word 0x0 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
hexmask.long.word 0x0 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
line.long 0x4 "EADC_STATUS1,EADC Status Register 1"
bitfld.long 0x4 16.--18. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "VALID,EADC_DAT16~18 Data Valid Flag" "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x0 "EADC_STATUS2,EADC Status Register 2"
rbitfld.long 0x0 27. "AOV,for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1." "0: None of sample module data register overrun flag..,1: Any one of sample module data register overrun.."
rbitfld.long 0x0 26. "AVALID,for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1." "0: None of sample module data register valid flag..,1: Any one of sample module data register valid.."
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rbitfld.long 0x0 25. "STOVF,for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1." "0: None of sample module event overrun flag SPOVFn..,1: Any one of sample module event overrun flag.."
rbitfld.long 0x0 24. "ADOVIF,All EADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1." "0: None of ADINT interrupt flag ADOVIFn n=0~3 is..,1: Any one of ADINT interrupt flag ADOVIFn n=0~3 is.."
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rbitfld.long 0x0 23. "BUSY,Busy/Idle (Read Only)\nNote: This flag will be high after 4*EADC_CLK cycles when the trigger source is coming." "0: EADC is in idle state,1: EADC is busy at conversion"
hexmask.long.byte 0x0 16.--20. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x0 15. "ADCMPO3,EADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT3..,1: Conversion result in EADC_DAT great than or.."
rbitfld.long 0x0 14. "ADCMPO2,EADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT2..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x0 13. "ADCMPO1,EADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT1..,1: Conversion result in EADC_DAT great than or.."
rbitfld.long 0x0 12. "ADCMPO0,EADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT0..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x0 11. "ADOVIF3,EADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
bitfld.long 0x0 10. "ADOVIF2,EADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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bitfld.long 0x0 9. "ADOVIF1,EADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
bitfld.long 0x0 8. "ADOVIF0,EADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x0 7. "ADCMPF3,EADC Compare 3 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
bitfld.long 0x0 6. "ADCMPF2,EADC Compare 2 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x0 5. "ADCMPF1,EADC Compare 1 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
bitfld.long 0x0 4. "ADCMPF0,EADC Compare 0 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x0 3. "ADIF3,EADC ADINT3 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: This bit is cleared by writing 1 to it"
bitfld.long 0x0 2. "ADIF2,EADC ADINT2 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it. \nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT2 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 1. "ADIF1,EADC ADINT1 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: This bit is cleared by writing 1 to it"
bitfld.long 0x0 0. "ADIF0,EADC ADINT0 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: This bit is cleared by writing 1 to it"
rgroup.long 0xFC++0x13
line.long 0x0 "EADC_STATUS3,EADC Status Register 3"
hexmask.long.byte 0x0 0.--4. 1. "CURSPL,EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle  the bit filed will be set to 0x1F."
line.long 0x4 "EADC_DDAT0,EADC Double Data Register 0 for Sample Module 0"
bitfld.long 0x4 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0x8 "EADC_DDAT1,EADC Double Data Register 1 for Sample Module 1"
bitfld.long 0x8 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0xC "EADC_DDAT2,EADC Double Data Register 2 for Sample Module 2"
bitfld.long 0xC 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0x10 "EADC_DDAT3,EADC Double Data Register 3 for Sample Module 3"
bitfld.long 0x10 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
group.long 0x114++0x7
line.long 0x0 "EADC_CALCTL,EADC Calibration Control Register"
bitfld.long 0x0 1. "CALIE,Calibration Interrupt Enable Bit" "0: Calibration interrupt Disabled,1: Calibration interrupt Enabled"
bitfld.long 0x0 0. "CAL,Calibration Enable Bit\nNote: This bit is hardware auto cleared when calibration is done" "0: = Calibration Disabled,1: = Calibration Enabled"
line.long 0x4 "EADC_CALSR,EADC Calibration Status Register"
bitfld.long 0x4 16. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished  this flag will be set to 1. It is cleared by writing 1 to it." "0,1"
group.long 0x130++0x3
line.long 0x0 "EADC_PDMACTL,EADC PDMA Control Register"
hexmask.long.tbyte 0x0 0.--18. 1. "PDMATEN,PDMA Transfer Enable Bit\nWhen EADC conversion is completed  the converted data is loaded into EADC_DATn (n: 0 ~ 18) register  user can enable this bit to generate a PDMA data transfer request."
group.long 0x140++0x3F
line.long 0x0 "EADC_M0CTL1,EADC Sample Module0 Control Register 1"
hexmask.long.byte 0x0 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x0 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x0 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x4 "EADC_M1CTL1,EADC Sample Module1 Control Register 1"
hexmask.long.byte 0x4 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x4 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x4 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x8 "EADC_M2CTL1,EADC Sample Module2 Control Register 1"
hexmask.long.byte 0x8 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x8 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x8 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0xC "EADC_M3CTL1,EADC Sample Module3 Control Register 1"
hexmask.long.byte 0xC 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0xC 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0xC 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x10 "EADC_M4CTL1,EADC Sample Module4 Control Register 1"
hexmask.long.byte 0x10 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x10 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x10 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x14 "EADC_M5CTL1,EADC Sample Module5 Control Register 1"
hexmask.long.byte 0x14 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x14 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x14 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x18 "EADC_M6CTL1,EADC Sample Module6 Control Register 1"
hexmask.long.byte 0x18 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x18 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x18 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x1C "EADC_M7CTL1,EADC Sample Module7 Control Register 1"
hexmask.long.byte 0x1C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x1C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x1C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x20 "EADC_M8CTL1,EADC Sample Module8 Control Register 1"
hexmask.long.byte 0x20 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x20 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x20 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x24 "EADC_M9CTL1,EADC Sample Module9 Control Register 1"
hexmask.long.byte 0x24 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x24 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x24 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x28 "EADC_M10CTL1,EADC Sample Module10 Control Register 1"
hexmask.long.byte 0x28 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x28 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x28 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x2C "EADC_M11CTL1,EADC Sample Module11 Control Register 1"
hexmask.long.byte 0x2C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x2C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x2C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x30 "EADC_M12CTL1,EADC Sample Module12 Control Register 1"
hexmask.long.byte 0x30 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x30 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x30 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x34 "EADC_M13CTL1,EADC Sample Module13 Control Register 1"
hexmask.long.byte 0x34 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x34 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x34 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x38 "EADC_M14CTL1,EADC Sample Module14 Control Register 1"
hexmask.long.byte 0x38 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x38 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x38 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x3C "EADC_M15CTL1,EADC Sample Module15 Control Register 1"
hexmask.long.byte 0x3C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x3C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x3C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
group.long 0xFF8++0x3
line.long 0x0 "EADC_VREF,EADC Reference Voltage Control Register"
tree.end
tree "EADC1"
base ad:0x4004B000
rgroup.long 0x0++0x4F
line.long 0x0 "EADC_DAT0,EADC Data Register 0 for Sample Module 0"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x0 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x0 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x4 "EADC_DAT1,EADC Data Register 1 for Sample Module 1"
bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x8 "EADC_DAT2,EADC Data Register 2 for Sample Module 2"
bitfld.long 0x8 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0xC "EADC_DAT3,EADC Data Register 3 for Sample Module 3"
bitfld.long 0xC 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x10 "EADC_DAT4,EADC Data Register 4 for Sample Module 4"
bitfld.long 0x10 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x14 "EADC_DAT5,EADC Data Register 5 for Sample Module 5"
bitfld.long 0x14 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x14 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x14 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x18 "EADC_DAT6,EADC Data Register 6 for Sample Module 6"
bitfld.long 0x18 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x18 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x18 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x1C "EADC_DAT7,EADC Data Register 7 for Sample Module 7"
bitfld.long 0x1C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x1C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x1C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x20 "EADC_DAT8,EADC Data Register 8 for Sample Module 8"
bitfld.long 0x20 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x20 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x20 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x24 "EADC_DAT9,EADC Data Register 9 for Sample Module 9"
bitfld.long 0x24 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x24 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x24 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x28 "EADC_DAT10,EADC Data Register 10 for Sample Module 10"
bitfld.long 0x28 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x28 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x28 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x2C "EADC_DAT11,EADC Data Register 11 for Sample Module 11"
bitfld.long 0x2C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x2C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x2C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x30 "EADC_DAT12,EADC Data Register 12 for Sample Module 12"
bitfld.long 0x30 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x30 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x30 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x34 "EADC_DAT13,EADC Data Register 13 for Sample Module 13"
bitfld.long 0x34 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x34 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x34 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x38 "EADC_DAT14,EADC Data Register 14 for Sample Module 14"
bitfld.long 0x38 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x38 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x38 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x3C "EADC_DAT15,EADC Data Register 15 for Sample Module 15"
bitfld.long 0x3C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x3C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x3C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x40 "EADC_DAT16,EADC Data Register 16 for Sample Module 16"
bitfld.long 0x40 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x40 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x40 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x44 "EADC_DAT17,EADC Data Register 17 for Sample Module 17"
bitfld.long 0x44 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x44 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x44 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x48 "EADC_DAT18,EADC Data Register 18 for Sample Module 18"
bitfld.long 0x48 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x48 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x48 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x4C "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
hexmask.long.tbyte 0x4C 0.--18. 1. "CURDAT,EADC PDMA Current Transfer Data (Read Only)"
group.long 0x50++0x3
line.long 0x0 "EADC_CTL,EADC Control Register"
hexmask.long.byte 0x0 28.--31. 1. "INTDELAY3,ADC Start Of Conversion ADINT3 Delay Cycle Selection\nStart of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
hexmask.long.byte 0x0 24.--27. 1. "INTDELAY2,ADC Start Of Conversion ADINT2 Delay Cycle Selection\nStart of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
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hexmask.long.byte 0x0 20.--23. 1. "INTDELAY1,ADC Start Of Conversion ADINT1 Delay Cycle Selection\nStart of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
hexmask.long.byte 0x0 16.--19. 1. "INTDELAY0,ADC Start Of Conversion ADINT0 Delay Cycle Selection\nStart of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
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bitfld.long 0x0 9. "DMOF,ADC Differential Input Mode Output Format" "0: ADC conversion result will be filled in RESULT..,1: ADC conversion result will be filled in RESULT.."
bitfld.long 0x0 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 5. "ADCIEN3,Specific Sample Module EADC ADINT3 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT3 interrupt..,1: Specific sample module EADC ADINT3 interrupt.."
bitfld.long 0x0 4. "ADCIEN2,Specific Sample Module EADC ADINT2 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT2 interrupt..,1: Specific sample module EADC ADINT2 interrupt.."
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bitfld.long 0x0 3. "ADCIEN1,Specific Sample Module EADC ADINT1 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT1 interrupt..,1: Specific sample module EADC ADINT1 interrupt.."
bitfld.long 0x0 2. "ADCIEN0,Specific Sample Module EADC ADINT0 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If ADCIEN0 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT0 interrupt..,1: Specific sample module EADC ADINT0 interrupt.."
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bitfld.long 0x0 1. "ADCRST,EADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset  when EADC reset end  the EADCRST bit is automatically cleared to 0." "0: No effect,1: Cause EADC control circuits reset to initial.."
bitfld.long 0x0 0. "ADCEN,EADC Converter Enable Bit\nNote: Before starting EADC conversion function  this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption." "0: EADC Disabled,1: EADC Enabled"
wgroup.long 0x54++0x3
line.long 0x0 "EADC_SWTRG,EADC Sample Module Software Start Register"
hexmask.long.tbyte 0x0 0.--18. 1. "SWTRG,EADC Sample Module 0~18 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion  the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the.."
group.long 0x58++0xB
line.long 0x0 "EADC_PENDSTS,EADC Start of Conversion Pending Flag Register"
hexmask.long.tbyte 0x0 0.--18. 1. "STPF,EADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation:"
line.long 0x4 "EADC_OVSTS,EADC Sample Module Start of Conversion Overrun Flag Register"
hexmask.long.tbyte 0x4 0.--18. 1. "SPOVF,EADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it."
line.long 0x8 "EADC_CTL1,EADC Control1 Register"
bitfld.long 0x8 23. "CMP3TRG,ADC Comparator 3 Trigger EPWM Brake Enable Bit" "0: Comparator 3 trigger EPWM brake Disabled,1: Comparator 3 trigger EPWM brake Enabled"
bitfld.long 0x8 22. "CMP2TRG,ADC Comparator 2 Trigger EPWM Brake Enable Bit" "0: Comparator 2 trigger EPWM brake Disabled,1: Comparator 2 trigger EPWM brake Enabled"
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bitfld.long 0x8 21. "CMP1TRG,ADC Comparator 1 Trigger EPWM Brake Enable Bit" "0: Comparator 1 trigger EPWM brake Disabled,1: Comparator 1 trigger EPWM brake Enabled"
bitfld.long 0x8 20. "CMP0TRG,ADC Comparator 0 Trigger EPWM Brake Enable Bit" "0: Comparator 0 trigger EPWM brake Disabled,1: Comparator 0 trigger EPWM brake Enabled"
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bitfld.long 0x8 4.--5. "RESSEL,Resolution Select Bits" "0: ADC resolution 12 bits,1: ADC resolution 10 bits,?,?"
group.long 0x80++0x4B
line.long 0x0 "EADC_SCTL0,EADC Sample Module 0 Control Register"
hexmask.long.byte 0x0 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x0 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x0 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x0 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x0 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x0 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x0 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x0 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x0 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x4 "EADC_SCTL1,EADC Sample Module 1 Control Register"
hexmask.long.byte 0x4 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x4 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x4 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x4 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x4 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x4 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x4 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x4 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x4 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x8 "EADC_SCTL2,EADC Sample Module 2 Control Register"
hexmask.long.byte 0x8 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x8 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x8 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x8 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x8 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x8 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x8 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x8 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x8 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0xC "EADC_SCTL3,EADC Sample Module 3 Control Register"
hexmask.long.byte 0xC 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0xC 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0xC 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0xC 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0xC 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0xC 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0xC 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0xC 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0xC 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x10 "EADC_SCTL4,EADC Sample Module 4 Control Register"
hexmask.long.byte 0x10 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x10 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x10 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x10 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x10 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x10 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x10 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x10 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x14 "EADC_SCTL5,EADC Sample Module 5 Control Register"
hexmask.long.byte 0x14 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x14 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x14 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x14 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x14 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x14 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x14 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x14 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x18 "EADC_SCTL6,EADC Sample Module 6 Control Register"
hexmask.long.byte 0x18 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x18 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x18 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x18 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x18 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x18 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x18 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x18 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x1C "EADC_SCTL7,EADC Sample Module 7 Control Register"
hexmask.long.byte 0x1C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x1C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x1C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x1C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x1C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x1C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x1C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x1C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x20 "EADC_SCTL8,EADC Sample Module 8 Control Register"
hexmask.long.byte 0x20 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x20 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x20 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x20 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x20 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x20 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x20 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x20 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x24 "EADC_SCTL9,EADC Sample Module 9 Control Register"
hexmask.long.byte 0x24 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x24 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x24 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x24 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x24 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x24 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x24 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x24 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x28 "EADC_SCTL10,EADC Sample Module 10 Control Register"
hexmask.long.byte 0x28 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x28 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x28 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x28 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x28 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x28 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x28 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x28 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x2C "EADC_SCTL11,EADC Sample Module 11 Control Register"
hexmask.long.byte 0x2C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x2C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x2C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x2C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x2C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x2C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x2C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x2C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x30 "EADC_SCTL12,EADC Sample Module 12 Control Register"
hexmask.long.byte 0x30 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x30 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x30 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x30 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x30 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x30 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x30 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x30 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x34 "EADC_SCTL13,EADC Sample Module 13 Control Register"
hexmask.long.byte 0x34 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x34 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x34 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x34 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x34 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x34 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x34 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x34 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x38 "EADC_SCTL14,EADC Sample Module 14 Control Register"
hexmask.long.byte 0x38 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x38 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x38 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x38 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x38 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x38 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x38 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x38 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x3C "EADC_SCTL15,EADC Sample Module 15 Control Register"
hexmask.long.byte 0x3C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x3C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x3C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x3C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x3C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x3C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x3C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x3C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x40 "EADC_SCTL16,EADC Sample Module 16 Control Register"
hexmask.long.byte 0x40 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
line.long 0x44 "EADC_SCTL17,EADC Sample Module 17 Control Register"
hexmask.long.byte 0x44 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
line.long 0x48 "EADC_SCTL18,EADC Sample Module 18 Control Register"
hexmask.long.byte 0x48 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
group.long 0xD0++0x1F
line.long 0x0 "EADC_INTSRC0,EADC Interrupt 0 Source Enable Control Register."
bitfld.long 0x0 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x0 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x0 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x0 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x0 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x0 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x0 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x0 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x0 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x0 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x0 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x0 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x0 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x0 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x0 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x0 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x0 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x0 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x0 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x4 "EADC_INTSRC1,EADC Interrupt 1 Source Enable Control Register."
bitfld.long 0x4 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x4 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x4 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x4 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x4 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x4 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x4 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x4 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x4 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x4 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x4 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x4 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x4 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x4 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x4 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x4 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x4 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x4 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x4 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x8 "EADC_INTSRC2,EADC Interrupt 2 Source Enable Control Register."
bitfld.long 0x8 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x8 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x8 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x8 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x8 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x8 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x8 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x8 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x8 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x8 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x8 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x8 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x8 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x8 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x8 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x8 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x8 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x8 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x8 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0xC "EADC_INTSRC3,EADC Interrupt 3 Source Enable Control Register."
bitfld.long 0xC 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0xC 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0xC 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0xC 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0xC 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0xC 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0xC 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0xC 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0xC 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0xC 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0xC 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0xC 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0xC 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0xC 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0xC 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0xC 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0xC 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0xC 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0xC 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x10 "EADC_CMP0,EADC Result Compare Register 0"
hexmask.long.word 0x10 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x10 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x10 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x10 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x10 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x10 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x10 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x14 "EADC_CMP1,EADC Result Compare Register 1"
hexmask.long.word 0x14 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x14 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x14 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x14 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x14 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x14 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x14 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x18 "EADC_CMP2,EADC Result Compare Register 2"
hexmask.long.word 0x18 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x18 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x18 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x18 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x18 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x18 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x18 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x1C "EADC_CMP3,EADC Result Compare Register 3"
hexmask.long.word 0x1C 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x1C 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x1C 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x1C 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x1C 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x1C 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x1C 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
rgroup.long 0xF0++0x7
line.long 0x0 "EADC_STATUS0,EADC Status Register 0"
hexmask.long.word 0x0 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
hexmask.long.word 0x0 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
line.long 0x4 "EADC_STATUS1,EADC Status Register 1"
bitfld.long 0x4 16.--18. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "VALID,EADC_DAT16~18 Data Valid Flag" "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x0 "EADC_STATUS2,EADC Status Register 2"
rbitfld.long 0x0 27. "AOV,for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1." "0: None of sample module data register overrun flag..,1: Any one of sample module data register overrun.."
rbitfld.long 0x0 26. "AVALID,for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1." "0: None of sample module data register valid flag..,1: Any one of sample module data register valid.."
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rbitfld.long 0x0 25. "STOVF,for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1." "0: None of sample module event overrun flag SPOVFn..,1: Any one of sample module event overrun flag.."
rbitfld.long 0x0 24. "ADOVIF,All EADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1." "0: None of ADINT interrupt flag ADOVIFn n=0~3 is..,1: Any one of ADINT interrupt flag ADOVIFn n=0~3 is.."
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rbitfld.long 0x0 23. "BUSY,Busy/Idle (Read Only)\nNote: This flag will be high after 4*EADC_CLK cycles when the trigger source is coming." "0: EADC is in idle state,1: EADC is busy at conversion"
hexmask.long.byte 0x0 16.--20. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x0 15. "ADCMPO3,EADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT3..,1: Conversion result in EADC_DAT great than or.."
rbitfld.long 0x0 14. "ADCMPO2,EADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT2..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x0 13. "ADCMPO1,EADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT1..,1: Conversion result in EADC_DAT great than or.."
rbitfld.long 0x0 12. "ADCMPO0,EADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT0..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x0 11. "ADOVIF3,EADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
bitfld.long 0x0 10. "ADOVIF2,EADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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bitfld.long 0x0 9. "ADOVIF1,EADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
bitfld.long 0x0 8. "ADOVIF0,EADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x0 7. "ADCMPF3,EADC Compare 3 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
bitfld.long 0x0 6. "ADCMPF2,EADC Compare 2 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x0 5. "ADCMPF1,EADC Compare 1 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
bitfld.long 0x0 4. "ADCMPF0,EADC Compare 0 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x0 3. "ADIF3,EADC ADINT3 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: This bit is cleared by writing 1 to it"
bitfld.long 0x0 2. "ADIF2,EADC ADINT2 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it. \nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT2 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 1. "ADIF1,EADC ADINT1 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: This bit is cleared by writing 1 to it"
bitfld.long 0x0 0. "ADIF0,EADC ADINT0 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: This bit is cleared by writing 1 to it"
rgroup.long 0xFC++0x13
line.long 0x0 "EADC_STATUS3,EADC Status Register 3"
hexmask.long.byte 0x0 0.--4. 1. "CURSPL,EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle  the bit filed will be set to 0x1F."
line.long 0x4 "EADC_DDAT0,EADC Double Data Register 0 for Sample Module 0"
bitfld.long 0x4 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0x8 "EADC_DDAT1,EADC Double Data Register 1 for Sample Module 1"
bitfld.long 0x8 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0xC "EADC_DDAT2,EADC Double Data Register 2 for Sample Module 2"
bitfld.long 0xC 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0x10 "EADC_DDAT3,EADC Double Data Register 3 for Sample Module 3"
bitfld.long 0x10 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
group.long 0x114++0x7
line.long 0x0 "EADC_CALCTL,EADC Calibration Control Register"
bitfld.long 0x0 1. "CALIE,Calibration Interrupt Enable Bit" "0: Calibration interrupt Disabled,1: Calibration interrupt Enabled"
bitfld.long 0x0 0. "CAL,Calibration Enable Bit\nNote: This bit is hardware auto cleared when calibration is done" "0: = Calibration Disabled,1: = Calibration Enabled"
line.long 0x4 "EADC_CALSR,EADC Calibration Status Register"
bitfld.long 0x4 16. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished  this flag will be set to 1. It is cleared by writing 1 to it." "0,1"
group.long 0x130++0x3
line.long 0x0 "EADC_PDMACTL,EADC PDMA Control Register"
hexmask.long.tbyte 0x0 0.--18. 1. "PDMATEN,PDMA Transfer Enable Bit\nWhen EADC conversion is completed  the converted data is loaded into EADC_DATn (n: 0 ~ 18) register  user can enable this bit to generate a PDMA data transfer request."
group.long 0x140++0x3F
line.long 0x0 "EADC_M0CTL1,EADC Sample Module0 Control Register 1"
hexmask.long.byte 0x0 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x0 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x0 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x4 "EADC_M1CTL1,EADC Sample Module1 Control Register 1"
hexmask.long.byte 0x4 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x4 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x4 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x8 "EADC_M2CTL1,EADC Sample Module2 Control Register 1"
hexmask.long.byte 0x8 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x8 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x8 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0xC "EADC_M3CTL1,EADC Sample Module3 Control Register 1"
hexmask.long.byte 0xC 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0xC 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0xC 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x10 "EADC_M4CTL1,EADC Sample Module4 Control Register 1"
hexmask.long.byte 0x10 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x10 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x10 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x14 "EADC_M5CTL1,EADC Sample Module5 Control Register 1"
hexmask.long.byte 0x14 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x14 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x14 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x18 "EADC_M6CTL1,EADC Sample Module6 Control Register 1"
hexmask.long.byte 0x18 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x18 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x18 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x1C "EADC_M7CTL1,EADC Sample Module7 Control Register 1"
hexmask.long.byte 0x1C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x1C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x1C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x20 "EADC_M8CTL1,EADC Sample Module8 Control Register 1"
hexmask.long.byte 0x20 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x20 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x20 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x24 "EADC_M9CTL1,EADC Sample Module9 Control Register 1"
hexmask.long.byte 0x24 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x24 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x24 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x28 "EADC_M10CTL1,EADC Sample Module10 Control Register 1"
hexmask.long.byte 0x28 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x28 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x28 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x2C "EADC_M11CTL1,EADC Sample Module11 Control Register 1"
hexmask.long.byte 0x2C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x2C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x2C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x30 "EADC_M12CTL1,EADC Sample Module12 Control Register 1"
hexmask.long.byte 0x30 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x30 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x30 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x34 "EADC_M13CTL1,EADC Sample Module13 Control Register 1"
hexmask.long.byte 0x34 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x34 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x34 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x38 "EADC_M14CTL1,EADC Sample Module14 Control Register 1"
hexmask.long.byte 0x38 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x38 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x38 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x3C "EADC_M15CTL1,EADC Sample Module15 Control Register 1"
hexmask.long.byte 0x3C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x3C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x3C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
group.long 0xFF8++0x3
line.long 0x0 "EADC_VREF,EADC Reference Voltage Control Register"
tree.end
tree "EADC2"
base ad:0x40097000
rgroup.long 0x0++0x4F
line.long 0x0 "EADC_DAT0,EADC Data Register 0 for Sample Module 0"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x0 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x0 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x4 "EADC_DAT1,EADC Data Register 1 for Sample Module 1"
bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x8 "EADC_DAT2,EADC Data Register 2 for Sample Module 2"
bitfld.long 0x8 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0xC "EADC_DAT3,EADC Data Register 3 for Sample Module 3"
bitfld.long 0xC 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x10 "EADC_DAT4,EADC Data Register 4 for Sample Module 4"
bitfld.long 0x10 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x14 "EADC_DAT5,EADC Data Register 5 for Sample Module 5"
bitfld.long 0x14 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x14 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x14 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x18 "EADC_DAT6,EADC Data Register 6 for Sample Module 6"
bitfld.long 0x18 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x18 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x18 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x1C "EADC_DAT7,EADC Data Register 7 for Sample Module 7"
bitfld.long 0x1C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x1C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x1C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x20 "EADC_DAT8,EADC Data Register 8 for Sample Module 8"
bitfld.long 0x20 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x20 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x20 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x24 "EADC_DAT9,EADC Data Register 9 for Sample Module 9"
bitfld.long 0x24 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x24 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x24 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x28 "EADC_DAT10,EADC Data Register 10 for Sample Module 10"
bitfld.long 0x28 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x28 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x28 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x2C "EADC_DAT11,EADC Data Register 11 for Sample Module 11"
bitfld.long 0x2C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x2C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x2C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x30 "EADC_DAT12,EADC Data Register 12 for Sample Module 12"
bitfld.long 0x30 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x30 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x30 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x34 "EADC_DAT13,EADC Data Register 13 for Sample Module 13"
bitfld.long 0x34 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x34 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x34 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x38 "EADC_DAT14,EADC Data Register 14 for Sample Module 14"
bitfld.long 0x38 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x38 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x38 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x3C "EADC_DAT15,EADC Data Register 15 for Sample Module 15"
bitfld.long 0x3C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x3C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x3C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x40 "EADC_DAT16,EADC Data Register 16 for Sample Module 16"
bitfld.long 0x40 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x40 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x40 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x44 "EADC_DAT17,EADC Data Register 17 for Sample Module 17"
bitfld.long 0x44 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x44 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x44 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x48 "EADC_DAT18,EADC Data Register 18 for Sample Module 18"
bitfld.long 0x48 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
bitfld.long 0x48 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register  OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x48 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
line.long 0x4C "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
hexmask.long.tbyte 0x4C 0.--18. 1. "CURDAT,EADC PDMA Current Transfer Data (Read Only)"
group.long 0x50++0x3
line.long 0x0 "EADC_CTL,EADC Control Register"
hexmask.long.byte 0x0 28.--31. 1. "INTDELAY3,ADC Start Of Conversion ADINT3 Delay Cycle Selection\nStart of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
hexmask.long.byte 0x0 24.--27. 1. "INTDELAY2,ADC Start Of Conversion ADINT2 Delay Cycle Selection\nStart of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
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hexmask.long.byte 0x0 20.--23. 1. "INTDELAY1,ADC Start Of Conversion ADINT1 Delay Cycle Selection\nStart of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
hexmask.long.byte 0x0 16.--19. 1. "INTDELAY0,ADC Start Of Conversion ADINT0 Delay Cycle Selection\nStart of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt. The function supports delay 1 PCLK to 15 PCLK cycles. User can select one of the options.."
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bitfld.long 0x0 9. "DMOF,ADC Differential Input Mode Output Format" "0: ADC conversion result will be filled in RESULT..,1: ADC conversion result will be filled in RESULT.."
bitfld.long 0x0 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 5. "ADCIEN3,Specific Sample Module EADC ADINT3 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT3 interrupt..,1: Specific sample module EADC ADINT3 interrupt.."
bitfld.long 0x0 4. "ADCIEN2,Specific Sample Module EADC ADINT2 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT2 interrupt..,1: Specific sample module EADC ADINT2 interrupt.."
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bitfld.long 0x0 3. "ADCIEN1,Specific Sample Module EADC ADINT1 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT1 interrupt..,1: Specific sample module EADC ADINT1 interrupt.."
bitfld.long 0x0 2. "ADCIEN0,Specific Sample Module EADC ADINT0 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If ADCIEN0 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT0 interrupt..,1: Specific sample module EADC ADINT0 interrupt.."
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bitfld.long 0x0 1. "ADCRST,EADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset  when EADC reset end  the EADCRST bit is automatically cleared to 0." "0: No effect,1: Cause EADC control circuits reset to initial.."
bitfld.long 0x0 0. "ADCEN,EADC Converter Enable Bit\nNote: Before starting EADC conversion function  this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption." "0: EADC Disabled,1: EADC Enabled"
wgroup.long 0x54++0x3
line.long 0x0 "EADC_SWTRG,EADC Sample Module Software Start Register"
hexmask.long.tbyte 0x0 0.--18. 1. "SWTRG,EADC Sample Module 0~18 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion  the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the.."
group.long 0x58++0xB
line.long 0x0 "EADC_PENDSTS,EADC Start of Conversion Pending Flag Register"
hexmask.long.tbyte 0x0 0.--18. 1. "STPF,EADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation:"
line.long 0x4 "EADC_OVSTS,EADC Sample Module Start of Conversion Overrun Flag Register"
hexmask.long.tbyte 0x4 0.--18. 1. "SPOVF,EADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it."
line.long 0x8 "EADC_CTL1,EADC Control1 Register"
bitfld.long 0x8 23. "CMP3TRG,ADC Comparator 3 Trigger EPWM Brake Enable Bit" "0: Comparator 3 trigger EPWM brake Disabled,1: Comparator 3 trigger EPWM brake Enabled"
bitfld.long 0x8 22. "CMP2TRG,ADC Comparator 2 Trigger EPWM Brake Enable Bit" "0: Comparator 2 trigger EPWM brake Disabled,1: Comparator 2 trigger EPWM brake Enabled"
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bitfld.long 0x8 21. "CMP1TRG,ADC Comparator 1 Trigger EPWM Brake Enable Bit" "0: Comparator 1 trigger EPWM brake Disabled,1: Comparator 1 trigger EPWM brake Enabled"
bitfld.long 0x8 20. "CMP0TRG,ADC Comparator 0 Trigger EPWM Brake Enable Bit" "0: Comparator 0 trigger EPWM brake Disabled,1: Comparator 0 trigger EPWM brake Enabled"
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bitfld.long 0x8 4.--5. "RESSEL,Resolution Select Bits" "0: ADC resolution 12 bits,1: ADC resolution 10 bits,?,?"
group.long 0x80++0x4B
line.long 0x0 "EADC_SCTL0,EADC Sample Module 0 Control Register"
hexmask.long.byte 0x0 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x0 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x0 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x0 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x0 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x0 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x0 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x0 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x0 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x4 "EADC_SCTL1,EADC Sample Module 1 Control Register"
hexmask.long.byte 0x4 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x4 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x4 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x4 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x4 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x4 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x4 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x4 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x4 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x8 "EADC_SCTL2,EADC Sample Module 2 Control Register"
hexmask.long.byte 0x8 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0x8 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x8 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0x8 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x8 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0x8 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x8 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0x8 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x8 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0xC "EADC_SCTL3,EADC Sample Module 3 Control Register"
hexmask.long.byte 0xC 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and user can extend EADC sampling time after trigger source is coming to get.."
bitfld.long 0xC 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0xC 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
bitfld.long 0xC 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0xC 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
hexmask.long.byte 0xC 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0xC 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
bitfld.long 0xC 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0xC 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x10 "EADC_SCTL4,EADC Sample Module 4 Control Register"
hexmask.long.byte 0x10 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x10 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x10 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x10 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x10 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x10 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x10 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x10 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x14 "EADC_SCTL5,EADC Sample Module 5 Control Register"
hexmask.long.byte 0x14 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x14 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x14 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x14 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x14 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x14 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x14 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x14 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x18 "EADC_SCTL6,EADC Sample Module 6 Control Register"
hexmask.long.byte 0x18 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x18 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x18 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x18 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x18 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x18 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x18 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x18 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x1C "EADC_SCTL7,EADC Sample Module 7 Control Register"
hexmask.long.byte 0x1C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x1C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x1C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x1C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x1C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x1C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x1C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x1C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x20 "EADC_SCTL8,EADC Sample Module 8 Control Register"
hexmask.long.byte 0x20 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x20 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x20 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x20 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x20 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x20 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x20 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x20 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x24 "EADC_SCTL9,EADC Sample Module 9 Control Register"
hexmask.long.byte 0x24 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x24 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x24 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x24 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x24 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x24 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x24 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x24 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x28 "EADC_SCTL10,EADC Sample Module 10 Control Register"
hexmask.long.byte 0x28 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x28 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x28 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x28 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x28 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x28 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x28 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x28 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x2C "EADC_SCTL11,EADC Sample Module 11 Control Register"
hexmask.long.byte 0x2C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x2C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x2C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x2C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x2C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x2C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x2C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x2C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x30 "EADC_SCTL12,EADC Sample Module 12 Control Register"
hexmask.long.byte 0x30 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x30 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x30 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x30 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x30 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x30 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x30 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x30 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x34 "EADC_SCTL13,EADC Sample Module 13 Control Register"
hexmask.long.byte 0x34 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x34 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x34 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x34 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x34 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x34 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
newline
bitfld.long 0x34 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x34 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x38 "EADC_SCTL14,EADC Sample Module 14 Control Register"
hexmask.long.byte 0x38 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x38 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x38 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x38 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x38 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x38 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
newline
bitfld.long 0x38 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x38 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x3C "EADC_SCTL15,EADC Sample Module 15 Control Register"
hexmask.long.byte 0x3C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not be enough if input channel loading is heavy  and software can extend EADC sampling time after trigger source is coming to.."
bitfld.long 0x3C 22. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x3C 21. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
hexmask.long.byte 0x3C 16.--20. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x3C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
bitfld.long 0x3C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
newline
bitfld.long 0x3C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
hexmask.long.byte 0x3C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
line.long 0x40 "EADC_SCTL16,EADC Sample Module 16 Control Register"
hexmask.long.byte 0x40 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
line.long 0x44 "EADC_SCTL17,EADC Sample Module 17 Control Register"
hexmask.long.byte 0x44 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
line.long 0x48 "EADC_SCTL18,EADC Sample Module 18 Control Register"
hexmask.long.byte 0x48 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate  the sampling time of analog input voltage may not enough if input channel loading is heavy  SW can extend ADC sampling time after trigger source is coming to get enough.."
group.long 0xD0++0x1F
line.long 0x0 "EADC_INTSRC0,EADC Interrupt 0 Source Enable Control Register."
bitfld.long 0x0 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x0 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x0 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x0 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x0 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x0 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x0 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x0 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x0 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x0 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x0 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x0 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x0 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x0 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x0 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x0 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x0 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x0 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x0 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x4 "EADC_INTSRC1,EADC Interrupt 1 Source Enable Control Register."
bitfld.long 0x4 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x4 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x4 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x4 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x4 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x4 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x4 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x4 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x4 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x4 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x4 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x4 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x4 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x4 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x4 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x4 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x4 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x4 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x4 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x8 "EADC_INTSRC2,EADC Interrupt 2 Source Enable Control Register."
bitfld.long 0x8 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0x8 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x8 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0x8 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x8 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0x8 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x8 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0x8 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x8 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0x8 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x8 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0x8 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x8 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0x8 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x8 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0x8 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x8 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0x8 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x8 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0xC "EADC_INTSRC3,EADC Interrupt 3 Source Enable Control Register."
bitfld.long 0xC 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
bitfld.long 0xC 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0xC 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
bitfld.long 0xC 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0xC 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
bitfld.long 0xC 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0xC 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
bitfld.long 0xC 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0xC 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
bitfld.long 0xC 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0xC 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
bitfld.long 0xC 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0xC 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
bitfld.long 0xC 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0xC 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
bitfld.long 0xC 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0xC 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
bitfld.long 0xC 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0xC 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
line.long 0x10 "EADC_CMP0,EADC Result Compare Register 0"
hexmask.long.word 0x10 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x10 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x10 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x10 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x10 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x10 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x10 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x14 "EADC_CMP1,EADC Result Compare Register 1"
hexmask.long.word 0x14 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x14 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x14 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x14 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x14 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x14 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x14 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x18 "EADC_CMP2,EADC Result Compare Register 2"
hexmask.long.word 0x18 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x18 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x18 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x18 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x18 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x18 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x18 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
line.long 0x1C "EADC_CMP3,EADC Result Compare Register 3"
hexmask.long.word 0x1C 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
bitfld.long 0x1C 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode  the CMPCNT setting only follow EADC_CMP0  EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x1C 8.--11. 1. "CMPMCNT,Compare Match Count"
hexmask.long.byte 0x1C 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x1C 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
bitfld.long 0x1C 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x1C 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
rgroup.long 0xF0++0x7
line.long 0x0 "EADC_STATUS0,EADC Status Register 0"
hexmask.long.word 0x0 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
hexmask.long.word 0x0 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
line.long 0x4 "EADC_STATUS1,EADC Status Register 1"
bitfld.long 0x4 16.--18. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "VALID,EADC_DAT16~18 Data Valid Flag" "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x0 "EADC_STATUS2,EADC Status Register 2"
rbitfld.long 0x0 27. "AOV,for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1." "0: None of sample module data register overrun flag..,1: Any one of sample module data register overrun.."
rbitfld.long 0x0 26. "AVALID,for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1." "0: None of sample module data register valid flag..,1: Any one of sample module data register valid.."
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rbitfld.long 0x0 25. "STOVF,for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1." "0: None of sample module event overrun flag SPOVFn..,1: Any one of sample module event overrun flag.."
rbitfld.long 0x0 24. "ADOVIF,All EADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1." "0: None of ADINT interrupt flag ADOVIFn n=0~3 is..,1: Any one of ADINT interrupt flag ADOVIFn n=0~3 is.."
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rbitfld.long 0x0 23. "BUSY,Busy/Idle (Read Only)\nNote: This flag will be high after 4*EADC_CLK cycles when the trigger source is coming." "0: EADC is in idle state,1: EADC is busy at conversion"
hexmask.long.byte 0x0 16.--20. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x0 15. "ADCMPO3,EADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT3..,1: Conversion result in EADC_DAT great than or.."
rbitfld.long 0x0 14. "ADCMPO2,EADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT2..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x0 13. "ADCMPO1,EADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT1..,1: Conversion result in EADC_DAT great than or.."
rbitfld.long 0x0 12. "ADCMPO0,EADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT0..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x0 11. "ADOVIF3,EADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
bitfld.long 0x0 10. "ADOVIF2,EADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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bitfld.long 0x0 9. "ADOVIF1,EADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
bitfld.long 0x0 8. "ADOVIF0,EADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x0 7. "ADCMPF3,EADC Compare 3 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
bitfld.long 0x0 6. "ADCMPF2,EADC Compare 2 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x0 5. "ADCMPF1,EADC Compare 1 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
bitfld.long 0x0 4. "ADCMPF0,EADC Compare 0 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x0 3. "ADIF3,EADC ADINT3 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: This bit is cleared by writing 1 to it"
bitfld.long 0x0 2. "ADIF2,EADC ADINT2 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it. \nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT2 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 1. "ADIF1,EADC ADINT1 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: This bit is cleared by writing 1 to it"
bitfld.long 0x0 0. "ADIF0,EADC ADINT0 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: This bit is cleared by writing 1 to it"
rgroup.long 0xFC++0x13
line.long 0x0 "EADC_STATUS3,EADC Status Register 3"
hexmask.long.byte 0x0 0.--4. 1. "CURSPL,EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle  the bit filed will be set to 0x1F."
line.long 0x4 "EADC_DDAT0,EADC Double Data Register 0 for Sample Module 0"
bitfld.long 0x4 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0x8 "EADC_DDAT1,EADC Double Data Register 1 for Sample Module 1"
bitfld.long 0x8 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0xC "EADC_DDAT2,EADC Double Data Register 2 for Sample Module 2"
bitfld.long 0xC 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
line.long 0x10 "EADC_DDAT3,EADC Double Data Register 3 for Sample Module 3"
bitfld.long 0x10 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register  OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
group.long 0x114++0x7
line.long 0x0 "EADC_CALCTL,EADC Calibration Control Register"
bitfld.long 0x0 1. "CALIE,Calibration Interrupt Enable Bit" "0: Calibration interrupt Disabled,1: Calibration interrupt Enabled"
bitfld.long 0x0 0. "CAL,Calibration Enable Bit\nNote: This bit is hardware auto cleared when calibration is done" "0: = Calibration Disabled,1: = Calibration Enabled"
line.long 0x4 "EADC_CALSR,EADC Calibration Status Register"
bitfld.long 0x4 16. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished  this flag will be set to 1. It is cleared by writing 1 to it." "0,1"
group.long 0x130++0x3
line.long 0x0 "EADC_PDMACTL,EADC PDMA Control Register"
hexmask.long.tbyte 0x0 0.--18. 1. "PDMATEN,PDMA Transfer Enable Bit\nWhen EADC conversion is completed  the converted data is loaded into EADC_DATn (n: 0 ~ 18) register  user can enable this bit to generate a PDMA data transfer request."
group.long 0x140++0x3F
line.long 0x0 "EADC_M0CTL1,EADC Sample Module0 Control Register 1"
hexmask.long.byte 0x0 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x0 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x0 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x4 "EADC_M1CTL1,EADC Sample Module1 Control Register 1"
hexmask.long.byte 0x4 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x4 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x4 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x8 "EADC_M2CTL1,EADC Sample Module2 Control Register 1"
hexmask.long.byte 0x8 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x8 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x8 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0xC "EADC_M3CTL1,EADC Sample Module3 Control Register 1"
hexmask.long.byte 0xC 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0xC 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0xC 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x10 "EADC_M4CTL1,EADC Sample Module4 Control Register 1"
hexmask.long.byte 0x10 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x10 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x10 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x14 "EADC_M5CTL1,EADC Sample Module5 Control Register 1"
hexmask.long.byte 0x14 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x14 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x14 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x18 "EADC_M6CTL1,EADC Sample Module6 Control Register 1"
hexmask.long.byte 0x18 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x18 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x18 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x1C "EADC_M7CTL1,EADC Sample Module7 Control Register 1"
hexmask.long.byte 0x1C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x1C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x1C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x20 "EADC_M8CTL1,EADC Sample Module8 Control Register 1"
hexmask.long.byte 0x20 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x20 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x20 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x24 "EADC_M9CTL1,EADC Sample Module9 Control Register 1"
hexmask.long.byte 0x24 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x24 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x24 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x28 "EADC_M10CTL1,EADC Sample Module10 Control Register 1"
hexmask.long.byte 0x28 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x28 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x28 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x2C "EADC_M11CTL1,EADC Sample Module11 Control Register 1"
hexmask.long.byte 0x2C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x2C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x2C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x30 "EADC_M12CTL1,EADC Sample Module12 Control Register 1"
hexmask.long.byte 0x30 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x30 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x30 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x34 "EADC_M13CTL1,EADC Sample Module13 Control Register 1"
hexmask.long.byte 0x34 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x34 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x34 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x38 "EADC_M14CTL1,EADC Sample Module14 Control Register 1"
hexmask.long.byte 0x38 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x38 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x38 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
line.long 0x3C "EADC_M15CTL1,EADC Sample Module15 Control Register 1"
hexmask.long.byte 0x3C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
bitfld.long 0x3C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x3C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
group.long 0xFF8++0x3
line.long 0x0 "EADC_VREF,EADC Reference Voltage Control Register"
tree.end
tree.end
tree "EBI (External Bus Interface)"
base ad:0x40010000
group.long 0x0++0x7
line.long 0x0 "EBI_CTL0,External Bus Interface Bank0 Control Register"
bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register." "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled  the tASU  tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x0 3. "ADSEPEN,EBI Address/Data Bus Separate Mode Enable Bit" "0: Address/Data Bus Separate Mode Disabled,1: Address/Data Bus Separate Mode Enabled"
bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
bitfld.long 0x0 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
line.long 0x4 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read  R2R idle cycle is inserted and EBI_nCS return to idle state."
bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.."
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.."
hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished  W2X idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)."
group.long 0x10++0x7
line.long 0x0 "EBI_CTL1,External Bus Interface Bank1 Control Register"
bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register." "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled  the tASU  tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x0 3. "ADSEPEN,EBI Address/Data Bus Separate Mode Enable Bit" "0: Address/Data Bus Separate Mode Disabled,1: Address/Data Bus Separate Mode Enabled"
bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
bitfld.long 0x0 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
line.long 0x4 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read  R2R idle cycle is inserted and EBI_nCS return to idle state."
bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.."
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.."
hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished  W2X idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)."
group.long 0x20++0x7
line.long 0x0 "EBI_CTL2,External Bus Interface Bank2 Control Register"
bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register." "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled  the tASU  tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x0 3. "ADSEPEN,EBI Address/Data Bus Separate Mode Enable Bit" "0: Address/Data Bus Separate Mode Disabled,1: Address/Data Bus Separate Mode Enabled"
bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
bitfld.long 0x0 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
line.long 0x4 "EBI_TCTL2,External Bus Interface Bank2 Timing Control Register"
hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read  R2R idle cycle is inserted and EBI_nCS return to idle state."
bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.."
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.."
hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished  W2X idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)."
tree.end
tree "ECAP (Enhanced Input Capture Timer)"
base ad:0x0
tree "ECAP0"
base ad:0x400B4000
group.long 0x0++0x1F
line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP  if ECAP_CNT value reaches ECAP_CNTCMP  the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
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bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1  the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the ." "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: CAP2 input is from ACMP2 output,?,?"
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bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: CAP1 input is from ACMP1 output,?,?"
bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: CAP0 input is from ACMP0 output,?,?"
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bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Bit" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Bit" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Bit" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Bit" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: ECAP_CLK,1: ECAP_CLK/2,?,?,?,?,?,?"
line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: ECAP_CLK (default),1: CAP0,?,?"
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bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: ECAP_CLK/1,1: ECAP_CLK/4,?,?,?,?,?,?"
bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only  rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
rbitfld.long 0x1C 8. "CAP2,Value of Input Channel 2  CAP2 (Read Only)\nReflecting the value of input channel 2  CAP2.\nNote: The bit is read only and write is ignored." "0,1"
rbitfld.long 0x1C 7. "CAP1,Value of Input Channel 1  CAP1 (Read Only)\nReflecting the value of input channel 1  CAP1\nNote: The bit is read only and write is ignored." "0,1"
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rbitfld.long 0x1C 6. "CAP0,Value of Input Channel 0  CAP0 (Read Only)\nReflecting the value of input channel 0  CAP0\nNote: The bit is read only and write is ignored." "0,1"
bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled  the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input  it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input  it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input  it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
tree.end
tree "ECAP1"
base ad:0x400B5000
group.long 0x0++0x1F
line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP  if ECAP_CNT value reaches ECAP_CNTCMP  the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
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bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1  the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the ." "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: CAP2 input is from ACMP2 output,?,?"
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bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: CAP1 input is from ACMP1 output,?,?"
bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: CAP0 input is from ACMP0 output,?,?"
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bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Bit" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Bit" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Bit" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Bit" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: ECAP_CLK,1: ECAP_CLK/2,?,?,?,?,?,?"
line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: ECAP_CLK (default),1: CAP0,?,?"
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bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: ECAP_CLK/1,1: ECAP_CLK/4,?,?,?,?,?,?"
bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only  rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
rbitfld.long 0x1C 8. "CAP2,Value of Input Channel 2  CAP2 (Read Only)\nReflecting the value of input channel 2  CAP2.\nNote: The bit is read only and write is ignored." "0,1"
rbitfld.long 0x1C 7. "CAP1,Value of Input Channel 1  CAP1 (Read Only)\nReflecting the value of input channel 1  CAP1\nNote: The bit is read only and write is ignored." "0,1"
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rbitfld.long 0x1C 6. "CAP0,Value of Input Channel 0  CAP0 (Read Only)\nReflecting the value of input channel 0  CAP0\nNote: The bit is read only and write is ignored." "0,1"
bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled  the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input  it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input  it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input  it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
tree.end
tree "ECAP2"
base ad:0x400B6000
group.long 0x0++0x1F
line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP  if ECAP_CNT value reaches ECAP_CNTCMP  the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
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bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1  the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the ." "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: CAP2 input is from ACMP2 output,?,?"
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bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: CAP1 input is from ACMP1 output,?,?"
bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: CAP0 input is from ACMP0 output,?,?"
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bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Bit" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Bit" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Bit" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Bit" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: ECAP_CLK,1: ECAP_CLK/2,?,?,?,?,?,?"
line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: ECAP_CLK (default),1: CAP0,?,?"
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bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: ECAP_CLK/1,1: ECAP_CLK/4,?,?,?,?,?,?"
bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only  rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
rbitfld.long 0x1C 8. "CAP2,Value of Input Channel 2  CAP2 (Read Only)\nReflecting the value of input channel 2  CAP2.\nNote: The bit is read only and write is ignored." "0,1"
rbitfld.long 0x1C 7. "CAP1,Value of Input Channel 1  CAP1 (Read Only)\nReflecting the value of input channel 1  CAP1\nNote: The bit is read only and write is ignored." "0,1"
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rbitfld.long 0x1C 6. "CAP0,Value of Input Channel 0  CAP0 (Read Only)\nReflecting the value of input channel 0  CAP0\nNote: The bit is read only and write is ignored." "0,1"
bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled  the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input  it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input  it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input  it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
tree.end
tree "ECAP3"
base ad:0x400B7000
group.long 0x0++0x1F
line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change  the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP  if ECAP_CNT value reaches ECAP_CNTCMP  the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
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bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1  the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the ." "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: CAP2 input is from ACMP2 output,?,?"
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bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: CAP1 input is from ACMP1 output,?,?"
bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: CAP0 input is from ACMP0 output,?,?"
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bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Bit" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Bit" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Bit" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Bit" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: ECAP_CLK,1: ECAP_CLK/2,?,?,?,?,?,?"
line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: ECAP_CLK (default),1: CAP0,?,?"
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bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: ECAP_CLK/1,1: ECAP_CLK/4,?,?,?,?,?,?"
bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only  rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only  rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
rbitfld.long 0x1C 8. "CAP2,Value of Input Channel 2  CAP2 (Read Only)\nReflecting the value of input channel 2  CAP2.\nNote: The bit is read only and write is ignored." "0,1"
rbitfld.long 0x1C 7. "CAP1,Value of Input Channel 1  CAP1 (Read Only)\nReflecting the value of input channel 1  CAP1\nNote: The bit is read only and write is ignored." "0,1"
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rbitfld.long 0x1C 6. "CAP0,Value of Input Channel 0  CAP0 (Read Only)\nReflecting the value of input channel 0  CAP0\nNote: The bit is read only and write is ignored." "0,1"
bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled  the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input  it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input  it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input  it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
tree.end
tree.end
tree "EMAC (Ethernet MAC)"
base ad:0x40012000
group.long 0x0++0x7
line.long 0x0 "MAC_Configuration,Register 0 (MAC Configuration Register)"
bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control \nThis field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 27. "TWOKPE,IEEE 802.3as Support for 2K Packets \nWhen set  the MAC considers all frames  with up to 2 000 bytes length  as normal packets. When Bit 20 (JE) is not set  the MAC considers all received frames of size more than 2 Kbytes as Giant frames. When.." "0,1"
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bitfld.long 0x0 25. "CST,CRC Stripping for Type Frames\nWhen this bit is set  the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1 536) are stripped and dropped before forwarding the frame to the application. This function is not.." "0,1"
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bitfld.long 0x0 23. "WD,Watchdog Disable\nWhen this bit is set  the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 384 bytes. When this bit is reset  the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is.." "0,1"
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bitfld.long 0x0 22. "JD,Jabber Disable\nWhen this bit is set  the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 384 bytes. When this bit is reset  the MAC cuts off the transmitter if the application sends out more than 2 048 bytes.." "0,1"
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bitfld.long 0x0 20. "JE,Jumbo Frame Enable\nWhen this bit is set  the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." "0,1"
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bitfld.long 0x0 17.--19. "IFG,Inter-Frame Gap\nThese bits control the minimum IFG between frames during transmission." "0: 96 bit times,1: 88 bit times,?,?,?,?,?,?"
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bitfld.long 0x0 16. "DCRS,Disable Carrier Sense During Transmission\nWhen set high  this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No.." "0,1"
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bitfld.long 0x0 14. "FES,Speed\nThis bit selects the speed in the RMII interface" "0: 10 Mbps,1: 100 Mbps"
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bitfld.long 0x0 13. "DO,Disable Receive Own\nWhen this bit is set  the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset  the MAC receives all packets that are given by the PHY while transmitting. This bit is.." "0,1"
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bitfld.long 0x0 12. "LM,Loopback Mode\nWhen this bit is set  the MAC operates in the loopback mode at MII. The (G)MII Receive clock input is required for the loopback to work properly  because the Transmit clock is not looped-back internally." "0,1"
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bitfld.long 0x0 11. "DM,Duplex Mode\nWhen this bit is set  the MAC operates in the full-duplex mode where it can transmit and receive simultaneously." "0,1"
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bitfld.long 0x0 10. "IPC,Checksum Offload\nWhen this bit is set  the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 2526 or 2930.." "0,1"
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bitfld.long 0x0 9. "DR,Disable Retry\nWhen this bit is set  the MAC attempts only one transmission. When a collision occurs on the MII interface  the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame.." "0,1"
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bitfld.long 0x0 7. "ACS,Automatic Pad or CRC Stripping\nWhen this bit is set  the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536.." "0,1"
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bitfld.long 0x0 5.--6. "BL,Back-Off Limit\nThe Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable.." "0: k is the min of (n 10),1: k is the min of (n 8),?,?"
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bitfld.long 0x0 4. "DC,Deferral Check\nWhen this bit is set  the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status  along with the excessive deferral error bit set in the transmit frame status  when the transmit state machine is deferred for.." "0,1"
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bitfld.long 0x0 3. "TE,Transmitter Enable\nWhen this bit is set  the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset  the MAC transmit state machine is disabled after the completion of the transmission of the current frame .." "0,1"
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bitfld.long 0x0 2. "RE,Receiver Enable\nWhen this bit is set  the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset  the MAC receive state machine is disabled after the completion of the reception of the current frame .." "0,1"
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bitfld.long 0x0 0.--1. "PRELEN,Preamble Length for Transmit Frames\nThese bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode." "0,1,2,3"
line.long 0x4 "MAC_Frame_Filter,Register 1 (MAC Frame Filter)"
bitfld.long 0x4 31. "RA,Receive All\nWhen this bit is set  the MAC Receiver module passes all received frames  irrespective of whether they pass the address filter or not  to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding.." "0,1"
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bitfld.long 0x4 16. "VTFE,VLAN Tag Filter Enable\nWhen set  this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. \nWhen reset  the MAC forwards all frames irrespective of the match status of the VLAN Tag." "0,1"
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bitfld.long 0x4 9. "SAF,Source Address Filter Enable\nWhen this bit is set  the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails  the MAC drops the frame. When this bit is reset  the MAC.." "0,1"
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bitfld.long 0x4 8. "SAIF,SA Inverse Filtering\nWhen this bit is set  the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. \nWhen this bit is reset .." "0,1"
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bitfld.long 0x4 6.--7. "PCF,Pass Control Frames\nThese bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). \nThe following conditions should be true for the PAUSE control frames processing: \nCondition 1: The MAC is in the.." "0: MAC filters all control frames from reaching the..,1: The MAC is in the full-duplex mode and flow..,2: The destination address,3: The Type field of the received frame is 0x8808.."
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bitfld.long 0x4 5. "DBF,Disable Broadcast Frames\nWhen this bit is set  the AFM module filters all incoming broadcast frames. In addition  it overrides all other filter settings. \nWhen this bit is reset  the AFM module passes all received broadcast frames." "0,1"
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bitfld.long 0x4 4. "PM,Pass All Multicast\nWhen set  this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.\nWhen reset  filtering of multicast frame depends on HMC bit." "0,1"
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bitfld.long 0x4 3. "DAIF,DA Inverse Filtering\nWhen this bit is set  the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.\nWhen reset  normal filtering of frames is performed." "0,1"
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bitfld.long 0x4 0. "PR,Promiscuous Mode\nWhen this bit is set  the Address Filter module passes all incoming frames regardless of its destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set." "0,1"
group.long 0x10++0xF
line.long 0x0 "GMII_Address,Register 4 (GMII Address Register)"
hexmask.long.byte 0x0 11.--15. 1. "PA,Physical Layer Address\nThis field indicates which of the 32 possible PHY devices are being accessed."
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hexmask.long.byte 0x0 6.--10. 1. "GR,GMII Register\nThese bits select the desired GMII register in the selected PHY device."
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hexmask.long.byte 0x0 2.--5. 1. "CR,CSR Clock Range"
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bitfld.long 0x0 1. "GW,GMII Write\nWhen set  this bit indicates to the PHY that this is a Write operation using the GMII Data register. If this bit is not set  it indicates that this is a Read operation  that is  placing the data in the GMII Data register." "0,1"
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bitfld.long 0x0 0. "GB,GMII Busy\nThis bit should read logic 0 before writing to Register 4 and Register 5. During a PHY register access  the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress.\nRegister 5 is invalid until this bit is.." "0,1"
line.long 0x4 "GMII_Data,Register 5 (GMII Data Register)"
hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data\nThis field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation."
line.long 0x8 "Flow_Control,Register 6 (Flow Control Register)"
hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time\nThis field holds the value to be used in the Pause Time field in the transmit control frame. Consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain."
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bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause\nWhen this bit is set  it disables the automatic generation of the Zero-Quanta Pause Control frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset  normal operation with automatic.." "0,1"
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bitfld.long 0x8 4.--5. "PLT,Pause Low Threshold\nThis field configures the threshold of the PAUSE timer at which the input flow control signal is checked for automatic retransmission of PAUSE Frame. \nThe slot time is defined as the time taken to transmit 512 bits (64 bytes) on.." "0: The threshold is Pause time minus 4 slot times..,1: The threshold is Pause time minus 28 slot times..,?,?"
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bitfld.long 0x8 3. "UP,Unicast Pause Frame Detect\nA pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set  the MAC can also detect Pause frames with unicast address of the station. This unicast address.." "0,1"
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bitfld.long 0x8 2. "RFE,Receive Flow Control Enable\nWhen this bit is set  the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset  the decode function of the Pause frame is disabled." "0,1"
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bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable\nIn the full-duplex mode  when this bit is set  the MAC enables the flow control operation to transmit Pause frames. When this bit is reset  the flow control operation in the MAC is disabled  and the MAC does not transmit.." "0,1"
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bitfld.long 0x8 0. "FCA_BPA,Flow Control Busy or Backpressure Activate\nThis bit initiates a Pause Control frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. \nIn the full-duplex mode  this bit should be read.." "0,1"
line.long 0xC "VLAN_Tag,Register 7 (VLAN Tag Register)"
bitfld.long 0xC 18. "ESVL,Enable S-VLAN" "0,1"
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bitfld.long 0xC 17. "VTIM,VLAN Tag Inverse Match Enable\nWhen set  this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched.\nWhen reset  this bit enables the VLAN Tag perfect matching. The frames with matched VLAN.." "0,1"
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bitfld.long 0xC 16. "ETV,Enable 12-Bit VLAN Tag Comparison\nWhen this bit is set  a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received.." "0,1"
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hexmask.long.word 0xC 0.--15. 1. "VL,VLAN Tag Identifier for Receive Frames\nThis field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this.."
rgroup.long 0x20++0x7
line.long 0x0 "Version,Register 8 (Version Register)"
line.long 0x4 "Debug,Register 9 (Debug Register)"
bitfld.long 0x4 25. "TXSTSFSTS,MTL TxStatus FIFO Full Status\nWhen high  this bit indicates that the MTL TxStatus FIFO is full. Therefore  the MTL cannot accept any more frames for transmission." "0,1"
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bitfld.long 0x4 24. "TXFSTS,MTL Tx FIFO Not Empty Status\nWhen high  this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission." "0,1"
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bitfld.long 0x4 22. "TWCSTS,MTL Tx FIFO Write Controller Active Status\nWhen high  this bit indicates that the MTL Tx FIFO Write Controller is active and transferring data to the Tx FIFO." "0,1"
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bitfld.long 0x4 20.--21. "TRCSTS,MTL Tx FIFO Read Controller Status\nThis field indicates the state of the Tx FIFO Read Controller:" "0: IDLE state,1: READ state (transferring data to MAC transmitter),?,?"
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bitfld.long 0x4 19. "TXPAUSED,MAC transmitter in PAUSE\nWhen high  this bit indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission." "0,1"
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bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Frame Controller Status\nThis field indicates the state of the MAC Transmit Frame Controller module:" "0: IDLE state,1: Waiting for Status of previous frame or IFG or..,?,?"
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bitfld.long 0x4 16. "TPESTS,MAC MII Transmit Protocol Engine Status\nWhen high  this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state." "0,1"
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bitfld.long 0x4 8.--9. "RXFSTS,MTL Rx FIFO Fill-level Status\nThis field gives the status of the fill-level of the Rx FIFO:" "0: Rx FIFO Empty,1: Rx FIFO fill level is below the flow-control..,?,?"
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bitfld.long 0x4 5.--6. "RRCSTS,MTL Rx FIFO Read Controller State\nThis field gives the state of the Rx FIFO read Controller:" "0: IDLE state,1: Reading frame data,?,?"
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bitfld.long 0x4 4. "RWCSTS,MTL Rx FIFO Write Controller Active Status\nWhen high  this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO." "0,1"
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bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Frame Controller FIFO Status\nWhen high  this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module." "0,1,2,3"
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bitfld.long 0x4 0. "RPESTS,MAC MII Receive Protocol Engine Status\nWhen high  this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." "0,1"
group.long 0x2C++0x3
line.long 0x0 "PMT_Control_Status,Register 11 (PMT Control and Status Register)"
rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received (read only)\nWhen set  this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register." "0,1"
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bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable\nWhen set  enables generation of a power management event because of magic packet reception." "0,1"
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bitfld.long 0x0 0. "PWRDWN,Power Down\nWhen set  the MAC receiver drops all received frames until it receives the expected magic packet or wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the.." "0,1"
rgroup.long 0x38++0x3
line.long 0x0 "Interrupt_Status,Register 14 (Interrupt Register)"
bitfld.long 0x0 9. "TSIS,Timestamp Interrupt Status\nWhen the Advanced Timestamp feature is enabled  this bit is set when any of the following conditions is true: \nThe system time value equals or exceeds the value specified in the Target Time High and Low registers." "0,1"
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bitfld.long 0x0 3. "PMTIS,PMT Interrupt Status\nThis bit is set when a Magic packet or Wake-on-LAN frame is received in the power-down mode (see Bits 5 in the PMT Control and Status Register). This bit is cleared when Bit 5 is cleared because of a read operation to the PMT.." "0,1"
group.long 0x3C++0x4B
line.long 0x0 "Interrupt_Mask,Register 15 (Interrupt Mask Register)"
bitfld.long 0x0 9. "TSIM,Timestamp Interrupt Mask\nWhen set  this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). This bit is valid only when IEEE1588 timestamping is.." "0,1"
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bitfld.long 0x0 3. "PMTIM,PMT Interrupt Mask\nWhen set  this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register)." "0,1"
line.long 0x4 "MAC_Address0_High,Register 16 (MAC Address0 High Register)"
rbitfld.long 0x4 31. "AE,Address Enable (read only)\nThis bit is always set to 1." "0,1"
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hexmask.long.word 0x4 0.--15. 1. "ADDRHI,MAC Address0 [47:32]\nThis field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames."
line.long 0x8 "MAC_Address0_Low,Register 17 (MAC Address0 Low Register)"
hexmask.long 0x8 0.--31. 1. "ADDRLO,MAC Address0 [31:0]\nThis field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames."
line.long 0xC "MAC_Address1_High,Register 18 (MAC Address1 High Register)"
bitfld.long 0xC 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the second MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0xC 30. "SA,Source Address\nWhen this bit is set  the MAC Address1[47:0] is used to compare with the SA fields of the received frame.\nWhen this bit is reset  the MAC Address1[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0xC 24.--29. 1. "MBC,Mask Byte Control\nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls.."
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hexmask.long.word 0xC 0.--15. 1. "ADDRHI,MAC Address1 [47:32]\nThis field contains the upper 16 bits (47:32) of the second 6-byte MAC address."
line.long 0x10 "MAC_Address1_Low,Register 19 (MAC Address1 Low Register)"
hexmask.long 0x10 0.--31. 1. "ADDRLO,MAC Address1 [31:0]\nThis field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x14 "MAC_Address2_High,Register 20 (MAC Address2 High Register)"
bitfld.long 0x14 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the third MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x14 30. "SA,Source Address\nWhen this bit is set  the MAC Address2[47:0] is used to compare with the SA fields of the received frame.\nWhen this bit is reset  the MAC Address2[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x14 24.--29. 1. "MBC,Mask Byte Control\nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 registers. Each bit controls.."
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hexmask.long.word 0x14 0.--15. 1. "ADDRHI,MAC Address2 [47:32]\nThis field contains the upper 16 bits (47:32) of the third 6-byte MAC address."
line.long 0x18 "MAC_Address2_Low,Register 21 (MAC Address2 Low Register)"
hexmask.long 0x18 0.--31. 1. "ADDRLO,MAC Address2 [31:0]\nThis field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x1C "MAC_Address3_High,Register 22 (MAC Address3 High Register)"
bitfld.long 0x1C 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the fourth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x1C 30. "SA,Source Address \nWhen this bit is set  the MAC Address3[47:0] is used to compare with the SA fields of the received frame.\nWhen this bit is reset  the MAC Address3[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x1C 24.--29. 1. "MBC,Mask Byte Control\nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 registers. Each bit controls.."
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hexmask.long.word 0x1C 0.--15. 1. "ADDRHI,MAC Address3 [47:32]\nThis field contains the upper 16 bits (47:32) of the fourth 6-byte MAC address."
line.long 0x20 "MAC_Address3_Low,Register 23 (MAC Address3 Low Register)"
hexmask.long 0x20 0.--31. 1. "ADDRLO,MAC Address3 [31:0]\nThis field contains the lower 32 bits of the fourth 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x24 "MAC_Address4_High,Register 24 (MAC Address4 High Register)"
bitfld.long 0x24 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the fifth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x24 30. "SA,Source Address \nWhen this bit is set  the MAC Address4[47:0] is used to compare with the SA fields of the received frame.\nWhen this bit is reset  the MAC Address4[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x24 24.--29. 1. "MBC,Mask Byte Control\nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 registers. Each bit controls.."
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hexmask.long.word 0x24 0.--15. 1. "ADDRHI,MAC Address4 [47:32]\nThis field contains the upper 16 bits (47:32) of the fifth 6-byte MAC address."
line.long 0x28 "MAC_Address4_Low,Register 25 (MAC Address4 Low Register)"
hexmask.long 0x28 0.--31. 1. "ADDRLO,MAC Address4 [31:0]\nThis field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x2C "MAC_Address5_High,Register 26 (MAC Address5 High Register)"
bitfld.long 0x2C 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x2C 30. "SA,Source Address\nWhen this bit is set  the MAC Address5[47:0] is used to compare with the SA fields of the received frame. When this bit is reset  the MAC Address5[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x2C 24.--29. 1. "MBC,Mask Byte Control\nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 registers. Each bit controls.."
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hexmask.long.word 0x2C 0.--15. 1. "ADDRHI,MAC Address5 [47:32]\nThis field contains the upper 16 bits (47:32) of the sixth 6-byte MAC address."
line.long 0x30 "MAC_Address5_Low,Register 27 (MAC Address5 Low Register)"
hexmask.long 0x30 0.--31. 1. "ADDRLO,MAC Address5 [31:0]\nThis field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x34 "MAC_Address6_High,Register 28 (MAC Address6 High Register)"
bitfld.long 0x34 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the seventh MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x34 30. "SA,Source Address\nWhen this bit is set  the MAC Address6[47:0] is used to compare with the SA fields of the received frame. When this bit is reset  the MAC Address6[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x34 24.--29. 1. "MBC,Mask Byte Control \nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 registers. Each bit controls.."
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hexmask.long.word 0x34 0.--15. 1. "ADDRHI,MAC Address6 [47:32] \nThis field contains the upper 16 bits (47:32) of the seventh 6-byte MAC address."
line.long 0x38 "MAC_Address6_Low,Register 29 (MAC Address6 Low Register)"
hexmask.long 0x38 0.--31. 1. "ADDRLO,MAC Address6 [31:0]\nThis field contains the lower 32 bits of the seventh 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x3C "MAC_Address7_High,Register 30 (MAC Address7 High Register)"
bitfld.long 0x3C 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x3C 30. "SA,Source Address\nWhen this bit is set  the MAC Address7[47:0] is used to compare with the SA fields of the received frame. When this bit is reset  the MAC Address7[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x3C 24.--29. 1. "MBC,Mask Byte Control \nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 registers. Each bit controls.."
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hexmask.long.word 0x3C 0.--15. 1. "ADDRHI,MAC Address7 [47:32] \nThis field contains the upper 16 bits (47:32) of the eighth 6-byte MAC address."
line.long 0x40 "MAC_Address7_Low,Register 31 (MAC Address7 Low Register)"
hexmask.long 0x40 0.--31. 1. "ADDRLO,MAC Address7 [31:0]\nThis field contains the lower 32 bits of the eighth 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
line.long 0x44 "MAC_Address8_High,Register 32 (MAC Address8 High Register)"
bitfld.long 0x44 31. "AE,Address Enable\nWhen this bit is set  the address filter module uses the nineth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering." "0,1"
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bitfld.long 0x44 30. "SA,Source Address\nWhen this bit is set  the MAC Address8[47:0] is used to compare with the SA fields of the received frame. When this bit is reset  the MAC Address8[47:0] is used to compare with the DA fields of the received frame." "0,1"
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hexmask.long.byte 0x44 24.--29. 1. "MBC,Mask Byte Control\nThese bits are mask control bits for comparison of each of the MAC Address bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 registers. Each bit controls.."
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hexmask.long.word 0x44 0.--15. 1. "ADDRHI,MAC Address8 [47:32]\nThis field contains the upper 16 bits (47:32) of the nineth 6-byte MAC address."
line.long 0x48 "MAC_Address8_Low,Register 33 (MAC Address8 Low Register)"
hexmask.long 0x48 0.--31. 1. "ADDRLO,MAC Address8 [31:0]\nThis field contains the lower 32 bits of the nineth 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process."
group.long 0xDC++0x3
line.long 0x0 "WDog_Timeout,Register 55 (Watchdog Timeout Register)"
bitfld.long 0x0 16. "PWE,Programmable Watchdog Enable\nWhen this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset  the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared  the watchdog timeout for a.." "0,1"
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hexmask.long.word 0x0 0.--13. 1. "WTO,Watchdog Timeout\nWhen Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset  this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field  such frame.."
group.long 0x584++0x3
line.long 0x0 "VLAN_Incl_Reg,Register 353 (VLAN Tag Inclusion or Replacement Register)"
bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN\nWhen this bit is set  S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset  C-VLAN type (0x8100) is inserted or replaced in the transmitted frames." "0,1"
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bitfld.long 0x0 18. "VLP,VLAN Priority Control\nWhen this bit is set  the control Bits [17:16] are used for VLAN deletion  insertion  or replacement. When this bit is reset  the mti_vlan_ctrl_i control input is used  and Bits [17:16] are ignored." "0,1"
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bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Frames \nThe MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). \nNote: Changes to this field take effect only on the start of a frame. If you write this register.." "0,1,2,3"
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hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Frames\nThis field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits [15:13] are the User Priority  Bit 12.."
group.long 0x700++0x7
line.long 0x0 "Timestamp_Control,Register 448 (Timestamp Control Register)"
bitfld.long 0x0 18. "TSENMACADDR,Enable MAC address for PTP Frame Filtering\nWhen set  the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet." "0,1"
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bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots\nThese bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken." "0,1,2,3"
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bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master\nWhen set  the snapshot is taken only for the messages relevant to the master node. Otherwise  the snapshot is taken for the messages relevant to the slave node." "0,1"
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bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages \nWhen set  the timestamp snapshot is taken only for event messages (SYNC  Delay_Req  Pdelay_Req  or Pdelay_Resp). When reset  the snapshot is taken for all messages except Announce  Management  and.." "0,1"
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bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Frames Sent over IPv4-UDP\nWhen set  the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear  the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set.." "0,1"
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bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Frames Sent Over IPv6-UDP \nWhen set  the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear  the MAC ignores the PTP transported over UDP-IPv6 packets." "0,1"
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bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Frames\nWhen set  the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear  the MAC ignores the PTP over Ethernet packets." "0,1"
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bitfld.long 0x0 10. "TSVER2ENA,Enable PTP packet Processing for Version 2 Format\nWhen set  the PTP packets are processed using the 1588 version 2 format. Otherwise  the PTP packets are processed using the version 1 format." "0,1"
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bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control\nWhen set  the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is  1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset  the rollover value of sub-second.." "0,1"
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bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Frames\nWhen set  the timestamp snapshot is enabled for all frames received by the MAC." "0,1"
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bitfld.long 0x0 5. "TSADDREG,Addend Reg Update\nWhen set  the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it." "0,1"
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bitfld.long 0x0 4. "TSTRIG,Timestamp Interrupt Trigger Enable\nWhen set  the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt." "0,1"
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bitfld.long 0x0 3. "TSUPDT,Timestamp Update\nWhen set  the system time is updated (added or subtracted) with the value specified in Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). \nThis bit should be read.." "0,1"
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bitfld.long 0x0 2. "TSINIT,Timestamp Initialize\nWhen set  the system time is initialized (overwritten) with the value specified in the Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register).\nThis bit should be.." "0,1"
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bitfld.long 0x0 1. "TSCFUPDT,Timestamp Fine or Coarse Update\nWhen set  this bit indicates that the system times update should be done using the fine update method. When reset  it indicates the system timestamp update should be done using the Coarse method." "0,1"
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bitfld.long 0x0 0. "TSENA,Timestamp Enable\nWhen set  the timestamp is added for the transmit and receive frames. When disabled  timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp.." "0,1"
line.long 0x4 "Sub_Second_Increment,Register 449 (Sub-Second Increment Register)"
hexmask.long.byte 0x4 0.--7. 1. "SSINC,Sub-second Increment Value\nThe value programmed in this field is accumulated every clock cycle with the contents of the sub-second register. For example  when PTP clock is 50 MHz (period is 20 ns)  you should program 20 (0x14) when the System.."
rgroup.long 0x708++0x7
line.long 0x0 "System_Time_Seconds,Register 450 (System Time - Seconds Register)"
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second\nThe value in this field indicates the current value in seconds of the System Time maintained by the MAC."
line.long 0x4 "System_Time_Nanoseconds,Register 451 (System Time - Nanoseconds Register)"
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds\nThe value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the maximum value is.."
group.long 0x710++0x17
line.long 0x0 "System_Time_Seconds_Update,Register 452 (System Time - Seconds Update Register)"
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second\nThe value in this field indicates the time in seconds to be initialized or added to the system time."
line.long 0x4 "System_Time_Nanoseconds_Update,Register 453 (System Time - Nanoseconds Update Register)"
bitfld.long 0x4 31. "ADDSUB,Add or subtract time\nWhen this bit is set  the time value is subtracted with the contents of the update register. When this bit is reset  the time value is added with the contents of the update register." "0,1"
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hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Second\nThe value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the programmed value.."
line.long 0x8 "Timestamp_Addend,Register 454 (Timestamp Addend Register)"
hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register\nThis field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."
line.long 0xC "Target_Time_Seconds,Register 455 (Target Time Seconds Register)"
hexmask.long 0xC 0.--31. 1. "TSTR,Target Time Seconds Register\nThis register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers  then based on Bits [6:5] of Register 459 (PPS Control Register)  the MAC starts or stops the PPS.."
line.long 0x10 "Target_Time_Nanoseconds,Register 456 (Target Time Nanoseconds Register)"
rbitfld.long 0x10 31. "TRGTBUSY,Target Time Register Busy (read only)\nThe MAC sets this bit when the PPSCMD field (Bits [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011  instructs the MAC to synchronize the.." "0,1"
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hexmask.long 0x10 0.--30. 1. "TTSLO,Target Timestamp Low Register\nThis register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers  then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control.."
line.long 0x14 "System_Time_Higher_Word_Seconds,Register 457 (System Time - Higher Word Seconds Register)"
hexmask.long.word 0x14 0.--15. 1. "TSHWR,Timestamp Higher Word Register\nThis field contains the most significant 16-bits of the timestamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of.."
rgroup.long 0x728++0x3
line.long 0x0 "Timestamp_Status,Register 458 (Timestamp Status Register)"
hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier\nThese bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time  it means that.."
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bitfld.long 0x0 3. "TSTRGTERR,Timestamp Target Time Error\nThis bit is set when the target time  being programmed in Target Time Registers  is already elapsed. This bit is cleared when read by the application." "0,1"
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bitfld.long 0x0 1. "TSTARGT,Timestamp Target Time Reached\nWhen set  this bit indicates that the value of system time is greater or equal to the value specified in the Register 455 (Target Time Seconds Register) and Register 456 (Target Time Nanoseconds Register)." "0,1"
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bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow\nWhen set  this bit indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF." "0,1"
group.long 0x72C++0x3
line.long 0x0 "PPS_Control,Register 459 (PPS Control Register)"
bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output\nThis field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal:" "0: Indicates that the Target Time registers are..,1: Reserved.,?,?"
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bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable\nWhen set low  Bits [3:0] function as PPSCTRL (backward compatible). When set high  Bits [3:0] function as PPSCMD." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPSCTRL0 or PPSCMD0\nPPSCTRL0: PPS0 Output Frequency Control\nThis field controls the frequency of the PPS0 output signal. The default value of PPSCTRL is 0000  and the PPS output is 1 pulse every second. For other values of PPSCTRL  the.."
group.long 0x760++0x7
line.long 0x0 "PPS0_Interval,Register 472 (PPS0 Interval Register)"
hexmask.long 0x0 0.--31. 1. "PPSINT,PPS0 Output Signal Interval \nThese bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example  if the PTP.."
line.long 0x4 "PPS0_Width,Register 473 (PPS0 Width Register)"
hexmask.long 0x4 0.--31. 1. "PPSWIDTH,PPS0 Output Signal Width\nThese bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. \nYou need to program one value less than the required.."
group.long 0x1000++0x1F
line.long 0x0 "Bus_Mode,Register 1000 (Bus Mode Register)"
bitfld.long 0x0 25. "AAL,Address Aligned Beats\nWhen this bit is set high and the FB bit is equal to 1  the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0  the first burst (accessing the data buffer's start address) is.." "0,1"
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bitfld.long 0x0 24. "PBLx8,PBLx8 Mode\nWhen set high  this bit multiplies the programmed PBL value (Bits [22:17] and Bits [13:8]) eight times. Therefore  the DMA transfers the data in 8  16  32  64  128  and 256 beats depending on the PBL value." "0,1"
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bitfld.long 0x0 23. "USP,Use Separate PBL\nWhen set high  this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations.\nWhen reset to low  the PBL value in Bits [13:8] is.." "0,1"
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hexmask.long.byte 0x0 17.--22. 1. "RPBL,Rx DMA PBL\nThis field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.\nThe Rx DMA always attempts to burst as specified in the RPBL bit each.."
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bitfld.long 0x0 16. "FB,Fixed Burst\nThis bit controls whether the AHB Master interface performs fixed burst transfers or not. When set  the AHB interface uses only SINGLE  INCR4  INCR8  or INCR16 during start of the normal burst transfers. When reset  the AHB interface uses.." "0,1"
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hexmask.long.byte 0x0 8.--13. 1. "PBL,Programmable Burst Length\nThese bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each.."
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bitfld.long 0x0 7. "ATDS,Alternate Descriptor Size\nWhen set  the size of the alternate descriptor increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Offload Engine (Type 2) is enabled in the receiver. The enhanced.." "0,1"
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hexmask.long.byte 0x0 2.--6. 1. "DSL,Descriptor Skip Length\nThis bit specifies the number of Word  Dword  or Lword (depending on the 32-bit  64-bit  or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of.."
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bitfld.long 0x0 0. "SWR,Software Reset\nWhen this bit is set  the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation has completed in all of the EMAC clock domains. Before reprogramming any.." "0,1"
line.long 0x4 "Transmit_Poll_Demand,Register 1001 (Transmit Poll Demand Register)"
hexmask.long 0x4 0.--31. 1. "TPD,Transmit Poll Demand\nWhen these bits are written with any value  the DMA reads the current descriptor pointed to by Register 1018 (Current Host Transmit Descriptor Register). If that descriptor is not available (owned by the Host)  the transmission.."
line.long 0x8 "Receive_Poll_Demand,Register 1002 (Receive Poll Demand Register)"
hexmask.long 0x8 0.--31. 1. "RPD,Receive Poll Demand\nWhen these bits are written with any value  the DMA reads the current descriptor pointed to by Register 1019 (Current Host Receive Descriptor Register). If that descriptor is not available (owned by the Host)  the reception.."
line.long 0xC "Receive_Descriptor_List_Address,Register 1003 (Receive Descriptor List Address Register)"
hexmask.long 0xC 3.--31. 1. "RDESLA_64_bit,Start of Receive List\nThis field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (2:0) for 64-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore  these LSB.."
line.long 0x10 "Transmit_Descriptor_List_Address,Register 1004 (Transmit Descriptor List Address Register)"
hexmask.long 0x10 3.--31. 1. "TDESLA_64_bit,Start of Transmit List\nThis field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (2:0) for 64-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore  these LSB.."
line.long 0x14 "Status,Register 1005 (Status Register)"
rbitfld.long 0x14 29. "TTI,Timestamp Trigger Interrupt (read only)\nThis bit indicates an interrupt event in the Timestamp Generator block of EMAC. The software must read the corresponding registers in the EMAC to get the exact cause of interrupt and clear its source to reset.." "0,1"
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rbitfld.long 0x14 28. "GPI,GMAC PMT Interrupt (read only)\nThis bit indicates an interrupt event in the PMT module of the EMAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to.." "0,1"
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rbitfld.long 0x14 23.--25. "EB,Error Bits (read only)\nThis field indicates the type of error that caused a Bus Error  for example  error response on the AHB interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. \nNote: 001 and 010.." "0: Error during Rx DMA Write Data Transfer,?,?,?,?,?,?,?"
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rbitfld.long 0x14 20.--22. "TS,Transmit Process State (read only)\nThis field indicates the Transmit DMA FSM state. This field does not generate an interrupt." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 17.--19. "RS,Received Process State (read only)\nThis field indicates the Receive DMA FSM state. This field does not generate an interrupt." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 16. "NIS,Normal Interrupt Summary\nNormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 1007 (Interrupt Enable Register): \nRegister 1005[0]: Transmit Interrupt \nRegister 1005[2]:.." "0,1"
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bitfld.long 0x14 15. "AIS,Abnormal Interrupt Summary\nAbnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 1007 (Interrupt Enable Register): \nRegister 1005[1]: Transmit Process Stopped.." "0,1"
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bitfld.long 0x14 14. "ERI,Early Receive Interrupt\nThis bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier)." "0,1"
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bitfld.long 0x14 13. "FBI,Fatal Bus Error Interrupt\nThis bit indicates that a bus error occurred  as described in Bits [25:23]. When this bit is set  the corresponding DMA engine disables all of its bus accesses." "0,1"
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bitfld.long 0x14 10. "ETI,Early Transmit Interrupt\nThis bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO." "0,1"
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bitfld.long 0x14 9. "RWT,Receive Watchdog Timeout\nWhen set  this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout." "0,1"
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bitfld.long 0x14 8. "RPS,Receive Process Stopped\nThis bit is asserted when the Receive Process enters the Stopped state." "0,1"
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bitfld.long 0x14 7. "RU,Receive Buffer Unavailable\nThis bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors  the host should change the ownership.." "0,1"
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bitfld.long 0x14 6. "RI,Receive Interrupt\nThis bit indicates that the frame reception is complete. When reception is complete  the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor  and the specific frame status information is updated in the.." "0,1"
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bitfld.long 0x14 5. "UNF,Transmit Underflow\nThis bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." "0,1"
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bitfld.long 0x14 4. "OVF,Receive Overflow\nThis bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application  the overflow status is set in RDES0[11]." "0,1"
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bitfld.long 0x14 3. "TJT,Transmit Jabber Timeout\nThis bit indicates that the Transmit Jabber Timer expired  which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs  the transmission process is aborted.." "0,1"
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bitfld.long 0x14 2. "TU,Transmit Buffer Unavailable\nThis bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits [22:20] explain the Transmit Process state transitions. \nTo resume processing.." "0,1"
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bitfld.long 0x14 1. "TPS,Transmit Process Stopped\nThis bit is set when the transmission is stopped." "0,1"
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bitfld.long 0x14 0. "TI,Transmit Interrupt\nThis bit indicates that the frame transmission is complete. When transmission is complete  Bit 31 (OWN) of TDES0 is reset  and the specific frame status information is updated in the descriptor." "0,1"
line.long 0x18 "Operation_Mode,Register 1006 (Operation Mode Register)"
bitfld.long 0x18 26. "DT,Disable Dropping of TCP/IP Checksum Error Frames\nWhen this bit is set  the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet.." "0,1"
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bitfld.long 0x18 25. "RSF,Receive Store and Forward\nWhen this bit is set  the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it  ignoring the RTC bits. When this bit is reset  the Rx FIFO operates in the cut-through mode  subject to the.." "0,1"
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bitfld.long 0x18 24. "DFF,Disable Flushing of Received Frames\nWhen this bit is set  the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset." "0,1"
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bitfld.long 0x18 21. "TSF,Transmit Store and Forward\nWhen this bit is set  transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set  the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the.." "0,1"
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bitfld.long 0x18 20. "FTF,Flush Transmit FIFO\nWhen this bit is set  the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is completed. The Operation.." "0,1"
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bitfld.long 0x18 14.--16. "TTC,Transmit Threshold Control\nThese bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition  full frames with a length less than the.." "0: 64 bytes,1: 128 bytes,?,?,?,?,?,?"
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bitfld.long 0x18 13. "ST,Start or Stop Transmission Command\nWhen this bit is set  transmission is placed in the Running state  and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the.." "0,1"
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bitfld.long 0x18 11.--12. "RFD,Threshold for Deactivating Flow Control\nThese bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. \nThe de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8.." "0: Full minus 1 Kbytes that is FULL - 1 Kbytes,1: Full minus 2 Kbytes that is FULL - 2 Kbytes,?,?"
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bitfld.long 0x18 9.--10. "RFA,Threshold for Activating Flow Control\nThese bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated.\nThese values are applicable only to Rx FIFOs of 4 Kbytes or more and when Bit 8 (EFC) is set high. If the Rx FIFO.." "0: Full minus 1 Kbytes that is FULL - 1 Kbytes,1: Full minus 2 Kbytes that is FULL - 2 Kbytes,?,?"
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bitfld.long 0x18 8. "EFC,Enable HW Flow Control\nWhen this bit is set  the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset  the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is.." "0,1"
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bitfld.long 0x18 7. "FEF,Forward Error Frames\nWhen this bit is reset  the Rx FIFO drops frames with error status (CRC error  collision error  GMII_ER  giant frame  watchdog timeout  or overflow). However  if the start byte (write) pointer of a frame is already transferred.." "0,1"
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bitfld.long 0x18 6. "FUF,Forward Undersized Good Frames\nWhen set  the Rx FIFO forwards Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC." "0,1"
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bitfld.long 0x18 5. "DGF,Drop Giant Frames \nWhen set  the MAC drops the received giant frames in the Rx FIFO  that is  frames that are larger than the computed giant frame limit. When reset  the MAC does not drop the giant frames in the Rx FIFO." "0,1"
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bitfld.long 0x18 3.--4. "RTC,Receive Threshold Control\nThese two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition  full frames with length less.." "0: 64 bytes,1: 32 bytes,?,?"
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bitfld.long 0x18 2. "OSF,Operate on Second Frame\nWhen this bit is set  it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained." "0,1"
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bitfld.long 0x18 1. "SR,Start or Stop Receive\nWhen this bit is set  the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the.." "0,1"
line.long 0x1C "Interrupt_Enable,Register 1007 (Interrupt Enable Register)"
bitfld.long 0x1C 16. "NIE,Normal Interrupt Summary Enable\nWhen this bit is set  normal interrupt summary is enabled. When this bit is reset  normal interrupt summary is disabled. This bit enables the following interrupts in Register 1005 (Status Register):\nRegister 1005[0]:.." "0,1"
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bitfld.long 0x1C 15. "AIE,Abnormal Interrupt Summary Enable\nWhen this bit is set  abnormal interrupt summary is enabled. When this bit is reset  the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 1005 (Status.." "0,1"
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bitfld.long 0x1C 14. "ERE,Early Receive Interrupt Enable\nWhen this bit is set with Normal Interrupt Summary Enable (Bit 16)  the Early Receive Interrupt is enabled. When this bit is reset  the Early Receive Interrupt is disabled." "0,1"
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bitfld.long 0x1C 13. "FBE,Fatal Bus Error Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Fatal Bus Error Interrupt is enabled. When this bit is reset  the Fatal Bus Error Enable Interrupt is disabled." "0,1"
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bitfld.long 0x1C 10. "ETE,Early Transmit Interrupt Enable\nWhen this bit is set with an Abnormal Interrupt Summary Enable (Bit 15)  the Early Transmit Interrupt is enabled. When this bit is reset  the Early Transmit Interrupt is disabled." "0,1"
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bitfld.long 0x1C 9. "RWE,Receive Watchdog Timeout Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset  the Receive Watchdog Timeout Interrupt is disabled." "0,1"
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bitfld.long 0x1C 8. "RSE,Receive Stopped Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Receive Stopped Interrupt is enabled. When this bit is reset  the Receive Stopped Interrupt is disabled." "0,1"
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bitfld.long 0x1C 7. "RUE,Receive Buffer Unavailable Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset  the Receive Buffer Unavailable Interrupt is disabled." "0,1"
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bitfld.long 0x1C 6. "RIE,Receive Interrupt Enable\nWhen this bit is set with Normal Interrupt Summary Enable (Bit 16)  the Receive Interrupt is enabled. When this bit is reset  the Receive Interrupt is disabled." "0,1"
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bitfld.long 0x1C 5. "UNE,Underflow Interrupt Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Transmit Underflow Interrupt is enabled. When this bit is reset  the Underflow Interrupt is disabled." "0,1"
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bitfld.long 0x1C 4. "OVE,Overflow Interrupt Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Receive Overflow Interrupt is enabled. When this bit is reset  the Overflow Interrupt is disabled." "0,1"
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bitfld.long 0x1C 3. "TJE,Transmit Jabber Timeout Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset  the Transmit Jabber Timeout Interrupt is disabled." "0,1"
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bitfld.long 0x1C 2. "TUE,Transmit Buffer Unavailable Enable\nWhen this bit is set with Normal Interrupt Summary Enable (Bit 16)  the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset  the Transmit Buffer Unavailable Interrupt is disabled." "0,1"
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bitfld.long 0x1C 1. "TSE,Transmit Stopped Enable\nWhen this bit is set with Abnormal Interrupt Summary Enable (Bit 15)  the Transmission Stopped Interrupt is enabled. When this bit is reset  the Transmission Stopped Interrupt is disabled." "0,1"
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bitfld.long 0x1C 0. "TIE,Transmit Interrupt Enable\nWhen this bit is set with Normal Interrupt Summary Enable (Bit 16)  the Transmit Interrupt is enabled. When this bit is reset  the Transmit Interrupt is disabled." "0,1"
rgroup.long 0x1020++0x3
line.long 0x0 "Missed_Frame_And_Buffer_Overflow_Counter,Register 1008 (Missed Frame and Buffer Overflow Counter Register)"
bitfld.long 0x0 28. "OVFCNTOVF,Overflow Bit for FIFO Overflow Counter\nThis bit is set every time the Overflow Frame Counter (Bits [27:17]) overflows  that is  the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario  the overflow frame.." "0,1"
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hexmask.long.word 0x0 17.--27. 1. "OVFFRMCNT,Overflow Frame Counter\nThis field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1'b1."
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bitfld.long 0x0 16. "MISCNTOVF,Overflow Bit for Missed Frame Counter\nThis bit is set every time Missed Frame Counter (Bits [15:0]) overflows  that is  the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at.." "0,1"
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hexmask.long.word 0x0 0.--15. 1. "MISFRMCNT,Missed Frame Counter\nThis field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when.."
group.long 0x1024++0x3
line.long 0x0 "Receive_Interrupt_Watchdog_Timer,Register 1009 (Receive Interrupt Watchdog Timer Register)"
hexmask.long.byte 0x0 0.--7. 1. "RIWT,RI Watchdog Timer Count\nThis bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for.."
rgroup.long 0x102C++0x3
line.long 0x0 "AHB_Status,Register 1011 (AHB Status Register)"
bitfld.long 0x0 0. "AXWHSTS,AHB Master Write Channel Status\nWhen high  it indicates that AHB Master's write channel is active and transferring data." "0,1"
rgroup.long 0x1048++0x13
line.long 0x0 "Current_Host_Transmit_Descriptor,Register 1018 (Current Host Transmit Descriptor Register)"
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Host Transmit Descriptor Address Pointer\nCleared on Reset. Pointer updated by the DMA during operation."
line.long 0x4 "Current_Host_Receive_Descriptor,Register 1019 (Current Host Receive Descriptor Register)"
hexmask.long 0x4 0.--31. 1. "CURRDESAPTR,Host Receive Descriptor Address Pointer\nCleared on Reset. Pointer updated by the DMA during operation."
line.long 0x8 "Current_Host_Transmit_Buffer_Address,Register 1020 (Current Host Transmit Buffer Address Register)"
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Host Transmit Buffer Address Pointer\nCleared on Reset. Pointer updated by the DMA during operation."
line.long 0xC "Current_Host_Receive_Buffer_Address,Register 1021 (Current Host Receive Buffer Address Register)"
hexmask.long 0xC 0.--31. 1. "CURRBUFAPTR,Host Receive Buffer Address Pointer\nCleared on Reset. Pointer updated by the DMA during operation."
line.long 0x10 "HW_Feature,Register 1022 (HW Feature Register)"
bitfld.long 0x10 28.--30. "ACTPHYIF,Active or Selected PHY interface\nWhen you have multiple PHY interfaces in your configuration  this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "?,?,?,?,?,?,?,?"
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bitfld.long 0x10 27. "SAVLANINS,Source Address or VLAN Insertion" "0,1"
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bitfld.long 0x10 26. "FLEXIPPSEN,Flexible Pulse-Per-Second Output" "0,1"
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bitfld.long 0x10 25. "INTTSEN,Timestamping with Internal System Time" "0,1"
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bitfld.long 0x10 24. "ENHDESSEL,Alternate (Enhanced Descriptor)" "0,1"
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bitfld.long 0x10 22.--23. "TXCHCNT,Number of additional Tx channels" "0,1,2,3"
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bitfld.long 0x10 20.--21. "RXCHCNT,Number of additional Rx channels" "0,1,2,3"
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bitfld.long 0x10 19. "RXFIFOSIZE,Rx FIFO 2 048 Bytes" "0,1"
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bitfld.long 0x10 18. "RXTYP2COE,IP Checksum Offload (Type 2) in Rx" "0,1"
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bitfld.long 0x10 17. "RXTYP1COE,IP Checksum Offload (Type 1) in Rx" "0,1"
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bitfld.long 0x10 16. "TXCOESEL,Checksum Offload in Tx" "0,1"
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bitfld.long 0x10 14. "EEESEL,Energy Efficient Ethernet" "0,1"
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bitfld.long 0x10 13. "TSVER2SEL,IEEE 1588-2008 Advanced Timestamp" "0,1"
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bitfld.long 0x10 12. "TSVER1SEL,Only IEEE 1588-2002 Timestamp" "0,1"
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bitfld.long 0x10 11. "MMCSEL,RMON Module" "0,1"
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bitfld.long 0x10 10. "MGKSEL,PMT Magic Packet" "0,1"
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bitfld.long 0x10 9. "RWKSEL,PMT Remote Wakeup" "0,1"
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bitfld.long 0x10 8. "SMASEL,SMA (MDIO) Interface" "0,1"
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bitfld.long 0x10 7. "L3L4FLTREN,Layer 3 and Layer 4 Filter Feature" "0,1"
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bitfld.long 0x10 6. "PCSSEL,PCS registers (TBI  SGMII  or RTBI PHY interface)" "0,1"
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bitfld.long 0x10 5. "ADDMACADRSEL,Multiple MAC Address Registers" "0,1"
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bitfld.long 0x10 4. "HASHSEL,HASH Filter" "0,1"
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bitfld.long 0x10 3. "EXTHASHEN,Expanded DA Hash Filter" "0,1"
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bitfld.long 0x10 2. "HDSEL,Half-Duplex support" "0,1"
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bitfld.long 0x10 0. "MIISEL,10 or 100 Mbps support" "0,1"
tree.end
tree "EPWM (Enhanced PWM Generator)"
base ad:0x0
tree "EPWM0"
base ad:0x40058000
group.long 0x0++0xB
line.long 0x0 "EPWM_CTL0,EPWM Control Register 0"
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects EPWM output,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled  EPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
bitfld.long 0x0 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
bitfld.long 0x0 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
bitfld.long 0x0 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
bitfld.long 0x0 5. "CTRLD5,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 3. "CTRLD3,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 1. "CTRLD1,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
line.long 0x4 "EPWM_CTL1,EPWM Control Register 1"
bitfld.long 0x4 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function  these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
bitfld.long 0x4 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function  these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x4 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function  these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
bitfld.long 0x4 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
bitfld.long 0x4 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
bitfld.long 0x4 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
bitfld.long 0x4 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
bitfld.long 0x4 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
bitfld.long 0x4 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
line.long 0x8 "EPWM_SYNC,EPWM Synchronization Register"
bitfld.long 0x8 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
bitfld.long 0x8 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x8 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the negative..,1: The inversed state of pin SYNC is passed to the.."
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bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN Disabled,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
bitfld.long 0x8 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
bitfld.long 0x8 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
bitfld.long 0x8 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x8 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
wgroup.long 0xC++0x3
line.long 0x0 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
bitfld.long 0x0 2. "SWSYNC4,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0  SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
bitfld.long 0x0 1. "SWSYNC2,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0  SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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bitfld.long 0x0 0. "SWSYNC0,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0  SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
group.long 0x10++0x3
line.long 0x0 "EPWM_CLKSRC,EPWM Clock Source Register"
bitfld.long 0x0 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
group.long 0x20++0xB
line.long 0x0 "EPWM_CNTEN,EPWM Counter Enable Register"
bitfld.long 0x0 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
bitfld.long 0x0 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
bitfld.long 0x0 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
bitfld.long 0x0 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
line.long 0x4 "EPWM_CNTCLR,EPWM Clear Counter Register"
bitfld.long 0x4 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
bitfld.long 0x4 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
bitfld.long 0x4 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
bitfld.long 0x4 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
line.long 0x8 "EPWM_LOAD,EPWM Load Register"
bitfld.long 0x8 5. "LOAD5,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
bitfld.long 0x8 4. "LOAD4,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 3. "LOAD3,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
bitfld.long 0x8 2. "LOAD2,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 1. "LOAD1,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
bitfld.long 0x8 0. "LOAD0,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
group.long 0x30++0x17
line.long 0x0 "EPWM_PERIOD0,EPWM Period Register 0"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x4 "EPWM_PERIOD1,EPWM Period Register 1"
hexmask.long.word 0x4 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x8 "EPWM_PERIOD2,EPWM Period Register 2"
hexmask.long.word 0x8 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0xC "EPWM_PERIOD3,EPWM Period Register 3"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x10 "EPWM_PERIOD4,EPWM Period Register 4"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x14 "EPWM_PERIOD5,EPWM Period Register 5"
hexmask.long.word 0x14 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
group.long 0x50++0x17
line.long 0x0 "EPWM_CMPDAT0,EPWM Comparator Register 0"
hexmask.long.word 0x0 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x4 "EPWM_CMPDAT1,EPWM Comparator Register 1"
hexmask.long.word 0x4 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x8 "EPWM_CMPDAT2,EPWM Comparator Register 2"
hexmask.long.word 0x8 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0xC "EPWM_CMPDAT3,EPWM Comparator Register 3"
hexmask.long.word 0xC 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x10 "EPWM_CMPDAT4,EPWM Comparator Register 4"
hexmask.long.word 0x10 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x14 "EPWM_CMPDAT5,EPWM Comparator Register 5"
hexmask.long.word 0x14 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
group.long 0x80++0xB
line.long 0x0 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
hexmask.long.word 0x0 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
line.long 0x4 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
hexmask.long.word 0x4 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
line.long 0x8 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
hexmask.long.word 0x8 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
rgroup.long 0x90++0x17
line.long 0x0 "EPWM_CNT0,EPWM Counter Register 0"
bitfld.long 0x0 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x0 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x4 "EPWM_CNT1,EPWM Counter Register 1"
bitfld.long 0x4 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x4 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x8 "EPWM_CNT2,EPWM Counter Register 2"
bitfld.long 0x8 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x8 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0xC "EPWM_CNT3,EPWM Counter Register 3"
bitfld.long 0xC 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0xC 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x10 "EPWM_CNT4,EPWM Counter Register 4"
bitfld.long 0x10 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x10 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x14 "EPWM_CNT5,EPWM Counter Register 5"
bitfld.long 0x14 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x14 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
group.long 0xB0++0x2B
line.long 0x0 "EPWM_WGCTL0,EPWM Generation Register 0"
bitfld.long 0x0 26.--27. "PRDPCTL5,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
bitfld.long 0x0 24.--25. "PRDPCTL4,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
bitfld.long 0x0 20.--21. "PRDPCTL2,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
bitfld.long 0x0 16.--17. "PRDPCTL0,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
bitfld.long 0x0 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
bitfld.long 0x0 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
bitfld.long 0x0 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
line.long 0x4 "EPWM_WGCTL1,EPWM Generation Register 1"
bitfld.long 0x4 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
bitfld.long 0x4 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
bitfld.long 0x4 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
bitfld.long 0x4 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
bitfld.long 0x4 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
bitfld.long 0x4 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
bitfld.long 0x4 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
line.long 0x8 "EPWM_MSKEN,EPWM Mask Enable Register"
bitfld.long 0x8 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
line.long 0xC "EPWM_MSK,EPWM Mask Data Register"
bitfld.long 0xC 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
bitfld.long 0xC 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
bitfld.long 0xC 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
bitfld.long 0xC 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
line.long 0x10 "EPWM_BNF,EPWM Brake Noise Filter Register"
bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting:" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting:" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE1..,1: brake pin event will be detected if EPWMx_BRAKE1.."
bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
bitfld.long 0x10 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE0..,1: brake pin event will be detected if EPWMx_BRAKE0.."
bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
bitfld.long 0x10 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
line.long 0x14 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
line.long 0x18 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
bitfld.long 0x18 30. "EADC2LBEN,Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC2RM as level-detect brake source Disabled,1: EADC2RM as level-detect brake source Enabled"
bitfld.long 0x18 29. "EADC1LBEN,Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as level-detect brake source Disabled,1: EADC1RM as level-detect brake source Enabled"
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bitfld.long 0x18 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
bitfld.long 0x18 22. "EADC2EBEN,Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
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bitfld.long 0x18 21. "EADC1EBEN,Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
bitfld.long 0x18 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
bitfld.long 0x18 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x18 11. "CPO3LBEN,Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as level-detect brake source Disabled,1: ACMP3_O as level-detect brake source Enabled"
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bitfld.long 0x18 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
bitfld.long 0x18 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x18 3. "CPO3EBEN,Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as edge-detect brake source Disabled,1: ACMP3_O as edge-detect brake source Enabled"
bitfld.long 0x18 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
line.long 0x1C "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
bitfld.long 0x1C 30. "EADC2LBEN,Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC2RM as level-detect brake source Disabled,1: EADC2RM as level-detect brake source Enabled"
bitfld.long 0x1C 29. "EADC1LBEN,Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as level-detect brake source Disabled,1: EADC1RM as level-detect brake source Enabled"
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bitfld.long 0x1C 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
bitfld.long 0x1C 22. "EADC2EBEN,Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 21. "EADC1EBEN,Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
bitfld.long 0x1C 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
bitfld.long 0x1C 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x1C 11. "CPO3LBEN,Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as level-detect brake source Disabled,1: ACMP3_O as level-detect brake source Enabled"
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bitfld.long 0x1C 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
bitfld.long 0x1C 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x1C 3. "CPO3EBEN,Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as edge-detect brake source Disabled,1: ACMP3_O as edge-detect brake source Enabled"
bitfld.long 0x1C 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
line.long 0x20 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
bitfld.long 0x20 30. "EADC2LBEN,Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC2RM as level-detect brake source Disabled,1: EADC2RM as level-detect brake source Enabled"
bitfld.long 0x20 29. "EADC1LBEN,Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as level-detect brake source Disabled,1: EADC1RM as level-detect brake source Enabled"
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bitfld.long 0x20 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
bitfld.long 0x20 22. "EADC2EBEN,Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
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bitfld.long 0x20 21. "EADC1EBEN,Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
bitfld.long 0x20 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
bitfld.long 0x20 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x20 11. "CPO3LBEN,Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as level-detect brake source Disabled,1: ACMP3_O as level-detect brake source Enabled"
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bitfld.long 0x20 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
bitfld.long 0x20 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x20 3. "CPO3EBEN,Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as edge-detect brake source Disabled,1: ACMP3_O as edge-detect brake source Enabled"
bitfld.long 0x20 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
line.long 0x24 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
bitfld.long 0x24 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
bitfld.long 0x24 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
bitfld.long 0x24 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
bitfld.long 0x24 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
line.long 0x28 "EPWM_POEN,EPWM Output Enable Register"
bitfld.long 0x28 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
bitfld.long 0x28 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
bitfld.long 0x28 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
bitfld.long 0x28 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
wgroup.long 0xDC++0x3
line.long 0x0 "EPWM_SWBRK,EPWM Software Brake Control Register"
bitfld.long 0x0 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake  and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
bitfld.long 0x0 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake  and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake  and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
bitfld.long 0x0 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake  and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake  and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
bitfld.long 0x0 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake  and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
group.long 0xE0++0xF
line.long 0x0 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
bitfld.long 0x0 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
bitfld.long 0x0 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
bitfld.long 0x0 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
bitfld.long 0x0 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x0 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x0 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
line.long 0x4 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
bitfld.long 0x4 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
bitfld.long 0x4 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
bitfld.long 0x4 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
bitfld.long 0x4 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
line.long 0x8 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
bitfld.long 0x8 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
bitfld.long 0x8 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
bitfld.long 0x8 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
bitfld.long 0x8 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
bitfld.long 0x8 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
bitfld.long 0x8 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
bitfld.long 0x8 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
bitfld.long 0x8 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
bitfld.long 0x8 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
bitfld.long 0x8 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x8 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x8 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x8 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
line.long 0xC "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
rbitfld.long 0xC 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
rbitfld.long 0xC 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
rbitfld.long 0xC 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
rbitfld.long 0xC 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
rbitfld.long 0xC 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
rbitfld.long 0xC 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
rbitfld.long 0xC 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
bitfld.long 0xC 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
bitfld.long 0xC 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
bitfld.long 0xC 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
bitfld.long 0xC 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
bitfld.long 0xC 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
bitfld.long 0xC 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
group.long 0xF4++0x17
line.long 0x0 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
bitfld.long 0x0 29. "CDTRGEN5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 28. "CDTRGEN4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 27. "CDTRGEN3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 26. "CDTRGEN2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 25. "CDTRGEN1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 24. "CDTRGEN0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 21. "CUTRGEN5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 20. "CUTRGEN4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 19. "CUTRGEN3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 18. "CUTRGEN2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 17. "CUTRGEN1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 16. "CUTRGEN0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
line.long 0x4 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
bitfld.long 0x4 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
hexmask.long.byte 0x4 24.--28. 1. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x4 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
hexmask.long.byte 0x4 16.--20. 1. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x4 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
hexmask.long.byte 0x4 8.--12. 1. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x4 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
hexmask.long.byte 0x4 0.--4. 1. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select"
line.long 0x8 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
bitfld.long 0x8 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
hexmask.long.byte 0x8 8.--12. 1. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x8 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
hexmask.long.byte 0x8 0.--4. 1. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select"
line.long 0xC "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
hexmask.long.word 0xC 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
line.long 0x10 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
hexmask.long.word 0x10 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
line.long 0x14 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
hexmask.long.word 0x14 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
group.long 0x110++0x3
line.long 0x0 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
bitfld.long 0x0 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
bitfld.long 0x0 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
bitfld.long 0x0 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
bitfld.long 0x0 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
wgroup.long 0x114++0x3
line.long 0x0 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
bitfld.long 0x0 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
group.long 0x118++0xB
line.long 0x0 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
bitfld.long 0x0 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source rising..,1: When detect leading edge blanking source falling..,2: When detect leading edge blanking source rising..,3: Reserved."
bitfld.long 0x0 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH4..,1: EPWM Leading Edge Blanking Source from EPWM_CH4.."
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bitfld.long 0x0 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH2..,1: EPWM Leading Edge Blanking Source from EPWM_CH2.."
bitfld.long 0x0 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH0..,1: EPWM Leading Edge Blanking Source from EPWM_CH0.."
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bitfld.long 0x0 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
line.long 0x4 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
hexmask.long.word 0x4 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
line.long 0x8 "EPWM_STATUS,EPWM Status Register"
bitfld.long 0x8 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
bitfld.long 0x8 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
bitfld.long 0x8 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
bitfld.long 0x8 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
bitfld.long 0x8 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
bitfld.long 0x8 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
bitfld.long 0x8 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
bitfld.long 0x8 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
bitfld.long 0x8 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
group.long 0x130++0x17
line.long 0x0 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
bitfld.long 0x0 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x0 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x0 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x4 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
bitfld.long 0x4 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x4 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x4 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x4 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x8 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
bitfld.long 0x8 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x8 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x8 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x8 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0xC "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
bitfld.long 0xC 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0xC 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0xC 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0xC 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x10 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
bitfld.long 0x10 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x10 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x10 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x10 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x14 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
bitfld.long 0x14 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x14 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x14 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x14 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
group.long 0x150++0xB
line.long 0x0 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
bitfld.long 0x0 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
line.long 0x4 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
bitfld.long 0x4 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
bitfld.long 0x4 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
bitfld.long 0x4 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
bitfld.long 0x4 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
line.long 0x8 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
group.long 0x160++0x37
line.long 0x0 "EPWM_FDEN,EPWM Fault Detect Enable Register"
bitfld.long 0x0 21. "FDCKS5,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
bitfld.long 0x0 20. "FDCKS4,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 19. "FDCKS3,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
bitfld.long 0x0 18. "FDCKS2,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 17. "FDCKS1,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
bitfld.long 0x0 16. "FDCKS0,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 13. "FDODIS5,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
bitfld.long 0x0 12. "FDODIS4,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x0 11. "FDODIS3,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
bitfld.long 0x0 10. "FDODIS2,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x0 9. "FDODIS1,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
bitfld.long 0x0 8. "FDODIS0,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x0 5. "FDEN5,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
bitfld.long 0x0 4. "FDEN4,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x0 3. "FDEN3,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
bitfld.long 0x0 2. "FDEN2,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x0 1. "FDEN1,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
bitfld.long 0x0 0. "FDEN0,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
line.long 0x4 "EPWM_FDCTL0,EPWM Fault Detect Control Register 0"
bitfld.long 0x4 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x4 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x4 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x4 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x8 "EPWM_FDCTL1,EPWM Fault Detect Control Register 1"
bitfld.long 0x8 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x8 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x8 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x8 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0xC "EPWM_FDCTL2,EPWM Fault Detect Control Register 2"
bitfld.long 0xC 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0xC 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0xC 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0xC 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x10 "EPWM_FDCTL3,EPWM Fault Detect Control Register 3"
bitfld.long 0x10 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x10 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x10 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x10 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x14 "EPWM_FDCTL4,EPWM Fault Detect Control Register 4"
bitfld.long 0x14 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x14 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x14 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x14 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x14 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x18 "EPWM_FDCTL5,EPWM Fault Detect Control Register 5"
bitfld.long 0x18 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x18 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x18 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x18 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x1C "EPWM_FDIEN,EPWM Fault Detect Interrupt Enable Register"
bitfld.long 0x1C 0. "FDIENn,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disabled,1: EPWM Channel n Fault Detect Interrupt Enabled"
line.long 0x20 "EPWM_FDSTS,EPWM Fault Detect Interrupt Flag Register"
hexmask.long.byte 0x20 0.--5. 1. "FDIFn,EPWM Channel n Fault Detect Interrupt Flag Bit\nFault Detect Interrupt Flag will be set when EPWM output short. Software can clear this bit by writing 1 to it."
line.long 0x24 "EPWM_EADCPSCCTL,EPWM Trigger EADC Prescale Control Register"
bitfld.long 0x24 5. "PSCEN5,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
bitfld.long 0x24 4. "PSCEN4,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
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bitfld.long 0x24 3. "PSCEN3,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
bitfld.long 0x24 2. "PSCEN2,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
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bitfld.long 0x24 1. "PSCEN1,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
bitfld.long 0x24 0. "PSCEN0,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
line.long 0x28 "EPWM_EADCPSC0,EPWM Trigger EADC Prescale Register 0"
hexmask.long.byte 0x28 24.--27. 1. "EADCPSC3,EPWM Channel 3 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3."
hexmask.long.byte 0x28 16.--19. 1. "EADCPSC2,EPWM Channel 2 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2."
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hexmask.long.byte 0x28 8.--11. 1. "EADCPSC1,EPWM Channel 1 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1."
hexmask.long.byte 0x28 0.--3. 1. "EADCPSC0,EPWM Channel 0 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0."
line.long 0x2C "EPWM_EADCPSC1,EPWM Trigger EADC Prescale Register 1"
hexmask.long.byte 0x2C 8.--11. 1. "EADCPSC5,EPWM Channel 5 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5."
hexmask.long.byte 0x2C 0.--3. 1. "EADCPSC4,EPWM Channel 4 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4."
line.long 0x30 "EPWM_EADCPSCNT0,EPWM Trigger EADC Prescale Counter Register 0"
hexmask.long.byte 0x30 24.--27. 1. "PSCNT3,EPWM Trigger EADC Prescale Counter 3\nUser can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN3 is 0.\nNote 2: Write data limitation: PSCNT3 EADCPSC3."
hexmask.long.byte 0x30 16.--19. 1. "PSCNT2,EPWM Trigger EADC Prescale Counter 2\nUser can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN2 is 0.\nNote 2: Write data limitation: PSCNT2 EADCPSC2."
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hexmask.long.byte 0x30 8.--11. 1. "PSCNT1,EPWM Trigger EADC Prescale Counter 1\nUser can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN1 is 0.\nNote 2: Write data limitation: PSCNT1 EADCPSC1."
hexmask.long.byte 0x30 0.--3. 1. "PSCNT0,EPWM Trigger EADC Prescale Counter 0\nUser can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN0 is 0.\nNote 2: Write data limitation: PSCNT0 EADCPSC0."
line.long 0x34 "EPWM_EADCPSCNT1,EPWM Trigger EADC Prescale Counter Register 1"
hexmask.long.byte 0x34 8.--11. 1. "PSCNT5,EPWM Trigger EADC Prescale Counter 5\nUser can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: User can write only when PSCEN5 is 0.\nNote 2: Write data limitation: PSCNT5 EADCPSC5."
hexmask.long.byte 0x34 0.--3. 1. "PSCNT4,EPWM Trigger EADC Prescale Counter 4\nUser can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: User can write only when PSCEN4 is 0.\nNote 2: Write data limitation: PSCNT4 EADCPSC4."
group.long 0x200++0x7
line.long 0x0 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
line.long 0x4 "EPWM_CAPCTL,EPWM Capture Control Register"
bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
rgroup.long 0x208++0x33
line.long 0x0 "EPWM_CAPSTS,EPWM Capture Status Register"
bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
line.long 0x4 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x8 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0xC "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x10 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x14 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x18 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x1C "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x20 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x24 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x28 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x2C "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x30 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
group.long 0x23C++0x3
line.long 0x0 "EPWM_PDMACTL,EPWM PDMA Control Register"
bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT4/5,?,?"
bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT2/3,?,?"
bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT0/1,?,?"
bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
rgroup.long 0x240++0xB
line.long 0x0 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
hexmask.long.word 0x0 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
line.long 0x4 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
hexmask.long.word 0x4 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
line.long 0x8 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
hexmask.long.word 0x8 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
group.long 0x250++0x73
line.long 0x0 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
bitfld.long 0x0 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x0 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x0 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x0 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x0 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x0 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x0 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
line.long 0x4 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
bitfld.long 0x4 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
line.long 0x8 "EPWM_CAPNF0,EPWM Capture Input Noise Filter Register 0"
bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0xC "EPWM_CAPNF1,EPWM Capture Input Noise Filter Register 1"
bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x10 "EPWM_CAPNF2,EPWM Capture Input Noise Filter Register 2"
bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x14 "EPWM_CAPNF3,EPWM Capture Input Noise Filter Register 3"
bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x18 "EPWM_CAPNF4,EPWM Capture Input Noise Filter Register 4"
bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x1C "EPWM_CAPNF5,EPWM Capture Input Noise Filter Register 5"
bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x20 "EPWM_EXTETCTL0,EPWM External Event Trigger Control Register 0"
hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x20 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x24 "EPWM_EXTETCTL1,EPWM External Event Trigger Control Register 1"
hexmask.long.byte 0x24 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x24 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x24 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x28 "EPWM_EXTETCTL2,EPWM External Event Trigger Control Register 2"
hexmask.long.byte 0x28 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x28 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x28 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x2C "EPWM_EXTETCTL3,EPWM External Event Trigger Control Register 3"
hexmask.long.byte 0x2C 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x2C 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x2C 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x30 "EPWM_EXTETCTL4,EPWM External Event Trigger Control Register 4"
hexmask.long.byte 0x30 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x30 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x30 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x34 "EPWM_EXTETCTL5,EPWM External Event Trigger Control Register 5"
hexmask.long.byte 0x34 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x34 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x34 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x38 "EPWM_SWEOFCTL,EPWM Software Event Output Force Control Register"
bitfld.long 0x38 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
bitfld.long 0x38 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
bitfld.long 0x38 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
bitfld.long 0x38 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
line.long 0x3C "EPWM_SWEOFTRG,EPWM Software Event Output Force Trigger Register"
bitfld.long 0x3C 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
bitfld.long 0x3C 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
bitfld.long 0x3C 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
bitfld.long 0x3C 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
line.long 0x40 "EPWM_CLKPSC0,EPWM Clock Prescale Register 0"
hexmask.long.word 0x40 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x44 "EPWM_CLKPSC1,EPWM Clock Prescale Register 1"
hexmask.long.word 0x44 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x48 "EPWM_CLKPSC2,EPWM Clock Prescale Register 2"
hexmask.long.word 0x48 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x4C "EPWM_CLKPSC3,EPWM Clock Prescale Register 3"
hexmask.long.word 0x4C 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x50 "EPWM_CLKPSC4,EPWM Clock Prescale Register 4"
hexmask.long.word 0x50 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x54 "EPWM_CLKPSC5,EPWM Clock Prescale Register 5"
hexmask.long.word 0x54 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x58 "EPWM_RDTCNT0_1,EPWM Rising Dead-time Counter Register 0/1"
hexmask.long.word 0x58 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x5C "EPWM_RDTCNT2_3,EPWM Rising Dead-time Counter Register 2/3"
hexmask.long.word 0x5C 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x60 "EPWM_RDTCNT4_5,EPWM Rising Dead-time Counter Register 4/5"
hexmask.long.word 0x60 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x64 "EPWM_FDTCNT0_1,EPWM Falling Dead-time Counter Register 0/1"
hexmask.long.word 0x64 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x68 "EPWM_FDTCNT2_3,EPWM Falling Dead-time Counter Register 2/3"
hexmask.long.word 0x68 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x6C "EPWM_FDTCNT4_5,EPWM Falling Dead-time Counter Register 4/5"
hexmask.long.word 0x6C 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x70 "EPWM_DTCTL,EPWM Dead-time Control Register"
bitfld.long 0x70 16. "DTCKSELn,Dead-time Clock Select for EPWM Pair (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x70 10. "FDTEN4,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 9. "FDTEN2,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
bitfld.long 0x70 8. "FDTEN0,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 2. "RDTEN4,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
bitfld.long 0x70 1. "RDTEN2,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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bitfld.long 0x70 0. "RDTEN0,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
rgroup.long 0x304++0x2F
line.long 0x0 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
hexmask.long.word 0x0 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x4 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
hexmask.long.word 0x4 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x8 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
hexmask.long.word 0x8 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0xC "EPWM_PBUF3,EPWM PERIOD3 Buffer"
hexmask.long.word 0xC 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x10 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
hexmask.long.word 0x10 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x14 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
hexmask.long.word 0x14 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x18 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
hexmask.long.word 0x18 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x1C "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x20 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
hexmask.long.word 0x20 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x24 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
hexmask.long.word 0x24 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x28 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
hexmask.long.word 0x28 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x2C "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
rgroup.long 0x340++0xB
line.long 0x0 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
hexmask.long.word 0x0 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
line.long 0x4 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
hexmask.long.word 0x4 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
line.long 0x8 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
hexmask.long.word 0x8 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
group.long 0x34C++0x3
line.long 0x0 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
bitfld.long 0x0 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
rgroup.long 0x350++0x2F
line.long 0x0 "EPWM_CPSCBUF0,EPWM CLKPSC0 Buffer"
hexmask.long.word 0x0 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x4 "EPWM_CPSCBUF1,EPWM CLKPSC1 Buffer"
hexmask.long.word 0x4 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x8 "EPWM_CPSCBUF2,EPWM CLKPSC2 Buffer"
hexmask.long.word 0x8 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0xC "EPWM_CPSCBUF3,EPWM CLKPSC3 Buffer"
hexmask.long.word 0xC 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x10 "EPWM_CPSCBUF4,EPWM CLKPSC4 Buffer"
hexmask.long.word 0x10 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x14 "EPWM_CPSCBUF5,EPWM CLKPSC5 Buffer"
hexmask.long.word 0x14 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x18 "EPWM_IFACNT0,EPWM Interrupt Flag Accumulator Counter 0"
hexmask.long.word 0x18 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x1C "EPWM_IFACNT1,EPWM Interrupt Flag Accumulator Counter 1"
hexmask.long.word 0x1C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x20 "EPWM_IFACNT2,EPWM Interrupt Flag Accumulator Counter 2"
hexmask.long.word 0x20 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x24 "EPWM_IFACNT3,EPWM Interrupt Flag Accumulator Counter 3"
hexmask.long.word 0x24 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x28 "EPWM_IFACNT4,EPWM Interrupt Flag Accumulator Counter 4"
hexmask.long.word 0x28 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x2C "EPWM_IFACNT5,EPWM Interrupt Flag Accumulator Counter 5"
hexmask.long.word 0x2C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
tree.end
tree "EPWM1"
base ad:0x40059000
group.long 0x0++0xB
line.long 0x0 "EPWM_CTL0,EPWM Control Register 0"
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects EPWM output,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled  EPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled  WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
bitfld.long 0x0 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
bitfld.long 0x0 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
bitfld.long 0x0 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
bitfld.long 0x0 5. "CTRLD5,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 3. "CTRLD3,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
bitfld.long 0x0 1. "CTRLD1,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load\nIn up-down counter type  PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
line.long 0x4 "EPWM_CTL1,EPWM Control Register 1"
bitfld.long 0x4 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function  these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
bitfld.long 0x4 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function  these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x4 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function  these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
bitfld.long 0x4 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
bitfld.long 0x4 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
bitfld.long 0x4 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
bitfld.long 0x4 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
bitfld.long 0x4 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
bitfld.long 0x4 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
line.long 0x8 "EPWM_SYNC,EPWM Synchronization Register"
bitfld.long 0x8 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
bitfld.long 0x8 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x8 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the negative..,1: The inversed state of pin SYNC is passed to the.."
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bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN Disabled,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
bitfld.long 0x8 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
bitfld.long 0x8 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
bitfld.long 0x8 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x8 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
wgroup.long 0xC++0x3
line.long 0x0 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
bitfld.long 0x0 2. "SWSYNC4,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0  SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
bitfld.long 0x0 1. "SWSYNC2,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0  SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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bitfld.long 0x0 0. "SWSYNC0,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0  SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
group.long 0x10++0x3
line.long 0x0 "EPWM_CLKSRC,EPWM Clock Source Register"
bitfld.long 0x0 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
group.long 0x20++0xB
line.long 0x0 "EPWM_CNTEN,EPWM Counter Enable Register"
bitfld.long 0x0 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
bitfld.long 0x0 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
bitfld.long 0x0 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
bitfld.long 0x0 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
line.long 0x4 "EPWM_CNTCLR,EPWM Clear Counter Register"
bitfld.long 0x4 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
bitfld.long 0x4 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
bitfld.long 0x4 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
bitfld.long 0x4 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
line.long 0x8 "EPWM_LOAD,EPWM Load Register"
bitfld.long 0x8 5. "LOAD5,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
bitfld.long 0x8 4. "LOAD4,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 3. "LOAD3,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
bitfld.long 0x8 2. "LOAD2,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 1. "LOAD1,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
bitfld.long 0x8 0. "LOAD0,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
group.long 0x30++0x17
line.long 0x0 "EPWM_PERIOD0,EPWM Period Register 0"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x4 "EPWM_PERIOD1,EPWM Period Register 1"
hexmask.long.word 0x4 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x8 "EPWM_PERIOD2,EPWM Period Register 2"
hexmask.long.word 0x8 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0xC "EPWM_PERIOD3,EPWM Period Register 3"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x10 "EPWM_PERIOD4,EPWM Period Register 4"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
line.long 0x14 "EPWM_PERIOD5,EPWM Period Register 5"
hexmask.long.word 0x14 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode  EPWM counter counts from 0 to PERIOD  and restarts from 0."
group.long 0x50++0x17
line.long 0x0 "EPWM_CMPDAT0,EPWM Comparator Register 0"
hexmask.long.word 0x0 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x4 "EPWM_CMPDAT1,EPWM Comparator Register 1"
hexmask.long.word 0x4 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x8 "EPWM_CMPDAT2,EPWM Comparator Register 2"
hexmask.long.word 0x8 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0xC "EPWM_CMPDAT3,EPWM Comparator Register 3"
hexmask.long.word 0xC 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x10 "EPWM_CMPDAT4,EPWM Comparator Register 4"
hexmask.long.word 0x10 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
line.long 0x14 "EPWM_CMPDAT5,EPWM Comparator Register 5"
hexmask.long.word 0x14 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform  interrupt and trigger EADC/DAC.\nIn complementary mode  EPWM_CMPDAT0  EPWM_CMPDAT 2  EPWM_CMPDAT4 denote as first compared point  and.."
group.long 0x80++0xB
line.long 0x0 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
hexmask.long.word 0x0 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
line.long 0x4 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
hexmask.long.word 0x4 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
line.long 0x8 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
hexmask.long.word 0x8 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
rgroup.long 0x90++0x17
line.long 0x0 "EPWM_CNT0,EPWM Counter Register 0"
bitfld.long 0x0 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x0 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x4 "EPWM_CNT1,EPWM Counter Register 1"
bitfld.long 0x4 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x4 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x8 "EPWM_CNT2,EPWM Counter Register 2"
bitfld.long 0x8 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x8 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0xC "EPWM_CNT3,EPWM Counter Register 3"
bitfld.long 0xC 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0xC 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x10 "EPWM_CNT4,EPWM Counter Register 4"
bitfld.long 0x10 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x10 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
line.long 0x14 "EPWM_CNT5,EPWM Counter Register 5"
bitfld.long 0x14 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x14 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
group.long 0xB0++0x2B
line.long 0x0 "EPWM_WGCTL0,EPWM Generation Register 0"
bitfld.long 0x0 26.--27. "PRDPCTL5,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
bitfld.long 0x0 24.--25. "PRDPCTL4,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
bitfld.long 0x0 20.--21. "PRDPCTL2,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
bitfld.long 0x0 16.--17. "PRDPCTL0,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
bitfld.long 0x0 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
bitfld.long 0x0 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
bitfld.long 0x0 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
line.long 0x4 "EPWM_WGCTL1,EPWM Generation Register 1"
bitfld.long 0x4 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
bitfld.long 0x4 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
bitfld.long 0x4 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
bitfld.long 0x4 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode  CMPDCTL1  3  5 is used as another CMPDCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
bitfld.long 0x4 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
bitfld.long 0x4 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
bitfld.long 0x4 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode  CMPUCTL1  3  5 is used as another CMPUCTL for channel 0  2  4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
line.long 0x8 "EPWM_MSKEN,EPWM Mask Enable Register"
bitfld.long 0x8 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
bitfld.long 0x8 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
line.long 0xC "EPWM_MSK,EPWM Mask Data Register"
bitfld.long 0xC 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
bitfld.long 0xC 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
bitfld.long 0xC 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
bitfld.long 0xC 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin  if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
line.long 0x10 "EPWM_BNF,EPWM Brake Noise Filter Register"
bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting:" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting:" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE1..,1: brake pin event will be detected if EPWMx_BRAKE1.."
bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
bitfld.long 0x10 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE0..,1: brake pin event will be detected if EPWMx_BRAKE0.."
bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
bitfld.long 0x10 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
line.long 0x14 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
line.long 0x18 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
bitfld.long 0x18 30. "EADC2LBEN,Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC2RM as level-detect brake source Disabled,1: EADC2RM as level-detect brake source Enabled"
bitfld.long 0x18 29. "EADC1LBEN,Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as level-detect brake source Disabled,1: EADC1RM as level-detect brake source Enabled"
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bitfld.long 0x18 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
bitfld.long 0x18 22. "EADC2EBEN,Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
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bitfld.long 0x18 21. "EADC1EBEN,Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
bitfld.long 0x18 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
bitfld.long 0x18 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x18 11. "CPO3LBEN,Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as level-detect brake source Disabled,1: ACMP3_O as level-detect brake source Enabled"
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bitfld.long 0x18 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
bitfld.long 0x18 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x18 3. "CPO3EBEN,Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as edge-detect brake source Disabled,1: ACMP3_O as edge-detect brake source Enabled"
bitfld.long 0x18 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
line.long 0x1C "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
bitfld.long 0x1C 30. "EADC2LBEN,Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC2RM as level-detect brake source Disabled,1: EADC2RM as level-detect brake source Enabled"
bitfld.long 0x1C 29. "EADC1LBEN,Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as level-detect brake source Disabled,1: EADC1RM as level-detect brake source Enabled"
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bitfld.long 0x1C 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
bitfld.long 0x1C 22. "EADC2EBEN,Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 21. "EADC1EBEN,Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
bitfld.long 0x1C 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
bitfld.long 0x1C 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x1C 11. "CPO3LBEN,Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as level-detect brake source Disabled,1: ACMP3_O as level-detect brake source Enabled"
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bitfld.long 0x1C 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
bitfld.long 0x1C 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x1C 3. "CPO3EBEN,Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as edge-detect brake source Disabled,1: ACMP3_O as edge-detect brake source Enabled"
bitfld.long 0x1C 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
line.long 0x20 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
bitfld.long 0x20 30. "EADC2LBEN,Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC2RM as level-detect brake source Disabled,1: EADC2RM as level-detect brake source Enabled"
bitfld.long 0x20 29. "EADC1LBEN,Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as level-detect brake source Disabled,1: EADC1RM as level-detect brake source Enabled"
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bitfld.long 0x20 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
bitfld.long 0x20 22. "EADC2EBEN,Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
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bitfld.long 0x20 21. "EADC1EBEN,Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC1RM as edge-detect brake source Disabled,1: EADC1RM as edge-detect brake source Enabled"
bitfld.long 0x20 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
bitfld.long 0x20 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x20 11. "CPO3LBEN,Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as level-detect brake source Disabled,1: ACMP3_O as level-detect brake source Enabled"
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bitfld.long 0x20 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
bitfld.long 0x20 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x20 3. "CPO3EBEN,Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP3_O as edge-detect brake source Disabled,1: ACMP3_O as edge-detect brake source Enabled"
bitfld.long 0x20 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
line.long 0x24 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
bitfld.long 0x24 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
bitfld.long 0x24 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
bitfld.long 0x24 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
bitfld.long 0x24 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
line.long 0x28 "EPWM_POEN,EPWM Output Enable Register"
bitfld.long 0x28 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
bitfld.long 0x28 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
bitfld.long 0x28 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
bitfld.long 0x28 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
wgroup.long 0xDC++0x3
line.long 0x0 "EPWM_SWBRK,EPWM Software Brake Control Register"
bitfld.long 0x0 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake  and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
bitfld.long 0x0 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake  and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake  and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
bitfld.long 0x0 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake  and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake  and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
bitfld.long 0x0 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake  and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
group.long 0xE0++0xF
line.long 0x0 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
bitfld.long 0x0 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode  CMPDIEN1  3  5 is used as another CMPDIEN for channel 0  2  4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x0 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode  CMPUIEN1  3  5 is used as another CMPUIEN for channel 0  2  4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
bitfld.long 0x0 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
bitfld.long 0x0 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
bitfld.long 0x0 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x0 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x0 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
line.long 0x4 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
bitfld.long 0x4 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
bitfld.long 0x4 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
bitfld.long 0x4 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
bitfld.long 0x4 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
line.long 0x8 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
bitfld.long 0x8 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
bitfld.long 0x8 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
bitfld.long 0x8 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
bitfld.long 0x8 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPDIF1  3  5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
bitfld.long 0x8 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
bitfld.long 0x8 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
bitfld.long 0x8 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn  software can clear this bit by writing 1 to it.\nNote: In complementary mode  CMPUIF1  3  5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
bitfld.long 0x8 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
bitfld.long 0x8 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
bitfld.long 0x8 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x8 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x8 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x8 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
line.long 0xC "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
rbitfld.long 0xC 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
rbitfld.long 0xC 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
rbitfld.long 0xC 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
rbitfld.long 0xC 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
rbitfld.long 0xC 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
rbitfld.long 0xC 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
rbitfld.long 0xC 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared  EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
bitfld.long 0xC 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
bitfld.long 0xC 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
bitfld.long 0xC 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
bitfld.long 0xC 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
bitfld.long 0xC 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
bitfld.long 0xC 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
group.long 0xF4++0x17
line.long 0x0 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
bitfld.long 0x0 29. "CDTRGEN5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 28. "CDTRGEN4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 27. "CDTRGEN3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 26. "CDTRGEN2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 25. "CDTRGEN1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 24. "CDTRGEN0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 21. "CUTRGEN5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 20. "CUTRGEN4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 19. "CUTRGEN3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 18. "CUTRGEN2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 17. "CUTRGEN1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
bitfld.long 0x0 16. "CUTRGEN0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
bitfld.long 0x0 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
line.long 0x4 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
bitfld.long 0x4 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
hexmask.long.byte 0x4 24.--28. 1. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x4 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
hexmask.long.byte 0x4 16.--20. 1. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x4 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
hexmask.long.byte 0x4 8.--12. 1. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x4 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
hexmask.long.byte 0x4 0.--4. 1. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select"
line.long 0x8 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
bitfld.long 0x8 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
hexmask.long.byte 0x8 8.--12. 1. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x8 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
hexmask.long.byte 0x8 0.--4. 1. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select"
line.long 0xC "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
hexmask.long.word 0xC 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
line.long 0x10 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
hexmask.long.word 0x10 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
line.long 0x14 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
hexmask.long.word 0x14 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
group.long 0x110++0x3
line.long 0x0 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
bitfld.long 0x0 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
bitfld.long 0x0 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
bitfld.long 0x0 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
bitfld.long 0x0 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled  the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
wgroup.long 0x114++0x3
line.long 0x0 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
bitfld.long 0x0 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
group.long 0x118++0xB
line.long 0x0 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
bitfld.long 0x0 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source rising..,1: When detect leading edge blanking source falling..,2: When detect leading edge blanking source rising..,3: Reserved."
bitfld.long 0x0 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH4..,1: EPWM Leading Edge Blanking Source from EPWM_CH4.."
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bitfld.long 0x0 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH2..,1: EPWM Leading Edge Blanking Source from EPWM_CH2.."
bitfld.long 0x0 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH0..,1: EPWM Leading Edge Blanking Source from EPWM_CH0.."
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bitfld.long 0x0 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
line.long 0x4 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
hexmask.long.word 0x4 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
line.long 0x8 "EPWM_STATUS,EPWM Status Register"
bitfld.long 0x8 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
bitfld.long 0x8 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
bitfld.long 0x8 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
bitfld.long 0x8 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
bitfld.long 0x8 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
bitfld.long 0x8 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
bitfld.long 0x8 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
bitfld.long 0x8 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
bitfld.long 0x8 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
group.long 0x130++0x17
line.long 0x0 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
bitfld.long 0x0 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x0 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x0 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x4 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
bitfld.long 0x4 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x4 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x4 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x4 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x8 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
bitfld.long 0x8 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x8 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x8 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x8 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0xC "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
bitfld.long 0xC 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0xC 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0xC 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0xC 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x10 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
bitfld.long 0x10 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x10 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x10 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x10 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
line.long 0x14 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
bitfld.long 0x14 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
bitfld.long 0x14 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x14 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disabled,1: EPWM_CHn Stop Mode Enabled"
hexmask.long.word 0x14 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
group.long 0x150++0xB
line.long 0x0 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
bitfld.long 0x0 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register  software can clear this bit by writing 1 to it." "0,1"
line.long 0x4 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
bitfld.long 0x4 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
bitfld.long 0x4 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
bitfld.long 0x4 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
bitfld.long 0x4 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
line.long 0x8 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
group.long 0x160++0x37
line.long 0x0 "EPWM_FDEN,EPWM Fault Detect Enable Register"
bitfld.long 0x0 21. "FDCKS5,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
bitfld.long 0x0 20. "FDCKS4,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 19. "FDCKS3,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
bitfld.long 0x0 18. "FDCKS2,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 17. "FDCKS1,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
bitfld.long 0x0 16. "FDCKS0,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 13. "FDODIS5,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
bitfld.long 0x0 12. "FDODIS4,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x0 11. "FDODIS3,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
bitfld.long 0x0 10. "FDODIS2,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x0 9. "FDODIS1,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
bitfld.long 0x0 8. "FDODIS0,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enabled,1: EPWM detect fault and output Disabled"
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bitfld.long 0x0 5. "FDEN5,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
bitfld.long 0x0 4. "FDEN4,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x0 3. "FDEN3,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
bitfld.long 0x0 2. "FDEN2,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
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bitfld.long 0x0 1. "FDEN1,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
bitfld.long 0x0 0. "FDEN0,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disabled,1: Fault detect function Enabled"
line.long 0x4 "EPWM_FDCTL0,EPWM Fault Detect Control Register 0"
bitfld.long 0x4 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x4 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x4 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x4 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x8 "EPWM_FDCTL1,EPWM Fault Detect Control Register 1"
bitfld.long 0x8 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x8 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x8 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x8 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0xC "EPWM_FDCTL2,EPWM Fault Detect Control Register 2"
bitfld.long 0xC 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0xC 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0xC 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0xC 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x10 "EPWM_FDCTL3,EPWM Fault Detect Control Register 3"
bitfld.long 0x10 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x10 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x10 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x10 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x14 "EPWM_FDCTL4,EPWM Fault Detect Control Register 4"
bitfld.long 0x14 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x14 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x14 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x14 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x14 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x18 "EPWM_FDCTL5,EPWM Fault Detect Control Register 5"
bitfld.long 0x18 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disabled,1: Fault detect deglitch function Enabled"
bitfld.long 0x18 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x18 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disabled,1: Fault detect mask function Enabled"
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hexmask.long.byte 0x18 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL).."
line.long 0x1C "EPWM_FDIEN,EPWM Fault Detect Interrupt Enable Register"
bitfld.long 0x1C 0. "FDIENn,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disabled,1: EPWM Channel n Fault Detect Interrupt Enabled"
line.long 0x20 "EPWM_FDSTS,EPWM Fault Detect Interrupt Flag Register"
hexmask.long.byte 0x20 0.--5. 1. "FDIFn,EPWM Channel n Fault Detect Interrupt Flag Bit\nFault Detect Interrupt Flag will be set when EPWM output short. Software can clear this bit by writing 1 to it."
line.long 0x24 "EPWM_EADCPSCCTL,EPWM Trigger EADC Prescale Control Register"
bitfld.long 0x24 5. "PSCEN5,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
bitfld.long 0x24 4. "PSCEN4,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
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bitfld.long 0x24 3. "PSCEN3,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
bitfld.long 0x24 2. "PSCEN2,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
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bitfld.long 0x24 1. "PSCEN1,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
bitfld.long 0x24 0. "PSCEN0,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disabled,1: EPWM Trigger EADC Pre-scale Function Enabled"
line.long 0x28 "EPWM_EADCPSC0,EPWM Trigger EADC Prescale Register 0"
hexmask.long.byte 0x28 24.--27. 1. "EADCPSC3,EPWM Channel 3 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3."
hexmask.long.byte 0x28 16.--19. 1. "EADCPSC2,EPWM Channel 2 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2."
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hexmask.long.byte 0x28 8.--11. 1. "EADCPSC1,EPWM Channel 1 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1."
hexmask.long.byte 0x28 0.--3. 1. "EADCPSC0,EPWM Channel 0 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0."
line.long 0x2C "EPWM_EADCPSC1,EPWM Trigger EADC Prescale Register 1"
hexmask.long.byte 0x2C 8.--11. 1. "EADCPSC5,EPWM Channel 5 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5."
hexmask.long.byte 0x2C 0.--3. 1. "EADCPSC4,EPWM Channel 4 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4."
line.long 0x30 "EPWM_EADCPSCNT0,EPWM Trigger EADC Prescale Counter Register 0"
hexmask.long.byte 0x30 24.--27. 1. "PSCNT3,EPWM Trigger EADC Prescale Counter 3\nUser can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN3 is 0.\nNote 2: Write data limitation: PSCNT3 EADCPSC3."
hexmask.long.byte 0x30 16.--19. 1. "PSCNT2,EPWM Trigger EADC Prescale Counter 2\nUser can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN2 is 0.\nNote 2: Write data limitation: PSCNT2 EADCPSC2."
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hexmask.long.byte 0x30 8.--11. 1. "PSCNT1,EPWM Trigger EADC Prescale Counter 1\nUser can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN1 is 0.\nNote 2: Write data limitation: PSCNT1 EADCPSC1."
hexmask.long.byte 0x30 0.--3. 1. "PSCNT0,EPWM Trigger EADC Prescale Counter 0\nUser can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN0 is 0.\nNote 2: Write data limitation: PSCNT0 EADCPSC0."
line.long 0x34 "EPWM_EADCPSCNT1,EPWM Trigger EADC Prescale Counter Register 1"
hexmask.long.byte 0x34 8.--11. 1. "PSCNT5,EPWM Trigger EADC Prescale Counter 5\nUser can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: User can write only when PSCEN5 is 0.\nNote 2: Write data limitation: PSCNT5 EADCPSC5."
hexmask.long.byte 0x34 0.--3. 1. "PSCNT4,EPWM Trigger EADC Prescale Counter 4\nUser can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: User can write only when PSCEN4 is 0.\nNote 2: Write data limitation: PSCNT4 EADCPSC4."
group.long 0x200++0x7
line.long 0x0 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
line.long 0x4 "EPWM_CAPCTL,EPWM Capture Control Register"
bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
rgroup.long 0x208++0x33
line.long 0x0 "EPWM_CAPSTS,EPWM Capture Status Register"
bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clears corresponding.." "0,1"
line.long 0x4 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x8 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0xC "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x10 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x14 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x18 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x1C "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x20 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x24 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x28 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x2C "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened  the EPWM counter value will be saved in this register."
line.long 0x30 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened  the EPWM counter value will be saved in this register."
group.long 0x23C++0x3
line.long 0x0 "EPWM_PDMACTL,EPWM PDMA Control Register"
bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT4/5,?,?"
bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT2/3,?,?"
bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT0/1,?,?"
bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
rgroup.long 0x240++0xB
line.long 0x0 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
hexmask.long.word 0x0 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
line.long 0x4 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
hexmask.long.word 0x4 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
line.long 0x8 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
hexmask.long.word 0x8 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
group.long 0x250++0x73
line.long 0x0 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
bitfld.long 0x0 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x0 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x0 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x0 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x0 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x0 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x0 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
line.long 0x4 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
bitfld.long 0x4 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
bitfld.long 0x4 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating  EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
line.long 0x8 "EPWM_CAPNF0,EPWM Capture Input Noise Filter Register 0"
bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0xC "EPWM_CAPNF1,EPWM Capture Input Noise Filter Register 1"
bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x10 "EPWM_CAPNF2,EPWM Capture Input Noise Filter Register 2"
bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x14 "EPWM_CAPNF3,EPWM Capture Input Noise Filter Register 3"
bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x18 "EPWM_CAPNF4,EPWM Capture Input Noise Filter Register 4"
bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x1C "EPWM_CAPNF5,EPWM Capture Input Noise Filter Register 5"
bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
line.long 0x20 "EPWM_EXTETCTL0,EPWM External Event Trigger Control Register 0"
hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x20 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x24 "EPWM_EXTETCTL1,EPWM External Event Trigger Control Register 1"
hexmask.long.byte 0x24 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x24 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x24 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x28 "EPWM_EXTETCTL2,EPWM External Event Trigger Control Register 2"
hexmask.long.byte 0x28 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x28 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x28 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x2C "EPWM_EXTETCTL3,EPWM External Event Trigger Control Register 3"
hexmask.long.byte 0x2C 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x2C 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x2C 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x30 "EPWM_EXTETCTL4,EPWM External Event Trigger Control Register 4"
hexmask.long.byte 0x30 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x30 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x30 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x34 "EPWM_EXTETCTL5,EPWM External Event Trigger Control Register 5"
hexmask.long.byte 0x34 8.--11. 1. "EXTTRGS,External Trigger Selection"
bitfld.long 0x34 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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bitfld.long 0x34 0. "EXETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
line.long 0x38 "EPWM_SWEOFCTL,EPWM Software Event Output Force Control Register"
bitfld.long 0x38 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
bitfld.long 0x38 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
bitfld.long 0x38 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
bitfld.long 0x38 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
line.long 0x3C "EPWM_SWEOFTRG,EPWM Software Event Output Force Trigger Register"
bitfld.long 0x3C 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
bitfld.long 0x3C 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
bitfld.long 0x3C 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
bitfld.long 0x3C 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
line.long 0x40 "EPWM_CLKPSC0,EPWM Clock Prescale Register 0"
hexmask.long.word 0x40 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x44 "EPWM_CLKPSC1,EPWM Clock Prescale Register 1"
hexmask.long.word 0x44 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x48 "EPWM_CLKPSC2,EPWM Clock Prescale Register 2"
hexmask.long.word 0x48 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x4C "EPWM_CLKPSC3,EPWM Clock Prescale Register 3"
hexmask.long.word 0x4C 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x50 "EPWM_CLKPSC4,EPWM Clock Prescale Register 4"
hexmask.long.word 0x50 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x54 "EPWM_CLKPSC5,EPWM Clock Prescale Register 5"
hexmask.long.word 0x54 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair shares one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
line.long 0x58 "EPWM_RDTCNT0_1,EPWM Rising Dead-time Counter Register 0/1"
hexmask.long.word 0x58 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x5C "EPWM_RDTCNT2_3,EPWM Rising Dead-time Counter Register 2/3"
hexmask.long.word 0x5C 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x60 "EPWM_RDTCNT4_5,EPWM Rising Dead-time Counter Register 4/5"
hexmask.long.word 0x60 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x64 "EPWM_FDTCNT0_1,EPWM Falling Dead-time Counter Register 0/1"
hexmask.long.word 0x64 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x68 "EPWM_FDTCNT2_3,EPWM Falling Dead-time Counter Register 2/3"
hexmask.long.word 0x68 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x6C "EPWM_FDTCNT4_5,EPWM Falling Dead-time Counter Register 4/5"
hexmask.long.word 0x6C 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
line.long 0x70 "EPWM_DTCTL,EPWM Dead-time Control Register"
bitfld.long 0x70 16. "DTCKSELn,Dead-time Clock Select for EPWM Pair (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x70 10. "FDTEN4,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 9. "FDTEN2,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
bitfld.long 0x70 8. "FDTEN0,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 2. "RDTEN4,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
bitfld.long 0x70 1. "RDTEN2,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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bitfld.long 0x70 0. "RDTEN0,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive  the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
rgroup.long 0x304++0x2F
line.long 0x0 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
hexmask.long.word 0x0 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x4 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
hexmask.long.word 0x4 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x8 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
hexmask.long.word 0x8 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0xC "EPWM_PBUF3,EPWM PERIOD3 Buffer"
hexmask.long.word 0xC 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x10 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
hexmask.long.word 0x10 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x14 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
hexmask.long.word 0x14 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
line.long 0x18 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
hexmask.long.word 0x18 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x1C "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x20 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
hexmask.long.word 0x20 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x24 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
hexmask.long.word 0x24 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x28 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
hexmask.long.word 0x28 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
line.long 0x2C "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
rgroup.long 0x340++0xB
line.long 0x0 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
hexmask.long.word 0x0 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
line.long 0x4 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
hexmask.long.word 0x4 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
line.long 0x8 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
hexmask.long.word 0x8 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
group.long 0x34C++0x3
line.long 0x0 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
bitfld.long 0x0 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
bitfld.long 0x0 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn. Software can clear this bit by writing 1 to it." "0,1"
rgroup.long 0x350++0x2F
line.long 0x0 "EPWM_CPSCBUF0,EPWM CLKPSC0 Buffer"
hexmask.long.word 0x0 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x4 "EPWM_CPSCBUF1,EPWM CLKPSC1 Buffer"
hexmask.long.word 0x4 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x8 "EPWM_CPSCBUF2,EPWM CLKPSC2 Buffer"
hexmask.long.word 0x8 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0xC "EPWM_CPSCBUF3,EPWM CLKPSC3 Buffer"
hexmask.long.word 0xC 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x10 "EPWM_CPSCBUF4,EPWM CLKPSC4 Buffer"
hexmask.long.word 0x10 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x14 "EPWM_CPSCBUF5,EPWM CLKPSC5 Buffer"
hexmask.long.word 0x14 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
line.long 0x18 "EPWM_IFACNT0,EPWM Interrupt Flag Accumulator Counter 0"
hexmask.long.word 0x18 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x1C "EPWM_IFACNT1,EPWM Interrupt Flag Accumulator Counter 1"
hexmask.long.word 0x1C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x20 "EPWM_IFACNT2,EPWM Interrupt Flag Accumulator Counter 2"
hexmask.long.word 0x20 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x24 "EPWM_IFACNT3,EPWM Interrupt Flag Accumulator Counter 3"
hexmask.long.word 0x24 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x28 "EPWM_IFACNT4,EPWM Interrupt Flag Accumulator Counter 4"
hexmask.long.word 0x28 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
line.long 0x2C "EPWM_IFACNT5,EPWM Interrupt Flag Accumulator Counter 5"
hexmask.long.word 0x2C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
tree.end
tree.end
tree "EQEI (Enhanced Quadrature Encoder Interface)"
base ad:0x0
tree "EQEI0"
base ad:0x400B0000
group.long 0x0++0xF
line.long 0x0 "EQEI_CNT,EQEI Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Enhanced Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected  this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is 0."
line.long 0x4 "EQEI_CNTHOLD,EQEI Counter Hold Register"
hexmask.long 0x4 0.--31. 1. "CNTHOLD,Enhanced Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (EQEI_CTL[24]) goes from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register."
line.long 0x8 "EQEI_CNTLATCH,EQEI Counter Index Latch Register"
hexmask.long 0x8 0.--31. 1. "CNTLATCH,Enhanced Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (EQEI_STATUS[0]) bit is set  the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register."
line.long 0xC "EQEI_CNTCMP,EQEI Counter Compare Register"
hexmask.long 0xC 0.--31. 1. "CNTCMP,Enhanced Quadrature Encoder Interface Counter Compare"
group.long 0x14++0x13
line.long 0x0 "EQEI_CNTMAX,EQEI Pre-set Maximum Count Register"
hexmask.long 0x0 0.--31. 1. "CNTMAX,Enhanced Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode."
line.long 0x4 "EQEI_CTL,EQEI Controller Control Register"
bitfld.long 0x4 29. "EQEIEN,Enhanced Quadrature Encoder Interface Controller Enable Bit" "0: EQEI controller function Disabled,1: EQEI controller function Enabled"
bitfld.long 0x4 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0])  if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0])  the flag CMPF will.." "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x4 27. "IDXRLDEN,Index Trigger EQEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: EQEI_CNT re-initialized by Index signal Enabled"
bitfld.long 0x4 25. "IDXLATEN,Index Latch EQEI_CNT Enable Bit\nIf this bit is set to high  the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX." "0: The index signal latch EQEI counter function..,1: The index signal latch EQEI counter function.."
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bitfld.long 0x4 24. "HOLDCNT,Hold EQEI_CNT Control\nWhen this bit is set from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). \nNote: This bit is.." "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x4 23. "HOLDTMR3,Hold EQEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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bitfld.long 0x4 22. "HOLDTMR2,Hold EQEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
bitfld.long 0x4 21. "HOLDTMR1,Hold EQEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]) in.."
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bitfld.long 0x4 20. "HOLDTMR0,Hold EQEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
bitfld.long 0x4 19. "IDXIEN,IDXF Trigger EQEI Interrupt Enable Bit" "0: The IDXF can trigger EQEI interrupt Disabled,1: The IDXF can trigger EQEI interrupt Enabled"
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bitfld.long 0x4 18. "CMPIEN,CMPF Trigger EQEI Interrupt Enable Bit" "0: CMPF can trigger EQEI controller interrupt..,1: CMPF can trigger EQEI controller interrupt Enabled"
bitfld.long 0x4 17. "DIRIEN,DIRCHGF Trigger EQEI Interrupt Enable Bit" "0: DIRCHGF can trigger EQEI controller interrupt..,1: DIRCHGF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 16. "OVUNIEN,OVUNF Trigger EQEI Interrupt Enable Bit" "0: OVUNF can trigger EQEI controller interrupt..,1: OVUNF can trigger EQEI controller interrupt.."
bitfld.long 0x4 15. "IDXRSTEV,IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)" "0: The next IDX level high signal reset function..,1: The next IDX level high signal reset function.."
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bitfld.long 0x4 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to EQEI controller"
bitfld.long 0x4 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to EQEI controller"
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bitfld.long 0x4 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to EQEI controller"
bitfld.long 0x4 8.--10. "MODE,EQEI Counting Mode Selection\nThere are seven quadrature encoder pulse counter operation modes.\nNote: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode." "0: X4 Free-counting Mode,1: X2 Free-counting Mode,?,?,?,?,?,?"
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bitfld.long 0x4 7. "IDXRSTEN,IDX Reset EQEI Position Counter Enable Bit\nNote: IDXRLDEN(EQEI_CTL[27]) should be set 1." "0: Reset EQEI position counter in every time IDX..,1: Reset EQEI position counter in first time IDX.."
bitfld.long 0x4 6. "IDXEN,IDX Input to EQEI Controller Enable Bit" "0: IDX input to EQEI Controller Disabled,1: IDX input to EQEI Controller Enabled"
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bitfld.long 0x4 5. "CHBEN,QEB Input to EQEI Controller Enable Bit" "0: QEB input to EQEI Controller Disabled,1: QEB input to EQEI Controller Enabled"
bitfld.long 0x4 4. "CHAEN,QEA Input to EQEI Controller Enable Bit" "0: QEA input to EQEI Controller Disabled,1: QEA input to EQEI Controller Enabled"
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bitfld.long 0x4 3. "NFDIS,EQEI Controller Input Noise Filter Disable Bit" "0: The noise filter of EQEI controller Enabled,1: The noise filter of EQEI controller Disabled"
bitfld.long 0x4 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock." "0: EQEI_CLK,1: EQEI_CLK/2,?,?,?,?,?,?"
line.long 0x8 "EQEI_CTL2,EQEI Controller Control Register2"
bitfld.long 0x8 17. "UTIEIEN,UTIEF Trigger EQEI Interrupt Enable Bit" "0: UTIEF can trigger EQEI controller interrupt..,1: UTIEF can trigger EQEI controller interrupt.."
bitfld.long 0x8 16. "PHEIEN,PHEF Trigger EQEI Interrupt Enable Bit" "0: PHEF can trigger EQEI controller interrupt..,1: PHEF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x8 11. "IDXRSTUTS,IDX Resets Unit Timer Select Bit" "0: Unit timer will not be reset when IDX reset..,1: Resets unit timer or not will follow EQEI_CNT.."
bitfld.long 0x8 10. "UTEVTRST,Enable Bit to Reset EQEI Position Counter by Unit Timer Event" "0: Reset EQEI position counter feature when unit..,1: Reset EQEI position counter feature when unit.."
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bitfld.long 0x8 9. "UTHOLDEN,Unit Timer Counter Hold Enable Bit" "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x8 8. "UTEN,Unit Timer Function Enable Bit" "0: EQEI unit timer function Disabled,1: EQEI unit timer function Enabled"
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bitfld.long 0x8 4.--5. "DIRSRC,Direction Signal Source Select" "0: Direction signal is determined from EQEI system..,1: Reserved.,?,?"
bitfld.long 0x8 1.--2. "CRS,Clock Rate Setting without Quadrature Mode" "0: EQEI counter only counts the falling edge,1: EQEI counter only counts the rising edge,?,?"
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bitfld.long 0x8 0. "SWAPEN,Swap Function Enable Bit" "0: EQEI swap function Disabled,1: EQEI swap function Enabled"
line.long 0xC "EQEI_UTCNT,EQEI Unit Timer Counter Register"
hexmask.long 0xC 0.--31. 1. "UTCNT,Unit Timer Counter \nA 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:"
line.long 0x10 "EQEI_UTCMP,EQEI Unit Timer Compare Register"
hexmask.long 0x10 0.--31. 1. "UTCMP,Unit Timer Counter Compare"
group.long 0x2C++0x3
line.long 0x0 "EQEI_STATUS,EQEI Controller Status Register"
bitfld.long 0x0 17. "UTIEF,EQEI Unit Timer Event Flag\nNote: This bit is only cleared by writing 1 to it." "0: No timer event occurs in EQEI unit timer counter,1: Unit timer event occurs in EQEI unit timer counter"
bitfld.long 0x0 16. "PHEF,EQEI Phase Error Flag\nNote: This bit is only cleared by writing 1 to it." "0: No Phase error occurs in EQEI CHA and CHB,1: Phase error occurs in EQEI CHA and CHB"
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rbitfld.long 0x0 9. "FIDXEF,First IDX Signal Reset Event Flag (Read Only)" "0: The first IDX reset event has not happened yet,1: The first IDX reset event has happened"
bitfld.long 0x0 8. "DIRF,EQEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB." "0: EQEI Counter is in down-counting,1: EQEI Counter is in up-counting"
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bitfld.long 0x0 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while EQEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it." "0: No change in EQEI counter counting direction,1: EQEI counter counting direction is changed"
bitfld.long 0x0 2. "OVUNF,EQEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly  the flag is set while.." "0: No overflow or underflow occurs in EQEI counter,1: EQEI counter occurs counting overflow or underflow"
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bitfld.long 0x0 1. "CMPF,Compare-match Flag\nIf the EQEI compare function is enabled  the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it." "0: EQEI counter does not match with..,1: EQEI counter counts to the same as.."
bitfld.long 0x0 0. "IDXF,IDX Detected Flag\nWhen the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it." "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
tree.end
tree "EQEI1"
base ad:0x400B1000
group.long 0x0++0xF
line.long 0x0 "EQEI_CNT,EQEI Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Enhanced Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected  this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is 0."
line.long 0x4 "EQEI_CNTHOLD,EQEI Counter Hold Register"
hexmask.long 0x4 0.--31. 1. "CNTHOLD,Enhanced Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (EQEI_CTL[24]) goes from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register."
line.long 0x8 "EQEI_CNTLATCH,EQEI Counter Index Latch Register"
hexmask.long 0x8 0.--31. 1. "CNTLATCH,Enhanced Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (EQEI_STATUS[0]) bit is set  the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register."
line.long 0xC "EQEI_CNTCMP,EQEI Counter Compare Register"
hexmask.long 0xC 0.--31. 1. "CNTCMP,Enhanced Quadrature Encoder Interface Counter Compare"
group.long 0x14++0x13
line.long 0x0 "EQEI_CNTMAX,EQEI Pre-set Maximum Count Register"
hexmask.long 0x0 0.--31. 1. "CNTMAX,Enhanced Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode."
line.long 0x4 "EQEI_CTL,EQEI Controller Control Register"
bitfld.long 0x4 29. "EQEIEN,Enhanced Quadrature Encoder Interface Controller Enable Bit" "0: EQEI controller function Disabled,1: EQEI controller function Enabled"
bitfld.long 0x4 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0])  if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0])  the flag CMPF will.." "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x4 27. "IDXRLDEN,Index Trigger EQEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: EQEI_CNT re-initialized by Index signal Enabled"
bitfld.long 0x4 25. "IDXLATEN,Index Latch EQEI_CNT Enable Bit\nIf this bit is set to high  the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX." "0: The index signal latch EQEI counter function..,1: The index signal latch EQEI counter function.."
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bitfld.long 0x4 24. "HOLDCNT,Hold EQEI_CNT Control\nWhen this bit is set from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). \nNote: This bit is.." "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x4 23. "HOLDTMR3,Hold EQEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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bitfld.long 0x4 22. "HOLDTMR2,Hold EQEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
bitfld.long 0x4 21. "HOLDTMR1,Hold EQEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]) in.."
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bitfld.long 0x4 20. "HOLDTMR0,Hold EQEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
bitfld.long 0x4 19. "IDXIEN,IDXF Trigger EQEI Interrupt Enable Bit" "0: The IDXF can trigger EQEI interrupt Disabled,1: The IDXF can trigger EQEI interrupt Enabled"
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bitfld.long 0x4 18. "CMPIEN,CMPF Trigger EQEI Interrupt Enable Bit" "0: CMPF can trigger EQEI controller interrupt..,1: CMPF can trigger EQEI controller interrupt Enabled"
bitfld.long 0x4 17. "DIRIEN,DIRCHGF Trigger EQEI Interrupt Enable Bit" "0: DIRCHGF can trigger EQEI controller interrupt..,1: DIRCHGF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 16. "OVUNIEN,OVUNF Trigger EQEI Interrupt Enable Bit" "0: OVUNF can trigger EQEI controller interrupt..,1: OVUNF can trigger EQEI controller interrupt.."
bitfld.long 0x4 15. "IDXRSTEV,IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)" "0: The next IDX level high signal reset function..,1: The next IDX level high signal reset function.."
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bitfld.long 0x4 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to EQEI controller"
bitfld.long 0x4 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to EQEI controller"
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bitfld.long 0x4 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to EQEI controller"
bitfld.long 0x4 8.--10. "MODE,EQEI Counting Mode Selection\nThere are seven quadrature encoder pulse counter operation modes.\nNote: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode." "0: X4 Free-counting Mode,1: X2 Free-counting Mode,?,?,?,?,?,?"
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bitfld.long 0x4 7. "IDXRSTEN,IDX Reset EQEI Position Counter Enable Bit\nNote: IDXRLDEN(EQEI_CTL[27]) should be set 1." "0: Reset EQEI position counter in every time IDX..,1: Reset EQEI position counter in first time IDX.."
bitfld.long 0x4 6. "IDXEN,IDX Input to EQEI Controller Enable Bit" "0: IDX input to EQEI Controller Disabled,1: IDX input to EQEI Controller Enabled"
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bitfld.long 0x4 5. "CHBEN,QEB Input to EQEI Controller Enable Bit" "0: QEB input to EQEI Controller Disabled,1: QEB input to EQEI Controller Enabled"
bitfld.long 0x4 4. "CHAEN,QEA Input to EQEI Controller Enable Bit" "0: QEA input to EQEI Controller Disabled,1: QEA input to EQEI Controller Enabled"
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bitfld.long 0x4 3. "NFDIS,EQEI Controller Input Noise Filter Disable Bit" "0: The noise filter of EQEI controller Enabled,1: The noise filter of EQEI controller Disabled"
bitfld.long 0x4 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock." "0: EQEI_CLK,1: EQEI_CLK/2,?,?,?,?,?,?"
line.long 0x8 "EQEI_CTL2,EQEI Controller Control Register2"
bitfld.long 0x8 17. "UTIEIEN,UTIEF Trigger EQEI Interrupt Enable Bit" "0: UTIEF can trigger EQEI controller interrupt..,1: UTIEF can trigger EQEI controller interrupt.."
bitfld.long 0x8 16. "PHEIEN,PHEF Trigger EQEI Interrupt Enable Bit" "0: PHEF can trigger EQEI controller interrupt..,1: PHEF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x8 11. "IDXRSTUTS,IDX Resets Unit Timer Select Bit" "0: Unit timer will not be reset when IDX reset..,1: Resets unit timer or not will follow EQEI_CNT.."
bitfld.long 0x8 10. "UTEVTRST,Enable Bit to Reset EQEI Position Counter by Unit Timer Event" "0: Reset EQEI position counter feature when unit..,1: Reset EQEI position counter feature when unit.."
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bitfld.long 0x8 9. "UTHOLDEN,Unit Timer Counter Hold Enable Bit" "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x8 8. "UTEN,Unit Timer Function Enable Bit" "0: EQEI unit timer function Disabled,1: EQEI unit timer function Enabled"
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bitfld.long 0x8 4.--5. "DIRSRC,Direction Signal Source Select" "0: Direction signal is determined from EQEI system..,1: Reserved.,?,?"
bitfld.long 0x8 1.--2. "CRS,Clock Rate Setting without Quadrature Mode" "0: EQEI counter only counts the falling edge,1: EQEI counter only counts the rising edge,?,?"
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bitfld.long 0x8 0. "SWAPEN,Swap Function Enable Bit" "0: EQEI swap function Disabled,1: EQEI swap function Enabled"
line.long 0xC "EQEI_UTCNT,EQEI Unit Timer Counter Register"
hexmask.long 0xC 0.--31. 1. "UTCNT,Unit Timer Counter \nA 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:"
line.long 0x10 "EQEI_UTCMP,EQEI Unit Timer Compare Register"
hexmask.long 0x10 0.--31. 1. "UTCMP,Unit Timer Counter Compare"
group.long 0x2C++0x3
line.long 0x0 "EQEI_STATUS,EQEI Controller Status Register"
bitfld.long 0x0 17. "UTIEF,EQEI Unit Timer Event Flag\nNote: This bit is only cleared by writing 1 to it." "0: No timer event occurs in EQEI unit timer counter,1: Unit timer event occurs in EQEI unit timer counter"
bitfld.long 0x0 16. "PHEF,EQEI Phase Error Flag\nNote: This bit is only cleared by writing 1 to it." "0: No Phase error occurs in EQEI CHA and CHB,1: Phase error occurs in EQEI CHA and CHB"
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rbitfld.long 0x0 9. "FIDXEF,First IDX Signal Reset Event Flag (Read Only)" "0: The first IDX reset event has not happened yet,1: The first IDX reset event has happened"
bitfld.long 0x0 8. "DIRF,EQEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB." "0: EQEI Counter is in down-counting,1: EQEI Counter is in up-counting"
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bitfld.long 0x0 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while EQEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it." "0: No change in EQEI counter counting direction,1: EQEI counter counting direction is changed"
bitfld.long 0x0 2. "OVUNF,EQEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly  the flag is set while.." "0: No overflow or underflow occurs in EQEI counter,1: EQEI counter occurs counting overflow or underflow"
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bitfld.long 0x0 1. "CMPF,Compare-match Flag\nIf the EQEI compare function is enabled  the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it." "0: EQEI counter does not match with..,1: EQEI counter counts to the same as.."
bitfld.long 0x0 0. "IDXF,IDX Detected Flag\nWhen the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it." "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
tree.end
tree "EQEI2"
base ad:0x400B2000
group.long 0x0++0xF
line.long 0x0 "EQEI_CNT,EQEI Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Enhanced Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected  this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is 0."
line.long 0x4 "EQEI_CNTHOLD,EQEI Counter Hold Register"
hexmask.long 0x4 0.--31. 1. "CNTHOLD,Enhanced Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (EQEI_CTL[24]) goes from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register."
line.long 0x8 "EQEI_CNTLATCH,EQEI Counter Index Latch Register"
hexmask.long 0x8 0.--31. 1. "CNTLATCH,Enhanced Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (EQEI_STATUS[0]) bit is set  the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register."
line.long 0xC "EQEI_CNTCMP,EQEI Counter Compare Register"
hexmask.long 0xC 0.--31. 1. "CNTCMP,Enhanced Quadrature Encoder Interface Counter Compare"
group.long 0x14++0x13
line.long 0x0 "EQEI_CNTMAX,EQEI Pre-set Maximum Count Register"
hexmask.long 0x0 0.--31. 1. "CNTMAX,Enhanced Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode."
line.long 0x4 "EQEI_CTL,EQEI Controller Control Register"
bitfld.long 0x4 29. "EQEIEN,Enhanced Quadrature Encoder Interface Controller Enable Bit" "0: EQEI controller function Disabled,1: EQEI controller function Enabled"
bitfld.long 0x4 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0])  if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0])  the flag CMPF will.." "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x4 27. "IDXRLDEN,Index Trigger EQEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: EQEI_CNT re-initialized by Index signal Enabled"
bitfld.long 0x4 25. "IDXLATEN,Index Latch EQEI_CNT Enable Bit\nIf this bit is set to high  the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX." "0: The index signal latch EQEI counter function..,1: The index signal latch EQEI counter function.."
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bitfld.long 0x4 24. "HOLDCNT,Hold EQEI_CNT Control\nWhen this bit is set from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). \nNote: This bit is.." "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x4 23. "HOLDTMR3,Hold EQEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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bitfld.long 0x4 22. "HOLDTMR2,Hold EQEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
bitfld.long 0x4 21. "HOLDTMR1,Hold EQEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]) in.."
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bitfld.long 0x4 20. "HOLDTMR0,Hold EQEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
bitfld.long 0x4 19. "IDXIEN,IDXF Trigger EQEI Interrupt Enable Bit" "0: The IDXF can trigger EQEI interrupt Disabled,1: The IDXF can trigger EQEI interrupt Enabled"
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bitfld.long 0x4 18. "CMPIEN,CMPF Trigger EQEI Interrupt Enable Bit" "0: CMPF can trigger EQEI controller interrupt..,1: CMPF can trigger EQEI controller interrupt Enabled"
bitfld.long 0x4 17. "DIRIEN,DIRCHGF Trigger EQEI Interrupt Enable Bit" "0: DIRCHGF can trigger EQEI controller interrupt..,1: DIRCHGF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 16. "OVUNIEN,OVUNF Trigger EQEI Interrupt Enable Bit" "0: OVUNF can trigger EQEI controller interrupt..,1: OVUNF can trigger EQEI controller interrupt.."
bitfld.long 0x4 15. "IDXRSTEV,IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)" "0: The next IDX level high signal reset function..,1: The next IDX level high signal reset function.."
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bitfld.long 0x4 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to EQEI controller"
bitfld.long 0x4 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to EQEI controller"
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bitfld.long 0x4 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to EQEI controller"
bitfld.long 0x4 8.--10. "MODE,EQEI Counting Mode Selection\nThere are seven quadrature encoder pulse counter operation modes.\nNote: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode." "0: X4 Free-counting Mode,1: X2 Free-counting Mode,?,?,?,?,?,?"
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bitfld.long 0x4 7. "IDXRSTEN,IDX Reset EQEI Position Counter Enable Bit\nNote: IDXRLDEN(EQEI_CTL[27]) should be set 1." "0: Reset EQEI position counter in every time IDX..,1: Reset EQEI position counter in first time IDX.."
bitfld.long 0x4 6. "IDXEN,IDX Input to EQEI Controller Enable Bit" "0: IDX input to EQEI Controller Disabled,1: IDX input to EQEI Controller Enabled"
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bitfld.long 0x4 5. "CHBEN,QEB Input to EQEI Controller Enable Bit" "0: QEB input to EQEI Controller Disabled,1: QEB input to EQEI Controller Enabled"
bitfld.long 0x4 4. "CHAEN,QEA Input to EQEI Controller Enable Bit" "0: QEA input to EQEI Controller Disabled,1: QEA input to EQEI Controller Enabled"
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bitfld.long 0x4 3. "NFDIS,EQEI Controller Input Noise Filter Disable Bit" "0: The noise filter of EQEI controller Enabled,1: The noise filter of EQEI controller Disabled"
bitfld.long 0x4 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock." "0: EQEI_CLK,1: EQEI_CLK/2,?,?,?,?,?,?"
line.long 0x8 "EQEI_CTL2,EQEI Controller Control Register2"
bitfld.long 0x8 17. "UTIEIEN,UTIEF Trigger EQEI Interrupt Enable Bit" "0: UTIEF can trigger EQEI controller interrupt..,1: UTIEF can trigger EQEI controller interrupt.."
bitfld.long 0x8 16. "PHEIEN,PHEF Trigger EQEI Interrupt Enable Bit" "0: PHEF can trigger EQEI controller interrupt..,1: PHEF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x8 11. "IDXRSTUTS,IDX Resets Unit Timer Select Bit" "0: Unit timer will not be reset when IDX reset..,1: Resets unit timer or not will follow EQEI_CNT.."
bitfld.long 0x8 10. "UTEVTRST,Enable Bit to Reset EQEI Position Counter by Unit Timer Event" "0: Reset EQEI position counter feature when unit..,1: Reset EQEI position counter feature when unit.."
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bitfld.long 0x8 9. "UTHOLDEN,Unit Timer Counter Hold Enable Bit" "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x8 8. "UTEN,Unit Timer Function Enable Bit" "0: EQEI unit timer function Disabled,1: EQEI unit timer function Enabled"
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bitfld.long 0x8 4.--5. "DIRSRC,Direction Signal Source Select" "0: Direction signal is determined from EQEI system..,1: Reserved.,?,?"
bitfld.long 0x8 1.--2. "CRS,Clock Rate Setting without Quadrature Mode" "0: EQEI counter only counts the falling edge,1: EQEI counter only counts the rising edge,?,?"
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bitfld.long 0x8 0. "SWAPEN,Swap Function Enable Bit" "0: EQEI swap function Disabled,1: EQEI swap function Enabled"
line.long 0xC "EQEI_UTCNT,EQEI Unit Timer Counter Register"
hexmask.long 0xC 0.--31. 1. "UTCNT,Unit Timer Counter \nA 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:"
line.long 0x10 "EQEI_UTCMP,EQEI Unit Timer Compare Register"
hexmask.long 0x10 0.--31. 1. "UTCMP,Unit Timer Counter Compare"
group.long 0x2C++0x3
line.long 0x0 "EQEI_STATUS,EQEI Controller Status Register"
bitfld.long 0x0 17. "UTIEF,EQEI Unit Timer Event Flag\nNote: This bit is only cleared by writing 1 to it." "0: No timer event occurs in EQEI unit timer counter,1: Unit timer event occurs in EQEI unit timer counter"
bitfld.long 0x0 16. "PHEF,EQEI Phase Error Flag\nNote: This bit is only cleared by writing 1 to it." "0: No Phase error occurs in EQEI CHA and CHB,1: Phase error occurs in EQEI CHA and CHB"
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rbitfld.long 0x0 9. "FIDXEF,First IDX Signal Reset Event Flag (Read Only)" "0: The first IDX reset event has not happened yet,1: The first IDX reset event has happened"
bitfld.long 0x0 8. "DIRF,EQEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB." "0: EQEI Counter is in down-counting,1: EQEI Counter is in up-counting"
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bitfld.long 0x0 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while EQEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it." "0: No change in EQEI counter counting direction,1: EQEI counter counting direction is changed"
bitfld.long 0x0 2. "OVUNF,EQEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly  the flag is set while.." "0: No overflow or underflow occurs in EQEI counter,1: EQEI counter occurs counting overflow or underflow"
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bitfld.long 0x0 1. "CMPF,Compare-match Flag\nIf the EQEI compare function is enabled  the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it." "0: EQEI counter does not match with..,1: EQEI counter counts to the same as.."
bitfld.long 0x0 0. "IDXF,IDX Detected Flag\nWhen the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it." "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
tree.end
tree "EQEI3"
base ad:0x400B3000
group.long 0x0++0xF
line.long 0x0 "EQEI_CNT,EQEI Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Enhanced Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected  this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is 0."
line.long 0x4 "EQEI_CNTHOLD,EQEI Counter Hold Register"
hexmask.long 0x4 0.--31. 1. "CNTHOLD,Enhanced Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (EQEI_CTL[24]) goes from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register."
line.long 0x8 "EQEI_CNTLATCH,EQEI Counter Index Latch Register"
hexmask.long 0x8 0.--31. 1. "CNTLATCH,Enhanced Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (EQEI_STATUS[0]) bit is set  the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register."
line.long 0xC "EQEI_CNTCMP,EQEI Counter Compare Register"
hexmask.long 0xC 0.--31. 1. "CNTCMP,Enhanced Quadrature Encoder Interface Counter Compare"
group.long 0x14++0x13
line.long 0x0 "EQEI_CNTMAX,EQEI Pre-set Maximum Count Register"
hexmask.long 0x0 0.--31. 1. "CNTMAX,Enhanced Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode."
line.long 0x4 "EQEI_CTL,EQEI Controller Control Register"
bitfld.long 0x4 29. "EQEIEN,Enhanced Quadrature Encoder Interface Controller Enable Bit" "0: EQEI controller function Disabled,1: EQEI controller function Enabled"
bitfld.long 0x4 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0])  if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0])  the flag CMPF will.." "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x4 27. "IDXRLDEN,Index Trigger EQEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: EQEI_CNT re-initialized by Index signal Enabled"
bitfld.long 0x4 25. "IDXLATEN,Index Latch EQEI_CNT Enable Bit\nIf this bit is set to high  the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX." "0: The index signal latch EQEI counter function..,1: The index signal latch EQEI counter function.."
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bitfld.long 0x4 24. "HOLDCNT,Hold EQEI_CNT Control\nWhen this bit is set from low to high  the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). \nNote: This bit is.." "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x4 23. "HOLDTMR3,Hold EQEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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bitfld.long 0x4 22. "HOLDTMR2,Hold EQEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
bitfld.long 0x4 21. "HOLDTMR1,Hold EQEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]) in.."
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bitfld.long 0x4 20. "HOLDTMR0,Hold EQEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
bitfld.long 0x4 19. "IDXIEN,IDXF Trigger EQEI Interrupt Enable Bit" "0: The IDXF can trigger EQEI interrupt Disabled,1: The IDXF can trigger EQEI interrupt Enabled"
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bitfld.long 0x4 18. "CMPIEN,CMPF Trigger EQEI Interrupt Enable Bit" "0: CMPF can trigger EQEI controller interrupt..,1: CMPF can trigger EQEI controller interrupt Enabled"
bitfld.long 0x4 17. "DIRIEN,DIRCHGF Trigger EQEI Interrupt Enable Bit" "0: DIRCHGF can trigger EQEI controller interrupt..,1: DIRCHGF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 16. "OVUNIEN,OVUNF Trigger EQEI Interrupt Enable Bit" "0: OVUNF can trigger EQEI controller interrupt..,1: OVUNF can trigger EQEI controller interrupt.."
bitfld.long 0x4 15. "IDXRSTEV,IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)" "0: The next IDX level high signal reset function..,1: The next IDX level high signal reset function.."
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bitfld.long 0x4 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to EQEI controller"
bitfld.long 0x4 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to EQEI controller"
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bitfld.long 0x4 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to EQEI controller"
bitfld.long 0x4 8.--10. "MODE,EQEI Counting Mode Selection\nThere are seven quadrature encoder pulse counter operation modes.\nNote: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode." "0: X4 Free-counting Mode,1: X2 Free-counting Mode,?,?,?,?,?,?"
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bitfld.long 0x4 7. "IDXRSTEN,IDX Reset EQEI Position Counter Enable Bit\nNote: IDXRLDEN(EQEI_CTL[27]) should be set 1." "0: Reset EQEI position counter in every time IDX..,1: Reset EQEI position counter in first time IDX.."
bitfld.long 0x4 6. "IDXEN,IDX Input to EQEI Controller Enable Bit" "0: IDX input to EQEI Controller Disabled,1: IDX input to EQEI Controller Enabled"
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bitfld.long 0x4 5. "CHBEN,QEB Input to EQEI Controller Enable Bit" "0: QEB input to EQEI Controller Disabled,1: QEB input to EQEI Controller Enabled"
bitfld.long 0x4 4. "CHAEN,QEA Input to EQEI Controller Enable Bit" "0: QEA input to EQEI Controller Disabled,1: QEA input to EQEI Controller Enabled"
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bitfld.long 0x4 3. "NFDIS,EQEI Controller Input Noise Filter Disable Bit" "0: The noise filter of EQEI controller Enabled,1: The noise filter of EQEI controller Disabled"
bitfld.long 0x4 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock." "0: EQEI_CLK,1: EQEI_CLK/2,?,?,?,?,?,?"
line.long 0x8 "EQEI_CTL2,EQEI Controller Control Register2"
bitfld.long 0x8 17. "UTIEIEN,UTIEF Trigger EQEI Interrupt Enable Bit" "0: UTIEF can trigger EQEI controller interrupt..,1: UTIEF can trigger EQEI controller interrupt.."
bitfld.long 0x8 16. "PHEIEN,PHEF Trigger EQEI Interrupt Enable Bit" "0: PHEF can trigger EQEI controller interrupt..,1: PHEF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x8 11. "IDXRSTUTS,IDX Resets Unit Timer Select Bit" "0: Unit timer will not be reset when IDX reset..,1: Resets unit timer or not will follow EQEI_CNT.."
bitfld.long 0x8 10. "UTEVTRST,Enable Bit to Reset EQEI Position Counter by Unit Timer Event" "0: Reset EQEI position counter feature when unit..,1: Reset EQEI position counter feature when unit.."
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bitfld.long 0x8 9. "UTHOLDEN,Unit Timer Counter Hold Enable Bit" "0: No operation,1: EQEI_CNT content is captured and stored in.."
bitfld.long 0x8 8. "UTEN,Unit Timer Function Enable Bit" "0: EQEI unit timer function Disabled,1: EQEI unit timer function Enabled"
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bitfld.long 0x8 4.--5. "DIRSRC,Direction Signal Source Select" "0: Direction signal is determined from EQEI system..,1: Reserved.,?,?"
bitfld.long 0x8 1.--2. "CRS,Clock Rate Setting without Quadrature Mode" "0: EQEI counter only counts the falling edge,1: EQEI counter only counts the rising edge,?,?"
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bitfld.long 0x8 0. "SWAPEN,Swap Function Enable Bit" "0: EQEI swap function Disabled,1: EQEI swap function Enabled"
line.long 0xC "EQEI_UTCNT,EQEI Unit Timer Counter Register"
hexmask.long 0xC 0.--31. 1. "UTCNT,Unit Timer Counter \nA 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:"
line.long 0x10 "EQEI_UTCMP,EQEI Unit Timer Compare Register"
hexmask.long 0x10 0.--31. 1. "UTCMP,Unit Timer Counter Compare"
group.long 0x2C++0x3
line.long 0x0 "EQEI_STATUS,EQEI Controller Status Register"
bitfld.long 0x0 17. "UTIEF,EQEI Unit Timer Event Flag\nNote: This bit is only cleared by writing 1 to it." "0: No timer event occurs in EQEI unit timer counter,1: Unit timer event occurs in EQEI unit timer counter"
bitfld.long 0x0 16. "PHEF,EQEI Phase Error Flag\nNote: This bit is only cleared by writing 1 to it." "0: No Phase error occurs in EQEI CHA and CHB,1: Phase error occurs in EQEI CHA and CHB"
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rbitfld.long 0x0 9. "FIDXEF,First IDX Signal Reset Event Flag (Read Only)" "0: The first IDX reset event has not happened yet,1: The first IDX reset event has happened"
bitfld.long 0x0 8. "DIRF,EQEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB." "0: EQEI Counter is in down-counting,1: EQEI Counter is in up-counting"
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bitfld.long 0x0 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while EQEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it." "0: No change in EQEI counter counting direction,1: EQEI counter counting direction is changed"
bitfld.long 0x0 2. "OVUNF,EQEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly  the flag is set while.." "0: No overflow or underflow occurs in EQEI counter,1: EQEI counter occurs counting overflow or underflow"
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bitfld.long 0x0 1. "CMPF,Compare-match Flag\nIf the EQEI compare function is enabled  the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it." "0: EQEI counter does not match with..,1: EQEI counter counts to the same as.."
bitfld.long 0x0 0. "IDXF,IDX Detected Flag\nWhen the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it." "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
tree.end
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x4000C000
group.long 0x0++0x13
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
bitfld.long 0x0 24. "INTEN,Secure ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. Before using INT  user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time." "0: ISP INT Disabled,1: ISP INT Enabled"
bitfld.long 0x0 16. "BL,Boot Loader Booting (Write Protect)\nThis bit is initiated with the inversed value of MBS (CONFIG0[5]). Any reset  except CPU reset (CPU is 1) or system reset (SYS)  BL will be reloaded. This bit is used to check chip boot from Boot Loader or not." "0: Boot from APROM or LDROM,1: Boot from Boot Loader"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN.." "0,1"
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated"
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bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated"
bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled"
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address\nThe M460 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor CRC32 Checksum Calculation command  this field is the Flash starting.."
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
line.long 0xC "FMC_ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid."
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed"
rgroup.long 0x14++0x3
line.long 0x0 "FMC_DFBA,Data Flash Base Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1"
group.long 0x18++0x3
line.long 0x0 "FMC_FTCTL,Flash Access Time Control Register"
bitfld.long 0x0 9. "CACHEINV,Flash Cache Invalidation (Write Protect)\nNote 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes.\nNote 2: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: Flash Cache Invalidation finished (default),1: Write 1 to start cache invalidation"
group.long 0x40++0x3
line.long 0x0 "FMC_ISPSTS,ISP Status Register"
bitfld.long 0x0 30. "FBS,Flash Bank Selection\nThis bit indicate which bank is selected to boot." "0: Booting from BANK0,1: Booting from BANK1"
bitfld.long 0x0 28. "ISPCERR,ISP Conflict Error\nThis bit shows when FMC is doing ISP operation. User cannot access FMC_ISP_ADDR FMC_ISPDAT FMC_ISPCMD FMC_ISPTRG. It would cause ISPFF." "0,1"
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bitfld.long 0x0 24. "INTFLAG,ISP Interrupt Flag\nNote: This function needs to be enabled by FMC_ISPCTRL[24]." "0: ISP Not Finished,1: ISP done or ISPFF set"
hexmask.long.word 0x0 9.--23. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0]  9'h000} ~ {VECMAP[14:0]  9'h1FF}"
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bitfld.long 0x0 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1  and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit also can be clear by writing 1" "0: All of Flash bits are 1 after 'Run Flash All-One..,1: Flash bits are not all 1 after 'Run Flash.."
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6])  it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM.." "0,1"
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rbitfld.long 0x0 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation" "0: Flash Program is success,1: Flash Program is fail. Program data is different.."
rbitfld.long 0x0 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?"
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rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed"
group.long 0x4C++0x3
line.long 0x0 "FMC_CYCCTL,Flash Access Cycle Control Register"
hexmask.long.byte 0x0 0.--3. 1. "CYCLE,Flash Access Cycle Control (Write Protect)\nThis register is updated by user before HCLK running in different frequency. \nThe optimized HCLK working frequency range is 176 MHz\nNote: This bit is write protected. Refer to the SYS_REGLCTL register."
group.long 0x80++0xF
line.long 0x0 "FMC_MPDAT0,ISP Data0 Register"
hexmask.long 0x0 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming  and it is also the mirror of FMC_ISPDAT  both registers keep the same data."
line.long 0x4 "FMC_MPDAT1,ISP Data1 Register"
hexmask.long 0x4 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming."
line.long 0x8 "FMC_MPDAT2,ISP Data2 Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming."
line.long 0xC "FMC_MPDAT3,ISP Data3 Register"
hexmask.long 0xC 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming."
rgroup.long 0xC0++0x7
line.long 0x0 "FMC_MPSTS,ISP Multi-program Status Register"
bitfld.long 0x0 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete." "0: FMC_MPDAT3 register is empty or program to Flash..,1: FMC_MPDAT3 register has been written and not.."
bitfld.long 0x0 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete." "0: FMC_MPDAT2 register is empty or program to Flash..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x0 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete." "0: FMC_MPDAT1 register is empty or program to Flash..,1: FMC_MPDAT1 register has been written and not.."
bitfld.long 0x0 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete." "0: FMC_MPDAT0 register is empty or program to Flash..,1: FMC_MPDAT0 register has been written and not.."
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bitfld.long 0x0 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]). It needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes.." "0,1"
bitfld.long 0x0 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
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bitfld.long 0x0 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
line.long 0x4 "FMC_MPADDR,ISP Multi-program Address Register"
hexmask.long 0x4 0.--31. 1. "MPADDR,ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete."
rgroup.long 0xD0++0x13
line.long 0x0 "FMC_XOMR0STS,XOM Region 0 Status Register"
hexmask.long.tbyte 0x0 8.--31. 1. "BASE,XOM Region 0 Base Address\nBASE is the base address of XOM Region 0."
hexmask.long.byte 0x0 0.--7. 1. "SIZE,XOM Region 0 Size\nSIZE is the page number of XOM Region 0."
line.long 0x4 "FMC_XOMR1STS,XOM Region 1 Status Register"
hexmask.long.tbyte 0x4 8.--31. 1. "BASE,XOM Region 1 Base Address\nBASE is the base address of XOM Region 1."
hexmask.long.byte 0x4 0.--7. 1. "SIZE,XOM Region 1 Size\nSIZE is the page number of XOM Region 1."
line.long 0x8 "FMC_XOMR2STS,XOM Region 2 Status Register"
hexmask.long.tbyte 0x8 8.--31. 1. "BASE,XOM Region 2 Base Address\nBASE is the base address of XOM Region 2."
hexmask.long.byte 0x8 0.--7. 1. "SIZE,XOM Region 2 Size\nSIZE is the page number of XOM Region 2."
line.long 0xC "FMC_XOMR3STS,XOM Region 3 Status Register"
hexmask.long.tbyte 0xC 8.--31. 1. "BASE,XOM Region 3 Base Address\nBASE is the base address of XOM Region 3."
hexmask.long.byte 0xC 0.--7. 1. "SIZE,XOM Region 3 Size\nSIZE is the page number of XOM Region 3."
line.long 0x10 "FMC_XOMSTS,XOM Status Register"
bitfld.long 0x10 4. "XOMPEF,XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1  user needs to erase XOM region again." "0: Sucess,1: Fail"
bitfld.long 0x10 3. "XOMR3ON,XOM Region 3 On\nXOM Region 3 active status." "0: No active,1: XOM region 3 is active"
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bitfld.long 0x10 2. "XOMR2ON,XOM Region 2 On\nXOM Region 2 active status." "0: No active,1: XOM region 2 is active"
bitfld.long 0x10 1. "XOMR1ON,XOM Region 1 On\nXOM Region 1 active status." "0: No active,1: XOM region 1 is active"
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bitfld.long 0x10 0. "XOMR0ON,XOM Region 0 On\nXOM Region 0 active status." "0: No active,1: XOM region 0 is active"
group.long 0x110++0x3
line.long 0x0 "FMC_APPROT,APROM Protect Register"
bitfld.long 0x0 31. "APPROEN31,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 30. "APPROEN30,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 29. "APPROEN29,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 28. "APPROEN28,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 27. "APPROEN27,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 26. "APPROEN26,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 25. "APPROEN25,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 24. "APPROEN24,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 23. "APPROEN23,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 22. "APPROEN22,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 21. "APPROEN21,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 20. "APPROEN20,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 19. "APPROEN19,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 18. "APPROEN18,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 17. "APPROEN17,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 16. "APPROEN16,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 15. "APPROEN15,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 14. "APPROEN14,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 13. "APPROEN13,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 12. "APPROEN12,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 11. "APPROEN11,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 10. "APPROEN10,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 9. "APPROEN9,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 8. "APPROEN8,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 7. "APPROEN7,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 6. "APPROEN6,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 5. "APPROEN5,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 4. "APPROEN4,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 3. "APPROEN3,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 2. "APPROEN2,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 1. "APPROEN1,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
bitfld.long 0x0 0. "APPROEN0,APROM Proect Enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)" "0: APROM region n is not protected,1: APROM region n is protected"
tree.end
tree "GPIO (General Purpose I/Os)"
base ad:0x0
tree "GPIOA"
base ad:0x40004000
group.long 0x0++0xF
line.long 0x0 "PA_MODE,PA I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PA_DOUT,PA Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PA_DATMSK,PA Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PA_PIN,PA Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PA_DBEN,PA De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PA_INTEN,PA Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PA_INTSRC,PA Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PA_SLEWCTL,PA High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PA_PUSEL,PA Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PA_DBCTL,PA Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOB"
base ad:0x40004040
group.long 0x0++0xF
line.long 0x0 "PB_MODE,PB I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PB_DOUT,PB Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PB_PIN,PB Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PB_DBEN,PB De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PB_PUSEL,PB Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PB_DBCTL,PB Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOC"
base ad:0x40004080
group.long 0x0++0xF
line.long 0x0 "PC_MODE,PC I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PC_DOUT,PC Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PC_PIN,PC Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PC_DBEN,PC De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PC_PUSEL,PC Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PC_DBCTL,PC Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOD"
base ad:0x400040C0
group.long 0x0++0xF
line.long 0x0 "PD_MODE,PD I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PD_DOUT,PD Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PD_DATMSK,PD Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PD_PIN,PD Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PD_DBEN,PD De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PD_INTEN,PD Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PD_INTSRC,PD Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PD_SLEWCTL,PD High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PD_PUSEL,PD Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PD_DBCTL,PD Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOE"
base ad:0x40004100
group.long 0x0++0xF
line.long 0x0 "PE_MODE,PE I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PE_DINOFF,PE Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PE_DOUT,PE Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PE_DATMSK,PE Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PE_PIN,PE Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PE_DBEN,PE De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PE_INTTYPE,PE Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PE_INTEN,PE Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PE_INTSRC,PE Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PE_SMTEN,PE Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PE_SLEWCTL,PE High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PE_PUSEL,PE Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PE_DBCTL,PE Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOF"
base ad:0x40004140
group.long 0x0++0xF
line.long 0x0 "PF_MODE,PF I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PF_DOUT,PF Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PF_DATMSK,PF Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PF_PIN,PF Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PF_DBEN,PF De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PF_INTEN,PF Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PF_INTSRC,PF Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PF_PUSEL,PF Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PF_DBCTL,PF Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOG"
base ad:0x40004180
group.long 0x0++0xF
line.long 0x0 "PG_MODE,PG I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PG_DINOFF,PG Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PG_DOUT,PG Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PG_DATMSK,PG Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PG_PIN,PG Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PG_DBEN,PG De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PG_INTTYPE,PG Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PG_INTEN,PG Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PG_INTSRC,PG Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PG_SMTEN,PG Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PG_SLEWCTL,PG High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PG_PUSEL,PG Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PG_DBCTL,PG Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOH"
base ad:0x400041C0
group.long 0x0++0xF
line.long 0x0 "PH_MODE,PH I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PH_DINOFF,PH Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PH_DOUT,PH Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PH_DATMSK,PH Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PH_PIN,PH Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PH_DBEN,PH De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PH_INTTYPE,PH Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PH_INTEN,PH Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PH_INTSRC,PH Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PH_SMTEN,PH Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PH_SLEWCTL,PH High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PH_PUSEL,PH Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PH_DBCTL,PH Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOI"
base ad:0x40004200
group.long 0x0++0xF
line.long 0x0 "PI_MODE,PI I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PI_DINOFF,PI Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PI_DOUT,PI Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PI_DATMSK,PI Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PI_PIN,PI Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PI_DBEN,PI De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PI_INTTYPE,PI Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PI_INTEN,PI Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PI_INTSRC,PI Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PI_SMTEN,PI Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PI_SLEWCTL,PI High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PI_PUSEL,PI Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PI_DBCTL,PI Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "GPIOINT"
base ad:0x40004450
group.long 0x0++0x1F
line.long 0x0 "INT0_INNF,INT0 Input Noise Filter Register"
bitfld.long 0x0 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0x4 "INT1_INNF,INT1 Input Noise Filter Register"
bitfld.long 0x4 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x4 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0x8 "INT2_INNF,INT2 Input Noise Filter Register"
bitfld.long 0x8 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0xC "INT3_INNF,INT3 Input Noise Filter Register"
bitfld.long 0xC 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0xC 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0x10 "INT4_INNF,INT4 Input Noise Filter Register"
bitfld.long 0x10 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0x14 "INT5_INNF,INT5 Input Noise Filter Register"
bitfld.long 0x14 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x14 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x14 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0x18 "INT6_INNF,INT6 Input Noise Filter Register"
bitfld.long 0x18 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x18 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
line.long 0x1C "INT7_INNF,INT7 Input Noise Filter Register"
bitfld.long 0x1C 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
group.long 0x40++0x3
line.long 0x0 "INT_EDETCTL,INT Edge Detect Control Register"
bitfld.long 0x0 14.--15. "EDETCTL7,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
bitfld.long 0x0 12.--13. "EDETCTL6,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
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bitfld.long 0x0 10.--11. "EDETCTL5,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
bitfld.long 0x0 8.--9. "EDETCTL4,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
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bitfld.long 0x0 6.--7. "EDETCTL3,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
bitfld.long 0x0 4.--5. "EDETCTL2,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
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bitfld.long 0x0 2.--3. "EDETCTL1,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
bitfld.long 0x0 0.--1. "EDETCTL0,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enable,?,?"
group.long 0x48++0x7
line.long 0x0 "INT_EDINTEN,INT Edge Detect Interrupt Enable Control Register"
bitfld.long 0x0 7. "EDIEN7,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
bitfld.long 0x0 6. "EDIEN6,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
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bitfld.long 0x0 5. "EDIEN5,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
bitfld.long 0x0 4. "EDIEN4,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
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bitfld.long 0x0 3. "EDIEN3,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
bitfld.long 0x0 2. "EDIEN2,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
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bitfld.long 0x0 1. "EDIEN1,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
bitfld.long 0x0 0. "EDIEN0,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disable,1: INTn Edge Detect Interrupt Enable"
line.long 0x4 "INT_EDSTS,INT Edge Detect Interrupt Flag Register"
bitfld.long 0x4 7. "EDIF7,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
bitfld.long 0x4 6. "EDIF6,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 5. "EDIF5,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
bitfld.long 0x4 4. "EDIF4,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 3. "EDIF3,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
bitfld.long 0x4 2. "EDIF2,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 1. "EDIF1,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
bitfld.long 0x4 0. "EDIF0,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
tree.end
tree "GPIOJ"
base ad:0x40004240
group.long 0x0++0xF
line.long 0x0 "PJ_MODE,PJ I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-J I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PJ_DINOFF,PJ Digital Input Path Disable Control"
bitfld.long 0x4 31. "DINOFF15,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 30. "DINOFF14,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 28. "DINOFF12,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 26. "DINOFF10,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 24. "DINOFF8,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-J Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal  users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PJ_DOUT,PJ Data Output Value"
bitfld.long 0x8 15. "DOUT15,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 14. "DOUT14,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 12. "DOUT12,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 10. "DOUT10,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 8. "DOUT8,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-J Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output  Open-drain output or Quasi-bidirectional mode." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PJ_DATMSK,PJ Data Output Write Mask"
bitfld.long 0xC 15. "DATMSK15,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 14. "DATMSK14,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 12. "DATMSK12,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 10. "DATMSK10,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 8. "DATMSK8,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-J Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1  the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PJ_PIN,PJ Pin Value"
bitfld.long 0x0 15. "PIN15,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 14. "PIN14,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 12. "PIN12,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 10. "PIN10,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 8. "PIN8,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-J Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1  it indicates the corresponding pin status is high; else the pin status is low.\nNote:" "0,1"
group.long 0x14++0x17
line.long 0x0 "PJ_DBEN,PJ De-bounce Enable Control Register"
bitfld.long 0x0 15. "DBEN15,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 14. "DBEN14,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 12. "DBEN12,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 10. "DBEN10,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 8. "DBEN8,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-J Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle  the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PJ_INTTYPE,PJ Interrupt Trigger Type Control"
bitfld.long 0x4 15. "TYPE15,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 14. "TYPE14,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 12. "TYPE12,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 10. "TYPE10,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 8. "TYPE8,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger  the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PJ_INTEN,PJ Interrupt Enable Control Register"
bitfld.long 0x8 31. "RHIEN15,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 30. "RHIEN14,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 28. "RHIEN12,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 26. "RHIEN10,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 24. "RHIEN8,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 14. "FLIEN14,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 12. "FLIEN12,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 10. "FLIEN10,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 8. "FLIEN8,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PJ_INTSRC,PJ Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-J Pin[n] Interrupt Source Flag\nWrite Operation:" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PJ_SMTEN,PJ Input Schmitt Trigger Enable Register"
bitfld.long 0x10 15. "SMTEN15,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 14. "SMTEN14,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 12. "SMTEN12,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 10. "SMTEN10,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 8. "SMTEN8,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-J Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PJ_SLEWCTL,PJ High Slew Rate Control Register"
bitfld.long 0x14 30.--31. "HSREN15,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 28.--29. "HSREN14,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 24.--25. "HSREN12,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 20.--21. "HSREN10,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 16.--17. "HSREN8,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 12.--13. "HSREN6,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 8.--9. "HSREN4,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 4.--5. "HSREN2,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
bitfld.long 0x14 0.--1. "HSREN0,Port A-J Pin[n] High Slew Rate Control\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD  VDDIO and VBAT electrical characteristics." "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Please refer to the Datasheet for detailed pin..,?"
group.long 0x30++0x7
line.long 0x0 "PJ_PUSEL,PJ Pull-up and Pull-down Selection Register"
bitfld.long 0x0 30.--31. "PUSEL15,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 28.--29. "PUSEL14,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 24.--25. "PUSEL12,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 20.--21. "PUSEL10,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 16.--17. "PUSEL8,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 12.--13. "PUSEL6,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 8.--9. "PUSEL4,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 4.--5. "PUSEL2,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
bitfld.long 0x0 0.--1. "PUSEL0,Port A-J Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins." "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,?,?"
line.long 0x4 "PJ_DBCTL,PJ Interrupt De-bounce Control Register"
rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode" "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
tree.end
tree "PA"
base ad:0x40004800
group.long 0x0++0x3F
line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PB"
base ad:0x40004840
group.long 0x0++0x3F
line.long 0x0 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x3C "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PC"
base ad:0x40004880
group.long 0x0++0x3B
line.long 0x0 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PD"
base ad:0x400048C0
group.long 0x0++0x3B
line.long 0x0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PE"
base ad:0x40004900
group.long 0x0++0x3F
line.long 0x0 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x3C "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PF"
base ad:0x40004940
group.long 0x0++0x2F
line.long 0x0 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PG"
base ad:0x40004980
group.long 0x0++0x3F
line.long 0x0 "PG0_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PG1_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PG2_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PG3_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PG4_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PG5_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PG6_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PG7_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PG8_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PG9_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PG10_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PG11_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PG12_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PG13_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PG14_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x3C "PG15_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PH"
base ad:0x400049C0
group.long 0x0++0x3F
line.long 0x0 "PH0_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PH1_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PH2_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PH3_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PH4_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PH5_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PH6_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PH7_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PH8_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PH9_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PH10_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PH11_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PH12_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PH13_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x38 "PH14_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x3C "PH15_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PI"
base ad:0x40004A00
group.long 0x18++0x27
line.long 0x0 "PI6_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PI7_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PI8_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PI9_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PI10_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PI11_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PI12_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PI13_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PI14_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PI15_PDIO,GPIO PI.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "PJ"
base ad:0x40004A40
group.long 0x0++0x37
line.long 0x0 "PJ0_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PJ1_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PJ2_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PJ3_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PJ4_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PJ5_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PJ6_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "PJ7_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x20 "PJ8_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x24 "PJ9_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x28 "PJ10_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x2C "PJ11_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x30 "PJ12_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x34 "PJ13_PDIO,GPIO PJ.n Pin Data Input/Output Register"
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree.end
tree "HBI (HyperBus Interface Controller)"
base ad:0x400CE000
group.long 0x0++0x1B
line.long 0x0 "HBI_CMD,HyperBus Command and Status Register"
hexmask.long.byte 0x0 0.--3. 1. "HYPCMD,HyperBus Command and Status\nWrite \nNote: When an operation is Done  the read value automatically return to 4'b0000."
line.long 0x4 "HBI_CONFIG,HyperBus Configuration Register"
hexmask.long.word 0x4 16.--26. 1. "CSMAXLT,Chip Select Maximum Low Time\nThis field indicates the maximum Low period of the chip select (CS#) in one transaction\nNote: This field indicates the timing of HyperRAM Chip Select specification so that it has to relative the frequency of HCLK.."
bitfld.long 0x4 14. "ENDIAN,Endian Condition on the HyperBus Data Pipe" "0: Little-Endian,1: Big-Endian"
bitfld.long 0x4 12.--13. "BGSIZE,Burst Group Size\nThis field indicates the burst length on the HyperBus transaction\nNote: This field must be set to the same value as 'Burst Length' in HyperRAM's Configuration Register 0." "0: 128 Bytes,1: 64 Bytes,?,?"
hexmask.long.byte 0x4 8.--11. 1. "CSHI,Chip Select High between Transaction\nThis field indicates the inactive period between two HyperBus transactions\nNote: This field must meet the HyperRAM device's specification of tCSHI."
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bitfld.long 0x4 6.--7. "CSH,Chip Select Hold Time After CK Falling Edge\nThis field indicates the hold time between the last CK falling edge and chip select" "0: 0.5 HCLK cycles,1: 1.5 HCLK cycles,?,?"
hexmask.long.byte 0x4 2.--5. 1. "ACCT,Initial Access Time\nThis field indicates the initial access cycles of the HyperBus transaction\nNote: This field must be set to the same value as 'Initial Latency' in HyperRAM's Configuration Register 0."
bitfld.long 0x4 0.--1. "CSST,Chip Select Setup Time to Next CK Rising Edge\nThis field indicates the setup time between the chip select and the next CK rising edge" "0: 1.5 HCLK cycles,1: 2.5 HCLK cycles,?,?"
line.long 0x8 "HBI_ADR,HyperBus Byte Address access Register"
hexmask.long 0x8 0.--31. 1. "ADR,HyperBus Byte Address\nMemory Space Range:\n 0x0000_0000 ~ 0x01FF_FFFF\nRegister Space Range:\nNote:\nIt is 'Byte' address  not 'word' address\nUp to 32M Bytes of memory space is supported."
line.long 0xC "HBI_WDATA,HyperBus 32-Bits Write Data Register"
hexmask.long 0xC 0.--31. 1. "WDATA,HyperBus 32-Bits Write Data\nTo write 1 Byte to HyperRAM  Byte 0 (Data[7:0]) is used\nTo write 2 Bytes to HyperRAM  Byte 1~0 (Data[15:0]) is used\nTo write 3 Bytes to HyperRAM  Byte 2~0 (Data[23:0]) is used\nTo write 4 Bytes to HyperRAM  Byte 3~0.."
line.long 0x10 "HBI_RDATA,HyperBus 32-Bits Read Data Register"
hexmask.long 0x10 0.--31. 1. "RDATA,HyperBus 32-Bits Read Data\n32-Bits Data for HyperBus Read\nNote: The data order depends on the ENDIAN (HBI_CONFIG[14]). Refer to Memory and Data Map section for detailed information."
line.long 0x14 "HBI_INTEN,HyperBus Interrupt Enable Register"
bitfld.long 0x14 0. "OPINTEN,HyperBus Operation Done Interrupt Enable" "0: Operation done interrupt Disabled,1: Operation done interrupt Enabled"
line.long 0x18 "HBI_INTSTS,HyperBus Interrupt Status Register"
bitfld.long 0x18 0. "OPDONE,HyperBus Operation Done Interrupt" "0: HyperBus operation is busy,1: HyperBus operation is done"
tree.end
tree "HSOTG (High Speed USB 2.0 On-The-Go)"
base ad:0x4004F000
group.long 0x0++0xF
line.long 0x0 "HSOTG_CTL,HSOTG Control Register"
bitfld.long 0x0 5. "WKEN,OTG ID Pin Wake-up Enable Bit" "0: OTG ID pin status change wake-up function Disabled,1: OTG ID pin status change wake-up function Enabled"
bitfld.long 0x0 4. "OTGEN,OTG Function Enable Bit\nUser needs to set this bit to enable OTG function while the USB frame configured as OTG device. When the USB frame is not configured as OTG device  this bit is must be low." "0: OTG function Disabled,1: OTG function Enabled"
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bitfld.long 0x0 2. "HNPREQEN,OTG HNP Request Enable Bit\nWhen the USB frame acts as A-device  set this bit when A-device allows to process HNP protocolA-device changes role from Host to Peripheral. This bit will be cleared when OTG state changes from a_suspend to.." "0: HNP request Disabled,1: HNP request Enabled (A-device can change role.."
bitfld.long 0x0 1. "BUSREQ,OTG Bus Request\nIf OTG A-device wants to do data transfers via USB bus  setting this bit will drive VBUS high to detect USB device connection. If user won't use the bus any more  clearing this bit will drop VBUS to save power. This bit will be.." "0: Not launch VBUS in OTG A-device or not request..,1: Launch VBUS in OTG A-device or request SRP in.."
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bitfld.long 0x0 0. "VBUSDROP,Drop VBUS Control\nIf user application running on this OTG A-device wants to conserve power  set this bit to drop VBUS. BUSREQ (HSOTG_CTL[1]) will be also cleared no matter A-device or B-device." "0: Not drop the VBUS,1: Drop the VBUS"
line.long 0x4 "HSOTG_PHYCTL,HSOTG PHY Control Register"
bitfld.long 0x4 8.--10. "FSEL,Reference Clock Frequency Select\nSelects OTG PHY reference clock frequency which is from HXT." "0: Reference clock is 9.6 MHz,1: Reference clock is 10 MHz,?,?,?,?,?,?"
bitfld.long 0x4 5. "VBSTSPOL,Off-chip USB VBUS Power Switch Status Polarity\nThe polarity of off-chip USB VBUS power switch valid signal depends on the selected component. A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch. Set this.." "0: The polarity of off-chip USB VBUS power switch..,1: The polarity of off-chip USB VBUS power switch.."
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bitfld.long 0x4 4. "VBENPOL,Off-chip USB VBUS Power Switch Enable Polarity\nThe OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need. A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.\nThe polarity of enabling.." "0: The off-chip USB VBUS power switch enable is..,1: The off-chip USB VBUS power switch enable is.."
bitfld.long 0x4 1. "IDDETEN,ID Detection Enable Bit" "0: Detect ID pin status Disabled,1: Detect ID pin status Enabled"
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bitfld.long 0x4 0. "OTGPHYEN,OTG PHY Enable Bit\nWhen the USB frame is configured as either OTG device or ID dependent  user needs to set this bit before using OTG function. If device is configured as neither OTG device nor ID dependent  this bit is 'don't care'." "0: OTG PHY Disabled,1: OTG PHY Enabled"
line.long 0x8 "HSOTG_INTEN,HSOTG Interrupt Enable Register"
bitfld.long 0x8 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and SESSEND (HSOTG_STATUS[2]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 10. "VBCHGIEN,VBUSVLD Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and VBUSVLD (HSOTG_STATUS[5]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 9. "AVLDCHGIEN,A-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and AVLD (HSOTG_STATUS[4]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 8. "BVLDCHGIEN,B-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and BVLD (HSOTG_STATUS[3]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 7. "HOSTIEN,Act As Host Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a host  an interrupt will be asserted." "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
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bitfld.long 0x8 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a peripheral  an interrupt will be asserted." "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
bitfld.long 0x8 5. "IDCHGIEN,IDSTS Changed Interrupt Enable Bit\nIf this bit is set to 1 and IDSTS (HSOTG_STATUS[1]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 4. "GOIDLEIEN,OTG Device Going to IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state. Please refer to A-device state diagram and B-device state diagram in OTG specification." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 3. "HNPFIEN,HNP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 2. "SRPFIEN,SRP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 1. "VBEIEN,VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 0. "ROLECHGIEN,Role Changed Interrupt Enable Bit\nNote: The role can be Host or Peripheral." "0: Interrupt Disabled,1: Interrupt Enabled"
line.long 0xC "HSOTG_INTSTS,HSOTG Interrupt Status Register"
bitfld.long 0xC 13. "SRPDETIF,SRP Detected Interrupt Status\nNote: Write 1 to clear this status." "0: SRP not detected,1: SRP detected"
bitfld.long 0xC 11. "SECHGIF,SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag." "0: SESSEND (HSOTG_STATUS[2]) not toggled,1: SESSEND (HSOTG_STATUS[2]) from high to low or.."
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bitfld.long 0xC 10. "VBCHGIF,VBUSVLD State Change Interrupt Status\nNote: Write 1 to clear this status." "0: VBUSVLD (HSOTG_STATUS[5]) not toggled,1: VBUSVLD (HSOTG_STATUS[5]) from high to low or.."
bitfld.long 0xC 9. "AVLDCHGIF,A-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status." "0: AVLD (HSOTG_STATUS[4]) not toggled,1: AVLD (HSOTG_STATUS[4]) from high to low or low.."
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bitfld.long 0xC 8. "BVLDCHGIF,B-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status." "0: BVLD (HSOTG_STATUS[3]) not toggled,1: BVLD (HSOTG_STATUS[3]) from high to low or low.."
bitfld.long 0xC 7. "HOSTIF,Act As Host Interrupt Status\nNote: Write 1 to clear this flag." "0: This device does not act as a host,1: This device acts as a host"
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bitfld.long 0xC 6. "PDEVIF,Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag." "0: This device does not act as a peripheral,1: This device acts as a peripheral"
bitfld.long 0xC 5. "IDCHGIF,ID State Change Interrupt Status\nNote: Write 1 to clear this flag." "0: IDSTS (HSOTG_STATUS[1]) not toggled,1: IDSTS (HSOTG_STATUS[1]) from high to low or from.."
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bitfld.long 0xC 4. "GOIDLEIF,OTG Device Goes to IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state. The OTG device will be neither a host nor a peripheral.\nNote 1: Going to idle state means going to a_idle or b_idle state." "0: OTG device does not go back to idle state..,1: Going to idle state means going to a_idle or.."
bitfld.long 0xC 3. "HNPFIF,HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus is in SE0 (both HSUSB_D+ and HSUSB_D- low) state  this bit will be set when A-device does not connect after specified interval expires. \nNote: Write 1 to clear.." "0: A-device connects to B-device before specified..,1: A-device does not connect to B-device before.."
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bitfld.long 0xC 2. "SRPFIF,SRP Fail Interrupt Status\nAfter initiating SRP  an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum  defined in OTG specification. This flag is set when the OTG B-device does not get VBUS high after this.." "0: OTG B-device gets VBUS high before this interval,1: OTG B-device does not get VBUS high before this.."
bitfld.long 0xC 1. "VBEIF,VBUS Error Interrupt Status\nThis bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. \nNote: Write 1 to clear this flag and recover from.." "0: OTG A-device drives VBUS over threshold voltage..,1: OTG A-device cannot drive VBUS over threshold.."
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bitfld.long 0xC 0. "ROLECHGIF,OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral  or changed from a peripheral to a host while USB_ID pin status does not change.\nNote: Write 1 to clear this flag." "0: OTG device role not changed,1: OTG device role changed"
rgroup.long 0x10++0x3
line.long 0x0 "HSOTG_STATUS,HSOTG Status Register"
bitfld.long 0x0 7. "ASHOST,As Host Status\nWhen OTG acts as Host  this bit is set." "0: OTG not as Host,1: OTG as Host"
bitfld.long 0x0 6. "ASPERI,As Peripheral Status\nWhen OTG acts as peripheral  this bit is set." "0: OTG not as peripheral,1: OTG as peripheral"
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bitfld.long 0x0 5. "VBUSVLD,VBUS Valid Status\nWhen VBUS is larger than 4.7V  this bit will be set to 1." "0: VBUS is not valid,1: VBUS is valid"
bitfld.long 0x0 4. "AVLD,A-Device Session Valid Status" "0: A-device session is not valid,1: A-device session is valid"
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bitfld.long 0x0 3. "BVLD,B-device Session Valid Status" "0: B-device session is not valid,1: B-device session is valid"
bitfld.long 0x0 2. "SESSEND,Session End Status\nWhen VBUS voltage is lower than 0.4V  this bit will be set to 1. Session end means no meaningful power on VBUS." "0: Session is not end,1: Session is end"
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bitfld.long 0x0 1. "IDSTS,USB_ID Pin State of Mini-/Micro-Plug" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
bitfld.long 0x0 0. "OVERCUR,Overcurrent Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold  4.4V minimum  within a maximum time of 100ms after OTG A-device drives VBUS high." "0: OTG A-device drives VBUS successfully,1: OTG A-device cannot drive VBUS high in this.."
tree.end
tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
base ad:0x0
tree "I2C0"
base ad:0x40080000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL0,I2C Control Register 0"
bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nNote: This bit is cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode  setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register  the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set  the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width.\nNote: Filter width Min :3*PCLK  Max : 18*PCLK"
hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled  the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled  the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
group.long 0x3C++0x23
line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear  it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear  user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF. This bit will be cleared by software writing 1." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C  this bit is set to 1. \nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration section." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
bitfld.long 0x8 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer." "0,1"
bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
line.long 0xC "I2C_STATUS1,I2C Status Register 1"
rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
rbitfld.long 0xC 7. "UDR,I2C Under Run Status Bit (Read Only)" "0,1"
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rbitfld.long 0xC 6. "OVR,I2C over Run Status Bit (Read Only)" "0,1"
rbitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY (Read Only)\nThis bit is set when POINTER is equal to 0." "0,1"
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rbitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL (Read Only)\nThis bit is set when POINTER is equal to 2." "0,1"
bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched  hardware will inform which address used. This bit will be set to 1  and will be cleared by software writing 1." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched  hardware will inform which address used. This bit will be set to 1 and will be cleared by software writing 1." "0,1"
bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State\nThe BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled  the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disabled. When the..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode  the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data  slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master  it calculates the period from START to ACK\nFor Slave  it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: This bit will be cleared by software writing 1." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy  the bit indicates the total clock low time-out event occurred; otherwise  it indicates the bus idle time-out event occurred.\nNote: This bit will be cleared by software writing 1." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin  the pull-high resistor is must in the system. 2. This bit will be cleared by software writing 1." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: This bit will be cleared by software writing 1." "0: PEC value equal to the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address  command code  and data frame."
rgroup.long 0x60++0x3
line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value (Read Only)"
group.long 0x64++0x7
line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT  the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT  the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
tree.end
tree "I2C1"
base ad:0x40081000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL0,I2C Control Register 0"
bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nNote: This bit is cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode  setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register  the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set  the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width.\nNote: Filter width Min :3*PCLK  Max : 18*PCLK"
hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled  the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled  the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
group.long 0x3C++0x23
line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear  it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear  user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF. This bit will be cleared by software writing 1." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C  this bit is set to 1. \nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration section." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
bitfld.long 0x8 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer." "0,1"
bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
line.long 0xC "I2C_STATUS1,I2C Status Register 1"
rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
rbitfld.long 0xC 7. "UDR,I2C Under Run Status Bit (Read Only)" "0,1"
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rbitfld.long 0xC 6. "OVR,I2C over Run Status Bit (Read Only)" "0,1"
rbitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY (Read Only)\nThis bit is set when POINTER is equal to 0." "0,1"
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rbitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL (Read Only)\nThis bit is set when POINTER is equal to 2." "0,1"
bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched  hardware will inform which address used. This bit will be set to 1  and will be cleared by software writing 1." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched  hardware will inform which address used. This bit will be set to 1 and will be cleared by software writing 1." "0,1"
bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State\nThe BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled  the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disabled. When the..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode  the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data  slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master  it calculates the period from START to ACK\nFor Slave  it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: This bit will be cleared by software writing 1." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy  the bit indicates the total clock low time-out event occurred; otherwise  it indicates the bus idle time-out event occurred.\nNote: This bit will be cleared by software writing 1." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin  the pull-high resistor is must in the system. 2. This bit will be cleared by software writing 1." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: This bit will be cleared by software writing 1." "0: PEC value equal to the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address  command code  and data frame."
rgroup.long 0x60++0x3
line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value (Read Only)"
group.long 0x64++0x7
line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT  the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT  the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
tree.end
tree "I2C2"
base ad:0x40082000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL0,I2C Control Register 0"
bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nNote: This bit is cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode  setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register  the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set  the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width.\nNote: Filter width Min :3*PCLK  Max : 18*PCLK"
hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled  the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled  the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
group.long 0x3C++0x23
line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear  it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear  user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF. This bit will be cleared by software writing 1." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C  this bit is set to 1. \nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration section." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
bitfld.long 0x8 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer." "0,1"
bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
line.long 0xC "I2C_STATUS1,I2C Status Register 1"
rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
rbitfld.long 0xC 7. "UDR,I2C Under Run Status Bit (Read Only)" "0,1"
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rbitfld.long 0xC 6. "OVR,I2C over Run Status Bit (Read Only)" "0,1"
rbitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY (Read Only)\nThis bit is set when POINTER is equal to 0." "0,1"
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rbitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL (Read Only)\nThis bit is set when POINTER is equal to 2." "0,1"
bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched  hardware will inform which address used. This bit will be set to 1  and will be cleared by software writing 1." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched  hardware will inform which address used. This bit will be set to 1 and will be cleared by software writing 1." "0,1"
bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State\nThe BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled  the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disabled. When the..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode  the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data  slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master  it calculates the period from START to ACK\nFor Slave  it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: This bit will be cleared by software writing 1." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy  the bit indicates the total clock low time-out event occurred; otherwise  it indicates the bus idle time-out event occurred.\nNote: This bit will be cleared by software writing 1." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin  the pull-high resistor is must in the system. 2. This bit will be cleared by software writing 1." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: This bit will be cleared by software writing 1." "0: PEC value equal to the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address  command code  and data frame."
rgroup.long 0x60++0x3
line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value (Read Only)"
group.long 0x64++0x7
line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT  the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT  the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
tree.end
tree "I2C3"
base ad:0x40083000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL0,I2C Control Register 0"
bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nNote: This bit is cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode  setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register  the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set  the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width.\nNote: Filter width Min :3*PCLK  Max : 18*PCLK"
hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled  the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled  the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
group.long 0x3C++0x23
line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear  it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear  user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF. This bit will be cleared by software writing 1." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C  this bit is set to 1. \nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration section." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
bitfld.long 0x8 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer." "0,1"
bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
line.long 0xC "I2C_STATUS1,I2C Status Register 1"
rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
rbitfld.long 0xC 7. "UDR,I2C Under Run Status Bit (Read Only)" "0,1"
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rbitfld.long 0xC 6. "OVR,I2C over Run Status Bit (Read Only)" "0,1"
rbitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY (Read Only)\nThis bit is set when POINTER is equal to 0." "0,1"
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rbitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL (Read Only)\nThis bit is set when POINTER is equal to 2." "0,1"
bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched  hardware will inform which address used. This bit will be set to 1  and will be cleared by software writing 1." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched  hardware will inform which address used. This bit will be set to 1 and will be cleared by software writing 1." "0,1"
bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State\nThe BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled  the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disabled. When the..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode  the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data  slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master  it calculates the period from START to ACK\nFor Slave  it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: This bit will be cleared by software writing 1." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy  the bit indicates the total clock low time-out event occurred; otherwise  it indicates the bus idle time-out event occurred.\nNote: This bit will be cleared by software writing 1." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin  the pull-high resistor is must in the system. 2. This bit will be cleared by software writing 1." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: This bit will be cleared by software writing 1." "0: PEC value equal to the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address  command code  and data frame."
rgroup.long 0x60++0x3
line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value (Read Only)"
group.long 0x64++0x7
line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT  the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT  the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
tree.end
tree "I2C4"
base ad:0x40084000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL0,I2C Control Register 0"
bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nNote: This bit is cleared by writing 1 to it." "0,1"
bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nNote: This bit is cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode  setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register  the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set  the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width.\nNote: Filter width Min :3*PCLK  Max : 18*PCLK"
hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled  the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled  the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode  the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set.."
group.long 0x3C++0x23
line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear  it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear  user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF. This bit will be cleared by software writing 1." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C  this bit is set to 1. \nNote: This bit will be cleared by software writing 1." "0,1"
line.long 0x8 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration section." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
bitfld.long 0x8 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer." "0,1"
bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
line.long 0xC "I2C_STATUS1,I2C Status Register 1"
rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
rbitfld.long 0xC 7. "UDR,I2C Under Run Status Bit (Read Only)" "0,1"
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rbitfld.long 0xC 6. "OVR,I2C over Run Status Bit (Read Only)" "0,1"
rbitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY (Read Only)\nThis bit is set when POINTER is equal to 0." "0,1"
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rbitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL (Read Only)\nThis bit is set when POINTER is equal to 2." "0,1"
bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched  hardware will inform which address used. This bit will be set to 1  and will be cleared by software writing 1." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched  hardware will inform which address used. This bit will be set to 1 and will be cleared by software writing 1." "0,1"
bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched  hardware will inform which address used. This bit will be set to 1 and cleared by software writing 1." "0,1"
line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State\nThe BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled  the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disabled. When the..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode  the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data  slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master  it calculates the period from START to ACK\nFor Slave  it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: This bit will be cleared by software writing 1." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy  the bit indicates the total clock low time-out event occurred; otherwise  it indicates the bus idle time-out event occurred.\nNote: This bit will be cleared by software writing 1." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin  the pull-high resistor is must in the system. 2. This bit will be cleared by software writing 1." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: This bit will be cleared by software writing 1." "0: PEC value equal to the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: This bit will be cleared by software writing 1." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address  command code  and data frame."
rgroup.long 0x60++0x3
line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value (Read Only)"
group.long 0x64++0x7
line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT  the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT  the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
tree.end
tree.end
tree "I2S (Inter-IC Sound)"
base ad:0x0
tree "I2S0"
base ad:0x40048000
group.long 0x0++0xF
line.long 0x0 "I2Sx_CTL0,I2S Control Register 0"
bitfld.long 0x0 30.--31. "TDMCHNUM,TDM Channel Number" "0: 2 channels in audio frame,1: 4 channels in audio frame,?,?"
bitfld.long 0x0 28.--29. "CHWIDTH,Channel Width\nThis bit fields are used to define the length of audio channel. If CHWIDTH DATWIDTH  the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH." "0: The bit-width of each audio channel is 8-bit,1: The bit-width of each audio channel is 16-bit,?,?"
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bitfld.long 0x0 27. "PCMSYNC,PCM Synchronization Pulse Length Selection\nThis bit field is used to select the high pulse length of frame synchronization signal in PCM protocol\nNote: This bit is only available in master mode" "0: One BCLK period,1: One channel period"
bitfld.long 0x0 24.--26. "FORMAT,Data Format Selection" "0: I2S standard data format,1: I2S with MSB justified,?,?,?,?,?,?"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive channel1 data in MONO mode,1: Receive channel0 data in MONO mode"
bitfld.long 0x0 21. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 20. "TXPDMAEN,Transmit PDMA Enable Bit" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
bitfld.long 0x0 19. "RXFBCLR,Receive FIFO Buffer Clear\nNote 1: Write 1 to clear receive FIFO  internal pointer is reset to FIFO start point  and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.\nNote 2: This bit is cleared by hardware automatically  read.." "0: No Effect,1: Write 1 to clear receive FIFO"
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bitfld.long 0x0 18. "TXFBCLR,Transmit FIFO Buffer Clear\nNote 1: Write 1 to clear transmit FIFO  internal pointer is reset to FIFO start point  and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nNote 2: This.." "0: No Effect,1: Write 1 to clear transmit FIFO"
bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1  I2S controller will generate master clock on I2S_MCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode Enable Bit\nNote: I2S can operate as master or slave. For Master mode  I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode  I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and.." "0: Master mode,1: Slave mode"
bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO\nIn 8-bit/16-bit data width  this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width  this is used to select the left/right alignment method of audio data which is.." "0: Even channel data at high byte in 8-bit/16-bit..,1: Even channel data at low byte in 8-bit/16-bit.."
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bitfld.long 0x0 6. "MONO,Monaural Data Control\nNote: When chip records data  RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected." "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x0 4.--5. "DATWIDTH,Data Width\nThis bit field is used to define the bit-width of data word in each audio channel" "0: The bit-width of data word is 8-bit,1: The bit-width of data word is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Send zero on transmit channel"
bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receiving Disabled,1: Data receiving Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmission Disabled,1: Data transmission Enabled"
bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit" "0: I2S controller Disabled,1: I2S controller Enabled"
line.long 0x4 "I2Sx_CLKDIV,I2S Clock Divider Register"
hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency.\nNote: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK"
hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0  MCLK is the same as external clock input.\nNote:.."
line.long 0x8 "I2Sx_IEN,I2S Interrupt Enable Register"
bitfld.long 0x8 23. "CH7ZCIEN,Channel7 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 22. "CH6ZCIEN,Channel6 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 21. "CH5ZCIEN,Channel5 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 20. "CH4ZCIEN,Channel4 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 19. "CH3ZCIEN,Channel3 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 18. "CH2ZCIEN,Channel2 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 17. "CH1ZCIEN,Channel1 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 16. "CH0ZCIEN,Channel0 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8])." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 9. "TXOVFIEN,Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 8. "TXUDFIEN,Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16])." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 1. "RXOVFIEN,Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 0. "RXUDFIEN,Receive FIFO Underflow Interrupt Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. If RXUDFIEN bit is enabled  interrupt occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
line.long 0xC "I2Sx_STATUS0,I2S Status Register 0"
rbitfld.long 0xC 21. "TXBUSY,Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer." "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
rbitfld.long 0xC 20. "TXEMPTY,Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is 0" "0: Not empty,1: Empty"
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rbitfld.long 0xC 19. "TXFULL,Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 16" "0: Not full,1: Full"
rbitfld.long 0xC 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is larger.." "0: Data word(s) in FIFO is larger than threshold..,1: Data word(s) in FIFO is less than or equal to.."
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bitfld.long 0xC 17. "TXOVIF,Transmit FIFO Overflow Interrupt Flag\nNote 1: Write data to transmit FIFO when it is full and this bit set to 1\nNote 2: Write 1 to clear this bit to 0." "0: No overflow,1: Write data to transmit FIFO when it is full and.."
bitfld.long 0xC 16. "TXUDIF,Transmit FIFO Underflow Interrupt Flag\nNote 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.\nNote 2: Write 1 to clear this.." "0: No underflow,1: This bit will be set to 1 when shift logic.."
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rbitfld.long 0xC 12. "RXEMPTY,Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is 0" "0: Not empty,1: Empty"
rbitfld.long 0xC 11. "RXFULL,Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 16." "0: Not full,1: Full"
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rbitfld.long 0xC 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is less than or.." "0: Data word(s) in FIFO is less than or equal to..,1: Data word(s) in FIFO is larger than threshold.."
bitfld.long 0xC 9. "RXOVIF,Receive FIFO Overflow Interrupt Flag\nNote 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1  data in 1st buffer is overwritten.\nNote 2: Write 1 to clear this bit to 0." "0: No overflow occur,1: When receive FIFO is full and receive hardware.."
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bitfld.long 0xC 8. "RXUDIF,Receive FIFO Underflow Interrupt Flag\nNote 1: When receive FIFO is empty  and software reads the receive FIFO again. This bit will be set to 1  and it indicates underflow situation occurs.\nNote 2: Write 1 to clear this bit to 0" "0: No underflow occur,1: When receive FIFO is empty"
rbitfld.long 0xC 3.--5. "DATACH,Transmission Data Channel (Read Only)\nThis bit fields are used to indicate which audio channel is current transmit data belong." "0: channel0 (means left channel while 2-channel..,1: channel1 (means right channel while 2-channel..,?,?,?,?,?,?"
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rbitfld.long 0xC 2. "I2STXINT,I2S Transmit Interrupt (Read Only)" "0: No transmit interrupt,1: Transmit interrupt"
rbitfld.long 0xC 1. "I2SRXINT,I2S Receive Interrupt (Read Only)" "0: No receive interrupt,1: Receive interrupt"
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rbitfld.long 0xC 0. "I2SINT,I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of I2STXINT and I2SRXINT bits." "0: No I2S interrupt,1: I2S interrupt"
wgroup.long 0x10++0x3
line.long 0x0 "I2Sx_TXFIFO,I2S Transmit FIFO Register"
hexmask.long 0x0 0.--31. 1. "TXFIFO,Transmit FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8])."
rgroup.long 0x14++0x3
line.long 0x0 "I2Sx_RXFIFO,I2S Receive FIFO Register"
hexmask.long 0x0 0.--31. 1. "RXFIFO,Receive FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16])."
group.long 0x20++0x7
line.long 0x0 "I2Sx_CTL1,I2S Control Register 1"
bitfld.long 0x0 25. "PB16ORD,FIFO Read/Write Order in 16-bit Width of Peripheral Bus" "0: Low 16-bit read/write access first,1: High 16-bit read/write access first"
bitfld.long 0x0 24. "PBWIDTH,Peripheral Bus Data Width Selection\nThis bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode" "0: 32 bits data width,1: 16 bits data width"
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hexmask.long.byte 0x0 16.--19. 1. "RXTH,Receive FIFO Threshold Level\nNote: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set."
hexmask.long.byte 0x0 8.--11. 1. "TXTH,Transmit FIFO Threshold Level\nNote: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set."
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bitfld.long 0x0 7. "CH7ZCEN,Channel7 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.\nNote 3: If CH7ZCIF flag is set to 1  the channel7 will.." "0: channel7 zero-cross detect Disabled,1: channel7 zero-cross detect Enabled"
bitfld.long 0x0 6. "CH6ZCEN,Channel6 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.\nNote 3: If CH6ZCIF flag is set to 1  the channel6 will be.." "0: channel6 zero-cross detect Disabled,1: channel6 zero-cross detect Enabled"
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bitfld.long 0x0 5. "CH5ZCEN,Channel5 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.\nNote 3: If CH5ZCIF flag is set to 1  the channel5 will be.." "0: channel5 zero-cross detect Disabled,1: channel5 zero-cross detect Enabled"
bitfld.long 0x0 4. "CH4ZCEN,Channel4 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.\nNote 3: If CH4ZCIF flag is set to 1  the channel4 will be.." "0: channel4 zero-cross detect Disabled,1: channel4 zero-cross detect Enabled"
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bitfld.long 0x0 3. "CH3ZCEN,Channel3 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.\nNote 3: If CH3ZCIF flag is set to 1  the channel3 will be.." "0: channel3 zero-cross detect Disabled,1: channel3 zero-cross detect Enabled"
bitfld.long 0x0 2. "CH2ZCEN,Channel2 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.\nNote 3: If CH2ZCIF flag is set to 1  the channel2 will be.." "0: channel2 zero-cross detect Disabled,1: channel2 zero-cross detect Enabled"
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bitfld.long 0x0 1. "CH1ZCEN,Channel1 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.\nNote 3: If CH1ZCIF flag is set to 1  the channel1 will be.." "0: channel1 zero-cross detect Disabled,1: channel1 zero-cross detect Enabled"
bitfld.long 0x0 0. "CH0ZCEN,Channel0 Zero-cross Detection Enable Bit\nNote 2: If this bit is set to 1  when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.\nNote 3: If CH0ZCIF flag is set to 1  the channel0 will.." "0: channel0 zero-cross detect Disabled,1: channel0 zero-cross detect Enabled"
line.long 0x4 "I2Sx_STATUS1,I2S Status Register 1"
hexmask.long.byte 0x4 16.--20. 1. "RXCNT,Receive FIFO Level (Read Only)\nThese bits indicate the number of available entries in receive FIFO\nOthers are reserved."
hexmask.long.byte 0x4 8.--12. 1. "TXCNT,Transmit FIFO Level (Read Only)\nThese bits indicate the number of available entries in transmit FIFO\nOthers are reserved."
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bitfld.long 0x4 7. "CH7ZCIF,Channel7 Zero-cross Interrupt Flag\nIt indicates channel7 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel7,1: Channel7 zero-cross is detected"
bitfld.long 0x4 6. "CH6ZCIF,Channel6 Zero-cross Interrupt Flag\nIt indicates channel6 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel6,1: Channel6 zero-cross is detected"
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bitfld.long 0x4 5. "CH5ZCIF,Channel5 Zero-cross Interrupt Flag\nIt indicates channel5 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel5,1: Channel5 zero-cross is detected"
bitfld.long 0x4 4. "CH4ZCIF,Channel4 Zero-cross Interrupt Flag\nIt indicates channel4 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel4,1: Channel4 zero-cross is detected"
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bitfld.long 0x4 3. "CH3ZCIF,Channel3 Zero-cross Interrupt Flag\nIt indicates channel3 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel3,1: Channel3 zero-cross is detected"
bitfld.long 0x4 2. "CH2ZCIF,Channel2 Zero-cross Interrupt Flag\nIt indicates channel2 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel2,1: Channel2 zero-cross is detected"
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bitfld.long 0x4 1. "CH1ZCIF,Channel1 Zero-cross Interrupt Flag\nIt indicates channel1 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel1,1: Channel1 zero-cross is detected"
bitfld.long 0x4 0. "CH0ZCIF,Channel0 Zero-cross Interrupt Flag\nIt indicates channel0 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel0,1: Channel0 zero-cross is detected"
tree.end
tree "I2S1"
base ad:0x40049000
group.long 0x0++0xF
line.long 0x0 "I2Sx_CTL0,I2S Control Register 0"
bitfld.long 0x0 30.--31. "TDMCHNUM,TDM Channel Number" "0: 2 channels in audio frame,1: 4 channels in audio frame,?,?"
bitfld.long 0x0 28.--29. "CHWIDTH,Channel Width\nThis bit fields are used to define the length of audio channel. If CHWIDTH DATWIDTH  the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH." "0: The bit-width of each audio channel is 8-bit,1: The bit-width of each audio channel is 16-bit,?,?"
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bitfld.long 0x0 27. "PCMSYNC,PCM Synchronization Pulse Length Selection\nThis bit field is used to select the high pulse length of frame synchronization signal in PCM protocol\nNote: This bit is only available in master mode" "0: One BCLK period,1: One channel period"
bitfld.long 0x0 24.--26. "FORMAT,Data Format Selection" "0: I2S standard data format,1: I2S with MSB justified,?,?,?,?,?,?"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive channel1 data in MONO mode,1: Receive channel0 data in MONO mode"
bitfld.long 0x0 21. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 20. "TXPDMAEN,Transmit PDMA Enable Bit" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
bitfld.long 0x0 19. "RXFBCLR,Receive FIFO Buffer Clear\nNote 1: Write 1 to clear receive FIFO  internal pointer is reset to FIFO start point  and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.\nNote 2: This bit is cleared by hardware automatically  read.." "0: No Effect,1: Write 1 to clear receive FIFO"
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bitfld.long 0x0 18. "TXFBCLR,Transmit FIFO Buffer Clear\nNote 1: Write 1 to clear transmit FIFO  internal pointer is reset to FIFO start point  and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nNote 2: This.." "0: No Effect,1: Write 1 to clear transmit FIFO"
bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1  I2S controller will generate master clock on I2S_MCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode Enable Bit\nNote: I2S can operate as master or slave. For Master mode  I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode  I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and.." "0: Master mode,1: Slave mode"
bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO\nIn 8-bit/16-bit data width  this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width  this is used to select the left/right alignment method of audio data which is.." "0: Even channel data at high byte in 8-bit/16-bit..,1: Even channel data at low byte in 8-bit/16-bit.."
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bitfld.long 0x0 6. "MONO,Monaural Data Control\nNote: When chip records data  RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected." "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x0 4.--5. "DATWIDTH,Data Width\nThis bit field is used to define the bit-width of data word in each audio channel" "0: The bit-width of data word is 8-bit,1: The bit-width of data word is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Send zero on transmit channel"
bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receiving Disabled,1: Data receiving Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmission Disabled,1: Data transmission Enabled"
bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit" "0: I2S controller Disabled,1: I2S controller Enabled"
line.long 0x4 "I2Sx_CLKDIV,I2S Clock Divider Register"
hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency.\nNote: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK"
hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0  MCLK is the same as external clock input.\nNote:.."
line.long 0x8 "I2Sx_IEN,I2S Interrupt Enable Register"
bitfld.long 0x8 23. "CH7ZCIEN,Channel7 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 22. "CH6ZCIEN,Channel6 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 21. "CH5ZCIEN,Channel5 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 20. "CH4ZCIEN,Channel4 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 19. "CH3ZCIEN,Channel3 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 18. "CH2ZCIEN,Channel2 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 17. "CH1ZCIEN,Channel1 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 16. "CH0ZCIEN,Channel0 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8])." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 9. "TXOVFIEN,Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 8. "TXUDFIEN,Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16])." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 1. "RXOVFIEN,Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 0. "RXUDFIEN,Receive FIFO Underflow Interrupt Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. If RXUDFIEN bit is enabled  interrupt occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
line.long 0xC "I2Sx_STATUS0,I2S Status Register 0"
rbitfld.long 0xC 21. "TXBUSY,Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer." "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
rbitfld.long 0xC 20. "TXEMPTY,Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is 0" "0: Not empty,1: Empty"
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rbitfld.long 0xC 19. "TXFULL,Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 16" "0: Not full,1: Full"
rbitfld.long 0xC 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is larger.." "0: Data word(s) in FIFO is larger than threshold..,1: Data word(s) in FIFO is less than or equal to.."
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bitfld.long 0xC 17. "TXOVIF,Transmit FIFO Overflow Interrupt Flag\nNote 1: Write data to transmit FIFO when it is full and this bit set to 1\nNote 2: Write 1 to clear this bit to 0." "0: No overflow,1: Write data to transmit FIFO when it is full and.."
bitfld.long 0xC 16. "TXUDIF,Transmit FIFO Underflow Interrupt Flag\nNote 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.\nNote 2: Write 1 to clear this.." "0: No underflow,1: This bit will be set to 1 when shift logic.."
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rbitfld.long 0xC 12. "RXEMPTY,Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is 0" "0: Not empty,1: Empty"
rbitfld.long 0xC 11. "RXFULL,Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 16." "0: Not full,1: Full"
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rbitfld.long 0xC 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is less than or.." "0: Data word(s) in FIFO is less than or equal to..,1: Data word(s) in FIFO is larger than threshold.."
bitfld.long 0xC 9. "RXOVIF,Receive FIFO Overflow Interrupt Flag\nNote 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1  data in 1st buffer is overwritten.\nNote 2: Write 1 to clear this bit to 0." "0: No overflow occur,1: When receive FIFO is full and receive hardware.."
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bitfld.long 0xC 8. "RXUDIF,Receive FIFO Underflow Interrupt Flag\nNote 1: When receive FIFO is empty  and software reads the receive FIFO again. This bit will be set to 1  and it indicates underflow situation occurs.\nNote 2: Write 1 to clear this bit to 0" "0: No underflow occur,1: When receive FIFO is empty"
rbitfld.long 0xC 3.--5. "DATACH,Transmission Data Channel (Read Only)\nThis bit fields are used to indicate which audio channel is current transmit data belong." "0: channel0 (means left channel while 2-channel..,1: channel1 (means right channel while 2-channel..,?,?,?,?,?,?"
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rbitfld.long 0xC 2. "I2STXINT,I2S Transmit Interrupt (Read Only)" "0: No transmit interrupt,1: Transmit interrupt"
rbitfld.long 0xC 1. "I2SRXINT,I2S Receive Interrupt (Read Only)" "0: No receive interrupt,1: Receive interrupt"
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rbitfld.long 0xC 0. "I2SINT,I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of I2STXINT and I2SRXINT bits." "0: No I2S interrupt,1: I2S interrupt"
wgroup.long 0x10++0x3
line.long 0x0 "I2Sx_TXFIFO,I2S Transmit FIFO Register"
hexmask.long 0x0 0.--31. 1. "TXFIFO,Transmit FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8])."
rgroup.long 0x14++0x3
line.long 0x0 "I2Sx_RXFIFO,I2S Receive FIFO Register"
hexmask.long 0x0 0.--31. 1. "RXFIFO,Receive FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16])."
group.long 0x20++0x7
line.long 0x0 "I2Sx_CTL1,I2S Control Register 1"
bitfld.long 0x0 25. "PB16ORD,FIFO Read/Write Order in 16-bit Width of Peripheral Bus" "0: Low 16-bit read/write access first,1: High 16-bit read/write access first"
bitfld.long 0x0 24. "PBWIDTH,Peripheral Bus Data Width Selection\nThis bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode" "0: 32 bits data width,1: 16 bits data width"
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hexmask.long.byte 0x0 16.--19. 1. "RXTH,Receive FIFO Threshold Level\nNote: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set."
hexmask.long.byte 0x0 8.--11. 1. "TXTH,Transmit FIFO Threshold Level\nNote: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set."
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bitfld.long 0x0 7. "CH7ZCEN,Channel7 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.\nNote 3: If CH7ZCIF flag is set to 1  the channel7 will.." "0: channel7 zero-cross detect Disabled,1: channel7 zero-cross detect Enabled"
bitfld.long 0x0 6. "CH6ZCEN,Channel6 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.\nNote 3: If CH6ZCIF flag is set to 1  the channel6 will be.." "0: channel6 zero-cross detect Disabled,1: channel6 zero-cross detect Enabled"
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bitfld.long 0x0 5. "CH5ZCEN,Channel5 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.\nNote 3: If CH5ZCIF flag is set to 1  the channel5 will be.." "0: channel5 zero-cross detect Disabled,1: channel5 zero-cross detect Enabled"
bitfld.long 0x0 4. "CH4ZCEN,Channel4 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.\nNote 3: If CH4ZCIF flag is set to 1  the channel4 will be.." "0: channel4 zero-cross detect Disabled,1: channel4 zero-cross detect Enabled"
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bitfld.long 0x0 3. "CH3ZCEN,Channel3 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.\nNote 3: If CH3ZCIF flag is set to 1  the channel3 will be.." "0: channel3 zero-cross detect Disabled,1: channel3 zero-cross detect Enabled"
bitfld.long 0x0 2. "CH2ZCEN,Channel2 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.\nNote 3: If CH2ZCIF flag is set to 1  the channel2 will be.." "0: channel2 zero-cross detect Disabled,1: channel2 zero-cross detect Enabled"
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bitfld.long 0x0 1. "CH1ZCEN,Channel1 Zero-cross Detect Enable Bit\nNote 2: If this bit is set to 1  when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.\nNote 3: If CH1ZCIF flag is set to 1  the channel1 will be.." "0: channel1 zero-cross detect Disabled,1: channel1 zero-cross detect Enabled"
bitfld.long 0x0 0. "CH0ZCEN,Channel0 Zero-cross Detection Enable Bit\nNote 2: If this bit is set to 1  when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.\nNote 3: If CH0ZCIF flag is set to 1  the channel0 will.." "0: channel0 zero-cross detect Disabled,1: channel0 zero-cross detect Enabled"
line.long 0x4 "I2Sx_STATUS1,I2S Status Register 1"
hexmask.long.byte 0x4 16.--20. 1. "RXCNT,Receive FIFO Level (Read Only)\nThese bits indicate the number of available entries in receive FIFO\nOthers are reserved."
hexmask.long.byte 0x4 8.--12. 1. "TXCNT,Transmit FIFO Level (Read Only)\nThese bits indicate the number of available entries in transmit FIFO\nOthers are reserved."
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bitfld.long 0x4 7. "CH7ZCIF,Channel7 Zero-cross Interrupt Flag\nIt indicates channel7 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel7,1: Channel7 zero-cross is detected"
bitfld.long 0x4 6. "CH6ZCIF,Channel6 Zero-cross Interrupt Flag\nIt indicates channel6 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel6,1: Channel6 zero-cross is detected"
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bitfld.long 0x4 5. "CH5ZCIF,Channel5 Zero-cross Interrupt Flag\nIt indicates channel5 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel5,1: Channel5 zero-cross is detected"
bitfld.long 0x4 4. "CH4ZCIF,Channel4 Zero-cross Interrupt Flag\nIt indicates channel4 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel4,1: Channel4 zero-cross is detected"
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bitfld.long 0x4 3. "CH3ZCIF,Channel3 Zero-cross Interrupt Flag\nIt indicates channel3 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel3,1: Channel3 zero-cross is detected"
bitfld.long 0x4 2. "CH2ZCIF,Channel2 Zero-cross Interrupt Flag\nIt indicates channel2 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel2,1: Channel2 zero-cross is detected"
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bitfld.long 0x4 1. "CH1ZCIF,Channel1 Zero-cross Interrupt Flag\nIt indicates channel1 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel1,1: Channel1 zero-cross is detected"
bitfld.long 0x4 0. "CH0ZCIF,Channel0 Zero-cross Interrupt Flag\nIt indicates channel0 next sample data sign bit is changed or all data bits are 0." "0: No zero-cross in channel0,1: Channel0 zero-cross is detected"
tree.end
tree.end
tree "KPI (Keypad Interface)"
base ad:0x400C2000
group.long 0x0++0x3
line.long 0x0 "KPI_CTL,Keypad Control Register"
bitfld.long 0x0 28.--30. "KROW,Keypad Matrix ROW Number\nThe keypad matrix is set by ROW x COL. The ROW number can be set 2 to 6." "0: Reserved.,1: 2,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "KCOL,Keypad Matrix COL Number\nThe keypad matrix is set by ROW x COL. The COL number can be set 1 to 8." "0: 1,1: 2,?,?,?,?,?,?"
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bitfld.long 0x0 22.--23. "ROWDLY,Scan Row Delay\nSetting delay cycle when row change  for avoid KPI from detecting wrong key.\nNote:\nScan row delay cycle debounce sampling cycle.\nRow scan time scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle (change row).." "0: 4 KPI engine clock cycle,1: 8 KPI engine clock cycle,?,?"
hexmask.long.byte 0x0 16.--19. 1. "DBCLKSEL,Scan in De-bounce Sampling Cycle Selection"
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hexmask.long.byte 0x0 8.--15. 1. "PSC,Row Scan Cycle Pre-scale Value\nThis value is used to pre-scale row scan cycle. \nThe pre-scale counter is clocked by the divided crystal clock  xCLOCK. \nThe divided number is from 1 to 256.\nFor example  if the crystal clock is 1 MHz then the.."
bitfld.long 0x0 4.--5. "DBCT,De-bounce Cycle Time\nFor keypad debounce  keypad will generate an interrupt when key press or key release continued n * key array scan time.\nNote: It would need more time to indicate key press and release event when users selected more debounce.." "0: n=1,1: n=2,?,?"
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bitfld.long 0x0 3. "KIEN,Key Interrupt Enable\nNote: The bit will be reset when KPI reset occurs." "0: Keypad interrupt Disabled,1: Keypad interrupt Enabled"
bitfld.long 0x0 2. "KRIEN,Key Release Interrupt Enable\nThe keypad controller will generate an interrupt when the controller detects keypad status changes from press to release.\nNote: The bit will be reset when KPI reset occurs." "0: Keypad release interrupt Disabled,1: Keypad release interrupt Enabled"
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bitfld.long 0x0 1. "KPIEN,Key Press Interrupt Enable\nThe keypad controller will generate an interrupt when the controller detects any effective key press.\nNote: The bit will be reset when KPI reset occurs." "0: Keypad press interrupt Disabled,1: Keypad press interrupt Enabled"
bitfld.long 0x0 0. "KPEN,Keypad Enable\nSetting this bit high enables the key scan function." "0: Keypad scan Disabled,1: Keypad scan Enabled"
group.long 0x8++0x3
line.long 0x0 "KPI_STATUS,Keypad Status Register"
bitfld.long 0x0 4. "KPIF,Key Press Interrupt Flag\nThis bit indicates that some keys (one or multiple key) have been pressed.\nWhen READ:\nNote: To clear KPIF  software must clear each pressing flag that are shown on KPI_KPF0/1 registers." "0: No key press,1: At least one key press"
bitfld.long 0x0 3. "KRIF,Key Release Interrupt Flag\nThis bit indicates that some keys (one or multiple key) have been released.\nWhen READ:\nNote: To clear KRIF  software must clear each releasing flag that are shown on KPI_KRF0/1 registers." "0: No key release,1: At least one key release"
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bitfld.long 0x0 2. "KIF,Key Interrupt Flag\nThis bit indicates the key scan interrupt is active when any key press or key release.\nWhen READ:\nNote: To clear KIF  software must clear KPIF  KRIF and TKRIF." "0: No reset,1: Key press/Key release interrupt occurred"
rgroup.long 0x10++0x7
line.long 0x0 "KPI_KST0,Keypad State Register 0"
hexmask.long 0x0 0.--31. 1. "KSTmn,Key State\nm is row number  n is column number."
line.long 0x4 "KPI_KST1,Keypad State Register 1"
hexmask.long.word 0x4 0.--15. 1. "KESTmn,Key State\nm is row number  n is column number."
group.long 0x18++0x13
line.long 0x0 "KPI_KPF0,Lower 32 Key Press Flag Register 0"
hexmask.long 0x0 0.--31. 1. "KPFmn,Lower 32 Key Press Flag\nm is row number  n is column number.\nNote: This bit will be set by hardware  and should be cleared by software writing 1. KPIF (KPI_STATUS[4]) can be cleared by writing 1."
line.long 0x4 "KPI_KPF1,Upper 32 Key Press Flag Register 1"
hexmask.long.word 0x4 0.--15. 1. "KPEmn,Upper 32 Key Press Flag\nm is row number  n is column number.\nNote: This bit will be set by hardware  and should be cleared by software writing 1."
line.long 0x8 "KPI_KRF0,Lower 32 Key Release Flag Register 0"
hexmask.long 0x8 0.--31. 1. "KRFmn,Lower 32 Key Release Flag\nm is row number  n is column number.\nNote: This bit will be set by hardware  and should be cleared by software writing 1."
line.long 0xC "KPI_KRF1,Upper 32 Key Release Flag Register 1"
hexmask.long.word 0xC 0.--15. 1. "KRFmn,Upper 32 Key Release Flag\nm is row number  n is column number.\nNote: This bit will be set by hardware  and should be cleared by software writing 1."
line.long 0x10 "KPI_DLYCTL,Delay Control Register"
hexmask.long.tbyte 0x10 8.--31. 1. "SCANDLY,Key Array Scan Delay\nThis value is used to insert delay cycle between each key array scan. \nThe key array scan delay counter is clocked by the divided crystal clock  xCLOCK. \nNote: If the key array scan delay is set to 0  there is no delay.."
hexmask.long.byte 0x10 0.--7. 1. "PSCDIV,Pre-scale Divider\nThis value is used to divide RESCALE that is set in KPI_CTL[15:8]. The prescale divider counter is clocked by the divided crystal clock  xCLOCK. The number is from 1 to 256.\nFor example  if the crystal clock is 1 MHz then the.."
tree.end
tree "KS (Key Store)"
base ad:0x40035000
group.long 0x0++0xB
line.long 0x0 "KS_CTL,Key Store Control Register"
bitfld.long 0x0 15. "IEN,Key Store Interrupt Enable Bit" "0: Key Store Interrupt Disabled,1: Key Store Interrupt Enabled"
bitfld.long 0x0 8. "INIT,Key Store Initialization\nUser should to check BUSY(KS_STS[2]) is 0  and then write 1 to this bit and START(KS_CTL[0[)  Key Store will start to initialization.\nAfter Key Store is initialized  INIT will be cleared." "0,1"
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bitfld.long 0x0 7. "CONT,Read/Write Key Continue Bit" "0: Read/Write key operation is not continuous to..,1: Read/Write key operation is continuous to.."
bitfld.long 0x0 1.--3. "OPMODE,Key Store Operation Mode" "0: Read operation,1: Create operation,?,?,?,?,?,?"
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bitfld.long 0x0 0. "START,Key Store Start Control Bit" "0: No operation,1: Start the operation"
line.long 0x4 "KS_METADATA,Key Store Metadata Register"
bitfld.long 0x4 30.--31. "DST,Key Location Selection Bits" "0: Key is in SRAM,1: Key is in Flash,?,?"
hexmask.long.byte 0x4 20.--25. 1. "NUMBER,Key Number\nBefore read or erase one key operation is started  user should write the key number to be operated. When create operation is finished  user can read these bits to get its key number."
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bitfld.long 0x4 16.--18. "OWNER,Key Owner Selection Bits" "0: AES,1: HMAC,?,?,?,?,?,?"
hexmask.long.byte 0x4 8.--12. 1. "SIZE,Key Size Selection Bits"
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bitfld.long 0x4 4. "BS,Booting State Selection Bit" "0: Set key used at all state,1: Set key used at boot loader state 1 (BL1 state)"
bitfld.long 0x4 2. "READABLE,Key Readable Control Bit" "0: key is un-readable,1: key is readable"
line.long 0x8 "KS_STS,Key Store Status Register"
rbitfld.long 0x8 9. "KRVKF,Key Store Key Revoked Flag (read only)\nIf KSPLOCK(COFIG2[15:8]) is locked and mass erase occurs  Key Store will erase SRAM/Flash keys and revoke OTP keys at next initialization. When initialization is finished  KRVKF will be set forever." "0: All Keys have not been erased/revoked,1: All Keys have been erased/revoked"
rbitfld.long 0x8 8. "RAMINV,Key Store SRAM Invert Status (Read Only)" "0: Key Store key in SRAM is normal,1: Key Store key in SRAM is inverted"
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rbitfld.long 0x8 7. "INITDONE,Key Store Initialization Done Status (Read Only)" "0: Key Store is un-initialized,1: Key Store is initialized"
rbitfld.long 0x8 4. "FLASHFULL,Key Storage at Flash Full Status Bit (Read Only)" "0: Key Storage at Flash is not full,1: Key Storage at Flash is full"
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rbitfld.long 0x8 3. "SRAMFULL,Key Storage at SRAM Full Status Bit (Read Only)" "0: Key Storage at SRAM is not full,1: Key Storage at SRAM is full"
rbitfld.long 0x8 2. "BUSY,Key Store Busy Flag (read only)" "0: Key Store is idle or finished,1: Key Store is busy"
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bitfld.long 0x8 1. "EIF,Key Store Error Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0." "0: No Key Store error,1: Key Store error interrupt"
bitfld.long 0x8 0. "IF,Key Store Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0." "0: No Key Store interrupt,1: Key Store operation done interrupt"
rgroup.long 0xC++0x3
line.long 0x0 "KS_REMAIN,Key Store Remaining Space Register"
hexmask.long.word 0x0 16.--28. 1. "FRMNG,Key Store Flash Remaining Space\nThe FRMNG shows the remaining byte count space for Flash."
hexmask.long.word 0x0 0.--12. 1. "RRMNG,Key Store SRAM Remaining Space\nThe RRMNG shows the remaining byte count space for SRAM."
group.long 0x20++0x1F
line.long 0x0 "KS_KEY0,Key Store Entry Key Word 0 Register"
hexmask.long 0x0 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0x4 "KS_KEY1,Key Store Entry Key Word 1 Register"
hexmask.long 0x4 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0x8 "KS_KEY2,Key Store Entry Key Word 2 Register"
hexmask.long 0x8 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0xC "KS_KEY3,Key Store Entry Key Word 3 Register"
hexmask.long 0xC 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0x10 "KS_KEY4,Key Store Entry Key Word 4 Register"
hexmask.long 0x10 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0x14 "KS_KEY5,Key Store Entry Key Word 5 Register"
hexmask.long 0x14 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0x18 "KS_KEY6,Key Store Entry Key Word 6 Register"
hexmask.long 0x18 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
line.long 0x1C "KS_KEY7,Key Store Entry Key Word 7 Register"
hexmask.long 0x1C 0.--31. 1. "KEY,Key Data \nThe register will be cleared if the Key Store executes the write operation or CPU completes the reading key."
rgroup.long 0x40++0x7
line.long 0x0 "KS_OTPSTS,Key Store OTP Keys Status Register"
bitfld.long 0x0 7. "KEY7,OTP Key 7 Used Status" "0: OTP key 7 is unused,1: OTP key 7 is used"
bitfld.long 0x0 6. "KEY6,OTP Key 6 Used Status" "0: OTP key 6 is unused,1: OTP key 6 is used"
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bitfld.long 0x0 5. "KEY5,OTP Key 5 Used Status" "0: OTP key 5 is unused,1: OTP key 5 is used"
bitfld.long 0x0 4. "KEY4,OTP Key 4 Used Status" "0: OTP key 4 is unused,1: OTP key 4 is used"
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bitfld.long 0x0 3. "KEY3,OTP Key 3 Used Status" "0: OTP key 3 is unused,1: OTP key 3 is used"
bitfld.long 0x0 2. "KEY2,OTP Key 2 Used Status" "0: OTP key 2 is unused,1: OTP key 2 is used"
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bitfld.long 0x0 1. "KEY1,OTP Key 1 Used Status" "0: OTP key 1 is unused,1: OTP key 1 is used"
bitfld.long 0x0 0. "KEY0,OTP Key 0 Used Status" "0: OTP key 0 is unused,1: OTP key 0 is used"
line.long 0x4 "KS_REMKCNT,Key Store Remaining Key Count Register"
hexmask.long.byte 0x4 16.--21. 1. "FRMKCNT,Key Store Flash Remaining Key Count\nThe FRMKCNT shows the remaining key count for Flash."
hexmask.long.byte 0x4 0.--5. 1. "RRMKCNT,Key Store SRAM Remaining Key Count\nThe RRMKCNT shows the remaining key count for SRAM."
tree.end
tree "NMI (Non-maskable Interrupt)"
base ad:0x40000300
group.long 0x0++0x3
line.long 0x0 "NMIEN,NMI Source Interrupt Enable Register"
bitfld.long 0x0 15. "UART1INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
bitfld.long 0x0 14. "UART0INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
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bitfld.long 0x0 13. "EINT5,External Interrupt from INT5 Pins NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT5 pins NMI source..,1: External interrupt from INT5 pins NMI source.."
bitfld.long 0x0 12. "EINT4,External Interrupt from INT4 Pins NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT4 pins NMI source..,1: External interrupt from INT4 pins NMI source.."
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bitfld.long 0x0 11. "EINT3,External Interrupt from INT3 Pins NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT3 pins NMI source..,1: External interrupt from INT3 pins NMI source.."
bitfld.long 0x0 10. "EINT2,External Interrupt from INT2 Pins NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT2 pins NMI source..,1: External interrupt from INT2 pins NMI source.."
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bitfld.long 0x0 9. "EINT1,External Interrupt from INT1 Pins NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT1 pins NMI source..,1: External interrupt from INT1 pins NMI source.."
bitfld.long 0x0 8. "EINT0,External Interrupt from INT0 Pins NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT0 pins NMI source..,1: External interrupt from INT0 pins NMI source.."
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bitfld.long 0x0 7. "TAMPERINT,TAMPER NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Backup register tamper detected interrupt.NMI..,1: Backup register tamper detected interrupt.NMI.."
bitfld.long 0x0 6. "RTCINT,RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock fail detected interrupt NMI source Disabled,1: Clock fail detected interrupt NMI source Enabled"
bitfld.long 0x0 3. "SRAMPERR,SRAM Parity Check Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
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bitfld.long 0x0 2. "PWRWUINT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
bitfld.long 0x0 1. "IRCINT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
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bitfld.long 0x0 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
rgroup.long 0x4++0x3
line.long 0x0 "NMISTS,NMI Source Interrupt Status Register"
bitfld.long 0x0 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
bitfld.long 0x0 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
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bitfld.long 0x0 13. "EINT5,External Interrupt from INT5 Pins Interrupt Flag (Read Only)" "0: External Interrupt from INT5 interrupt is..,1: External Interrupt from INT5 interrupt is asserted"
bitfld.long 0x0 12. "EINT4,External Interrupt from INT4 Pins Interrupt Flag (Read Only)" "0: External Interrupt from INT4 interrupt is..,1: External Interrupt from INT4 interrupt is asserted"
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bitfld.long 0x0 11. "EINT3,External Interrupt from INT3 Pins Interrupt Flag (Read Only)" "0: External Interrupt from PD.0 interrupt is..,1: External Interrupt from PD.0 interrupt is asserted"
bitfld.long 0x0 10. "EINT2,External Interrupt from INT2 Pins Interrupt Flag (Read Only)" "0: External Interrupt from INT2 interrupt is..,1: External Interrupt from INT2 interrupt is asserted"
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bitfld.long 0x0 9. "EINT1,External Interrupt from INT1 Pins Interrupt Flag (Read Only)" "0: External Interrupt from INT1 interrupt is..,1: External Interrupt from INT1 interrupt is asserted"
bitfld.long 0x0 8. "EINT0,External Interrupt from INT0 Pins Interrupt Flag (Read Only)" "0: External Interrupt from INT0 interrupt is..,1: External Interrupt from INT0 interrupt is asserted"
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bitfld.long 0x0 7. "TAMPERINT,TAMPER Interrupt Flag (Read Only)" "0: Backup register tamper detected interrupt is..,1: Backup register tamper detected interrupt is.."
bitfld.long 0x0 6. "RTCINT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
bitfld.long 0x0 3. "SRAMPERR,SRAM Parity Check Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
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bitfld.long 0x0 2. "PWRWUINT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
bitfld.long 0x0 1. "IRCINT,IRC TRIM Interrupt Flag (Read Only)" "0: IRC TRIM interrupt is deasserted,1: IRC TRIM interrupt is asserted"
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bitfld.long 0x0 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
tree.end
tree "NVIC (Nested Vectored Interrupt Controller)"
base ad:0xE000E100
group.long 0x0++0xF
line.long 0x0 "NVIC_ISER0,IRQ0 ~ IRQ127 Set-enable Control Register"
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts  and show which interrupts are enabled\nWrite Operation:"
line.long 0x4 "NVIC_ISER1,IRQ0 ~ IRQ127 Set-enable Control Register"
hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts  and show which interrupts are enabled\nWrite Operation:"
line.long 0x8 "NVIC_ISER2,IRQ0 ~ IRQ127 Set-enable Control Register"
hexmask.long 0x8 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts  and show which interrupts are enabled\nWrite Operation:"
line.long 0xC "NVIC_ISER3,IRQ0 ~ IRQ127 Set-enable Control Register"
hexmask.long 0xC 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts  and show which interrupts are enabled\nWrite Operation:"
group.long 0x80++0xF
line.long 0x0 "NVIC_ICER0,IRQ0 ~ IRQ127 Clear-enable Control Register"
hexmask.long 0x0 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts  and show which interrupts are enabled.\nWrite Operation:"
line.long 0x4 "NVIC_ICER1,IRQ0 ~ IRQ127 Clear-enable Control Register"
hexmask.long 0x4 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts  and show which interrupts are enabled.\nWrite Operation:"
line.long 0x8 "NVIC_ICER2,IRQ0 ~ IRQ127 Clear-enable Control Register"
hexmask.long 0x8 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts  and show which interrupts are enabled.\nWrite Operation:"
line.long 0xC "NVIC_ICER3,IRQ0 ~ IRQ127 Clear-enable Control Register"
hexmask.long 0xC 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts  and show which interrupts are enabled.\nWrite Operation:"
group.long 0x100++0xF
line.long 0x0 "NVIC_ISPR0,IRQ0 ~ IRQ127 Set-pending Control Register"
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state  and show which interrupts are pending.\nWrite Operation:"
line.long 0x4 "NVIC_ISPR1,IRQ0 ~ IRQ127 Set-pending Control Register"
hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state  and show which interrupts are pending.\nWrite Operation:"
line.long 0x8 "NVIC_ISPR2,IRQ0 ~ IRQ127 Set-pending Control Register"
hexmask.long 0x8 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state  and show which interrupts are pending.\nWrite Operation:"
line.long 0xC "NVIC_ISPR3,IRQ0 ~ IRQ127 Set-pending Control Register"
hexmask.long 0xC 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state  and show which interrupts are pending.\nWrite Operation:"
group.long 0x180++0xF
line.long 0x0 "NVIC_ICPR0,IRQ0 ~ IRQ127 Clear-pending Control Register"
hexmask.long 0x0 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts  and show which interrupts are pending.\nWrite Operation:"
line.long 0x4 "NVIC_ICPR1,IRQ0 ~ IRQ127 Clear-pending Control Register"
hexmask.long 0x4 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts  and show which interrupts are pending.\nWrite Operation:"
line.long 0x8 "NVIC_ICPR2,IRQ0 ~ IRQ127 Clear-pending Control Register"
hexmask.long 0x8 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts  and show which interrupts are pending.\nWrite Operation:"
line.long 0xC "NVIC_ICPR3,IRQ0 ~ IRQ127 Clear-pending Control Register"
hexmask.long 0xC 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts  and show which interrupts are pending.\nWrite Operation:"
group.long 0x200++0xF
line.long 0x0 "NVIC_IABR0,IRQ0 ~ IRQ127 Active Bit Register"
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active."
line.long 0x4 "NVIC_IABR1,IRQ0 ~ IRQ127 Active Bit Register"
hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active."
line.long 0x8 "NVIC_IABR2,IRQ0 ~ IRQ127 Active Bit Register"
hexmask.long 0x8 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active."
line.long 0xC "NVIC_IABR3,IRQ0 ~ IRQ127 Active Bit Register"
hexmask.long 0xC 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active."
group.long 0x300++0x7F
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x0 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x0 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x0 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x0 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x4 "NVIC_IPR1,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x4 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x4 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x4 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x4 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x8 "NVIC_IPR2,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x8 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x8 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x8 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x8 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0xC "NVIC_IPR3,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0xC 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0xC 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0xC 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0xC 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x10 "NVIC_IPR4,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x10 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x10 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x10 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x10 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x14 "NVIC_IPR5,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x14 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x14 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x14 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x14 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x18 "NVIC_IPR6,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x18 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x18 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x18 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x18 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x1C "NVIC_IPR7,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x1C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x1C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x1C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x1C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x20 "NVIC_IPR8,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x20 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x20 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x20 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x20 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x24 "NVIC_IPR9,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x24 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x24 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x24 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x24 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x28 "NVIC_IPR10,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x28 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x28 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x28 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x28 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x2C "NVIC_IPR11,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x2C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x2C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x2C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x2C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x30 "NVIC_IPR12,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x30 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x30 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x30 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x30 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x34 "NVIC_IPR13,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x34 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x34 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x34 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x34 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x38 "NVIC_IPR14,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x38 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x38 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x38 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x38 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x3C "NVIC_IPR15,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x3C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x3C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x3C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x3C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x40 "NVIC_IPR16,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x40 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x40 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x40 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x40 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x44 "NVIC_IPR17,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x44 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x44 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x44 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x44 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x48 "NVIC_IPR18,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x48 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x48 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x48 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x48 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x4C "NVIC_IPR19,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x4C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x4C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x4C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x4C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x50 "NVIC_IPR20,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x50 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x50 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x50 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x50 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x54 "NVIC_IPR21,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x54 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x54 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x54 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x54 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x58 "NVIC_IPR22,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x58 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x58 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x58 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x58 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x5C "NVIC_IPR23,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x5C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x5C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x5C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x5C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x60 "NVIC_IPR24,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x60 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x60 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x60 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x60 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x64 "NVIC_IPR25,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x64 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x64 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x64 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x64 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x68 "NVIC_IPR26,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x68 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x68 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x68 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x68 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x6C "NVIC_IPR27,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x6C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x6C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x6C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x6C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x70 "NVIC_IPR28,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x70 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x70 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x70 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x70 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x74 "NVIC_IPR29,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x74 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x74 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x74 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x74 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x78 "NVIC_IPR30,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x78 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x78 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x78 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x78 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
line.long 0x7C "NVIC_IPR31,IRQ0 ~ IRQ127 Priority Control Register"
hexmask.long.byte 0x7C 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x7C 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x7C 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority"
hexmask.long.byte 0x7C 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority"
wgroup.long 0xE00++0x3
line.long 0x0 "STIR,Software Trigger Interrupt Registers"
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID (Write Only)\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the CCR is set to 1  unprivileged software can access the STIR.\nNumber of valid Interrupt ID refers to Table 6.29. For example  a.."
tree.end
tree "OTG (USB On-The-Go)"
base ad:0x4004D000
group.long 0x0++0xF
line.long 0x0 "OTG_CTL,OTG Control Register"
bitfld.long 0x0 5. "WKEN,OTG ID Pin Wake-up Enable Bit" "0: OTG ID pin status change wake-up function Disabled,1: OTG ID pin status change wake-up function Enabled"
bitfld.long 0x0 4. "OTGEN,OTG Function Enable Bit\nUser needs to set this bit to enable OTG function while the USB frame configured as OTG device. When the USB frame is not configured as OTG device  this bit must be low." "0: OTG function Disabled,1: OTG function Enabled"
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bitfld.long 0x0 2. "HNPREQEN,OTG HNP Request Enable Bit\nWhen the USB frame acts as A-device  set this bit when A-device allows to process HNP protocolA-device changes role from Host to Peripheral. This bit will be cleared when OTG state changes from a_suspend to.." "0: HNP request Disabled,1: HNP request Enabled (A-device can change role.."
bitfld.long 0x0 1. "BUSREQ,OTG Bus Request\nIf OTG A-device wants to do data transfers via USB bus  setting this bit will drive VBUS high to detect USB device connection. If user won't use the bus any more  clearing this bit will drop VBUS to save power. This bit will be.." "0: Not launch VBUS in OTG A-device or not request..,1: Launch VBUS in OTG A-device or request SRP in.."
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bitfld.long 0x0 0. "VBUSDROP,Drop VBUS Control\nIf user application running on this OTG A-device wants to conserve power  set this bit to drop VBUS. BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device." "0: Not drop the VBUS,1: Drop the VBUS"
line.long 0x4 "OTG_PHYCTL,OTG PHY Control Register"
bitfld.long 0x4 5. "VBSTSPOL,Off-chip USB VBUS Power Switch Status Polarity\nThe polarity of off-chip USB VBUS power switch valid signal depends on the selected component. A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch. Set this.." "0: The polarity of off-chip USB VBUS power switch..,1: The polarity of off-chip USB VBUS power switch.."
bitfld.long 0x4 4. "VBENPOL,Off-chip USB VBUS Power Switch Enable Polarity\nThe OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need. A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.\nThe polarity of enabling.." "0: The off-chip USB VBUS power switch enable is..,1: The off-chip USB VBUS power switch enable is.."
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bitfld.long 0x4 1. "IDDETEN,ID Detection Enable Bit" "0: Detect ID pin status Disabled,1: Detect ID pin status Enabled"
bitfld.long 0x4 0. "OTGPHYEN,OTG PHY Enable Bit\nWhen the USB frame is configured as either OTG device or ID dependent  user needs to set this bit before using OTG function. If device is configured as neither OTG device nor ID dependent  this bit is 'don't care'." "0: OTG PHY Disabled,1: OTG PHY Enabled"
line.long 0x8 "OTG_INTEN,OTG Interrupt Enable Register"
bitfld.long 0x8 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 10. "VBCHGIEN,VBUSVLD Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 9. "AVLDCHGIEN,A-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 8. "BVLDCHGIEN,B-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 7. "HOSTIEN,Act As Host Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a host  an interrupt will be asserted." "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
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bitfld.long 0x8 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a peripheral  an interrupt will be asserted." "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
bitfld.long 0x8 5. "IDCHGIEN,IDSTS Changed Interrupt Enable Bit\nIf this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high  an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 4. "GOIDLEIEN,OTG Device Going to IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state. Please refer to A-device state diagram and B-device state diagram in OTG specification." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 3. "HNPFIEN,HNP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 2. "SRPFIEN,SRP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x8 1. "VBEIEN,VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 0. "ROLECHGIEN,Role Changed Interrupt Enable Bit\nNote: Role is Host or Peripheral." "0: Interrupt Disabled,1: Interrupt Enabled"
line.long 0xC "OTG_INTSTS,OTG Interrupt Status Register"
bitfld.long 0xC 13. "SRPDETIF,SRP Detected Interrupt Status\nNote: Write 1 to clear this status." "0: SRP not detected,1: SRP detected"
bitfld.long 0xC 11. "SECHGIF,SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag." "0: SESSEND (OTG_STATUS[2]) not toggled,1: SESSEND (OTG_STATUS[2]) from high to low or from.."
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bitfld.long 0xC 10. "VBCHGIF,VBUSVLD State Change Interrupt Status\nNote: Write 1 to clear this status." "0: VBUSVLD (OTG_STATUS[5]) not toggled,1: VBUSVLD (OTG_STATUS[5]) from high to low or from.."
bitfld.long 0xC 9. "AVLDCHGIF,A-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status." "0: AVLD (OTG_STATUS[4]) not toggled,1: AVLD (OTG_STATUS[4]) from high to low or low to.."
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bitfld.long 0xC 8. "BVLDCHGIF,B-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status." "0: BVLD (OTG_STATUS[3]) not toggled,1: BVLD (OTG_STATUS[3]) from high to low or low to.."
bitfld.long 0xC 7. "HOSTIF,Act As Host Interrupt Status\nNote: Write 1 to clear this flag." "0: This device does not act as a host,1: This device acts as a host"
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bitfld.long 0xC 6. "PDEVIF,Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag." "0: This device does not act as a peripheral,1: This device acts as a peripheral"
bitfld.long 0xC 5. "IDCHGIF,ID State Change Interrupt Status\nNote: Write 1 to clear this flag." "0: IDSTS (OTG_STATUS[1]) not toggled,1: IDSTS (OTG_STATUS[1]) from high to low or from.."
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bitfld.long 0xC 4. "GOIDLEIF,OTG Device Goes to IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state. The OTG device will be neither a host nor a peripheral.\nNote 1: Going to idle state means going to a_idle or b_idle state." "0: OTG device does not go back to idle state..,1: Going to idle state means going to a_idle or.."
bitfld.long 0xC 3. "HNPFIF,HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state  this bit will be set when A-device does not connect after specified interval expires. \nNote: Write 1 to clear this.." "0: A-device connects to B-device before specified..,1: A-device does not connect to B-device before.."
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bitfld.long 0xC 2. "SRPFIF,SRP Fail Interrupt Status\nAfter initiating SRP  an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum  defined in OTG specification. This flag is set when the OTG B-device does not get VBUS high after this.." "0: OTG B-device gets VBUS high before this interval,1: OTG B-device does not get VBUS high before this.."
bitfld.long 0xC 1. "VBEIF,VBUS Error Interrupt Status\nThis bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. \nNote: Write 1 to clear this flag and recover from.." "0: OTG A-device drives VBUS over threshold voltage..,1: OTG A-device cannot drive VBUS over threshold.."
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bitfld.long 0xC 0. "ROLECHGIF,OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral  or changed from a peripheral to a host while USB_ID pin status does not change.\nNote: Write 1 to clear this flag." "0: OTG device role not changed,1: OTG device role changed"
rgroup.long 0x10++0x3
line.long 0x0 "OTG_STATUS,OTG Status Register"
bitfld.long 0x0 7. "ASHOST,As Host Status\nWhen OTG acts as Host  this bit is set." "0: OTG not as Host,1: OTG as Host"
bitfld.long 0x0 6. "ASPERI,As Peripheral Status\nWhen OTG acts as peripheral  this bit is set." "0: OTG not as peripheral,1: OTG as peripheral"
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bitfld.long 0x0 5. "VBUSVLD,VBUS Valid Status\nWhen VBUS is larger than 4.7V  this bit will be set to 1." "0: VBUS is not valid,1: VBUS is valid"
bitfld.long 0x0 4. "AVLD,A-Device Session Valid Status" "0: A-device session is not valid,1: A-device session is valid"
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bitfld.long 0x0 3. "BVLD,B-device Session Valid Status" "0: B-device session is not valid,1: B-device session is valid"
bitfld.long 0x0 2. "SESSEND,Session End Status\nWhen VBUS voltage is lower than 0.4V  this bit will be set to 1. Session end means no meaningful power on VBUS." "0: Session is not end,1: Session is end"
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bitfld.long 0x0 1. "IDSTS,USB_ID Pin State of Mini-/Micro-Plug" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
bitfld.long 0x0 0. "OVERCUR,Overcurrent Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold  4.4V minimum  within a maximum time of 100ms after OTG A-device drives VBUS high." "0: OTG A-device drives VBUS successfully,1: OTG A-device cannot drives VBUS high in this.."
tree.end
tree "PDMA (Peripheral Direct Memory Access)"
base ad:0x0
tree "PDMA0"
base ad:0x40008000
group.long 0x0++0x3
line.long 0x0 "PDMAx_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x10++0x3
line.long 0x0 "PDMAx_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x20++0x3
line.long 0x0 "PDMAx_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x30++0x3
line.long 0x0 "PDMAx_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x40++0x3
line.long 0x0 "PDMAx_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x50++0x3
line.long 0x0 "PDMAx_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x60++0x3
line.long 0x0 "PDMAx_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x70++0x3
line.long 0x0 "PDMAx_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x80++0x3
line.long 0x0 "PDMAx_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x90++0x3
line.long 0x0 "PDMAx_DSCT9_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xA0++0x3
line.long 0x0 "PDMAx_DSCT10_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xB0++0x3
line.long 0x0 "PDMAx_DSCT11_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xC0++0x3
line.long 0x0 "PDMAx_DSCT12_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
newline
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
newline
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
newline
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xD0++0x3
line.long 0x0 "PDMAx_DSCT13_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
newline
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
newline
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
newline
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xE0++0x3
line.long 0x0 "PDMAx_DSCT14_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
newline
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
newline
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
newline
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
newline
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xF0++0x3
line.long 0x0 "PDMAx_DSCT15_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
newline
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
newline
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
newline
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x4++0x3
line.long 0x0 "PDMAx_DSCT0_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x14++0x3
line.long 0x0 "PDMAx_DSCT1_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x24++0x3
line.long 0x0 "PDMAx_DSCT2_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x34++0x3
line.long 0x0 "PDMAx_DSCT3_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x44++0x3
line.long 0x0 "PDMAx_DSCT4_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x54++0x3
line.long 0x0 "PDMAx_DSCT5_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x64++0x3
line.long 0x0 "PDMAx_DSCT6_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x74++0x3
line.long 0x0 "PDMAx_DSCT7_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x84++0x3
line.long 0x0 "PDMAx_DSCT8_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x94++0x3
line.long 0x0 "PDMAx_DSCT9_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xA4++0x3
line.long 0x0 "PDMAx_DSCT10_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xB4++0x3
line.long 0x0 "PDMAx_DSCT11_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xC4++0x3
line.long 0x0 "PDMAx_DSCT12_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xD4++0x3
line.long 0x0 "PDMAx_DSCT13_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xE4++0x3
line.long 0x0 "PDMAx_DSCT14_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xF4++0x3
line.long 0x0 "PDMAx_DSCT15_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x8++0x3
line.long 0x0 "PDMAx_DSCT0_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x18++0x3
line.long 0x0 "PDMAx_DSCT1_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x28++0x3
line.long 0x0 "PDMAx_DSCT2_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x38++0x3
line.long 0x0 "PDMAx_DSCT3_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x48++0x3
line.long 0x0 "PDMAx_DSCT4_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x58++0x3
line.long 0x0 "PDMAx_DSCT5_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x68++0x3
line.long 0x0 "PDMAx_DSCT6_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x78++0x3
line.long 0x0 "PDMAx_DSCT7_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x88++0x3
line.long 0x0 "PDMAx_DSCT8_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x98++0x3
line.long 0x0 "PDMAx_DSCT9_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xA8++0x3
line.long 0x0 "PDMAx_DSCT10_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xB8++0x3
line.long 0x0 "PDMAx_DSCT11_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xC8++0x3
line.long 0x0 "PDMAx_DSCT12_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xD8++0x3
line.long 0x0 "PDMAx_DSCT13_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xE8++0x3
line.long 0x0 "PDMAx_DSCT14_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xF8++0x3
line.long 0x0 "PDMAx_DSCT15_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xC++0x3
line.long 0x0 "PDMAx_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x1C++0x3
line.long 0x0 "PDMAx_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x2C++0x3
line.long 0x0 "PDMAx_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x3C++0x3
line.long 0x0 "PDMAx_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x4C++0x3
line.long 0x0 "PDMAx_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x5C++0x3
line.long 0x0 "PDMAx_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x6C++0x3
line.long 0x0 "PDMAx_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x7C++0x3
line.long 0x0 "PDMAx_DSCT7_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x8C++0x3
line.long 0x0 "PDMAx_DSCT8_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x9C++0x3
line.long 0x0 "PDMAx_DSCT9_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xAC++0x3
line.long 0x0 "PDMAx_DSCT10_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xBC++0x3
line.long 0x0 "PDMAx_DSCT11_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xCC++0x3
line.long 0x0 "PDMAx_DSCT12_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xDC++0x3
line.long 0x0 "PDMAx_DSCT13_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xEC++0x3
line.long 0x0 "PDMAx_DSCT14_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xFC++0x3
line.long 0x0 "PDMAx_DSCT15_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
rgroup.long 0x80++0x3F
line.long 0x0 "PDMAx_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x4 "PDMAx_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x4 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x8 "PDMAx_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x8 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0xC "PDMAx_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0xC 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x10 "PDMAx_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x10 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x14 "PDMAx_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x14 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x18 "PDMAx_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x18 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x1C "PDMAx_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x1C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x20 "PDMAx_CURSCAT8,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x20 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x24 "PDMAx_CURSCAT9,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x24 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x28 "PDMAx_CURSCAT10,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x28 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x2C "PDMAx_CURSCAT11,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x2C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x30 "PDMAx_CURSCAT12,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x30 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x34 "PDMAx_CURSCAT13,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x34 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x38 "PDMAx_CURSCAT14,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x38 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x3C "PDMAx_CURSCAT15,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x3C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
group.long 0x400++0x3
line.long 0x0 "PDMAx_CHCTL,PDMA Channel Control Register"
bitfld.long 0x0 15. "CHEN15,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 14. "CHEN14,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 13. "CHEN13,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 12. "CHEN12,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 11. "CHEN11,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 10. "CHEN10,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 9. "CHEN9,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 8. "CHEN8,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 7. "CHEN7,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
wgroup.long 0x404++0x7
line.long 0x0 "PDMAx_PAUSE,PDMA Transfer Pause Control Register"
bitfld.long 0x0 15. "PAUSE15,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 14. "PAUSE14,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 13. "PAUSE13,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 12. "PAUSE12,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 11. "PAUSE11,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 10. "PAUSE10,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 9. "PAUSE9,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 8. "PAUSE8,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 7. "PAUSE7,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 6. "PAUSE6,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 5. "PAUSE5,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
line.long 0x4 "PDMAx_SWREQ,PDMA Software Request Register"
bitfld.long 0x4 15. "SWREQ15,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 14. "SWREQ14,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 13. "SWREQ13,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 12. "SWREQ12,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 11. "SWREQ11,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 10. "SWREQ10,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 9. "SWREQ9,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 8. "SWREQ8,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 7. "SWREQ7,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
rgroup.long 0x40C++0x3
line.long 0x0 "PDMAx_TRGSTS,PDMA Channel Request Status Register"
bitfld.long 0x0 15. "REQSTS15,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 14. "REQSTS14,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 13. "REQSTS13,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 12. "REQSTS12,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 11. "REQSTS11,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 10. "REQSTS10,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 9. "REQSTS9,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 8. "REQSTS8,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 7. "REQSTS7,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
group.long 0x410++0x3
line.long 0x0 "PDMAx_PRISET,PDMA Fixed Priority Setting Register"
bitfld.long 0x0 15. "FPRISET15,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 14. "FPRISET14,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 13. "FPRISET13,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 12. "FPRISET12,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 11. "FPRISET11,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 10. "FPRISET10,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 9. "FPRISET9,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 8. "FPRISET8,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 7. "FPRISET7,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
wgroup.long 0x414++0x3
line.long 0x0 "PDMAx_PRICLR,PDMA Fixed Priority Clear Register"
bitfld.long 0x0 15. "FPRICLR15,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 14. "FPRICLR14,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 13. "FPRICLR13,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 12. "FPRICLR12,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 11. "FPRICLR11,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 10. "FPRICLR10,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 9. "FPRICLR9,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 8. "FPRICLR8,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 7. "FPRICLR7,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
group.long 0x418++0x13
line.long 0x0 "PDMAx_INTEN,PDMA Interrupt Enable Register"
bitfld.long 0x0 15. "INTEN15,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 14. "INTEN14,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 13. "INTEN13,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 12. "INTEN12,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 11. "INTEN11,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 10. "INTEN10,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 9. "INTEN9,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 8. "INTEN8,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 7. "INTEN7,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 6. "INTEN6,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
line.long 0x4 "PDMAx_INTSTS,PDMA Interrupt Status Register"
bitfld.long 0x4 23. "REQTOF15,Request Time-out Flag for Channel 15\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC15(PDMA_TOC15_14[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 22. "REQTOF14,Request Time-out Flag for Channel 14\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC14(PDMA_TOC15_14[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 21. "REQTOF13,Request Time-out Flag for Channel 13\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC13(PDMA_TOC13_12[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 20. "REQTOF12,Request Time-out Flag for Channel 12\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC12(PDMA_TOC13_12[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 19. "REQTOF11,Request Time-out Flag for Channel 11\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC11(PDMA_TOC10_11[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 18. "REQTOF10,Request Time-out Flag for Channel 10\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC10(PDMA_TOC10_11[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 17. "REQTOF9,Request Time-out Flag for Channel 9\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC9(PDMA_TOC8_9[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 16. "REQTOF8,Request Time-out Flag for Channel 8\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC8(PDMA_TOC8_9[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 15. "REQTOF7,Request Time-out Flag for Channel 7\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC7(PDMA_TOC6_7[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 14. "REQTOF6,Request Time-out Flag for Channel 6\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC6(PDMA_TOC6_7[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 13. "REQTOF5,Request Time-out Flag for Channel 5\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC5(PDMA_TOC4_5[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 12. "REQTOF4,Request Time-out Flag for Channel 4\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC4(PDMA_TOC4_5[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 11. "REQTOF3,Request Time-out Flag for Channel 3\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC3(PDMA_TOC2_3[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 10. "REQTOF2,Request Time-out Flag for Channel 2\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC2(PDMA_TOC2_3[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC1(PDMA_TOC0_1[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC0(PDMA_TOC0_1[15:0].\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit will.." "0: No request time-out,1: Please disable time-out function before clearing.."
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rbitfld.long 0x4 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
line.long 0x8 "PDMAx_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
bitfld.long 0x8 15. "ABTIF15,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 14. "ABTIF14,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 13. "ABTIF13,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 12. "ABTIF12,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 11. "ABTIF11,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 10. "ABTIF10,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 9. "ABTIF9,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 8. "ABTIF8,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 7. "ABTIF7,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
line.long 0xC "PDMAx_TDSTS,PDMA Channel Transfer Done Flag Register"
bitfld.long 0xC 15. "TDIF15,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 14. "TDIF14,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 13. "TDIF13,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 12. "TDIF12,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 11. "TDIF11,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 10. "TDIF10,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 9. "TDIF9,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 8. "TDIF8,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 7. "TDIF7,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 6. "TDIF6,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
line.long 0x10 "PDMAx_ALIGN,PDMA Transfer Alignment Status Register"
bitfld.long 0x10 15. "ALIGN15,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 14. "ALIGN14,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 13. "ALIGN13,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 12. "ALIGN12,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 11. "ALIGN11,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 10. "ALIGN10,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 9. "ALIGN9,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 8. "ALIGN8,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 7. "ALIGN7,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 6. "ALIGN6,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 5. "ALIGN5,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 4. "ALIGN4,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
rgroup.long 0x42C++0x3
line.long 0x0 "PDMAx_TACTSTS,PDMA Transfer Active Flag Register"
bitfld.long 0x0 15. "TXACTF15,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 14. "TXACTF14,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 13. "TXACTF13,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 12. "TXACTF12,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 11. "TXACTF11,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 10. "TXACTF10,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 9. "TXACTF9,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 8. "TXACTF8,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 7. "TXACTF7,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
group.long 0x430++0x33
line.long 0x0 "PDMAx_TOUTPSC0_7,PDMA Time-out Prescaler Register(CH0 to CH7)"
bitfld.long 0x0 28.--30. "TOUTPSC7,PDMA Channel 7 Time-out Clock Source Prescaler Bits" "0: PDMA channel 7 time-out clock source is HCLK/28,1: PDMA channel 7 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "TOUTPSC6,PDMA Channel 6 Time-out Clock Source Prescaler Bits" "0: PDMA channel 6 time-out clock source is HCLK/28,1: PDMA channel 6 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "TOUTPSC5,PDMA Channel 5 Time-out Clock Source Prescaler Bits" "0: PDMA channel 5 time-out clock source is HCLK/28,1: PDMA channel 5 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "TOUTPSC4,PDMA Channel 4 Time-out Clock Source Prescaler Bits" "0: PDMA channel 4 time-out clock source is HCLK/28,1: PDMA channel 4 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "TOUTPSC3,PDMA Channel 3 Time-out Clock Source Prescaler Bits" "0: PDMA channel 3 time-out clock source is HCLK/28,1: PDMA channel 3 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "TOUTPSC2,PDMA Channel 2 Time-out Clock Source Prescaler Bits" "0: PDMA channel 2 time-out clock source is HCLK/28,1: PDMA channel 2 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,?,?,?,?,?,?"
line.long 0x4 "PDMAx_TOUTEN,PDMA Time-out Enable Register"
bitfld.long 0x4 15. "TOUTEN15,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 14. "TOUTEN14,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 13. "TOUTEN13,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 12. "TOUTEN12,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 11. "TOUTEN11,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 10. "TOUTEN10,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 9. "TOUTEN9,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 8. "TOUTEN8,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 7. "TOUTEN7,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 6. "TOUTEN6,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 5. "TOUTEN5,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 4. "TOUTEN4,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 3. "TOUTEN3,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 2. "TOUTEN2,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
line.long 0x8 "PDMAx_TOUTIEN,PDMA Time-out Interrupt Enable Register"
bitfld.long 0x8 15. "TOUTIEN15,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 14. "TOUTIEN14,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 13. "TOUTIEN13,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 12. "TOUTIEN12,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 11. "TOUTIEN11,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 10. "TOUTIEN10,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 9. "TOUTIEN9,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 8. "TOUTIEN8,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 7. "TOUTIEN7,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 6. "TOUTIEN6,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 5. "TOUTIEN5,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 4. "TOUTIEN4,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 3. "TOUTIEN3,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 2. "TOUTIEN2,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
line.long 0xC "PDMAx_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
hexmask.long.word 0xC 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode  this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode."
line.long 0x10 "PDMAx_TOC0_1,PDMA Time-out Counter Ch0 and Ch1 Register"
hexmask.long.word 0x10 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC0_7[6:4]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x10 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC0_7[2:0]) clock."
line.long 0x14 "PDMAx_TOC2_3,PDMA Time-out Counter Ch2 and Ch3 Register"
hexmask.long.word 0x14 16.--31. 1. "TOC3,Time-out Counter for Channel 3\nThis controls the period of time-out function for channel 3. The calculation unit is based on TOUTPSC3 (PDMA_TOUTPSC0_7[14:12]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x14 0.--15. 1. "TOC2,Time-out Counter for Channel 2\nThis controls the period of time-out function for channel 2. The calculation unit is based on TOUTPSC2 (PDMA_TOUTPSC0_7[10:8]) clock."
line.long 0x18 "PDMAx_TOC4_5,PDMA Time-out Counter Ch4 and Ch5 Register"
hexmask.long.word 0x18 16.--31. 1. "TOC5,Time-out Counter for Channel 5\nThis controls the period of time-out function for channel 5. The calculation unit is based on TOUTPSC5 (PDMA_TOUTPSC0_7[22:20]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x18 0.--15. 1. "TOC4,Time-out Counter for Channel 4\nThis controls the period of time-out function for channel 4. The calculation unit is based on TOUTPSC4 (PDMA_TOUTPSC0_7[18:16]) clock."
line.long 0x1C "PDMAx_TOC6_7,PDMA Time-out Counter Ch6 and Ch7 Register"
hexmask.long.word 0x1C 16.--31. 1. "TOC7,Time-out Counter for Channel 7\nThis controls the period of time-out function for channel 7. The calculation unit is based on TOUTPSC7 (PDMA_TOUTPSC0_7[30:28]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x1C 0.--15. 1. "TOC6,Time-out Counter for Channel 6\nThis controls the period of time-out function for channel 6. The calculation unit is based on TOUTPSC6 (PDMA_TOUTPSC0_7[26:24]) clock."
line.long 0x20 "PDMAx_TOC8_9,PDMA Time-out Counter Ch8 and Ch9 Register"
hexmask.long.word 0x20 16.--31. 1. "TOC9,Time-out Counter for Channel 9\nThis controls the period of time-out function for channel 9. The calculation unit is based on TOUTPSC9 (PDMA_TOUTPSC8_15[6:4]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x20 0.--15. 1. "TOC8,Time-out Counter for Channel 8\nThis controls the period of time-out function for channel 8. The calculation unit is based on TOUTPSC8 (PDMA_TOUTPSC8_15[2:0]) clock."
line.long 0x24 "PDMAx_TOC10_11,PDMA Time-out Counter Ch10 and Ch11 Register"
hexmask.long.word 0x24 16.--31. 1. "TOC11,Time-out Counter for Channel 11\nThis controls the period of time-out function for channel 11. The calculation unit is based on TOUTPSC11 (PDMA_TOUTPSC8_15[14:12]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x24 0.--15. 1. "TOC10,Time-out Counter for Channel 10\nThis controls the period of time-out function for channel 10. The calculation unit is based on TOUTPSC10 (PDMA_TOUTPSC8_15[10:8]) clock."
line.long 0x28 "PDMAx_TOC12_13,PDMA Time-out Counter Ch12 and Ch13 Register"
hexmask.long.word 0x28 16.--31. 1. "TOC13,Time-out Counter for Channel 13\nThis controls the period of time-out function for channel 13. The calculation unit is based on TOUTPSC13 (PDMA_TOUTPSC8_15[22:20]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x28 0.--15. 1. "TOC12,Time-out Counter for Channel 12\nThis controls the period of time-out function for channel 12. The calculation unit is based on TOUTPSC12 (PDMA_TOUTPSC8_15[18:16]) clock."
line.long 0x2C "PDMAx_TOC14_15,PDMA Time-out Counter Ch14 and Ch15 Register"
hexmask.long.word 0x2C 16.--31. 1. "TOC15,Time-out Counter for Channel 15\nThis controls the period of time-out function for channel 15. The calculation unit is based on TOUTPSC15 (PDMA_TOUTPSC8_15[30:28]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x2C 0.--15. 1. "TOC14,Time-out Counter for Channel 14\nThis controls the period of time-out function for channel 14. The calculation unit is based on TOUTPSC14 (PDMA_TOUTPSC8_15[26:24]) clock."
line.long 0x30 "PDMAx_CHRST,PDMA Channel Reset Register"
bitfld.long 0x30 15. "CH15RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 14. "CH14RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 13. "CH13RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 12. "CH12RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 11. "CH11RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 10. "CH10RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 9. "CH9RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 8. "CH8RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 7. "CH7RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 6. "CH6RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 5. "CH5RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 4. "CH4RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 3. "CH3RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 2. "CH2RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 1. "CH1RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 0. "CH0RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
group.long 0x468++0x3
line.long 0x0 "PDMAx_TOUTPSC8_15,PDMA Time-out Prescaler Register(CH8 to CH15)"
bitfld.long 0x0 28.--30. "TOUTPSC15,PDMA Channel 15 Time-out Clock Source Prescaler Bits" "0: PDMA channel 15 time-out clock source is HCLK/28,1: PDMA channel 15 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "TOUTPSC14,PDMA Channel 14 Time-out Clock Source Prescaler Bits" "0: PDMA channel 14 time-out clock source is HCLK/28,1: PDMA channel 14 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "TOUTPSC13,PDMA Channel 13 Time-out Clock Source Prescaler Bits" "0: PDMA channel 13 time-out clock source is HCLK/28,1: PDMA channel 13 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "TOUTPSC12,PDMA Channel 12 Time-out Clock Source Prescaler Bits" "0: PDMA channel 12 time-out clock source is HCLK/28,1: PDMA channel 12 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "TOUTPSC11,PDMA Channel 11 Time-out Clock Source Prescaler Bits" "0: PDMA channel 11 time-out clock source is HCLK/28,1: PDMA channel 11 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "TOUTPSC10,PDMA Channel 10 Time-out Clock Source Prescaler Bits" "0: PDMA channel 10 time-out clock source is HCLK/28,1: PDMA channel 10 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "TOUTPSC9,PDMA Channel 9 Time-out Clock Source Prescaler Bits" "0: PDMA channel 9 time-out clock source is HCLK/28,1: PDMA channel 9 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "TOUTPSC8,PDMA Channel 8 Time-out Clock Source Prescaler Bits" "0: PDMA channel 8 time-out clock source is HCLK/28,1: PDMA channel 8 time-out clock source is HCLK/29,?,?,?,?,?,?"
group.long 0x480++0xF
line.long 0x0 "PDMAx_REQSEL0_3,PDMA Request Source Select Register 0"
hexmask.long.byte 0x0 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x0 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x0 0.--6. 1. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This.."
line.long 0x4 "PDMAx_REQSEL4_7,PDMA Request Source Select Register 1"
hexmask.long.byte 0x4 24.--30. 1. "REQSRC7,Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x4 16.--22. 1. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 8.--14. 1. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x4 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
line.long 0x8 "PDMAx_REQSEL8_11,PDMA Request Source Select Register 2"
hexmask.long.byte 0x8 24.--30. 1. "REQSRC11,Channel 11 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 11. User can configure the peripheral setting by REQSRC11. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x8 16.--22. 1. "REQSRC10,Channel 10 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x8 8.--14. 1. "REQSRC9,Channel 9 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x8 0.--6. 1. "REQSRC8,Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
line.long 0xC "PDMAx_REQSEL12_15,PDMA Request Source Select Register 3"
hexmask.long.byte 0xC 24.--30. 1. "REQSRC15,Channel 15 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 15. User can configure the peripheral setting by REQSRC15. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0xC 16.--22. 1. "REQSRC14,Channel 14 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 14. User can configure the peripheral setting by REQSRC14. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0xC 8.--14. 1. "REQSRC13,Channel 13 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 13. User can configure the peripheral setting by REQSRC13. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0xC 0.--6. 1. "REQSRC12,Channel 12 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 12. User can configure the peripheral setting by REQSRC12. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
group.long 0x500++0x2F
line.long 0x0 "PDMAx_STCR0,Stride Transfer Count Register of PDMA Channel 0"
hexmask.long.word 0x0 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x4 "PDMAx_ASOCR0,Address Stride Offset Register of PDMA Channel 0"
hexmask.long.word 0x4 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x4 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x8 "PDMAx_STCR1,Stride Transfer Count Register of PDMA Channel 1"
hexmask.long.word 0x8 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0xC "PDMAx_ASOCR1,Address Stride Offset Register of PDMA Channel 1"
hexmask.long.word 0xC 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0xC 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x10 "PDMAx_STCR2,Stride Transfer Count Register of PDMA Channel 2"
hexmask.long.word 0x10 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x14 "PDMAx_ASOCR2,Address Stride Offset Register of PDMA Channel 2"
hexmask.long.word 0x14 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x14 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x18 "PDMAx_STCR3,Stride Transfer Count Register of PDMA Channel 3"
hexmask.long.word 0x18 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x1C "PDMAx_ASOCR3,Address Stride Offset Register of PDMA Channel 3"
hexmask.long.word 0x1C 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x1C 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x20 "PDMAx_STCR4,Stride Transfer Count Register of PDMA Channel 4"
hexmask.long.word 0x20 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x24 "PDMAx_ASOCR4,Address Stride Offset Register of PDMA Channel 4"
hexmask.long.word 0x24 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x24 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x28 "PDMAx_STCR5,Stride Transfer Count Register of PDMA Channel 5"
hexmask.long.word 0x28 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x2C "PDMAx_ASOCR5,Address Stride Offset Register of PDMA Channel 5"
hexmask.long.word 0x2C 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x2C 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
group.long 0x600++0xF
line.long 0x0 "PDMAx_AICTL0,Address Interval Control Register of PDMA Channel 0"
hexmask.long.word 0x0 16.--31. 1. "DAICNT,PDMA Destination Address Interval Count\nThe 16-bit register defines the destination address interval count of each row."
hexmask.long.word 0x0 0.--15. 1. "SAICNT,PDMA Source Address Interval Count\nThe 16-bit register defines the source address interval count of each row."
line.long 0x4 "PDMAx_RCNT0,Repeat Count Register of PDMA Channel 0"
hexmask.long.word 0x4 0.--15. 1. "RCNT,PDMA Repeat Count\nThe 16-bit register defines the repeat times of block transfer."
line.long 0x8 "PDMAx_AICTL1,Address Interval Control Register of PDMA Channel 1"
hexmask.long.word 0x8 16.--31. 1. "DAICNT,PDMA Destination Address Interval Count\nThe 16-bit register defines the destination address interval count of each row."
hexmask.long.word 0x8 0.--15. 1. "SAICNT,PDMA Source Address Interval Count\nThe 16-bit register defines the source address interval count of each row."
line.long 0xC "PDMAx_RCNT1,Repeat Count Register of PDMA Channel 1"
hexmask.long.word 0xC 0.--15. 1. "RCNT,PDMA Repeat Count\nThe 16-bit register defines the repeat times of block transfer."
tree.end
tree "PDMA1"
base ad:0x40018000
group.long 0x0++0x3
line.long 0x0 "PDMAx_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x10++0x3
line.long 0x0 "PDMAx_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x20++0x3
line.long 0x0 "PDMAx_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x30++0x3
line.long 0x0 "PDMAx_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x40++0x3
line.long 0x0 "PDMAx_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x50++0x3
line.long 0x0 "PDMAx_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x60++0x3
line.long 0x0 "PDMAx_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x70++0x3
line.long 0x0 "PDMAx_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x80++0x3
line.long 0x0 "PDMAx_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x90++0x3
line.long 0x0 "PDMAx_DSCT9_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xA0++0x3
line.long 0x0 "PDMAx_DSCT10_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xB0++0x3
line.long 0x0 "PDMAx_DSCT11_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xC0++0x3
line.long 0x0 "PDMAx_DSCT12_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xD0++0x3
line.long 0x0 "PDMAx_DSCT13_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xE0++0x3
line.long 0x0 "PDMAx_DSCT14_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0xF0++0x3
line.long 0x0 "PDMAx_DSCT15_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer  the real transfer count is (TXCNT + 1); The maximum transfer count is 65536  every transfer may be byte  half-word or word that is dependent on TXWIDTH field.\nNote: When.."
bitfld.long 0x0 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table  user must check the PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
group.long 0x4++0x3
line.long 0x0 "PDMAx_DSCT0_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x14++0x3
line.long 0x0 "PDMAx_DSCT1_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x24++0x3
line.long 0x0 "PDMAx_DSCT2_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x34++0x3
line.long 0x0 "PDMAx_DSCT3_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x44++0x3
line.long 0x0 "PDMAx_DSCT4_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x54++0x3
line.long 0x0 "PDMAx_DSCT5_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x64++0x3
line.long 0x0 "PDMAx_DSCT6_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x74++0x3
line.long 0x0 "PDMAx_DSCT7_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x84++0x3
line.long 0x0 "PDMAx_DSCT8_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x94++0x3
line.long 0x0 "PDMAx_DSCT9_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xA4++0x3
line.long 0x0 "PDMAx_DSCT10_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xB4++0x3
line.long 0x0 "PDMAx_DSCT11_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xC4++0x3
line.long 0x0 "PDMAx_DSCT12_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xD4++0x3
line.long 0x0 "PDMAx_DSCT13_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xE4++0x3
line.long 0x0 "PDMAx_DSCT14_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0xF4++0x3
line.long 0x0 "PDMAx_DSCT15_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
group.long 0x8++0x3
line.long 0x0 "PDMAx_DSCT0_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x18++0x3
line.long 0x0 "PDMAx_DSCT1_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x28++0x3
line.long 0x0 "PDMAx_DSCT2_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x38++0x3
line.long 0x0 "PDMAx_DSCT3_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x48++0x3
line.long 0x0 "PDMAx_DSCT4_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x58++0x3
line.long 0x0 "PDMAx_DSCT5_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x68++0x3
line.long 0x0 "PDMAx_DSCT6_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x78++0x3
line.long 0x0 "PDMAx_DSCT7_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x88++0x3
line.long 0x0 "PDMAx_DSCT8_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0x98++0x3
line.long 0x0 "PDMAx_DSCT9_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xA8++0x3
line.long 0x0 "PDMAx_DSCT10_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xB8++0x3
line.long 0x0 "PDMAx_DSCT11_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xC8++0x3
line.long 0x0 "PDMAx_DSCT12_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xD8++0x3
line.long 0x0 "PDMAx_DSCT13_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xE8++0x3
line.long 0x0 "PDMAx_DSCT14_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xF8++0x3
line.long 0x0 "PDMAx_DSCT15_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
group.long 0xC++0x3
line.long 0x0 "PDMAx_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x1C++0x3
line.long 0x0 "PDMAx_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x2C++0x3
line.long 0x0 "PDMAx_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x3C++0x3
line.long 0x0 "PDMAx_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x4C++0x3
line.long 0x0 "PDMAx_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x5C++0x3
line.long 0x0 "PDMAx_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x6C++0x3
line.long 0x0 "PDMAx_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x7C++0x3
line.long 0x0 "PDMAx_DSCT7_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x8C++0x3
line.long 0x0 "PDMAx_DSCT8_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0x9C++0x3
line.long 0x0 "PDMAx_DSCT9_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xAC++0x3
line.long 0x0 "PDMAx_DSCT10_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xBC++0x3
line.long 0x0 "PDMAx_DSCT11_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xCC++0x3
line.long 0x0 "PDMAx_DSCT12_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xDC++0x3
line.long 0x0 "PDMAx_DSCT13_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xEC++0x3
line.long 0x0 "PDMAx_DSCT14_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
group.long 0xFC++0x3
line.long 0x0 "PDMAx_DSCT15_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA)  and the next descriptor table is start.."
rgroup.long 0x80++0x3F
line.long 0x0 "PDMAx_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x4 "PDMAx_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x4 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x8 "PDMAx_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x8 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0xC "PDMAx_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0xC 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x10 "PDMAx_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x10 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x14 "PDMAx_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x14 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x18 "PDMAx_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x18 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x1C "PDMAx_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x1C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x20 "PDMAx_CURSCAT8,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x20 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x24 "PDMAx_CURSCAT9,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x24 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x28 "PDMAx_CURSCAT10,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x28 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x2C "PDMAx_CURSCAT11,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x2C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x30 "PDMAx_CURSCAT12,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x30 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x34 "PDMAx_CURSCAT13,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x34 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x38 "PDMAx_CURSCAT14,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x38 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
line.long 0x3C "PDMAx_CURSCAT15,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x3C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
group.long 0x400++0x3
line.long 0x0 "PDMAx_CHCTL,PDMA Channel Control Register"
bitfld.long 0x0 15. "CHEN15,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 14. "CHEN14,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
newline
bitfld.long 0x0 13. "CHEN13,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 12. "CHEN12,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
newline
bitfld.long 0x0 11. "CHEN11,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 10. "CHEN10,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
newline
bitfld.long 0x0 9. "CHEN9,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 8. "CHEN8,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
newline
bitfld.long 0x0 7. "CHEN7,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x0 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x0 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
wgroup.long 0x404++0x7
line.long 0x0 "PDMAx_PAUSE,PDMA Transfer Pause Control Register"
bitfld.long 0x0 15. "PAUSE15,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 14. "PAUSE14,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 13. "PAUSE13,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 12. "PAUSE12,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 11. "PAUSE11,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 10. "PAUSE10,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 9. "PAUSE9,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 8. "PAUSE8,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 7. "PAUSE7,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 6. "PAUSE6,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 5. "PAUSE5,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x0 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x0 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
line.long 0x4 "PDMAx_SWREQ,PDMA Software Request Register"
bitfld.long 0x4 15. "SWREQ15,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 14. "SWREQ14,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 13. "SWREQ13,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 12. "SWREQ12,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 11. "SWREQ11,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 10. "SWREQ10,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 9. "SWREQ9,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 8. "SWREQ8,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 7. "SWREQ7,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
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bitfld.long 0x4 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
bitfld.long 0x4 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
rgroup.long 0x40C++0x3
line.long 0x0 "PDMAx_TRGSTS,PDMA Channel Request Status Register"
bitfld.long 0x0 15. "REQSTS15,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 14. "REQSTS14,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 13. "REQSTS13,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 12. "REQSTS12,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 11. "REQSTS11,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 10. "REQSTS10,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 9. "REQSTS9,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 8. "REQSTS8,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 7. "REQSTS7,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x0 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not  no matter request from software or peripheral. When PDMA controller finishes channel transfer  this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
group.long 0x410++0x3
line.long 0x0 "PDMAx_PRISET,PDMA Fixed Priority Setting Register"
bitfld.long 0x0 15. "FPRISET15,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 14. "FPRISET14,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 13. "FPRISET13,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 12. "FPRISET12,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 11. "FPRISET11,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 10. "FPRISET10,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 9. "FPRISET9,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 8. "FPRISET8,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 7. "FPRISET7,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x0 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority  use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
wgroup.long 0x414++0x3
line.long 0x0 "PDMAx_PRICLR,PDMA Fixed Priority Clear Register"
bitfld.long 0x0 15. "FPRICLR15,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 14. "FPRICLR14,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 13. "FPRICLR13,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 12. "FPRICLR12,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 11. "FPRICLR11,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 10. "FPRICLR10,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 9. "FPRICLR9,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 8. "FPRICLR8,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 7. "FPRICLR7,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x0 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
group.long 0x418++0x13
line.long 0x0 "PDMAx_INTEN,PDMA Interrupt Enable Register"
bitfld.long 0x0 15. "INTEN15,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 14. "INTEN14,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 13. "INTEN13,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 12. "INTEN12,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 11. "INTEN11,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 10. "INTEN10,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 9. "INTEN9,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 8. "INTEN8,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 7. "INTEN7,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 6. "INTEN6,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x0 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out  abort  transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
line.long 0x4 "PDMAx_INTSTS,PDMA Interrupt Status Register"
bitfld.long 0x4 23. "REQTOF15,Request Time-out Flag for Channel 15\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC15(PDMA_TOC15_14[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 22. "REQTOF14,Request Time-out Flag for Channel 14\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC14(PDMA_TOC15_14[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 21. "REQTOF13,Request Time-out Flag for Channel 13\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC13(PDMA_TOC13_12[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 20. "REQTOF12,Request Time-out Flag for Channel 12\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC12(PDMA_TOC13_12[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 19. "REQTOF11,Request Time-out Flag for Channel 11\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC11(PDMA_TOC10_11[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 18. "REQTOF10,Request Time-out Flag for Channel 10\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC10(PDMA_TOC10_11[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 17. "REQTOF9,Request Time-out Flag for Channel 9\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC9(PDMA_TOC8_9[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 16. "REQTOF8,Request Time-out Flag for Channel 8\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC8(PDMA_TOC8_9[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 15. "REQTOF7,Request Time-out Flag for Channel 7\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC7(PDMA_TOC6_7[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 14. "REQTOF6,Request Time-out Flag for Channel 6\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC6(PDMA_TOC6_7[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 13. "REQTOF5,Request Time-out Flag for Channel 5\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC5(PDMA_TOC4_5[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 12. "REQTOF4,Request Time-out Flag for Channel 4\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC4(PDMA_TOC4_5[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 11. "REQTOF3,Request Time-out Flag for Channel 3\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC3(PDMA_TOC2_3[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 10. "REQTOF2,Request Time-out Flag for Channel 2\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC2(PDMA_TOC2_3[15:0]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC1(PDMA_TOC0_1[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit.." "0: No request time-out,1: Please disable time-out function before clearing.."
bitfld.long 0x4 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC0(PDMA_TOC0_1[15:0].\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: This bit will.." "0: No request time-out,1: Please disable time-out function before clearing.."
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rbitfld.long 0x4 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
line.long 0x8 "PDMAx_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
bitfld.long 0x8 15. "ABTIF15,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 14. "ABTIF14,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 13. "ABTIF13,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 12. "ABTIF12,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 11. "ABTIF11,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 10. "ABTIF10,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 9. "ABTIF9,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 8. "ABTIF8,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 7. "ABTIF7,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
bitfld.long 0x8 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort  REQSRCn should set0 to disable peripheral request.\nNote 2 This bit will be cleared by.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
line.long 0xC "PDMAx_TDSTS,PDMA Channel Transfer Done Flag Register"
bitfld.long 0xC 15. "TDIF15,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 14. "TDIF14,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 13. "TDIF13,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 12. "TDIF12,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 11. "TDIF11,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 10. "TDIF10,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 9. "TDIF9,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 8. "TDIF8,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 7. "TDIF7,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 6. "TDIF6,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0xC 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
line.long 0x10 "PDMAx_ALIGN,PDMA Transfer Alignment Status Register"
bitfld.long 0x10 15. "ALIGN15,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 14. "ALIGN14,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 13. "ALIGN13,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 12. "ALIGN12,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 11. "ALIGN11,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 10. "ALIGN10,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 9. "ALIGN9,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 8. "ALIGN8,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 7. "ALIGN7,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 6. "ALIGN6,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 5. "ALIGN5,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 4. "ALIGN4,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x10 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
rgroup.long 0x42C++0x3
line.long 0x0 "PDMAx_TACTSTS,PDMA Transfer Active Flag Register"
bitfld.long 0x0 15. "TXACTF15,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 14. "TXACTF14,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 13. "TXACTF13,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 12. "TXACTF12,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 11. "TXACTF11,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 10. "TXACTF10,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 9. "TXACTF9,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 8. "TXACTF8,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 7. "TXACTF7,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x0 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
group.long 0x430++0x33
line.long 0x0 "PDMAx_TOUTPSC0_7,PDMA Time-out Prescaler Register(CH0 to CH7)"
bitfld.long 0x0 28.--30. "TOUTPSC7,PDMA Channel 7 Time-out Clock Source Prescaler Bits" "0: PDMA channel 7 time-out clock source is HCLK/28,1: PDMA channel 7 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "TOUTPSC6,PDMA Channel 6 Time-out Clock Source Prescaler Bits" "0: PDMA channel 6 time-out clock source is HCLK/28,1: PDMA channel 6 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "TOUTPSC5,PDMA Channel 5 Time-out Clock Source Prescaler Bits" "0: PDMA channel 5 time-out clock source is HCLK/28,1: PDMA channel 5 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "TOUTPSC4,PDMA Channel 4 Time-out Clock Source Prescaler Bits" "0: PDMA channel 4 time-out clock source is HCLK/28,1: PDMA channel 4 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "TOUTPSC3,PDMA Channel 3 Time-out Clock Source Prescaler Bits" "0: PDMA channel 3 time-out clock source is HCLK/28,1: PDMA channel 3 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "TOUTPSC2,PDMA Channel 2 Time-out Clock Source Prescaler Bits" "0: PDMA channel 2 time-out clock source is HCLK/28,1: PDMA channel 2 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,?,?,?,?,?,?"
line.long 0x4 "PDMAx_TOUTEN,PDMA Time-out Enable Register"
bitfld.long 0x4 15. "TOUTEN15,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 14. "TOUTEN14,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 13. "TOUTEN13,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 12. "TOUTEN12,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 11. "TOUTEN11,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 10. "TOUTEN10,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 9. "TOUTEN9,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 8. "TOUTEN8,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 7. "TOUTEN7,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 6. "TOUTEN6,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 5. "TOUTEN5,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 4. "TOUTEN4,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 3. "TOUTEN3,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 2. "TOUTEN2,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x4 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
line.long 0x8 "PDMAx_TOUTIEN,PDMA Time-out Interrupt Enable Register"
bitfld.long 0x8 15. "TOUTIEN15,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 14. "TOUTIEN14,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 13. "TOUTIEN13,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 12. "TOUTIEN12,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 11. "TOUTIEN11,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 10. "TOUTIEN10,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 9. "TOUTIEN9,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 8. "TOUTIEN8,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 7. "TOUTIEN7,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 6. "TOUTIEN6,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 5. "TOUTIEN5,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 4. "TOUTIEN4,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 3. "TOUTIEN3,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 2. "TOUTIEN2,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x8 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
line.long 0xC "PDMAx_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
hexmask.long.word 0xC 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode  this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode."
line.long 0x10 "PDMAx_TOC0_1,PDMA Time-out Counter Ch0 and Ch1 Register"
hexmask.long.word 0x10 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC0_7[6:4]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x10 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC0_7[2:0]) clock."
line.long 0x14 "PDMAx_TOC2_3,PDMA Time-out Counter Ch2 and Ch3 Register"
hexmask.long.word 0x14 16.--31. 1. "TOC3,Time-out Counter for Channel 3\nThis controls the period of time-out function for channel 3. The calculation unit is based on TOUTPSC3 (PDMA_TOUTPSC0_7[14:12]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x14 0.--15. 1. "TOC2,Time-out Counter for Channel 2\nThis controls the period of time-out function for channel 2. The calculation unit is based on TOUTPSC2 (PDMA_TOUTPSC0_7[10:8]) clock."
line.long 0x18 "PDMAx_TOC4_5,PDMA Time-out Counter Ch4 and Ch5 Register"
hexmask.long.word 0x18 16.--31. 1. "TOC5,Time-out Counter for Channel 5\nThis controls the period of time-out function for channel 5. The calculation unit is based on TOUTPSC5 (PDMA_TOUTPSC0_7[22:20]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x18 0.--15. 1. "TOC4,Time-out Counter for Channel 4\nThis controls the period of time-out function for channel 4. The calculation unit is based on TOUTPSC4 (PDMA_TOUTPSC0_7[18:16]) clock."
line.long 0x1C "PDMAx_TOC6_7,PDMA Time-out Counter Ch6 and Ch7 Register"
hexmask.long.word 0x1C 16.--31. 1. "TOC7,Time-out Counter for Channel 7\nThis controls the period of time-out function for channel 7. The calculation unit is based on TOUTPSC7 (PDMA_TOUTPSC0_7[30:28]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x1C 0.--15. 1. "TOC6,Time-out Counter for Channel 6\nThis controls the period of time-out function for channel 6. The calculation unit is based on TOUTPSC6 (PDMA_TOUTPSC0_7[26:24]) clock."
line.long 0x20 "PDMAx_TOC8_9,PDMA Time-out Counter Ch8 and Ch9 Register"
hexmask.long.word 0x20 16.--31. 1. "TOC9,Time-out Counter for Channel 9\nThis controls the period of time-out function for channel 9. The calculation unit is based on TOUTPSC9 (PDMA_TOUTPSC8_15[6:4]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x20 0.--15. 1. "TOC8,Time-out Counter for Channel 8\nThis controls the period of time-out function for channel 8. The calculation unit is based on TOUTPSC8 (PDMA_TOUTPSC8_15[2:0]) clock."
line.long 0x24 "PDMAx_TOC10_11,PDMA Time-out Counter Ch10 and Ch11 Register"
hexmask.long.word 0x24 16.--31. 1. "TOC11,Time-out Counter for Channel 11\nThis controls the period of time-out function for channel 11. The calculation unit is based on TOUTPSC11 (PDMA_TOUTPSC8_15[14:12]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x24 0.--15. 1. "TOC10,Time-out Counter for Channel 10\nThis controls the period of time-out function for channel 10. The calculation unit is based on TOUTPSC10 (PDMA_TOUTPSC8_15[10:8]) clock."
line.long 0x28 "PDMAx_TOC12_13,PDMA Time-out Counter Ch12 and Ch13 Register"
hexmask.long.word 0x28 16.--31. 1. "TOC13,Time-out Counter for Channel 13\nThis controls the period of time-out function for channel 13. The calculation unit is based on TOUTPSC13 (PDMA_TOUTPSC8_15[22:20]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x28 0.--15. 1. "TOC12,Time-out Counter for Channel 12\nThis controls the period of time-out function for channel 12. The calculation unit is based on TOUTPSC12 (PDMA_TOUTPSC8_15[18:16]) clock."
line.long 0x2C "PDMAx_TOC14_15,PDMA Time-out Counter Ch14 and Ch15 Register"
hexmask.long.word 0x2C 16.--31. 1. "TOC15,Time-out Counter for Channel 15\nThis controls the period of time-out function for channel 15. The calculation unit is based on TOUTPSC15 (PDMA_TOUTPSC8_15[30:28]) clock. The example of time-out period can refer TOC0 bit description."
hexmask.long.word 0x2C 0.--15. 1. "TOC14,Time-out Counter for Channel 14\nThis controls the period of time-out function for channel 14. The calculation unit is based on TOUTPSC14 (PDMA_TOUTPSC8_15[26:24]) clock."
line.long 0x30 "PDMAx_CHRST,PDMA Channel Reset Register"
bitfld.long 0x30 15. "CH15RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 14. "CH14RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 13. "CH13RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 12. "CH12RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 11. "CH11RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 10. "CH10RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 9. "CH9RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 8. "CH8RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 7. "CH7RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 6. "CH6RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 5. "CH5RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 4. "CH4RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 3. "CH3RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 2. "CH2RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x30 1. "CH1RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
bitfld.long 0x30 0. "CH0RST,Channel n Reset" "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
group.long 0x468++0x3
line.long 0x0 "PDMAx_TOUTPSC8_15,PDMA Time-out Prescaler Register(CH8 to CH15)"
bitfld.long 0x0 28.--30. "TOUTPSC15,PDMA Channel 15 Time-out Clock Source Prescaler Bits" "0: PDMA channel 15 time-out clock source is HCLK/28,1: PDMA channel 15 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "TOUTPSC14,PDMA Channel 14 Time-out Clock Source Prescaler Bits" "0: PDMA channel 14 time-out clock source is HCLK/28,1: PDMA channel 14 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "TOUTPSC13,PDMA Channel 13 Time-out Clock Source Prescaler Bits" "0: PDMA channel 13 time-out clock source is HCLK/28,1: PDMA channel 13 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "TOUTPSC12,PDMA Channel 12 Time-out Clock Source Prescaler Bits" "0: PDMA channel 12 time-out clock source is HCLK/28,1: PDMA channel 12 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "TOUTPSC11,PDMA Channel 11 Time-out Clock Source Prescaler Bits" "0: PDMA channel 11 time-out clock source is HCLK/28,1: PDMA channel 11 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "TOUTPSC10,PDMA Channel 10 Time-out Clock Source Prescaler Bits" "0: PDMA channel 10 time-out clock source is HCLK/28,1: PDMA channel 10 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "TOUTPSC9,PDMA Channel 9 Time-out Clock Source Prescaler Bits" "0: PDMA channel 9 time-out clock source is HCLK/28,1: PDMA channel 9 time-out clock source is HCLK/29,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "TOUTPSC8,PDMA Channel 8 Time-out Clock Source Prescaler Bits" "0: PDMA channel 8 time-out clock source is HCLK/28,1: PDMA channel 8 time-out clock source is HCLK/29,?,?,?,?,?,?"
group.long 0x480++0xF
line.long 0x0 "PDMAx_REQSEL0_3,PDMA Request Source Select Register 0"
hexmask.long.byte 0x0 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x0 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x0 0.--6. 1. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This.."
line.long 0x4 "PDMAx_REQSEL4_7,PDMA Request Source Select Register 1"
hexmask.long.byte 0x4 24.--30. 1. "REQSRC7,Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x4 16.--22. 1. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 8.--14. 1. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x4 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
line.long 0x8 "PDMAx_REQSEL8_11,PDMA Request Source Select Register 2"
hexmask.long.byte 0x8 24.--30. 1. "REQSRC11,Channel 11 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 11. User can configure the peripheral setting by REQSRC11. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x8 16.--22. 1. "REQSRC10,Channel 10 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x8 8.--14. 1. "REQSRC9,Channel 9 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0x8 0.--6. 1. "REQSRC8,Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
line.long 0xC "PDMAx_REQSEL12_15,PDMA Request Source Select Register 3"
hexmask.long.byte 0xC 24.--30. 1. "REQSRC15,Channel 15 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 15. User can configure the peripheral setting by REQSRC15. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0xC 16.--22. 1. "REQSRC14,Channel 14 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 14. User can configure the peripheral setting by REQSRC14. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0xC 8.--14. 1. "REQSRC13,Channel 13 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 13. User can configure the peripheral setting by REQSRC13. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
hexmask.long.byte 0xC 0.--6. 1. "REQSRC12,Channel 12 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 12. User can configure the peripheral setting by REQSRC12. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
group.long 0x500++0x2F
line.long 0x0 "PDMAx_STCR0,Stride Transfer Count Register of PDMA Channel 0"
hexmask.long.word 0x0 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x4 "PDMAx_ASOCR0,Address Stride Offset Register of PDMA Channel 0"
hexmask.long.word 0x4 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x4 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x8 "PDMAx_STCR1,Stride Transfer Count Register of PDMA Channel 1"
hexmask.long.word 0x8 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0xC "PDMAx_ASOCR1,Address Stride Offset Register of PDMA Channel 1"
hexmask.long.word 0xC 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0xC 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x10 "PDMAx_STCR2,Stride Transfer Count Register of PDMA Channel 2"
hexmask.long.word 0x10 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x14 "PDMAx_ASOCR2,Address Stride Offset Register of PDMA Channel 2"
hexmask.long.word 0x14 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x14 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x18 "PDMAx_STCR3,Stride Transfer Count Register of PDMA Channel 3"
hexmask.long.word 0x18 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x1C "PDMAx_ASOCR3,Address Stride Offset Register of PDMA Channel 3"
hexmask.long.word 0x1C 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x1C 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x20 "PDMAx_STCR4,Stride Transfer Count Register of PDMA Channel 4"
hexmask.long.word 0x20 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x24 "PDMAx_ASOCR4,Address Stride Offset Register of PDMA Channel 4"
hexmask.long.word 0x24 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x24 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
line.long 0x28 "PDMAx_STCR5,Stride Transfer Count Register of PDMA Channel 5"
hexmask.long.word 0x28 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row."
line.long 0x2C "PDMAx_ASOCR5,Address Stride Offset Register of PDMA Channel 5"
hexmask.long.word 0x2C 16.--31. 1. "DASOL,PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row."
hexmask.long.word 0x2C 0.--15. 1. "SASOL,PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row."
group.long 0x600++0xF
line.long 0x0 "PDMAx_AICTL0,Address Interval Control Register of PDMA Channel 0"
hexmask.long.word 0x0 16.--31. 1. "DAICNT,PDMA Destination Address Interval Count\nThe 16-bit register defines the destination address interval count of each row."
hexmask.long.word 0x0 0.--15. 1. "SAICNT,PDMA Source Address Interval Count\nThe 16-bit register defines the source address interval count of each row."
line.long 0x4 "PDMAx_RCNT0,Repeat Count Register of PDMA Channel 0"
hexmask.long.word 0x4 0.--15. 1. "RCNT,PDMA Repeat Count\nThe 16-bit register defines the repeat times of block transfer."
line.long 0x8 "PDMAx_AICTL1,Address Interval Control Register of PDMA Channel 1"
hexmask.long.word 0x8 16.--31. 1. "DAICNT,PDMA Destination Address Interval Count\nThe 16-bit register defines the destination address interval count of each row."
hexmask.long.word 0x8 0.--15. 1. "SAICNT,PDMA Source Address Interval Count\nThe 16-bit register defines the source address interval count of each row."
line.long 0xC "PDMAx_RCNT1,Repeat Count Register of PDMA Channel 1"
hexmask.long.word 0xC 0.--15. 1. "RCNT,PDMA Repeat Count\nThe 16-bit register defines the repeat times of block transfer."
tree.end
tree.end
tree "PSIO (Programmable Serial I/O)"
base ad:0x400C3000
group.long 0x0++0x17
line.long 0x0 "PSIO_INTCTL,PSIO Interrupt Control Register"
bitfld.long 0x0 12.--13. "CONI1SCS,Configurable Interrupt 1 Slot Controller Selection \nSelect Slot controller for interrupt 1." "0: Slot controller 0,1: Slot controller 1,?,?"
bitfld.long 0x0 8.--9. "CONI0SCS,Configurable Interrupt 0 Slot Controller Selection \nSelect Slot controller for interrupt 0." "0: Slot controller 0,1: Slot controller 1,?,?"
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bitfld.long 0x0 4.--6. "CONI1SS,Configurable Interrupt 1 Slot Selection" "0: No use,1: SLOT0,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CONI0SS,Configurable Interrupt 0 Slot Selection" "0: No use,1: SLOT0,?,?,?,?,?,?"
line.long 0x4 "PSIO_INTEN,PSIO Interrupt Enable Register"
bitfld.long 0x4 7. "SC3IE,Slot Controller 3 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 3 finish interrupt." "0: Slot controller 3 finish interrupt Disabled,1: Slot controller 3 finish interrupt Enabled"
bitfld.long 0x4 6. "SC2IE,Slot Controller 2 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 2 finish interrupt." "0: Slot controller 2 finish interrupt Disabled,1: Slot controller 2 finish interrupt Enabled"
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bitfld.long 0x4 5. "SC1IE,Slot Controller 1 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 1 finish interrupt." "0: Slot controller 1 finish interrupt Disabled,1: Slot controller 1 finish interrupt Enabled"
bitfld.long 0x4 4. "SC0IE,Slot Controller 0 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 0 finish interrupt." "0: Slot controller 0 finish interrupt Disabled,1: Slot controller 0 finish interrupt Enabled"
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bitfld.long 0x4 3. "TERRIE,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
bitfld.long 0x4 2. "MISMATIE,Mismatch Interrupt Enable Bit\nThis field is used to enable mismatch interrupt." "0: Mismatch interrupt Disabled,1: Mismatch interrupt Enabled"
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bitfld.long 0x4 1. "CON1IE,Configurable Interrupt 1 Enable Bit\nThis field is used to enable selective interrupt 1." "0: Selective interrupt 1 Disabled,1: Selective interrupt 1 Enabled"
bitfld.long 0x4 0. "CON0IE,Configurable Interrupt 0 Enable Bit\nThis field is used to enable selective interrupt 0." "0: Selective interrupt 0 Disabled,1: Selective interrupt 0 Enabled"
line.long 0x8 "PSIO_INTSTS,PSIO Interrupt Status Register"
bitfld.long 0x8 7. "SC3IF,Slot Controller 3 Counting Done Interrupt Status Flag\nThis field is used for slot controller 3 finish interrupt status flag. \nNote: This bit can be cleared by writing 1." "0: Slot controller 3 done interrupt did not occur,1: Slot controller 3 done interrupt occurred"
bitfld.long 0x8 6. "SC2IF,Slot Controller 2 Counting Done Interrupt Status Flag\nThis field is used for slot controller 2 finish interrupt status flag. \nNote: This bit can be cleared by writing 1." "0: Slot controller 2 done interrupt did not occur,1: Slot controller 2 done interrupt occurred"
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bitfld.long 0x8 5. "SC1IF,Slot Controller 1 Counting Done Interrupt Status Flag\nThis field is used for slot controller 1 finish interrupt status flag. \nNote: This bit can be cleared by writing 1." "0: Slot controller 1 done interrupt did not occur,1: Slot controller 1 done interrupt occurred"
bitfld.long 0x8 4. "SC0IF,Slot Controller 0 Counting Done Interrupt Status Flag\nThis field is used for slot controller 0 finish interrupt status flag. \nNote: This bit can be cleared by writing 1." "0: Slot controller 0 done interrupt did not occur,1: Slot controller 0 done interrupt occurred"
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bitfld.long 0x8 3. "TERRIF,Transfer Error Interrupt Status Flag \nThis field is used for transfer error interrupt status flag. The transfer error states is at PSIO_TRANSTS register which includes input data overflow flag INOVERn (PSIO_TRANSTS[29 25 21 17 13 9 5 1] and.." "0: Transfer error interrupt did not occur,1: This field is the status flag of INOVER or OUTUFER"
bitfld.long 0x8 2. "MISMATIF,Mismatch Interrupt Flag\nThis flag shows the amounts of data are not the same in each pins with PDMA enabled. If this situation happens  all slot controllers stop counting.\nNote 1: This flag is only effective on the pin with PDMA enabled.\nNote.." "0: Each pin with PDMA enabled receive or transfer..,1: This flag is only effective on the pin with PDMA.."
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bitfld.long 0x8 1. "CON1IF,Configurable Interrupt 1 Flag \nThe setting interrupt is trigger at the end of the check point of the pin.\nNote: This bit can be cleared by writing 1." "0: Condition in PSIO_INTCTL is not triggered,1: Condition in PSIO_INTCTL is triggered"
bitfld.long 0x8 0. "CON0IF,Configurable Interrupt 0 Flag \nThe setting interrupt is trigger at the end of the check point of the pin.\nNote: This bit can be cleared by writing 1." "0: Condition in PSIO_INTCTL is not triggered,1: Condition in PSIO_INTCTL is triggered"
line.long 0xC "PSIO_TRANSTS,PSIO Transfer Status Register"
bitfld.long 0xC 31. "OUTUF7,Output Data Underflow Flag7\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready  this flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin7 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 30. "OUTEPY7,Output Data Empty Flag7 (Read Only)" "0: The pin7 output data is full,1: The pin7 output data is empty"
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bitfld.long 0xC 29. "INOVER7,Input Data Overflow Flag7\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin7 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 28. "INFULL7,Input Data Full Flag7 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin7 input data is empty,1: The pin7 input data is full"
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bitfld.long 0xC 27. "OUTUF6,Output Data Underflow Flag6\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready  this flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin6 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 26. "OUTEPY6,Output Data Empty Flag6 (Read Only)" "0: The pin6 output data is full,1: The pin6 output data is empty"
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bitfld.long 0xC 25. "INOVER6,Input Data Overflow Flag6\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin6 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 24. "INFULL6,Input Data Full Flag6 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin6 input data is empty,1: The pin6 input data is full"
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bitfld.long 0xC 23. "OUTUF5,Output Data Underflow Flag5\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin5 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 22. "OUTEPY5,Output Data Empty Flag5 (Read Only)" "0: The pin5 output data is full,1: The pin5 output data is empty"
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bitfld.long 0xC 21. "INOVER5,Input Data Overflow Flag5\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin5 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 20. "INFULL5,Input Data Full Flag5 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin5 input data is empty,1: The pin5 input data is full"
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bitfld.long 0xC 19. "OUTUF4,Output Data Underflow Flag4\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin4 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 18. "OUTEPY4,Output Data Empty Flag4 (Read Only)" "0: The pin4 output data is full,1: The pin4 output data is empty"
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bitfld.long 0xC 17. "INOVER4,Input Data Overflow Flag4\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin4 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 16. "INFULL4,Input Data Full Flag4 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin4 input data is empty,1: The pin4 input data is full"
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bitfld.long 0xC 15. "OUTUF3,Output Data Underflow Flag3\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin3 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 14. "OUTEPY3,Output Data Empty Flag3 (Read Only)" "0: The pin3 output data is full,1: The pin3 output data is empty"
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bitfld.long 0xC 13. "INOVER3,Input Data Overflow Flag3\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin3 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 12. "INFULL3,Input Data Full Flag3 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin3 input data is empty,1: The pin3 input data is full"
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bitfld.long 0xC 11. "OUTUF2,Output Data Underflow Flag2\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin3 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 10. "OUTEPY2,Output Data Empty Flag2 (Read Only)" "0: The pin2 output data is full,1: The pin2 output data is empty"
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bitfld.long 0xC 9. "INOVER2,Input Data Overflow Flag2\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin2 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 8. "INFULL2,Input Data Full Flag2 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin is enabled." "0: The pin2 input data is empty,1: The pin2 input data is full"
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bitfld.long 0xC 7. "OUTUF1,Output Data Underflow Flag1\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin1 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 6. "OUTEPY1,Output Data Empty Flag1 (Read Only)" "0: The pin1 output data is full,1: The pin1 output data is empty"
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bitfld.long 0xC 5. "INOVER1,Input Data Overflow Flag1\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin1 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 4. "INFULL1,Input Data Full Flag1 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin1 input data is empty,1: The pin1 input data is full"
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bitfld.long 0xC 3. "OUTUF0,Output Data Underflow Flag0\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote 1: When output data shortage happened  it will output 0.\nNote 2: When underflow happens  related slot controller.." "0: The pin0 output data is not underflow,1: When output data shortage happened"
rbitfld.long 0xC 2. "OUTEPY0,Output Data Empty Flag0 (Read Only)" "0: The pin0 output data is full,1: The pin0 output data is empty"
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bitfld.long 0xC 1. "INOVER0,Input Data Overflow Flag0\nNote 1: When input Overflow happened  it will keep the current data  and discard the upcoming data.\nNote 2: When overflow happens  related slot controller will be stopped.\nNote 3: This bit can be cleared by configure.." "0: The pin0 input data does not occur overflow,1: When input Overflow happened"
rbitfld.long 0xC 0. "INFULL0,Input Data Full Flag0 (Read Only)\nNote: This bit will be cleared automatically when related slot controller started and pin enabled." "0: The pin0 input data is empty,1: The pin0 input data is full"
line.long 0x10 "PSIO_ISSTS,PSIO Input Status State Register"
bitfld.long 0x10 15. "INSTSOV7,Input Status Overflow 7\nNote: This overflow bit can be cleared by writing 1." "0: The pin7 input status does not overflow,1: The pin7 input status occur overflow"
bitfld.long 0x10 14. "VALID7,Input Status Valid 7\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin7 input status is not ready,1: The pin7 input status is ready"
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bitfld.long 0x10 13. "INSTSOV6,Input Status Overflow 6\nNote: This overflow bit can be cleared by writing 1." "0: The pin 6 input status does not overflow,1: The pin 6 input status occur overflow"
bitfld.long 0x10 12. "VALID6,Input Status Valid 6\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 6 input status is not ready,1: The pin 6 input status is ready"
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bitfld.long 0x10 11. "INSTSOV5,Input Status Overflow 5\nNote: This overflow bit can be cleared by writing 1." "0: The pin 5 input status does not overflow,1: The pin 5 input status occur overflow"
bitfld.long 0x10 10. "VALID5,Input Status Valid 5\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 5 input status is not ready,1: The pin 5 input status is ready"
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bitfld.long 0x10 9. "INSTSOV4,Input Status Overflow 4\nNote: This overflow bit can be cleared by writing 1." "0: The pin 4 input status does not overflow,1: The pin 4 input status occur overflow"
bitfld.long 0x10 8. "VALID4,Input Status Valid 4\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 4 input status is not ready,1: The pin 4 input status is ready"
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bitfld.long 0x10 7. "INSTSOV3,Input Status Overflow 3\nNote: This overflow bit can be cleared by writing 1." "0: The pin 3 input status does not overflow,1: The pin 3 input status occur overflow"
bitfld.long 0x10 6. "VALID3,Input Status Valid 3\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 3 input Status is not ready,1: The pin 3 input Status is ready"
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bitfld.long 0x10 5. "INSTSOV2,Input Status Overflow 2\nNote: This overflow bit can be cleared by writing 1." "0: The pin 2 input status does not overflow,1: The pin 2 input status occur overflow"
bitfld.long 0x10 4. "VALID2,Input Status Valid 2\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 2 input status is not ready,1: The pin 2 input status is ready"
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bitfld.long 0x10 3. "INSTSOV1,Input Status Overflow 1\nNote: This overflow bit can be cleared by writing 1." "0: The pin 1 input status does not overflow,1: The pin 1 input status occur overflow"
bitfld.long 0x10 2. "VALID1,Input Status Valid 1\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 1 input status is not ready,1: The pin 1 input status is ready"
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bitfld.long 0x10 1. "INSTSOV0,Input Status Overflow 0\nNote: This overflow bit can be cleared by writing 1." "0: The pin 0 input status does not overflow,1: The pin 0 input status occur overflow"
bitfld.long 0x10 0. "VALID0,Input Status Valid 0\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read." "0: The pin 0 input status is not ready,1: The pin 0 input status is ready"
line.long 0x14 "PSIO_PDMACTL,PSIO PDMA Control Register"
bitfld.long 0x14 28.--29. "INSCSEL,PDMA Input Data Slot Controller Selection" "0: Slot controller 0,1: Slot controller 1,?,?"
hexmask.long.byte 0x14 24.--27. 1. "INNUM,PDMA Input Current Number (Read Only)\nThis register shows the current pin number of input register read by PDMA."
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bitfld.long 0x14 20.--21. "OUTSCSEL,PDMA Output Data Slot Controller Selection" "0: Slot controller 0,1: Slot controller 1,?,?"
hexmask.long.byte 0x14 16.--19. 1. "OUTNUM,PDMA Output Current Number (Read Only)\nThis register shows the current pin number of output register write by PDMA."
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bitfld.long 0x14 15. "IPIN7EN,Input PDMA Pin7 Enable Bit" "0: Pin7 input PDMA function Disabled,1: Pin7 input PDMA function Enabled"
bitfld.long 0x14 14. "IPIN6EN,Input PDMA Pin6 Enable Bit" "0: Pin6 input PDMA function Disabled,1: Pin6 input PDMA function Enabled"
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bitfld.long 0x14 13. "IPIN5EN,Input PDMA Pin5 Enable Bit" "0: Pin5 input PDMA function Disabled,1: Pin5 input PDMA function Enabled"
bitfld.long 0x14 12. "IPIN4EN,Input PDMA Pin4 Enable Bit" "0: Pin4 input PDMA function Disabled,1: Pin4 input PDMA function Enabled"
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bitfld.long 0x14 11. "IPIN3EN,Input PDMA Pin3 Enable Bit" "0: Pin3 input PDMA function Disabled,1: Pin3 input PDMA function Enabled"
bitfld.long 0x14 10. "IPIN2EN,Input PDMA Pin2 Enable Bit" "0: Pin2 input PDMA function Disabled,1: Pin2 input PDMA function Enabled"
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bitfld.long 0x14 9. "IPIN1EN,Input PDMA Pin1 Enable Bit" "0: Pin1 input PDMA function Disabled,1: Pin1 input PDMA function Enabled"
bitfld.long 0x14 8. "IPIN0EN,Input PDMA Pin0 Enable Bit" "0: Pin0 input PDMA function Disabled,1: Pin0 input PDMA function Enabled"
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bitfld.long 0x14 7. "OPIN7EN,Output PDMA Pin7 Enable Bit" "0: Pin7 output PDMA function Disabled,1: Pin7 output PDMA function Enabled"
bitfld.long 0x14 6. "OPIN6EN,Output PDMA Pin6 Enable Bit" "0: Pin6 output PDMA function Disabled,1: Pin6 output PDMA function Enabled"
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bitfld.long 0x14 5. "OPIN5EN,Output PDMA Pin5 Enable Bit" "0: Pin5 output PDMA function Disabled,1: Pin5 output PDMA function Enabled"
bitfld.long 0x14 4. "OPIN4EN,Output PDMA Pin4 Enable Bit" "0: Pin4 output PDMA function Disabled,1: Pin4 output PDMA function Enabled"
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bitfld.long 0x14 3. "OPIN3EN,Output PDMA Pin3 Enable Bit" "0: Pin3 output PDMA function Disabled,1: Pin3 output PDMA function Enabled"
bitfld.long 0x14 2. "OPIN2EN,Output PDMA Pin2 Enable Bit" "0: Pin2 output PDMA function Disabled,1: Pin2 output PDMA function Enabled"
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bitfld.long 0x14 1. "OPIN1EN,Output PDMA Pin1 Enable Bit" "0: Pin1 output PDMA function Disabled,1: Pin1 output PDMA function Enabled"
bitfld.long 0x14 0. "OPIN0EN,Output PDMA Pin0 Enable Bit" "0: Pin0 output PDMA function Disabled,1: Pin0 output PDMA function Enabled"
wgroup.long 0x18++0x3
line.long 0x0 "PSIO_PODAT,PSIO PDMA Output Data Register"
hexmask.long 0x0 0.--31. 1. "PDMAOUT,PDMA Output Data\nThis register is used for PSIO with PDMA single mode  and set PDMA with fixed address.\nWhen PSIO in PDMA mode  setting PDMA to write data to this register.\nThe data in this register will be placed to corresponding PSIOn_OUTDAT.."
group.long 0x1C++0x7
line.long 0x0 "PSIO_PIDAT,PSIO PDMA Input Data Register"
hexmask.long 0x0 0.--31. 1. "PDMAIN,PDMA Input Data\nThis register is used for PSIO with PDMA single mode  and set PDMA with fixed address.\nWhen PSIO in PDMA mode  setting PDMA to read data from this register.\nThe data in this register will be updated from corresponding.."
line.long 0x4 "PSIO_SC0CTL,PSIO Slot Controller n Control Register"
bitfld.long 0x4 25. "IDLE,PSIO_SCn Idle Flag\nNote 1: This bit will be cleared to 0 when slot controller starts to count automatically. \nNote 2: This bit will be set to 1 when configuring it 1 by software. \nNote 3: This bit is set to distinguish INTERVAL.." "0: PSIO_SCn is not IDLE,1: This bit will be cleared to 0 when slot.."
bitfld.long 0x4 24. "BUSY,PSIO_SCn Busy Flag\nNote: This bit will be set to 1 when slot controller starts to count automatically and it will be cleared to 0 automatically when slot controller stops counting  too." "0: PSIO_SCn is not busy,1: PSIO_SCn is busy"
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bitfld.long 0x4 18. "STOP,PSIO_SCn Stop\nNote: This bit is always read as 0." "0: No use,1: Stop PSIO_SCn"
bitfld.long 0x4 17. "REPEAT,Whole Repeat Mode\nSlot controller repeats counting forever.\nNote 1: If this bit is enabled with PDMA mode  slot controller will stop automatically when the PDMA finishes transferring number of data.\nNote 2: If PSIO receives stop instruction.." "0: Repeat mode Disabled,1: If this bit is enabled with PDMA mode"
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bitfld.long 0x4 16. "START,PSIO_SCn Start\nNote: This bit is always read as 0." "0: No use,1: Start PSIO_SCn to count and active related.."
bitfld.long 0x4 14.--15. "TRIGSRC,PSIO_SCn Trigger Source\nNote 1: PSIO slot controller pin can only be triggered by related pins set from SCSEL(PSIOn_GENCTL[25:24]).\nNote 2: Configuring rising or falling signal trigger PSIO  the signal needs to hold for at least two PSIO_CLK.." "0: Trigger by software,1: PSIO slot controller pin can only be triggered..,2: Configuring rising or falling signal trigger PSIO,?"
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hexmask.long.byte 0x4 8.--13. 1. "SPLCNT,Slot Period Loop Count\n000000 ~ 111110 is loop count.\nNote 1: If setting this register 111111 with PDMA mode and OUTPUT mode  it will stop automatically when PDMA is finished and output data in shift register is finished.\nNote 2: If setting.."
hexmask.long.byte 0x4 4.--7. 1. "ENDSLOT,End Slot Period\nThe end slot of the repeat period."
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hexmask.long.byte 0x4 0.--3. 1. "INISLOT,Initial Slot Period\nThe initial slot of the repeat period."
group.long 0x28++0x3
line.long 0x0 "PSIO_SC1CTL,PSIO Slot Controller n Control Register"
bitfld.long 0x0 25. "IDLE,PSIO_SCn Idle Flag\nNote 1: This bit will be cleared to 0 when slot controller starts to count automatically. \nNote 2: This bit will be set to 1 when configuring it 1 by software. \nNote 3: This bit is set to distinguish INTERVAL.." "0: PSIO_SCn is not IDLE,1: This bit will be cleared to 0 when slot.."
bitfld.long 0x0 24. "BUSY,PSIO_SCn Busy Flag\nNote: This bit will be set to 1 when slot controller starts to count automatically and it will be cleared to 0 automatically when slot controller stops counting  too." "0: PSIO_SCn is not busy,1: PSIO_SCn is busy"
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bitfld.long 0x0 18. "STOP,PSIO_SCn Stop\nNote: This bit is always read as 0." "0: No use,1: Stop PSIO_SCn"
bitfld.long 0x0 17. "REPEAT,Whole Repeat Mode\nSlot controller repeats counting forever.\nNote 1: If this bit is enabled with PDMA mode  slot controller will stop automatically when the PDMA finishes transferring number of data.\nNote 2: If PSIO receives stop instruction.." "0: Repeat mode Disabled,1: If this bit is enabled with PDMA mode"
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bitfld.long 0x0 16. "START,PSIO_SCn Start\nNote: This bit is always read as 0." "0: No use,1: Start PSIO_SCn to count and active related.."
bitfld.long 0x0 14.--15. "TRIGSRC,PSIO_SCn Trigger Source\nNote 1: PSIO slot controller pin can only be triggered by related pins set from SCSEL(PSIOn_GENCTL[25:24]).\nNote 2: Configuring rising or falling signal trigger PSIO  the signal needs to hold for at least two PSIO_CLK.." "0: Trigger by software,1: PSIO slot controller pin can only be triggered..,2: Configuring rising or falling signal trigger PSIO,?"
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hexmask.long.byte 0x0 8.--13. 1. "SPLCNT,Slot Period Loop Count\n000000 ~ 111110 is loop count.\nNote 1: If setting this register 111111 with PDMA mode and OUTPUT mode  it will stop automatically when PDMA is finished and output data in shift register is finished.\nNote 2: If setting.."
hexmask.long.byte 0x0 4.--7. 1. "ENDSLOT,End Slot Period\nThe end slot of the repeat period."
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hexmask.long.byte 0x0 0.--3. 1. "INISLOT,Initial Slot Period\nThe initial slot of the repeat period."
group.long 0x30++0x3
line.long 0x0 "PSIO_SC2CTL,PSIO Slot Controller n Control Register"
bitfld.long 0x0 25. "IDLE,PSIO_SCn Idle Flag\nNote 1: This bit will be cleared to 0 when slot controller starts to count automatically. \nNote 2: This bit will be set to 1 when configuring it 1 by software. \nNote 3: This bit is set to distinguish INTERVAL.." "0: PSIO_SCn is not IDLE,1: This bit will be cleared to 0 when slot.."
bitfld.long 0x0 24. "BUSY,PSIO_SCn Busy Flag\nNote: This bit will be set to 1 when slot controller starts to count automatically and it will be cleared to 0 automatically when slot controller stops counting  too." "0: PSIO_SCn is not busy,1: PSIO_SCn is busy"
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bitfld.long 0x0 18. "STOP,PSIO_SCn Stop\nNote: This bit is always read as 0." "0: No use,1: Stop PSIO_SCn"
bitfld.long 0x0 17. "REPEAT,Whole Repeat Mode\nSlot controller repeats counting forever.\nNote 1: If this bit is enabled with PDMA mode  slot controller will stop automatically when the PDMA finishes transferring number of data.\nNote 2: If PSIO receives stop instruction.." "0: Repeat mode Disabled,1: If this bit is enabled with PDMA mode"
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bitfld.long 0x0 16. "START,PSIO_SCn Start\nNote: This bit is always read as 0." "0: No use,1: Start PSIO_SCn to count and active related.."
bitfld.long 0x0 14.--15. "TRIGSRC,PSIO_SCn Trigger Source\nNote 1: PSIO slot controller pin can only be triggered by related pins set from SCSEL(PSIOn_GENCTL[25:24]).\nNote 2: Configuring rising or falling signal trigger PSIO  the signal needs to hold for at least two PSIO_CLK.." "0: Trigger by software,1: PSIO slot controller pin can only be triggered..,2: Configuring rising or falling signal trigger PSIO,?"
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hexmask.long.byte 0x0 8.--13. 1. "SPLCNT,Slot Period Loop Count\n000000 ~ 111110 is loop count.\nNote 1: If setting this register 111111 with PDMA mode and OUTPUT mode  it will stop automatically when PDMA is finished and output data in shift register is finished.\nNote 2: If setting.."
hexmask.long.byte 0x0 4.--7. 1. "ENDSLOT,End Slot Period\nThe end slot of the repeat period."
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hexmask.long.byte 0x0 0.--3. 1. "INISLOT,Initial Slot Period\nThe initial slot of the repeat period."
group.long 0x38++0x3
line.long 0x0 "PSIO_SC3CTL,PSIO Slot Controller n Control Register"
bitfld.long 0x0 25. "IDLE,PSIO_SCn Idle Flag\nNote 1: This bit will be cleared to 0 when slot controller starts to count automatically. \nNote 2: This bit will be set to 1 when configuring it 1 by software. \nNote 3: This bit is set to distinguish INTERVAL.." "0: PSIO_SCn is not IDLE,1: This bit will be cleared to 0 when slot.."
bitfld.long 0x0 24. "BUSY,PSIO_SCn Busy Flag\nNote: This bit will be set to 1 when slot controller starts to count automatically and it will be cleared to 0 automatically when slot controller stops counting  too." "0: PSIO_SCn is not busy,1: PSIO_SCn is busy"
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bitfld.long 0x0 18. "STOP,PSIO_SCn Stop\nNote: This bit is always read as 0." "0: No use,1: Stop PSIO_SCn"
bitfld.long 0x0 17. "REPEAT,Whole Repeat Mode\nSlot controller repeats counting forever.\nNote 1: If this bit is enabled with PDMA mode  slot controller will stop automatically when the PDMA finishes transferring number of data.\nNote 2: If PSIO receives stop instruction.." "0: Repeat mode Disabled,1: If this bit is enabled with PDMA mode"
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bitfld.long 0x0 16. "START,PSIO_SCn Start\nNote: This bit is always read as 0." "0: No use,1: Start PSIO_SCn to count and active related.."
bitfld.long 0x0 14.--15. "TRIGSRC,PSIO_SCn Trigger Source\nNote 1: PSIO slot controller pin can only be triggered by related pins set from SCSEL(PSIOn_GENCTL[25:24]).\nNote 2: Configuring rising or falling signal trigger PSIO  the signal needs to hold for at least two PSIO_CLK.." "0: Trigger by software,1: PSIO slot controller pin can only be triggered..,2: Configuring rising or falling signal trigger PSIO,?"
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hexmask.long.byte 0x0 8.--13. 1. "SPLCNT,Slot Period Loop Count\n000000 ~ 111110 is loop count.\nNote 1: If setting this register 111111 with PDMA mode and OUTPUT mode  it will stop automatically when PDMA is finished and output data in shift register is finished.\nNote 2: If setting.."
hexmask.long.byte 0x0 4.--7. 1. "ENDSLOT,End Slot Period\nThe end slot of the repeat period."
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hexmask.long.byte 0x0 0.--3. 1. "INISLOT,Initial Slot Period\nThe initial slot of the repeat period."
group.long 0x24++0x3
line.long 0x0 "PSIO_SC0SLOT,PSIO Slot Controller n Slot Register"
hexmask.long.byte 0x0 28.--31. 1. "SLOT7,PSIO Slot Controller Slot7 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 24.--27. 1. "SLOT6,PSIO Slot Controller Slot6 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 20.--23. 1. "SLOT5,PSIO Slot Controller Slot5 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 16.--19. 1. "SLOT4,PSIO Slot Controller Slot4 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 12.--15. 1. "SLOT3,PSIO Slot Controller Slot3 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 8.--11. 1. "SLOT2,PSIO Slot Controller Slot2 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 4.--7. 1. "SLOT1,PSIO Slot Controller Slot1 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 0.--3. 1. "SLOT0,PSIO Slot Controller Slot0 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
group.long 0x2C++0x3
line.long 0x0 "PSIO_SC1SLOT,PSIO Slot Controller n Slot Register"
hexmask.long.byte 0x0 28.--31. 1. "SLOT7,PSIO Slot Controller Slot7 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 24.--27. 1. "SLOT6,PSIO Slot Controller Slot6 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 20.--23. 1. "SLOT5,PSIO Slot Controller Slot5 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 16.--19. 1. "SLOT4,PSIO Slot Controller Slot4 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 12.--15. 1. "SLOT3,PSIO Slot Controller Slot3 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 8.--11. 1. "SLOT2,PSIO Slot Controller Slot2 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 4.--7. 1. "SLOT1,PSIO Slot Controller Slot1 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 0.--3. 1. "SLOT0,PSIO Slot Controller Slot0 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
group.long 0x34++0x3
line.long 0x0 "PSIO_SC2SLOT,PSIO Slot Controller n Slot Register"
hexmask.long.byte 0x0 28.--31. 1. "SLOT7,PSIO Slot Controller Slot7 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 24.--27. 1. "SLOT6,PSIO Slot Controller Slot6 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 20.--23. 1. "SLOT5,PSIO Slot Controller Slot5 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 16.--19. 1. "SLOT4,PSIO Slot Controller Slot4 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 12.--15. 1. "SLOT3,PSIO Slot Controller Slot3 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 8.--11. 1. "SLOT2,PSIO Slot Controller Slot2 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 4.--7. 1. "SLOT1,PSIO Slot Controller Slot1 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 0.--3. 1. "SLOT0,PSIO Slot Controller Slot0 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
group.long 0x3C++0x7
line.long 0x0 "PSIO_SC3SLOT,PSIO Slot Controller n Slot Register"
hexmask.long.byte 0x0 28.--31. 1. "SLOT7,PSIO Slot Controller Slot7 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 24.--27. 1. "SLOT6,PSIO Slot Controller Slot6 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 20.--23. 1. "SLOT5,PSIO Slot Controller Slot5 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 16.--19. 1. "SLOT4,PSIO Slot Controller Slot4 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 12.--15. 1. "SLOT3,PSIO Slot Controller Slot3 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 8.--11. 1. "SLOT2,PSIO Slot Controller Slot2 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
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hexmask.long.byte 0x0 4.--7. 1. "SLOT1,PSIO Slot Controller Slot1 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
hexmask.long.byte 0x0 0.--3. 1. "SLOT0,PSIO Slot Controller Slot0 Tick Count\n0 to 15.\nNote 1: Filling in all 0 to this field indicates to disable this slot.\nNote 2: The disabled slot should not be set between the enabled slots  or the order of enabled slot which is after the disabled.."
line.long 0x4 "PSIO0_GENCTL,PSIOn General Control Register"
bitfld.long 0x4 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x4 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x4 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x4 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x4 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x4 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x4 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x4 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x4 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0x60++0x3
line.long 0x0 "PSIO1_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0x80++0x3
line.long 0x0 "PSIO2_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0xA0++0x3
line.long 0x0 "PSIO3_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0xC0++0x3
line.long 0x0 "PSIO4_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0xE0++0x3
line.long 0x0 "PSIO5_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0x100++0x3
line.long 0x0 "PSIO6_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0x120++0x3
line.long 0x0 "PSIO7_GENCTL,PSIOn General Control Register"
bitfld.long 0x0 26. "PINEN,Pin Enable Bit" "0: Pin Disabled,1: Pin Enabled"
bitfld.long 0x0 24.--25. "SCSEL,Slot Controller Selection\nSelect slot controller for check point." "0: SLOT CONTROLLER0,1: SLOT CONTROLLER1,?,?"
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bitfld.long 0x0 18.--19. "MODESW1,Mode Switch1 Point\nMode at the switch1 point." "0: Input mode,1: Output mode,?,?"
bitfld.long 0x0 16.--17. "MODESW0,Mode Switch0 Point\nMode at the switch0 point." "0: Input mode,1: Output mode,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "SW1CP,Switch1 Check Point"
hexmask.long.byte 0x0 8.--11. 1. "SW0CP,Switch0 Check Point"
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bitfld.long 0x0 4.--5. "INTERVAL,Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote 1: Only when IOMODE is not input mode  then this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
bitfld.long 0x0 2.--3. "INITIAL,Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote 1: Only when IOMODE is not input mode  this register is effective.\nNote 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]).." "0: Low level,1: Only when IOMODE is not input mode,2: This bit is effective only when IDLE,?"
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bitfld.long 0x0 0.--1. "IOMODE,I/O Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote 1: When slot controller stops counting  it will switch.." "0: Input mode,1: When slot controller stops counting,2: When PSIO uses quasi-bidirectional mode or..,?"
group.long 0x44++0x3
line.long 0x0 "PSIO0_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0x64++0x3
line.long 0x0 "PSIO1_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0x84++0x3
line.long 0x0 "PSIO2_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0xA4++0x3
line.long 0x0 "PSIO3_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0xC4++0x3
line.long 0x0 "PSIO4_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0xE4++0x3
line.long 0x0 "PSIO5_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0x104++0x3
line.long 0x0 "PSIO6_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
group.long 0x124++0x3
line.long 0x0 "PSIO7_DATCTL,PSIOn Data Control Register"
bitfld.long 0x0 28.--29. "INDEPTH,Input Data Depth\nRepresent the data depth of the input buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The input data depth impacts when the input data full.." "0: INDEPTH[0] the data depth is 1.\nINDEPTH the..,1: The input data depth impacts when the input data..,2: There is no difference of data depth no matter..,3: INDEPTH the data depth is 4"
bitfld.long 0x0 24.--25. "OUTDEPTH,Output Data Depth\nRepresent the data depth of the output buffer  when data width is larger than 16-bit  this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit  \nNote 1: The output data depth impacts when the output data.." "0: OUTDEPTH [0] the data depth is 1.\nOUTDEPTH the..,1: The output data depth impacts when the output..,2: There is no difference of data depth no matter..,3: OUTDEPTH the data depth is 4"
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bitfld.long 0x0 16. "ORDER,Order\nThe order of output data and input data." "0: Data transfer start form LSB,1: Data transfer start form MSB"
hexmask.long.byte 0x0 8.--12. 1. "INDATWD,Input Data Width\nIndicate the data width of INPUT DATA register."
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hexmask.long.byte 0x0 0.--4. 1. "OUTDATWD,Output Data Width\nIndicate the data width of OUTPUT DATA register."
rgroup.long 0x48++0x3
line.long 0x0 "PSIO0_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0x68++0x3
line.long 0x0 "PSIO1_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0x88++0x3
line.long 0x0 "PSIO2_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0xA8++0x3
line.long 0x0 "PSIO3_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0xC8++0x3
line.long 0x0 "PSIO4_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0xE8++0x3
line.long 0x0 "PSIO5_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0x108++0x3
line.long 0x0 "PSIO6_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0x128++0x3
line.long 0x0 "PSIO7_INSTS,PSIOn Input Status Register"
hexmask.long.byte 0x0 0.--7. 1. "INSTS,Input Status\nStatus input buffer. This register can be read clear.\nNote: When the valid bit is set  the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update."
rgroup.long 0x4C++0x3
line.long 0x0 "PSIO0_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0x6C++0x3
line.long 0x0 "PSIO1_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0x8C++0x3
line.long 0x0 "PSIO2_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0xAC++0x3
line.long 0x0 "PSIO3_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0xCC++0x3
line.long 0x0 "PSIO4_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0xEC++0x3
line.long 0x0 "PSIO5_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0x10C++0x3
line.long 0x0 "PSIO6_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
rgroup.long 0x12C++0x3
line.long 0x0 "PSIO7_INDAT,PSIOn Input Data Register"
hexmask.long 0x0 0.--31. 1. "INDAT,Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  PSIO sample input.."
wgroup.long 0x50++0x3
line.long 0x0 "PSIO0_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0x70++0x3
line.long 0x0 "PSIO1_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0x90++0x3
line.long 0x0 "PSIO2_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0xB0++0x3
line.long 0x0 "PSIO3_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0xD0++0x3
line.long 0x0 "PSIO4_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0xF0++0x3
line.long 0x0 "PSIO5_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0x110++0x3
line.long 0x0 "PSIO6_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
wgroup.long 0x130++0x3
line.long 0x0 "PSIO7_OUTDAT,PSIOn Output Data Register"
hexmask.long 0x0 0.--31. 1. "OUTDAT,Output Data Buffer\nThis field is used to configure output data."
group.long 0x54++0x3
line.long 0x0 "PSIO0_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0x74++0x3
line.long 0x0 "PSIO1_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0x94++0x3
line.long 0x0 "PSIO2_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0xB4++0x3
line.long 0x0 "PSIO3_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0xD4++0x3
line.long 0x0 "PSIO4_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0xF4++0x3
line.long 0x0 "PSIO5_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0x114++0x3
line.long 0x0 "PSIO6_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0x134++0x3
line.long 0x0 "PSIO7_CPCTL0,PSIOn Check Point Control Register 0"
bitfld.long 0x0 28.--30. "CKPT7,Check Point 7\nThis field is used to link check point and slot controller slot.\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6,Check Point 6\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5,Check Point 5\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4,Check Point 4\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3,Check Point 3\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2,Check Point 2\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1,Check Point 1\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0,Check Point 0\nNote 1: If there are two check points that select the same SLOT  the pin will follow settings of the smaller check point number.\nNote 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7  or the check point action.." "0: No use,1: If there are two check points that select the..,2: The correlated SLOT should be filled in order..,?,?,?,?,?"
group.long 0x58++0x3
line.long 0x0 "PSIO0_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0x78++0x3
line.long 0x0 "PSIO1_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0x98++0x3
line.long 0x0 "PSIO2_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0xB8++0x3
line.long 0x0 "PSIO3_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0xD8++0x3
line.long 0x0 "PSIO4_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0xF8++0x3
line.long 0x0 "PSIO5_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0x118++0x3
line.long 0x0 "PSIO6_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
group.long 0x138++0x3
line.long 0x0 "PSIO7_CPCTL1,PSIOn Check Point Control Register 1"
bitfld.long 0x0 28.--30. "CKPT7ACT,Check Point 7 Action\nSelect check point action at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "CKPT6ACT,Check Point 6 Action\nSelect check point action at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "CKPT5ACT,Check Point 5 Action\nSelect check point action at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "CKPT4ACT,Check Point 4 Action\nSelect check point action at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CKPT3ACT,Check Point 3 Action\nSelect check point action at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "CKPT2ACT,Check Point 2 Action\nSelect check point action at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "CKPT1ACT,Check Point 1 Action\nSelect check point action at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "CKPT0ACT,Check Point 0 Action\nSelect check point action at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])." "0: Output level low,1: Output level high,?,?,?,?,?,?"
tree.end
tree "QSPI (Quad Serial Peripheral Interface)"
base ad:0x0
tree "QSPI0"
base ad:0x40060000
group.long 0x0++0x17
line.long 0x0 "QSPIx_CTL,QSPI Control Register"
bitfld.long 0x0 23. "TXDTREN,Transmit Double Transfer Rate Mode Enable Bit\nNote: QSPI Master mode supports TXDTR mode  and QSPI Slave mode does not support this mode." "0: TX DTR mode Disabled,1: TX DTR mode Enabled"
bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable Bit" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable Bit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: QSPI data is input direction,1: QSPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16  24  and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: QSPI unit transfer interrupt Disabled,1: QSPI unit transfer interrupt Enabled"
bitfld.long 0x0 16. "TWOBIT,2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled  the first serial transmitted bit data is from the first FIFO buffer data  and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as.." "0: 2-bit Transfer mode Disabled,1: 2-bit Transfer mode Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode  QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. (Master Only)" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x0 14. "HALFDPX,QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer. The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: QSPI operates in full-duplex transfer,1: QSPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the QSPIx TX register is sent.."
hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: QSPI bus clock is idle low,1: QSPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: In TX DTR mode  TXNEG equals to CLKPOL (QSPIx_CTL[3])." "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,QSPI Transfer Control Enable Bit\nIn Master mode  the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode  this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
line.long 0x4 "QSPIx_CLKDIV,QSPI Clock Divider Register"
hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock  fspi_eclk  and the QSPI bus clock of QSPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
line.long 0x8 "QSPIx_SSCTL,QSPI Slave Select Control Register"
hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode  these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0  it indicates the.."
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out Reset Control" "0: When Slave mode time-out event occurs the TX and..,1: When Slave mode time-out event occurs the TX and.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode  the QSPI controller can work with 3-wire interface including QSPIx_CLK  QSPIx_MISO and QSPIx_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable BitThis bit is supported in Master mode only" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS)." "0: The slave selection signal QSPIx_SS is active low,1: The slave selection signal QSPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 \nNote: This function is Master only.\n\n\nNote" "0: Set the QSPIx_SS line to inactive state.\nKeep..,1: Set the QSPIx_SS line to active state.\nQSPIx_SS.."
line.long 0xC "QSPIx_PDMACTL,QSPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the QSPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In QSPI Master mode with full duplex transfer  if both TX and RX PDMA functions are enabled  RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In QSPI Master mode with full duplex transfer"
line.long 0x10 "QSPIx_FIFOCTL,QSPI FIFO Control Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode  TXUFIF (QSPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs  QSPIx_MISO pin state will be determined by this setting even.." "0: The QSPI data out is kept 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode  this bit can be used to make QSPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
line.long 0x14 "QSPIx_STATUS,QSPI Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs  this bit will be set to 1  the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock. In order to make sure the QSPI control logic is disabled  this bit indicates the real status of QSPI controller." "0: QSPI controller Disabled,1: QSPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode  if TX underflow event occurs and the slave select line goes to inactive state  this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode  when the slave select line goes to inactive state  if bit counter is mismatch with DWIDTH  this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
bitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0  if the bus clock is detected  the slave time-out counter in QSPI controller logic will be started. When the value of time-out counter is greater.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (QSPIx_SSCTL[2]) is set 0  and the SSLINE is 1  the QSPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: QSPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications  this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT  RXCNT  TXTHIF  TXFULL  TXEMPTY  RXTHIF  RXFULL  RXEMPTY  and UNITIF. Therefore the QSPI transfer done.." "0: QSPI controller is in idle state,1: QSPI controller is in busy state"
rgroup.long 0x18++0x3
line.long 0x0 "QSPIx_STATUS2,QSPI Status2 Register"
hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX Data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI slave mode.\nThis status.."
wgroup.long 0x20++0x3
line.long 0x0 "QSPIx_TX,QSPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.\nIn QSPI mode  if DWIDTH is set to.."
rgroup.long 0x30++0x3
line.long 0x0 "QSPIx_RX,QSPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive RegisterThere are 8-level FIFO buffers in this controller The data receive register holds the data received from QSPI data input pin If the RXEMPTY (QSPIx_STATUS[8) is not set to 1  the receive FIFO buffers can be accessed through.."
tree.end
tree "QSPI1"
base ad:0x40069000
group.long 0x0++0x17
line.long 0x0 "QSPIx_CTL,QSPI Control Register"
bitfld.long 0x0 23. "TXDTREN,Transmit Double Transfer Rate Mode Enable Bit\nNote: QSPI Master mode supports TXDTR mode  and QSPI Slave mode does not support this mode." "0: TX DTR mode Disabled,1: TX DTR mode Enabled"
bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable Bit" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable Bit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: QSPI data is input direction,1: QSPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16  24  and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: QSPI unit transfer interrupt Disabled,1: QSPI unit transfer interrupt Enabled"
bitfld.long 0x0 16. "TWOBIT,2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled  the first serial transmitted bit data is from the first FIFO buffer data  and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as.." "0: 2-bit Transfer mode Disabled,1: 2-bit Transfer mode Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode  QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. (Master Only)" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x0 14. "HALFDPX,QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer. The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: QSPI operates in full-duplex transfer,1: QSPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the QSPIx TX register is sent.."
hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: QSPI bus clock is idle low,1: QSPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: In TX DTR mode  TXNEG equals to CLKPOL (QSPIx_CTL[3])." "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,QSPI Transfer Control Enable Bit\nIn Master mode  the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode  this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
line.long 0x4 "QSPIx_CLKDIV,QSPI Clock Divider Register"
hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock  fspi_eclk  and the QSPI bus clock of QSPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
line.long 0x8 "QSPIx_SSCTL,QSPI Slave Select Control Register"
hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode  these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0  it indicates the.."
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out Reset Control" "0: When Slave mode time-out event occurs the TX and..,1: When Slave mode time-out event occurs the TX and.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode  the QSPI controller can work with 3-wire interface including QSPIx_CLK  QSPIx_MISO and QSPIx_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable BitThis bit is supported in Master mode only" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS)." "0: The slave selection signal QSPIx_SS is active low,1: The slave selection signal QSPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 \nNote: This function is Master only.\n\n\nNote" "0: Set the QSPIx_SS line to inactive state.\nKeep..,1: Set the QSPIx_SS line to active state.\nQSPIx_SS.."
line.long 0xC "QSPIx_PDMACTL,QSPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the QSPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In QSPI Master mode with full duplex transfer  if both TX and RX PDMA functions are enabled  RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In QSPI Master mode with full duplex transfer"
line.long 0x10 "QSPIx_FIFOCTL,QSPI FIFO Control Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode  TXUFIF (QSPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs  QSPIx_MISO pin state will be determined by this setting even.." "0: The QSPI data out is kept 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode  this bit can be used to make QSPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
line.long 0x14 "QSPIx_STATUS,QSPI Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs  this bit will be set to 1  the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock. In order to make sure the QSPI control logic is disabled  this bit indicates the real status of QSPI controller." "0: QSPI controller Disabled,1: QSPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode  if TX underflow event occurs and the slave select line goes to inactive state  this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode  when the slave select line goes to inactive state  if bit counter is mismatch with DWIDTH  this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
bitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0  if the bus clock is detected  the slave time-out counter in QSPI controller logic will be started. When the value of time-out counter is greater.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (QSPIx_SSCTL[2]) is set 0  and the SSLINE is 1  the QSPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: QSPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications  this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT  RXCNT  TXTHIF  TXFULL  TXEMPTY  RXTHIF  RXFULL  RXEMPTY  and UNITIF. Therefore the QSPI transfer done.." "0: QSPI controller is in idle state,1: QSPI controller is in busy state"
rgroup.long 0x18++0x3
line.long 0x0 "QSPIx_STATUS2,QSPI Status2 Register"
hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX Data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI slave mode.\nThis status.."
wgroup.long 0x20++0x3
line.long 0x0 "QSPIx_TX,QSPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.\nIn QSPI mode  if DWIDTH is set to.."
rgroup.long 0x30++0x3
line.long 0x0 "QSPIx_RX,QSPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive RegisterThere are 8-level FIFO buffers in this controller The data receive register holds the data received from QSPI data input pin If the RXEMPTY (QSPIx_STATUS[8) is not set to 1  the receive FIFO buffers can be accessed through.."
tree.end
tree.end
tree "RTC (Real Time Clock)"
base ad:0x40041000
group.long 0x0++0x3
line.long 0x0 "RTC_INIT,RTC Initiation Register"
hexmask.long 0x0 1.--31. 1. "INIT,RTC Initiation (Write Only)\nWhen RTC block is powered on  RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357  the RTC will be in un-reset state.."
rbitfld.long 0x0 0. "ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
group.long 0x8++0x1B
line.long 0x0 "RTC_FREQADJ,RTC Frequency Compensation Register"
rbitfld.long 0x0 31. "FCRBUSY,Frequency Compensation Register Write Operation Busy (Read Only)\nNote: This bit is only used when DCOMPEN (RTC_CLKFMT[16]) enabled." "0: The new register write operation is acceptable,1: The last write operation is in progress and new.."
hexmask.long.byte 0x0 8.--12. 1. "INTEGER,Integer Part"
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hexmask.long.byte 0x0 0.--5. 1. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number."
line.long 0x4 "RTC_TIME,RTC Time Loading Register"
hexmask.long.byte 0x4 24.--30. 1. "HZCNT,Index of sub-second counter (0x00~0x7F)"
bitfld.long 0x4 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode  RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1  it indicates PM time message.)" "0,1,2,3"
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hexmask.long.byte 0x4 16.--19. 1. "HR,1-Hour Time Digit (0~9)"
bitfld.long 0x4 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 8.--11. 1. "MIN,1-Min Time Digit (0~9)"
bitfld.long 0x4 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 0.--3. 1. "SEC,1-Sec Time Digit (0~9)"
line.long 0x8 "RTC_CAL,RTC Calendar Loading Register"
hexmask.long.byte 0x8 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)"
hexmask.long.byte 0x8 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)"
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bitfld.long 0x8 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
hexmask.long.byte 0x8 8.--11. 1. "MON,1-Month Calendar Digit (0~9)"
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bitfld.long 0x8 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
hexmask.long.byte 0x8 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)"
line.long 0xC "RTC_CLKFMT,RTC Time Scale Selection Register"
bitfld.long 0xC 16. "DCOMPEN,Dynamic Compensation Enable Bit" "0: Dynamic Compensation Disabled,1: Dynamic Compensation Enabled"
bitfld.long 0xC 8. "HZCNTEN,Sub-second Counter Enable Bit" "0: HZCNT disabled in RTC_TIME and RTC_TALM,1: HZCNT enabled in RTC_TIME and RTC_TALM"
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bitfld.long 0xC 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
line.long 0x10 "RTC_WEEKDAY,RTC Day of the Week Register"
bitfld.long 0x10 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,?,?,?,?,?,?"
line.long 0x14 "RTC_TALM,RTC Time Alarm Register"
hexmask.long.byte 0x14 24.--30. 1. "HZCNT,Index of sub-second counter (0x00~0x7F)"
bitfld.long 0x14 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode  RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1  it indicates PM time message.)" "0,1,2,3"
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hexmask.long.byte 0x14 16.--19. 1. "HR,1-Hour Time Digit of Alarm Setting (0~9)"
bitfld.long 0x14 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 8.--11. 1. "MIN,1-Min Time Digit of Alarm Setting (0~9)"
bitfld.long 0x14 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 0.--3. 1. "SEC,1-Sec Time Digit of Alarm Setting (0~9)"
line.long 0x18 "RTC_CALM,RTC Calendar Alarm Register"
hexmask.long.byte 0x18 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)"
hexmask.long.byte 0x18 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)"
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bitfld.long 0x18 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
hexmask.long.byte 0x18 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)"
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bitfld.long 0x18 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
hexmask.long.byte 0x18 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)"
rgroup.long 0x24++0x3
line.long 0x0 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
group.long 0x28++0x67
line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register"
bitfld.long 0x0 13. "TAMP5IEN,Tamper 5 or Pair 2 Interrupt Enable Bit\nSet TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated." "0: Tamper 5 or Pair 2 interrupt Disabled,1: Tamper 5 or Pair 2 interrupt Enabled"
bitfld.long 0x0 12. "TAMP4IEN,Tamper 4 Interrupt Enable Bit\nSet TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated." "0: Tamper 4 interrupt Disabled,1: Tamper 4 interrupt Enabled"
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bitfld.long 0x0 11. "TAMP3IEN,Tamper 3 or Pair 1 Interrupt Enable Bit\nSet TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated." "0: Tamper 3 or Pair 1 interrupt Disabled,1: Tamper 3 or Pair 1 interrupt Enabled"
bitfld.long 0x0 10. "TAMP2IEN,Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated." "0: Tamper 2 interrupt Disabled,1: Tamper 2 interrupt Enabled"
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bitfld.long 0x0 9. "TAMP1IEN,Tamper 1 or Pair 0 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated." "0: Tamper 1 or Pair 0 interrupt Disabled,1: Tamper 1 or Pair 0 interrupt Enabled"
bitfld.long 0x0 8. "TAMP0IEN,Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated." "0: Tamper 0 interrupt Disabled,1: Tamper 0 interrupt Enabled"
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bitfld.long 0x0 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated." "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated." "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
line.long 0x4 "RTC_INTSTS,RTC Interrupt Status Register"
bitfld.long 0x4 13. "TAMP5IF,Tamper 5 or Pair 2 Interrupt Flag\nThis bit is set when TAMPER5 detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMPER4 and TAMPER5 disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMPER0 and TAMPER5 disconnected during.." "0: No Tamper 5 or Pair 2 interrupt flag is generated,1: Write 1 to clear this bit"
bitfld.long 0x4 12. "TAMP4IF,Tamper 4 Interrupt Flag\nThis bit is set when TAMPER4 detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote.." "0: No Tamper 4 interrupt flag is generated,1: Write 1 to clear this bit"
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bitfld.long 0x4 11. "TAMP3IF,Tamper 3 or Pair 1 Interrupt Flag\nThis bit is set when TAMPER3 detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMPER2 and TAMPER3 disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMPER0 and TAMPER3 disconnected during.." "0: No Tamper 3 or Pair 1 interrupt flag is generated,1: Write 1 to clear this bit"
bitfld.long 0x4 10. "TAMP2IF,Tamper 2 Interrupt Flag\nThis bit is set when TAMPER2 detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote.." "0: No Tamper 2 interrupt flag is generated,1: Write 1 to clear this bit"
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bitfld.long 0x4 9. "TAMP1IF,Tamper 1 or Pair 0 Interrupt Flag\nThis bit is set when TAMPER1 detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMPER0 and TAMPER1 disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.\nNote 1: Write 1 to clear this bit.\nNote 2:.." "0: No Tamper 1 or Pair 0 interrupt flag is generated,1: Write 1 to clear this bit"
bitfld.long 0x4 8. "TAMP0IF,Tamper 0 Interrupt Flag\nThis bit is set when TAMPER0 detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote.." "0: No Tamper 0 interrupt flag is generated,1: Write 1 to clear this bit"
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bitfld.long 0x4 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit." "0: Tick condition did not occur,1: Tick condition occurred"
bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit." "0: Alarm condition is not matched,1: Alarm condition is matched"
line.long 0x8 "RTC_TICK,RTC Time Tick Register"
bitfld.long 0x8 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request." "0: Time tick is 1 second,1: Time tick is 1/2 second,?,?,?,?,?,?"
line.long 0xC "RTC_TAMSK,RTC Time Alarm Mask Register"
bitfld.long 0xC 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
bitfld.long 0xC 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "?,1: Hour Time Digit of Alarm Setting"
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bitfld.long 0xC 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
bitfld.long 0xC 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "?,1: Min Time Digit of Alarm Setting"
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bitfld.long 0xC 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
bitfld.long 0xC 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "?,1: Sec Time Digit of Alarm Setting"
line.long 0x10 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
bitfld.long 0x10 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
bitfld.long 0x10 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "?,1: Year Calendar Digit of Alarm Setting"
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bitfld.long 0x10 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
bitfld.long 0x10 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "?,1: Month Calendar Digit of Alarm Setting"
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bitfld.long 0x10 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
bitfld.long 0x10 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "?,1: Day Calendar Digit of Alarm Setting"
line.long 0x14 "RTC_SPRCTL,RTC Spare Functional Control Register"
bitfld.long 0x14 8. "KSTRIGEN,Key Store Trigger Enable Bit" "0: Tamper event is detected and to trigger Key..,1: Tamper event is detected and to trigger Key.."
bitfld.long 0x14 5. "SPRCSTS,SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~ RTC_SPR19 content is cleared when specify tamper event is detected.\nNote 1: Write 1 to clear this bit.\nNote 2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0." "0: Spare register content is not cleared,1: Write 1 to clear this bit"
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bitfld.long 0x14 2. "SPRRWEN,Spare Register Enable Bit\nNote: When spare register is disabled  RTC_SPR0 ~ RTC_SPR19 cannot be accessed." "0: Spare register Disabled,1: Spare register Enabled"
line.long 0x18 "RTC_SPR0,RTC Spare Register 0"
hexmask.long 0x18 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x1C "RTC_SPR1,RTC Spare Register 1"
hexmask.long 0x1C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x20 "RTC_SPR2,RTC Spare Register 2"
hexmask.long 0x20 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x24 "RTC_SPR3,RTC Spare Register 3"
hexmask.long 0x24 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x28 "RTC_SPR4,RTC Spare Register 4"
hexmask.long 0x28 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x2C "RTC_SPR5,RTC Spare Register 5"
hexmask.long 0x2C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x30 "RTC_SPR6,RTC Spare Register 6"
hexmask.long 0x30 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x34 "RTC_SPR7,RTC Spare Register 7"
hexmask.long 0x34 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x38 "RTC_SPR8,RTC Spare Register 8"
hexmask.long 0x38 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x3C "RTC_SPR9,RTC Spare Register 9"
hexmask.long 0x3C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x40 "RTC_SPR10,RTC Spare Register 10"
hexmask.long 0x40 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x44 "RTC_SPR11,RTC Spare Register 11"
hexmask.long 0x44 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x48 "RTC_SPR12,RTC Spare Register 12"
hexmask.long 0x48 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x4C "RTC_SPR13,RTC Spare Register 13"
hexmask.long 0x4C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x50 "RTC_SPR14,RTC Spare Register 14"
hexmask.long 0x50 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x54 "RTC_SPR15,RTC Spare Register 15"
hexmask.long 0x54 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x58 "RTC_SPR16,RTC Spare Register 16"
hexmask.long 0x58 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x5C "RTC_SPR17,RTC Spare Register 17"
hexmask.long 0x5C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x60 "RTC_SPR18,RTC Spare Register 18"
hexmask.long 0x60 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
line.long 0x64 "RTC_SPR19,RTC Spare Register 19"
hexmask.long 0x64 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions  a tamper pin event is detected  or after Flash mass operation."
group.long 0x100++0xB
line.long 0x0 "RTC_LXTCTL,RTC 32.768 kHz Oscillator Control Register"
bitfld.long 0x0 8. "IOCTLSEL,I/O Pin Backup Control Selection\nWhen low speed 32 kHz oscillator is disabled or TAMPxEN is disabled  PF.4 pin (X32_OUT pin)  PF.5 pin (X32_IN pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. User can program IOCTLSEL to decide.." "0: PF.4~11 pin I/O function is controlled by GPIO..,1: PF.4~11 pin I/O function is controlled by VBAT.."
bitfld.long 0x0 7. "RTCCKSEL,RTC Clock Source Selection" "0: Clock source from external low speed crystal..,1: Clock source from internal low speed RC.."
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bitfld.long 0x0 1.--3. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption." "?,1: L1 mode,?,?,?,?,?,?"
line.long 0x4 "RTC_GPIOCTL0,RTC GPIO Control 0 Register"
bitfld.long 0x4 28.--29. "PUSEL3,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.7 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.7 pull-up and pull-down Disabled,1: PF.7 pull-up Enabled,?,?"
bitfld.long 0x4 27. "DINOFF3,I/O Pin Digital Input Path Disable Bit" "0: PF.7 digital input path Enabled,1: PF.7 digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DOUT3,I/O Output Data" "0: PF.7 output low,1: PF.7 output high"
bitfld.long 0x4 24.--25. "OPMODE3,I/O Operation Mode" "0: PF.7 is input only mode,1: PF.7 is output push pull mode,?,?"
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bitfld.long 0x4 20.--21. "PUSEL2,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.6 I/O Pull-up or Pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.6 pull-up and pull-down Disabled,1: PF.6 pull-up Enabled,?,?"
bitfld.long 0x4 19. "DINOFF2,I/O Pin Digital Input Path Disable Bit" "0: PF.6 digital input path Enabled,1: PF.6 digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DOUT2,I/O Output Data" "0: PF.6 output low,1: PF.6 output high"
bitfld.long 0x4 16.--17. "OPMODE2,I/O Operation Mode" "0: PF.6 is input only mode,1: PF.6 is output push pull mode,?,?"
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bitfld.long 0x4 12.--13. "PUSEL1,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.5 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.5 pull-up and pull-down Disabled,1: PF.5 pull-up Enabled,?,?"
bitfld.long 0x4 11. "DINOFF1,I/O Pin Digital Input Path Disable Bit" "0: PF.5 digital input path Enabled,1: PF.5 digital input path Disabled (digital input.."
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bitfld.long 0x4 10. "DOUT1,I/O Output Data" "0: PF.5 output low,1: PF.5 output high"
bitfld.long 0x4 8.--9. "OPMODE1,I/O Operation Mode" "0: PF.5 is input only mode,1: PF.5 is output push pull mode,?,?"
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bitfld.long 0x4 4.--5. "PUSEL0,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.4 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.4 pull-up and pull-down Disabled,1: PF.4 pull-up Enabled,?,?"
bitfld.long 0x4 3. "DINOFF0,I/O Pin Digital Input Path Disable Bit" "0: PF.4 digital input path Enabled,1: PF.4 digital input path Disabled (digital input.."
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bitfld.long 0x4 2. "DOUT0,I/O Output Data" "0: PF.4 output low,1: PF.4 output high"
bitfld.long 0x4 0.--1. "OPMODE0,I/O Operation Mode" "0: PF.4 is input only mode,1: PF.4 is output push pull mode,?,?"
line.long 0x8 "RTC_GPIOCTL1,RTC GPIO Control 1 Register"
bitfld.long 0x8 28.--29. "PUSEL7,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.11 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid.." "0: PF.11 pull-up and pull-down Disabled,1: PF.11 pull-up Enabled,?,?"
bitfld.long 0x8 27. "DINOFF7,I/O Pin Digital Input Path Disable Bit" "0: PF.11 digital input path Enabled,1: PF.11 digital input path Disabled (digital input.."
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bitfld.long 0x8 26. "DOUT7,I/O Output Data" "0: PF.11 output low,1: PF.11 output high"
bitfld.long 0x8 24.--25. "OPMODE7,I/O Operation Mode" "0: PF.11 is input only mode,1: PF.11 is output push pull mode,?,?"
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bitfld.long 0x8 20.--21. "PUSEL6,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid.." "0: PF.10 pull-up and pull-down Disabled,1: PF.10 pull-up Enabled,?,?"
bitfld.long 0x8 19. "DINOFF6,I/O Pin Digital Input Path Disable Bit" "0: PF.10 digital input path Enabled,1: PF.10 digital input path Disabled (digital input.."
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bitfld.long 0x8 18. "DOUT6,I/O Output Data" "0: PF.10 output low,1: PF.10 output high"
bitfld.long 0x8 16.--17. "OPMODE6,I/O Operation Mode" "0: PF.10 is input only mode,1: PF.10 is output push pull mode,?,?"
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bitfld.long 0x8 12.--13. "PUSEL5,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.9 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.9 pull-up and pull-down Disabled,1: PF.9 pull-up Enabled,?,?"
bitfld.long 0x8 11. "DINOFF5,I/O Pin Digital Input Path Disable Bit" "0: PF.9 digital input path Enabled,1: PF.9 digital input path Disabled (digital input.."
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bitfld.long 0x8 10. "DOUT5,I/O Output Data" "0: PF.9 output low,1: PF.9 output high"
bitfld.long 0x8 8.--9. "OPMODE5,I/O Operation Mode" "0: PF.9 is input only mode,1: PF.9 is output push pull mode,?,?"
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bitfld.long 0x8 4.--5. "PUSEL4,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.8 I/O pull-up or pull-down.\nNote: Basically  the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.8 pull-up and pull-down Disabled,1: PF.8 pull-up Enabled,?,?"
bitfld.long 0x8 3. "DINOFF4,I/O Pin Digital Input Path Disable Bit" "0: PF.8 digital input path Enabled,1: PF.8 digital input path Disabled (digital input.."
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bitfld.long 0x8 2. "DOUT4,I/O Output Data" "0: PF.8 output low,1: PF.8 output high"
bitfld.long 0x8 0.--1. "OPMODE4,I/O Operation Mode" "0: PF.8 is input only mode,1: PF.8 is output push pull mode,?,?"
group.long 0x110++0x3
line.long 0x0 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
bitfld.long 0x0 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Change is not performed,1: Daylight Saving Change is performed"
bitfld.long 0x0 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted one.."
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bitfld.long 0x0 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one hour.."
group.long 0x120++0x3
line.long 0x0 "RTC_TAMPCTL,RTC Tamper Pin Control Register"
bitfld.long 0x0 31. "DYNPR2EN,Dynamic Pair 2 Enable Bit" "0: Static detect,1: Dynamic detect"
bitfld.long 0x0 30. "TAMP5DEN,Tamper 5 De-bounce Enable Bit" "0: Tamper 5 de-bounce Disabled,1: Tamper 5 de-bounce Enabled tamper detection pin.."
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bitfld.long 0x0 29. "TAMP5LV,Tamper 5 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
bitfld.long 0x0 28. "TAMP5EN,Tamper 5 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock." "0: Tamper 5 detect Disabled,1: Tamper 5 detect Enabled"
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bitfld.long 0x0 26. "TAMP4DEN,Tamper 4 De-bounce Enable Bit" "0: Tamper 4 de-bounce Disabled,1: Tamper 4 de-bounce Enabled tamper detection pin.."
bitfld.long 0x0 25. "TAMP4LV,Tamper 4 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x0 24. "TAMP4EN,Tamper4 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock." "0: Tamper 4 detect Disabled,1: Tamper 4 detect Enabled"
bitfld.long 0x0 23. "DYNPR1EN,Dynamic Pair 1 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x0 22. "TAMP3DEN,Tamper 3 De-bounce Enable Bit" "0: Tamper 3 de-bounce Disabled,1: Tamper 3 de-bounce Enabled tamper detection pin.."
bitfld.long 0x0 21. "TAMP3LV,Tamper 3 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x0 20. "TAMP3EN,Tamper 3 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock." "0: Tamper 3 detect Disabled,1: Tamper 3 detect Enabled"
bitfld.long 0x0 18. "TAMP2DEN,Tamper 2 De-bounce Enable Bit" "0: Tamper 2 de-bounce Disabled,1: Tamper 2 de-bounce Enabled tamper detection pin.."
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bitfld.long 0x0 17. "TAMP2LV,Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
bitfld.long 0x0 16. "TAMP2EN,Tamper 2 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock." "0: Tamper 2 detect Disabled,1: Tamper 2 detect Enabled"
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bitfld.long 0x0 15. "DYNPR0EN,Dynamic Pair 0 Enable Bit" "0: Static detect,1: Dynamic detect"
bitfld.long 0x0 14. "TAMP1DEN,Tamper 1 De-bounce Enable Bit" "0: Tamper 1 de-bounce Disabled,1: Tamper 1 de-bounce Enabled tamper detection pin.."
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bitfld.long 0x0 13. "TAMP1LV,Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
bitfld.long 0x0 12. "TAMP1EN,Tamper 1 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock." "0: Tamper 1 detect Disabled,1: Tamper 1 detect Enabled"
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bitfld.long 0x0 10. "TAMP0DEN,Tamper 0 De-bounce Enable Bit" "0: Tamper 0 de-bounce Disabled,1: Tamper 0 de-bounce Enabled tamper detection pin.."
bitfld.long 0x0 9. "TAMP0LV,Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x0 8. "TAMP0EN,Tamper0 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock." "0: Tamper 0 detect Disabled,1: Tamper 0 detect Enabled"
bitfld.long 0x0 5.--7. "DYNRATE,Dynamic Change Rate\nThis item is choice the dynamic tamper output change rate.\nNote: After revising this field  set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately." "0: 210 * RTC_CLK,1: 211 * RTC_CLK,?,?,?,?,?,?"
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bitfld.long 0x0 4. "SEEDRLD,Reload New Seed for PRNG Engine\nSetting this bit  the tamper configuration will be reloaded.\nNote 1: Before this bit is set  the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed.." "0: Generating key based on the current seed,1: Before this bit is set"
bitfld.long 0x0 3. "DYNSRC,Dynamic Reference Pattern\nThis fields determine the new reference pattern when current pattern run out in dynamic pair mode.\nNote: After this bit is modified  the SEEDRLD (RTC_TAMPCTL[4]) should be set." "0: The new reference pattern is generated by random..,1: The new reference pattern is repeated from SEED.."
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bitfld.long 0x0 1. "DYN2ISS,Dynamic Pair 2 Input Source Select\nThis bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\nNote: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set." "0: Tamper input is from Tamper 4,1: Tamper input is from Tamper 0"
bitfld.long 0x0 0. "DYN1ISS,Dynamic Pair 1 Input Source Select\nThis bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\nNote: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set." "0: Tamper input is from Tamper 2,1: Tamper input is from Tamper 0"
group.long 0x128++0x3
line.long 0x0 "RTC_TAMPSEED,RTC Tamper Dynamic Seed Register"
hexmask.long 0x0 0.--31. 1. "SEED,Seed Value"
rgroup.long 0x130++0x7
line.long 0x0 "RTC_TAMPTIME,RTC Tamper Time Register"
hexmask.long.byte 0x0 24.--30. 1. "HZCNT,Index of sub-second counter (0x00~0x7F)"
bitfld.long 0x0 20.--21. "TENHR,10-Hour Time Digit of TAMPER Time (0~2)Note: 24-hour time scale only ." "0,1,2,3"
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hexmask.long.byte 0x0 16.--19. 1. "HR,1-Hour Time Digit of TAMPER Time (0~9)"
bitfld.long 0x0 12.--14. "TENMIN,10-Min Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "MIN,1-Min Time Digit of TAMPER Time (0~9)"
bitfld.long 0x0 4.--6. "TENSEC,10-Sec Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--3. 1. "SEC,1-Sec Time Digit of TAMPER Time (0~9)"
line.long 0x4 "RTC_TAMPCAL,RTC Tamper Calendar Register"
hexmask.long.byte 0x4 20.--23. 1. "TENYEAR,10-Year Calendar Digit of TAMPER Calendar (0~9)"
hexmask.long.byte 0x4 16.--19. 1. "YEAR,1-Year Calendar Digit of TAMPER Calendar (0~9)"
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bitfld.long 0x4 12. "TENMON,10-Month Calendar Digit of TAMPER Calendar (0~1)" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "MON,1-Month Calendar Digit of TAMPER Calendar (0~9)"
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bitfld.long 0x4 4.--5. "TENDAY,10-Day Calendar Digit of TAMPER Calendar (0~3)" "0,1,2,3"
hexmask.long.byte 0x4 0.--3. 1. "DAY,1-Day Calendar Digit of TAMPER Calendar (0~9)"
tree.end
tree "SC (Smart Card Host Interface)"
base ad:0x0
tree "SC0"
base ad:0x40090000
group.long 0x0++0x37
line.long 0x0 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT  the SC will send out an 8-bit data.\nRead Operation:\nBy reading DAT  the SC will return an 8-bit received data.\nNote: If SCEN (SCn_CTL[0]) is not enabled  DAT cannot be.."
line.long 0x4 "SC_CTL,SC Control Register"
rbitfld.long 0x4 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit before writing a new value to RXRTY and TXRTY fields." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
bitfld.long 0x4 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled." "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x4 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved." "0: De-bounce sample card insert once per 384 (128 *..,?,?,?"
bitfld.long 0x4 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred." "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x4 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote 1: The real retry number is TXRTY + 1  so 8 is the maximum retry number.\nNote 2: This field cannot.." "?,1: The real retry number is TXRTY + 1,2: This field cannot be changed when TXRTYEN enabled,?,?,?,?,?"
bitfld.long 0x4 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x4 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote 1: The real retry number is RXRTY + 1  so 8 is the maximum retry number.\nNote 2: This field cannot be.." "?,1: The real retry number is RXRTY + 1,2: This field cannot be changed when RXRTYEN enabled,?,?,?,?,?"
bitfld.long 0x4 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote 1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote 2: In UART mode  RX can receive the data sequence in 1 stop bit or 2 stop bits with.." "0: The stop bit length is 2 ETU,1: The default stop bit length is 2"
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bitfld.long 0x4 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved." "0: All internal timer function Disabled,?,?,?"
hexmask.long.byte 0x4 8.--12. 1. "BGT,Block Guard Time \nNote: The real block guard time is BGT + 1."
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bitfld.long 0x4 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV  the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled  an interrupt will be generated to CPU." "0: Rx Buffer Trigger Level with 1 bytes,1: Rx Buffer Trigger Level with 2 bytes,?,?"
bitfld.long 0x4 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled  this field is ignored." "0: Direct convention,1: Reserved.,?,?"
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bitfld.long 0x4 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nNote 1: If user enables auto convention function  the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After.." "0: Auto-convention Disabled,1: If user enables auto convention function"
bitfld.long 0x4 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function." "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x4 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled  this field is ignored." "0: The receiver Enabled,1: The receiver Disabled"
bitfld.long 0x4 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared  \nNote: SCEN must be set to 1 before filling in other SC registers  or smart card will not work properly." "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
line.long 0x8 "SC_ALTCTL,SC Alternate Control Register"
rbitfld.long 0x8 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_ALTCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
rbitfld.long 0x8 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer2.\nNote: Timer2 is active does not always mean Timer2 is counting the CNT (SCn_TMRCTL2[7:0])." "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x8 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer1.\nNote: Timer1 is active does not always mean Timer1 is counting the CNT (SCn_TMRCTL1[7:0])." "0: Timer1 is not active,1: Timer1 is active"
rbitfld.long 0x8 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer0.\nNote: Timer0 is active does not always mean Timer0 is counting the CNT (SCn_TMRCTL0[23:0])." "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x8 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function." "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
bitfld.long 0x8 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed  hardware will stop any process and then do deactivation sequence if this bit is set. If auto.." "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x8 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation  warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.254.\nWarm-reset:.." "0,1,2,3"
bitfld.long 0x8 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
bitfld.long 0x8 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote 1: When the warm reset sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: When the warm reset sequence completed"
bitfld.long 0x8 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote 1: When the activation sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: When the activation sequence completed"
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bitfld.long 0x8 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote 1: When the deactivation sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: When the deactivation sequence completed"
bitfld.long 0x8 1. "RXRST,Rx Software Reset\nWhen RXRST is set  all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x8 0. "TXRST,TX Software Reset\nWhen TXRST is set  all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers"
line.long 0xC "SC_EGT,SC Extra Guard Time Register"
hexmask.long.byte 0xC 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base."
line.long 0x10 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
hexmask.long.word 0x10 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT  a receiver.."
line.long 0x14 "SC_ETUCTL,SC Element Time Unit Control Register"
hexmask.long.word 0x14 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field  but this field must be greater than 0x04."
line.long 0x18 "SC_INTEN,SC Interrupt Enable Control Register"
bitfld.long 0x18 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt." "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
bitfld.long 0x18 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt." "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x18 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
bitfld.long 0x18 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13])." "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x18 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time." "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
bitfld.long 0x18 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function." "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x18 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function." "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
bitfld.long 0x18 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function." "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x18 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6])  frame error FEF (SCn_STATUS[5])  parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
bitfld.long 0x18 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt." "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x18 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt." "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
line.long 0x1C "SC_INTSTS,SC Interrupt Status Register"
bitfld.long 0x1C 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it." "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor 0x3F"
rbitfld.long 0x1C 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only  user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x1C 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3]))  deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
rbitfld.long 0x1C 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only  user must to clear CINSERT or.." "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x1C 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote 1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote 2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: This bit is valid only when RXBGTEN"
bitfld.long 0x1C 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x1C 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
bitfld.long 0x1C 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x1C 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6])  frame error FEF (SCn_STATUS[5]  parity.." "0: Transfer error interrupt did not occur,1: This field is the status flag of BEF"
rbitfld.long 0x1C 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit  user must write data to DAT (SCn_DAT[7:0]) and then this bit.." "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data.." "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the RXTRGLV.."
line.long 0x20 "SC_STATUS,SC Transfer Status Register"
rbitfld.long 0x20 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status." "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
bitfld.long 0x20 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it." "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over to.."
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bitfld.long 0x20 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: This bit is a flag and cannot generate any interrupt to CPU." "0: No Tx retry transfer,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT  TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register  TXPOINT decreases one." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x20 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status." "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer is.."
bitfld.long 0x20 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]) .." "0: Receiver retries counts is less than RXRTY..,1: This bit can be cleared by writing 1 to it"
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bitfld.long 0x20 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: This bit is a flag and cannot generate any interrupt to CPU.\nNote 3: If CPU enables receiver.." "0: No Rx retry transfer,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device  RXPOINT increases one. When one byte of Rx buffer is read by CPU  RXPOINT decreases one." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x20 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD." "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
bitfld.long 0x20 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote 1: This bit can be cleared by writing '1' to it.\nNote 2: The card detect function will start after SCEN (SCn_CTL[0]) set." "0: No effect,1: This bit can be cleared by writing '1' to it"
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bitfld.long 0x20 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote 1: This bit can be cleared by writing '1' to it.\nNote 2: Card detect function will start after SCEN (SCn_CTL[0]) set." "0: No effect,1: This bit can be cleared by writing '1' to it"
rbitfld.long 0x20 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not." "0: Tx buffer count is less than 4,1: Tx buffer count equals 4"
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rbitfld.long 0x20 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])." "0: Tx buffer is not empty,1: Tx buffer is empty which means the last byte of.."
bitfld.long 0x20 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it." "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full and.."
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bitfld.long 0x20 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is  the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: This bit can be cleared by writing 1 to it"
bitfld.long 0x20 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is  the stop bit following the last data bit or parity bit is detected as logic 0). \nNote 1: This bit can be cleared by.." "0: Receiver frame error flag did not occur,1: This bit can be cleared by writing 1 to it"
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bitfld.long 0x20 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not." "0: Rx buffer count is less than 4,1: Rx buffer count equals 4"
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rbitfld.long 0x20 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not." "0: Rx buffer is not empty,1: Rx buffer is empty which means the last byte of.."
bitfld.long 0x20 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it." "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
line.long 0x24 "SC_PINCTL,SC Pin Control State Register"
rbitfld.long 0x24 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_PINCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
rbitfld.long 0x24 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST." "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x24 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR." "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
rbitfld.long 0x24 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA." "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x24 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is.." "0: SCn_PWR pin is 0,1: SCn_PWR pin is 1"
bitfld.long 0x24 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation  warm reset or deactivation mode  this bit will be changed automatically. Thus  do.." "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x24 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation  warm reset or deactivation mode  this bit will be changed automatically. Thus  do not fill in this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
bitfld.long 0x24 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation  warm reset or deactivation mode  this bit will be changed.." "0: Drive SCn_RST pin to low.\nSCn_RST signal status..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x24 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin.\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
line.long 0x28 "SC_TMRCTL0,SC Internal Timer0 Control Register"
rbitfld.long 0x28 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to the SCn_TMRCTL0 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x28 24.--27. 1. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.253 for programming Timer0."
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hexmask.long.tbyte 0x28 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base."
line.long 0x2C "SC_TMRCTL1,SC Internal Timer1 Control Register"
rbitfld.long 0x2C 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  software should check this bit when writing a new value to SCn_TMRCTL1 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x2C 24.--27. 1. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.253 for programming Timer1."
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hexmask.long.byte 0x2C 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base."
line.long 0x30 "SC_TMRCTL2,SC Internal Timer2 Control Register"
rbitfld.long 0x30 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_TMRCTL2 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x30 24.--27. 1. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.253 for programming Timer2."
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hexmask.long.byte 0x30 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base."
line.long 0x34 "SC_UARTCTL,SC UART Mode Control Register"
bitfld.long 0x34 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0." "0: Even number of logic 1 are transmitted or check..,1: Odd number of logic 1 are transmitted or check.."
bitfld.long 0x34 6. "PBOFF,Parity Bit Disable Bit\nThis bit is used for disable parity check function.\nNote: In smart card mode  this field must be 0 (default setting is with parity bit)." "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).."
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bitfld.long 0x34 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode  this WLS must be 00." "0: Word length is 8 bits,1: Word length is 7 bits,?,?"
bitfld.long 0x34 0. "UARTEN,UART Mode Enable Bit\nSet this bit to enable UART mode function.\nNote 3: When UART mode is enabled  hardware will generate a reset to reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode"
group.long 0x4C++0x3
line.long 0x0 "SC_ACTCTL,SC Activation Control Register"
hexmask.long.byte 0x0 0.--4. 1. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3"
tree.end
tree "SC1"
base ad:0x40091000
group.long 0x0++0x37
line.long 0x0 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT  the SC will send out an 8-bit data.\nRead Operation:\nBy reading DAT  the SC will return an 8-bit received data.\nNote: If SCEN (SCn_CTL[0]) is not enabled  DAT cannot be.."
line.long 0x4 "SC_CTL,SC Control Register"
rbitfld.long 0x4 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit before writing a new value to RXRTY and TXRTY fields." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
bitfld.long 0x4 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled." "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x4 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved." "0: De-bounce sample card insert once per 384 (128 *..,?,?,?"
bitfld.long 0x4 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred." "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x4 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote 1: The real retry number is TXRTY + 1  so 8 is the maximum retry number.\nNote 2: This field cannot.." "?,1: The real retry number is TXRTY + 1,2: This field cannot be changed when TXRTYEN enabled,?,?,?,?,?"
bitfld.long 0x4 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x4 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote 1: The real retry number is RXRTY + 1  so 8 is the maximum retry number.\nNote 2: This field cannot be.." "?,1: The real retry number is RXRTY + 1,2: This field cannot be changed when RXRTYEN enabled,?,?,?,?,?"
bitfld.long 0x4 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote 1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote 2: In UART mode  RX can receive the data sequence in 1 stop bit or 2 stop bits with.." "0: The stop bit length is 2 ETU,1: The default stop bit length is 2"
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bitfld.long 0x4 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved." "0: All internal timer function Disabled,?,?,?"
hexmask.long.byte 0x4 8.--12. 1. "BGT,Block Guard Time \nNote: The real block guard time is BGT + 1."
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bitfld.long 0x4 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV  the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled  an interrupt will be generated to CPU." "0: Rx Buffer Trigger Level with 1 bytes,1: Rx Buffer Trigger Level with 2 bytes,?,?"
bitfld.long 0x4 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled  this field is ignored." "0: Direct convention,1: Reserved.,?,?"
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bitfld.long 0x4 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nNote 1: If user enables auto convention function  the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After.." "0: Auto-convention Disabled,1: If user enables auto convention function"
bitfld.long 0x4 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function." "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x4 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled  this field is ignored." "0: The receiver Enabled,1: The receiver Disabled"
bitfld.long 0x4 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared  \nNote: SCEN must be set to 1 before filling in other SC registers  or smart card will not work properly." "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
line.long 0x8 "SC_ALTCTL,SC Alternate Control Register"
rbitfld.long 0x8 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_ALTCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
rbitfld.long 0x8 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer2.\nNote: Timer2 is active does not always mean Timer2 is counting the CNT (SCn_TMRCTL2[7:0])." "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x8 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer1.\nNote: Timer1 is active does not always mean Timer1 is counting the CNT (SCn_TMRCTL1[7:0])." "0: Timer1 is not active,1: Timer1 is active"
rbitfld.long 0x8 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer0.\nNote: Timer0 is active does not always mean Timer0 is counting the CNT (SCn_TMRCTL0[23:0])." "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x8 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function." "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
bitfld.long 0x8 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed  hardware will stop any process and then do deactivation sequence if this bit is set. If auto.." "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x8 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation  warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.254.\nWarm-reset:.." "0,1,2,3"
bitfld.long 0x8 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
bitfld.long 0x8 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote 1: When the warm reset sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: When the warm reset sequence completed"
bitfld.long 0x8 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote 1: When the activation sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: When the activation sequence completed"
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bitfld.long 0x8 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote 1: When the deactivation sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: When the deactivation sequence completed"
bitfld.long 0x8 1. "RXRST,Rx Software Reset\nWhen RXRST is set  all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x8 0. "TXRST,TX Software Reset\nWhen TXRST is set  all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers"
line.long 0xC "SC_EGT,SC Extra Guard Time Register"
hexmask.long.byte 0xC 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base."
line.long 0x10 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
hexmask.long.word 0x10 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT  a receiver.."
line.long 0x14 "SC_ETUCTL,SC Element Time Unit Control Register"
hexmask.long.word 0x14 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field  but this field must be greater than 0x04."
line.long 0x18 "SC_INTEN,SC Interrupt Enable Control Register"
bitfld.long 0x18 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt." "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
bitfld.long 0x18 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt." "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x18 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
bitfld.long 0x18 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13])." "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x18 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time." "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
bitfld.long 0x18 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function." "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x18 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function." "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
bitfld.long 0x18 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function." "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x18 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6])  frame error FEF (SCn_STATUS[5])  parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
bitfld.long 0x18 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt." "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x18 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt." "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
line.long 0x1C "SC_INTSTS,SC Interrupt Status Register"
bitfld.long 0x1C 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it." "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor 0x3F"
rbitfld.long 0x1C 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only  user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x1C 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3]))  deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
rbitfld.long 0x1C 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only  user must to clear CINSERT or.." "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x1C 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote 1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote 2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: This bit is valid only when RXBGTEN"
bitfld.long 0x1C 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x1C 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
bitfld.long 0x1C 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x1C 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6])  frame error FEF (SCn_STATUS[5]  parity.." "0: Transfer error interrupt did not occur,1: This field is the status flag of BEF"
rbitfld.long 0x1C 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit  user must write data to DAT (SCn_DAT[7:0]) and then this bit.." "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data.." "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the RXTRGLV.."
line.long 0x20 "SC_STATUS,SC Transfer Status Register"
rbitfld.long 0x20 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status." "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
bitfld.long 0x20 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it." "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over to.."
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bitfld.long 0x20 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: This bit is a flag and cannot generate any interrupt to CPU." "0: No Tx retry transfer,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT  TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register  TXPOINT decreases one." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x20 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status." "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer is.."
bitfld.long 0x20 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]) .." "0: Receiver retries counts is less than RXRTY..,1: This bit can be cleared by writing 1 to it"
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bitfld.long 0x20 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: This bit is a flag and cannot generate any interrupt to CPU.\nNote 3: If CPU enables receiver.." "0: No Rx retry transfer,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device  RXPOINT increases one. When one byte of Rx buffer is read by CPU  RXPOINT decreases one." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x20 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD." "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
bitfld.long 0x20 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote 1: This bit can be cleared by writing '1' to it.\nNote 2: The card detect function will start after SCEN (SCn_CTL[0]) set." "0: No effect,1: This bit can be cleared by writing '1' to it"
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bitfld.long 0x20 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote 1: This bit can be cleared by writing '1' to it.\nNote 2: Card detect function will start after SCEN (SCn_CTL[0]) set." "0: No effect,1: This bit can be cleared by writing '1' to it"
rbitfld.long 0x20 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not." "0: Tx buffer count is less than 4,1: Tx buffer count equals 4"
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rbitfld.long 0x20 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])." "0: Tx buffer is not empty,1: Tx buffer is empty which means the last byte of.."
bitfld.long 0x20 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it." "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full and.."
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bitfld.long 0x20 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is  the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: This bit can be cleared by writing 1 to it"
bitfld.long 0x20 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is  the stop bit following the last data bit or parity bit is detected as logic 0). \nNote 1: This bit can be cleared by.." "0: Receiver frame error flag did not occur,1: This bit can be cleared by writing 1 to it"
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bitfld.long 0x20 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not." "0: Rx buffer count is less than 4,1: Rx buffer count equals 4"
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rbitfld.long 0x20 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not." "0: Rx buffer is not empty,1: Rx buffer is empty which means the last byte of.."
bitfld.long 0x20 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it." "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
line.long 0x24 "SC_PINCTL,SC Pin Control State Register"
rbitfld.long 0x24 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_PINCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
rbitfld.long 0x24 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST." "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x24 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR." "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
rbitfld.long 0x24 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA." "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x24 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is.." "0: SCn_PWR pin is 0,1: SCn_PWR pin is 1"
bitfld.long 0x24 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation  warm reset or deactivation mode  this bit will be changed automatically. Thus  do.." "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x24 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation  warm reset or deactivation mode  this bit will be changed automatically. Thus  do not fill in this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
bitfld.long 0x24 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation  warm reset or deactivation mode  this bit will be changed.." "0: Drive SCn_RST pin to low.\nSCn_RST signal status..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x24 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin.\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
line.long 0x28 "SC_TMRCTL0,SC Internal Timer0 Control Register"
rbitfld.long 0x28 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to the SCn_TMRCTL0 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x28 24.--27. 1. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.253 for programming Timer0."
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hexmask.long.tbyte 0x28 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base."
line.long 0x2C "SC_TMRCTL1,SC Internal Timer1 Control Register"
rbitfld.long 0x2C 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  software should check this bit when writing a new value to SCn_TMRCTL1 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x2C 24.--27. 1. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.253 for programming Timer1."
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hexmask.long.byte 0x2C 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base."
line.long 0x30 "SC_TMRCTL2,SC Internal Timer2 Control Register"
rbitfld.long 0x30 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_TMRCTL2 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x30 24.--27. 1. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.253 for programming Timer2."
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hexmask.long.byte 0x30 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base."
line.long 0x34 "SC_UARTCTL,SC UART Mode Control Register"
bitfld.long 0x34 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0." "0: Even number of logic 1 are transmitted or check..,1: Odd number of logic 1 are transmitted or check.."
bitfld.long 0x34 6. "PBOFF,Parity Bit Disable Bit\nThis bit is used for disable parity check function.\nNote: In smart card mode  this field must be 0 (default setting is with parity bit)." "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).."
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bitfld.long 0x34 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode  this WLS must be 00." "0: Word length is 8 bits,1: Word length is 7 bits,?,?"
bitfld.long 0x34 0. "UARTEN,UART Mode Enable Bit\nSet this bit to enable UART mode function.\nNote 3: When UART mode is enabled  hardware will generate a reset to reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode"
group.long 0x4C++0x3
line.long 0x0 "SC_ACTCTL,SC Activation Control Register"
hexmask.long.byte 0x0 0.--4. 1. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3"
tree.end
tree "SC2"
base ad:0x40092000
group.long 0x0++0x37
line.long 0x0 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT  the SC will send out an 8-bit data.\nRead Operation:\nBy reading DAT  the SC will return an 8-bit received data.\nNote: If SCEN (SCn_CTL[0]) is not enabled  DAT cannot be.."
line.long 0x4 "SC_CTL,SC Control Register"
rbitfld.long 0x4 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit before writing a new value to RXRTY and TXRTY fields." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
bitfld.long 0x4 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled." "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x4 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved." "0: De-bounce sample card insert once per 384 (128 *..,?,?,?"
bitfld.long 0x4 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred." "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x4 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote 1: The real retry number is TXRTY + 1  so 8 is the maximum retry number.\nNote 2: This field cannot.." "?,1: The real retry number is TXRTY + 1,2: This field cannot be changed when TXRTYEN enabled,?,?,?,?,?"
bitfld.long 0x4 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x4 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote 1: The real retry number is RXRTY + 1  so 8 is the maximum retry number.\nNote 2: This field cannot be.." "?,1: The real retry number is RXRTY + 1,2: This field cannot be changed when RXRTYEN enabled,?,?,?,?,?"
bitfld.long 0x4 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote 1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote 2: In UART mode  RX can receive the data sequence in 1 stop bit or 2 stop bits with.." "0: The stop bit length is 2 ETU,1: The default stop bit length is 2"
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bitfld.long 0x4 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved." "0: All internal timer function Disabled,?,?,?"
hexmask.long.byte 0x4 8.--12. 1. "BGT,Block Guard Time \nNote: The real block guard time is BGT + 1."
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bitfld.long 0x4 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV  the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled  an interrupt will be generated to CPU." "0: Rx Buffer Trigger Level with 1 bytes,1: Rx Buffer Trigger Level with 2 bytes,?,?"
bitfld.long 0x4 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled  this field is ignored." "0: Direct convention,1: Reserved.,?,?"
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bitfld.long 0x4 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nNote 1: If user enables auto convention function  the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After.." "0: Auto-convention Disabled,1: If user enables auto convention function"
bitfld.long 0x4 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function." "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x4 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled  this field is ignored." "0: The receiver Enabled,1: The receiver Disabled"
bitfld.long 0x4 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared  \nNote: SCEN must be set to 1 before filling in other SC registers  or smart card will not work properly." "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
line.long 0x8 "SC_ALTCTL,SC Alternate Control Register"
rbitfld.long 0x8 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_ALTCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
rbitfld.long 0x8 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer2.\nNote: Timer2 is active does not always mean Timer2 is counting the CNT (SCn_TMRCTL2[7:0])." "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x8 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer1.\nNote: Timer1 is active does not always mean Timer1 is counting the CNT (SCn_TMRCTL1[7:0])." "0: Timer1 is not active,1: Timer1 is active"
rbitfld.long 0x8 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of Timer0.\nNote: Timer0 is active does not always mean Timer0 is counting the CNT (SCn_TMRCTL0[23:0])." "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x8 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function." "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
bitfld.long 0x8 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed  hardware will stop any process and then do deactivation sequence if this bit is set. If auto.." "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x8 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation  warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.254.\nWarm-reset:.." "0,1,2,3"
bitfld.long 0x8 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
bitfld.long 0x8 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote 3: If SCEN (SCn_CTL[0]) is not enabled  this filed cannot be programmed." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote 1: When the warm reset sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: When the warm reset sequence completed"
bitfld.long 0x8 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote 1: When the activation sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: When the activation sequence completed"
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bitfld.long 0x8 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote 1: When the deactivation sequence completed  this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: When the deactivation sequence completed"
bitfld.long 0x8 1. "RXRST,Rx Software Reset\nWhen RXRST is set  all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x8 0. "TXRST,TX Software Reset\nWhen TXRST is set  all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers"
line.long 0xC "SC_EGT,SC Extra Guard Time Register"
hexmask.long.byte 0xC 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base."
line.long 0x10 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
hexmask.long.word 0x10 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT  a receiver.."
line.long 0x14 "SC_ETUCTL,SC Element Time Unit Control Register"
hexmask.long.word 0x14 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field  but this field must be greater than 0x04."
line.long 0x18 "SC_INTEN,SC Interrupt Enable Control Register"
bitfld.long 0x18 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt." "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
bitfld.long 0x18 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt." "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x18 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
bitfld.long 0x18 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13])." "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x18 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time." "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
bitfld.long 0x18 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function." "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x18 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function." "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
bitfld.long 0x18 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function." "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x18 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6])  frame error FEF (SCn_STATUS[5])  parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
bitfld.long 0x18 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt." "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x18 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt." "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
line.long 0x1C "SC_INTSTS,SC Interrupt Status Register"
bitfld.long 0x1C 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it." "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor 0x3F"
rbitfld.long 0x1C 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only  user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x1C 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3]))  deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
rbitfld.long 0x1C 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only  user must to clear CINSERT or.." "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x1C 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote 1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote 2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: This bit is valid only when RXBGTEN"
bitfld.long 0x1C 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x1C 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
bitfld.long 0x1C 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it." "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x1C 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6])  frame error FEF (SCn_STATUS[5]  parity.." "0: Transfer error interrupt did not occur,1: This field is the status flag of BEF"
rbitfld.long 0x1C 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit  user must write data to DAT (SCn_DAT[7:0]) and then this bit.." "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data.." "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the RXTRGLV.."
line.long 0x20 "SC_STATUS,SC Transfer Status Register"
rbitfld.long 0x20 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status." "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
bitfld.long 0x20 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it." "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over to.."
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bitfld.long 0x20 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: This bit is a flag and cannot generate any interrupt to CPU." "0: No Tx retry transfer,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT  TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register  TXPOINT decreases one." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x20 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status." "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer is.."
bitfld.long 0x20 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]) .." "0: Receiver retries counts is less than RXRTY..,1: This bit can be cleared by writing 1 to it"
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bitfld.long 0x20 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: This bit is a flag and cannot generate any interrupt to CPU.\nNote 3: If CPU enables receiver.." "0: No Rx retry transfer,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device  RXPOINT increases one. When one byte of Rx buffer is read by CPU  RXPOINT decreases one." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x20 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD." "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
bitfld.long 0x20 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote 1: This bit can be cleared by writing '1' to it.\nNote 2: The card detect function will start after SCEN (SCn_CTL[0]) set." "0: No effect,1: This bit can be cleared by writing '1' to it"
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bitfld.long 0x20 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote 1: This bit can be cleared by writing '1' to it.\nNote 2: Card detect function will start after SCEN (SCn_CTL[0]) set." "0: No effect,1: This bit can be cleared by writing '1' to it"
rbitfld.long 0x20 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not." "0: Tx buffer count is less than 4,1: Tx buffer count equals 4"
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rbitfld.long 0x20 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])." "0: Tx buffer is not empty,1: Tx buffer is empty which means the last byte of.."
bitfld.long 0x20 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it." "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full and.."
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bitfld.long 0x20 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is  the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: This bit can be cleared by writing 1 to it"
bitfld.long 0x20 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is  the stop bit following the last data bit or parity bit is detected as logic 0). \nNote 1: This bit can be cleared by.." "0: Receiver frame error flag did not occur,1: This bit can be cleared by writing 1 to it"
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bitfld.long 0x20 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit.\nNote 1: This bit can be cleared by writing 1 to it.\nNote 2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: This bit can be cleared by writing 1 to it"
rbitfld.long 0x20 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not." "0: Rx buffer count is less than 4,1: Rx buffer count equals 4"
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rbitfld.long 0x20 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not." "0: Rx buffer is not empty,1: Rx buffer is empty which means the last byte of.."
bitfld.long 0x20 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it." "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
line.long 0x24 "SC_PINCTL,SC Pin Control State Register"
rbitfld.long 0x24 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_PINCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
rbitfld.long 0x24 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST." "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x24 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR." "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
rbitfld.long 0x24 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA." "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x24 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is.." "0: SCn_PWR pin is 0,1: SCn_PWR pin is 1"
bitfld.long 0x24 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation  warm reset or deactivation mode  this bit will be changed automatically. Thus  do.." "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x24 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation  warm reset or deactivation mode  this bit will be changed automatically. Thus  do not fill in this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
bitfld.long 0x24 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation  warm reset or deactivation mode  this bit will be changed.." "0: Drive SCn_RST pin to low.\nSCn_RST signal status..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x24 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin.\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
line.long 0x28 "SC_TMRCTL0,SC Internal Timer0 Control Register"
rbitfld.long 0x28 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to the SCn_TMRCTL0 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x28 24.--27. 1. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.253 for programming Timer0."
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hexmask.long.tbyte 0x28 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base."
line.long 0x2C "SC_TMRCTL1,SC Internal Timer1 Control Register"
rbitfld.long 0x2C 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  software should check this bit when writing a new value to SCn_TMRCTL1 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x2C 24.--27. 1. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.253 for programming Timer1."
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hexmask.long.byte 0x2C 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base."
line.long 0x30 "SC_TMRCTL2,SC Internal Timer2 Control Register"
rbitfld.long 0x30 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization  user should check this bit when writing a new value to SCn_TMRCTL2 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
hexmask.long.byte 0x30 24.--27. 1. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.253 for programming Timer2."
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hexmask.long.byte 0x30 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base."
line.long 0x34 "SC_UARTCTL,SC UART Mode Control Register"
bitfld.long 0x34 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0." "0: Even number of logic 1 are transmitted or check..,1: Odd number of logic 1 are transmitted or check.."
bitfld.long 0x34 6. "PBOFF,Parity Bit Disable Bit\nThis bit is used for disable parity check function.\nNote: In smart card mode  this field must be 0 (default setting is with parity bit)." "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).."
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bitfld.long 0x34 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode  this WLS must be 00." "0: Word length is 8 bits,1: Word length is 7 bits,?,?"
bitfld.long 0x34 0. "UARTEN,UART Mode Enable Bit\nSet this bit to enable UART mode function.\nNote 3: When UART mode is enabled  hardware will generate a reset to reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode"
group.long 0x4C++0x3
line.long 0x0 "SC_ACTCTL,SC Activation Control Register"
hexmask.long.byte 0x0 0.--4. 1. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3"
tree.end
tree.end
tree "SCS (System Controller Space)"
base ad:0xE000E000
group.long 0x10++0xB
line.long 0x0 "SYST_CTRL,SysTick Control and Status Register"
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
line.long 0x4 "SYST_LOAD,SysTick Reload Value Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0."
line.long 0x8 "SYST_VAL,SysTick Current Value Register"
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-Write Protect. The register is write-clear. A software write of any value will clear the.."
group.long 0xD04++0x3
line.long 0x0 "ICSR,Interrupt Control and State Register"
bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception  normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0." "0: No effect.\nNMI exception is not pending,1: Change NMI exception state to pending.\nNMI.."
bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Change PendSV exception state to.."
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bitfld.long 0x0 27. "PENDSVRTC_CAL,PendSV Clear-pending Bit (Write Only)\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit  you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time." "0: No effect,1: Remove the pending state from the PendSV exception"
bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:" "0: No effect.\nSysTick exception is not pending,1: Change SysTick exception state to.."
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bitfld.long 0x0 25. "PENDSTRTC_CAL,SysTick Exception Clear-pending Bit (Write Only)\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit  you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time." "0: No effect,1: Remove the pending state from the SysTick.."
rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set  a pending exception will be serviced on exit from the debug halt state." "0,1"
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rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag  Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers  but not any effect of the.."
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bitfld.long 0x0 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions" "0: There are preempted active exceptions to execute,1: There are no active exceptions or the.."
hexmask.long.byte 0x0 0.--6. 1. "VECTACTIVE,Number of the Current Active Exception"
group.long 0xD0C++0x7
line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register  this field should be 0x05FA  otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
bitfld.long 0x0 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x0 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority " "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request (Write Only)\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence." "0,1"
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bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit (Write Only)\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the.." "0,1"
bitfld.long 0x0 0. "VECTRESET,Vector Reset Request (Write Only)\nWriting 1 to this bit causes a local system reset. This bit self-clears.\nThe effect of writing a 1 to this bit if the processor is not halted in Debug state is unpredictable\nWhen the processor is halted in.." "0,1"
line.long 0x4 "SCR,System Control Register"
bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state  the event signal wakes up the processor from WFE. If the processor is not waiting for an event  the event is registered and affects the next WFE.\nThe processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode." "0: Sleep,1: Deep sleep"
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bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicates Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSet this bit to 1 enable an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR.."
group.long 0xD18++0xB
line.long 0x0 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x0 20.--23. 1. "PRI_6,Priority of system handler 6  UsageFault"
hexmask.long.byte 0x0 12.--15. 1. "PRI_5,Priority of system handler 5  BusFault"
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hexmask.long.byte 0x0 4.--7. 1. "PRI_4,Priority of system handler 4  MemManage"
line.long 0x4 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x4 28.--31. 1. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '15' denotes the lowest priority."
line.long 0x8 "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x8 28.--31. 1. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '15' denotes the lowest priority."
hexmask.long.byte 0x8 20.--23. 1. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '15' denotes the lowest priority."
tree.end
tree "SDH (Secure Digital Host)"
base ad:0x0
tree "SDH0"
base ad:0x4000D000
group.long 0x0++0x7F
line.long 0x0 "SDH_FB_0,Shared Buffer"
hexmask.long 0x0 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x4 "SDH_FB_1,Shared Buffer"
hexmask.long 0x4 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x8 "SDH_FB_2,Shared Buffer"
hexmask.long 0x8 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0xC "SDH_FB_3,Shared Buffer"
hexmask.long 0xC 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x10 "SDH_FB_4,Shared Buffer"
hexmask.long 0x10 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x14 "SDH_FB_5,Shared Buffer"
hexmask.long 0x14 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x18 "SDH_FB_6,Shared Buffer"
hexmask.long 0x18 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x1C "SDH_FB_7,Shared Buffer"
hexmask.long 0x1C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x20 "SDH_FB_8,Shared Buffer"
hexmask.long 0x20 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x24 "SDH_FB_9,Shared Buffer"
hexmask.long 0x24 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x28 "SDH_FB_10,Shared Buffer"
hexmask.long 0x28 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x2C "SDH_FB_11,Shared Buffer"
hexmask.long 0x2C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x30 "SDH_FB_12,Shared Buffer"
hexmask.long 0x30 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x34 "SDH_FB_13,Shared Buffer"
hexmask.long 0x34 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x38 "SDH_FB_14,Shared Buffer"
hexmask.long 0x38 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x3C "SDH_FB_15,Shared Buffer"
hexmask.long 0x3C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x40 "SDH_FB_16,Shared Buffer"
hexmask.long 0x40 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x44 "SDH_FB_17,Shared Buffer"
hexmask.long 0x44 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x48 "SDH_FB_18,Shared Buffer"
hexmask.long 0x48 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x4C "SDH_FB_19,Shared Buffer"
hexmask.long 0x4C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x50 "SDH_FB_20,Shared Buffer"
hexmask.long 0x50 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x54 "SDH_FB_21,Shared Buffer"
hexmask.long 0x54 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x58 "SDH_FB_22,Shared Buffer"
hexmask.long 0x58 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x5C "SDH_FB_23,Shared Buffer"
hexmask.long 0x5C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x60 "SDH_FB_24,Shared Buffer"
hexmask.long 0x60 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x64 "SDH_FB_25,Shared Buffer"
hexmask.long 0x64 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x68 "SDH_FB_26,Shared Buffer"
hexmask.long 0x68 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x6C "SDH_FB_27,Shared Buffer"
hexmask.long 0x6C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x70 "SDH_FB_28,Shared Buffer"
hexmask.long 0x70 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x74 "SDH_FB_29,Shared Buffer"
hexmask.long 0x74 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x78 "SDH_FB_30,Shared Buffer"
hexmask.long 0x78 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x7C "SDH_FB_31,Shared Buffer"
hexmask.long 0x7C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
group.long 0x400++0x3
line.long 0x0 "SDH_DMACTL,DMA Control and Status Register"
bitfld.long 0x0 9. "DMABUSY,DMA Transfer Is in Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not." "0: DMA transfer is not in progress,1: DMA transfer is in progress"
bitfld.long 0x0 3. "SGEN,Scatter-gather Function Enable Bit" "0: Scatter-gather function Disabled (DMA will treat..,1: Scatter-gather function Enabled (DMA will treat.."
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bitfld.long 0x0 1. "DMARST,Software Engine Reset\nNote: The software reset DMA related registers." "0: No effect,1: Reset internal state machine and pointers. The.."
bitfld.long 0x0 0. "DMAEN,DMA Engine Enable Bit\nNote 1: If this bit is cleared  DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote 2: If target abort occurred  DMAEN will be cleared." "0: DMA Disabled,1: If this bit is cleared"
group.long 0x408++0x3
line.long 0x0 "SDH_DMASA,DMA Transfer Starting Address Register"
hexmask.long 0x0 1.--31. 1. "DMASA,DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode  this field will be interpreted as a starting.."
bitfld.long 0x0 0. "ORDER,Determined to the PAD Table Fetching Is in Order or Out of Order" "0: PAD table is fetched in order,1: PAD table is fetched out of order"
rgroup.long 0x40C++0x3
line.long 0x0 "SDH_DMABCNT,DMA Transfer Byte Count Register"
hexmask.long 0x0 0.--25. 1. "BCNT,DMA Transfer Byte Count (Read Only)\nThis field indicates the remained byte count of DMA transfer. The value of this field is valid only when DMA is busy; otherwise  it is 0."
group.long 0x410++0x3
line.long 0x0 "SDH_DMAINTEN,DMA Interrupt Enable Control Register"
bitfld.long 0x0 1. "WEOTIEN,Wrong EOT Encountered Interrupt Enable Bit" "0: Interrupt generation Disabled when wrong EOT is..,1: Interrupt generation Enabled when wrong EOT is.."
bitfld.long 0x0 0. "ABORTIEN,DMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
rgroup.long 0x414++0x3
line.long 0x0 "SDH_DMAINTSTS,DMA Interrupt Status Register"
bitfld.long 0x0 1. "WEOTIF,Wrong EOT Encountered Interrupt Flag (Read Only)\nWhen DMA Scatter-Gather function is enabled  and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD.." "0: No EOT encountered before DMA transfer finished,1: EOT encountered before DMA transfer finished"
bitfld.long 0x0 0. "ABORTIF,DMA Read/Write Target Abort Interrupt Flag (Read Only)\nNote 1: This bit is read only  but can be cleared by writing '1' to it.\nNote 2: When DMA's bus master received ERROR response  it means that target abort is happened. DMA will stop transfer.." "0: No bus ERROR response received,1: This bit is read only"
group.long 0x800++0x7
line.long 0x0 "SDH_GCTL,Global Control and Status Register"
bitfld.long 0x0 1. "SDEN,Secure Digital Functionality Enable Bit" "0: SD functionality Disabled,1: SD functionality Enabled"
bitfld.long 0x0 0. "GCTLRST,Software Engine Reset" "0: No effect,1: Reset SD host. The contents of control register.."
line.long 0x4 "SDH_GINTEN,Global Interrupt Control Register"
bitfld.long 0x4 0. "DTAIEN,DMA READ/WRITE Target Abort Interrupt Enable Bit" "0: DMA READ/WRITE target abort interrupt generation..,1: DMA READ/WRITE target abort interrupt generation.."
rgroup.long 0x808++0x3
line.long 0x0 "SDH_GINTSTS,Global Interrupt Status Register"
bitfld.long 0x0 0. "DTAIF,DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred  please reset all engine.\nNote: This bit is read only .." "0: No bus ERROR response received,1: Bus ERROR response received"
group.long 0x820++0xB
line.long 0x0 "SDH_CTL,SD Control and Status Register"
hexmask.long.byte 0x0 24.--27. 1. "SDNWR,NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1."
hexmask.long.byte 0x0 16.--23. 1. "BLKCNT,Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command  software can use this function to accelerate data transfer and improve.."
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bitfld.long 0x0 15. "DBW,SD Data Bus Width Selection" "0: Data bus width is 1-bit,1: Data bus width is 4-bit"
bitfld.long 0x0 14. "CTLRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and counters."
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hexmask.long.byte 0x0 8.--13. 1. "CMDCODE,SD Command Code\nThe bits contain the SD command code (0x00 - 0x3F)."
bitfld.long 0x0 7. "CLKKEEP,SD Clock Enable Control" "0: SD host decided when to output clock and when to..,1: SD clock always keeps free running"
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bitfld.long 0x0 6. "CLK8OEN,Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will output 8 clock cycles"
bitfld.long 0x0 5. "CLK74OEN,Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will output 74 clock cycles.."
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bitfld.long 0x0 4. "R2EN,Response R2 Input Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will wait to receive a.."
bitfld.long 0x0 3. "DOEN,Data Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will transfer block data.."
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bitfld.long 0x0 2. "DIEN,Data Input Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will wait to receive block.."
bitfld.long 0x0 1. "RIEN,Response Input Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will wait to receive a.."
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bitfld.long 0x0 0. "COEN,Command Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will output a command to SD.."
line.long 0x4 "SDH_CMDARG,SD Command Argument Register"
hexmask.long 0x4 0.--31. 1. "ARGUMENT,SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before trigger COEN (SDH_CTL [0])  software should fill argument in this field."
line.long 0x8 "SDH_INTEN,SD Interrupt Control Register"
bitfld.long 0x8 30. "CDSRC,SD Card Detect Source Selection" "0: From SD card's DAT3 pin,1: From GPIO pin"
bitfld.long 0x8 14. "WKIEN,Wake-up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD controller when card is inserted or removed." "0: SD Card interrupt to wake-up chip Disabled,1: SD Card interrupt to wake-up chip Enabled"
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bitfld.long 0x8 13. "DITOIEN,Data Input Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out. Time-out value is specified at TOUT register." "0: DITOIF (SDH_INTEN[13]) trigger interrupt Disabled,1: DITOIF (SDH_INTEN[13]) trigger interrupt Enabled"
bitfld.long 0x8 12. "RTOIEN,Response Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT register." "0: RTOIF (SDH_INTEN[12]) trigger interrupt Disabled,1: RTOIF (SDH_INTEN[12]) trigger interrupt Enabled"
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bitfld.long 0x8 8. "CDIEN,SD Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card is inserted or removed." "0: CDIF (SDH_INTEN[8]) trigger interrupt Disabled,1: CDIF (SDH_INTEN[8]) trigger interrupt Enabled"
bitfld.long 0x8 1. "CRCIEN,CRC7  CRC16 and CRC Status Error Interrupt Enable Bit" "0: CRCIF (SDH_INTEN[1]) trigger interrupt Disabled,1: CRCIF (SDH_INTEN[1]) trigger interrupt Enabled"
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bitfld.long 0x8 0. "BLKDIEN,Block Transfer Done Interrupt Enable Bit" "0: BLKDIF (SDH_INTEN[0]) trigger interrupt Disabled,1: BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled"
rgroup.long 0x82C++0xB
line.long 0x0 "SDH_INTSTS,SD Interrupt Status Register"
bitfld.long 0x0 18. "DAT1STS,DAT1 Pin Status of SD Card (Read Only)\nThis bit indicates the DAT1 pin status of SD card." "0,1"
bitfld.long 0x0 16. "CDSTS,Card Detect Status of SD (Read Only)\nThis bit indicates the card detect pin status of SD  and is used for card detection. When there is a card inserted in or removed from SD  software should check this bit to confirm if there is really a card.." "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
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bitfld.long 0x0 13. "DITOIF,Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only  but can be cleared by writing '1' to it." "0: Not time-out,1: Data input time-out"
bitfld.long 0x0 12. "RTOIF,Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only  but can be cleared by writing '1' to it." "0: Not time-out,1: Response time-out"
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bitfld.long 0x0 8. "CDIF,SD Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card is inserted or removed. Only when CDIEN (SDH_INTEN[8]) is set to 1  this bit is active.\nNote: This bit is read only  but can be cleared by writing '1' to it." "0: No card is inserted or removed,1: There is a card inserted in or removed from SD"
bitfld.long 0x0 7. "DAT0STS,DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port." "0,1"
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bitfld.long 0x0 4.--6. "CRCSTS,CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer." "?,?,?,?,?,?,?,?"
bitfld.long 0x0 3. "CRC16,CRC16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC16 correctness after data-in transfer." "0: Fault,1: OK"
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bitfld.long 0x0 2. "CRC7,CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in. If that response does not contain CRC7 information (ex. R3)  then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit." "0: Fault,1: OK"
bitfld.long 0x0 1. "CRCIF,CRC7  CRC16 and CRC Status Error Interrupt Flag (Read Only)\nThis bit indicates that SD host has occurred CRC error during response in  data-in or data-out (CRC status error) transfer. When CRC error is occurred  software should reset SD engine." "0: No CRC error is occurred,1: CRC error is occurred"
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bitfld.long 0x0 0. "BLKDIF,Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer  the transfer will be broken.." "0: Not finished yet,1: Done"
line.long 0x4 "SDH_RESP0,SD Receiving Response Token Register 0"
hexmask.long 0x4 0.--31. 1. "RESPTK0,SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token."
line.long 0x8 "SDH_RESP1,SD Receiving Response Token Register 1"
hexmask.long.byte 0x8 0.--7. 1. "RESPTK1,SD Receiving Response Token 1\nThe SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token."
group.long 0x838++0x7
line.long 0x0 "SDH_BLEN,SD Block Length Register"
hexmask.long.word 0x0 0.--10. 1. "BLKLEN,SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN+1.\nNote: The default SD block length is 512 bytes"
line.long 0x4 "SDH_TOUT,SD Response/Data-in Time-out Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TOUT,SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached. The time period depends on SD engine clock.."
tree.end
tree "SDH1"
base ad:0x4000E000
group.long 0x0++0x7F
line.long 0x0 "SDH_FB_0,Shared Buffer"
hexmask.long 0x0 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x4 "SDH_FB_1,Shared Buffer"
hexmask.long 0x4 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x8 "SDH_FB_2,Shared Buffer"
hexmask.long 0x8 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0xC "SDH_FB_3,Shared Buffer"
hexmask.long 0xC 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x10 "SDH_FB_4,Shared Buffer"
hexmask.long 0x10 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x14 "SDH_FB_5,Shared Buffer"
hexmask.long 0x14 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x18 "SDH_FB_6,Shared Buffer"
hexmask.long 0x18 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x1C "SDH_FB_7,Shared Buffer"
hexmask.long 0x1C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x20 "SDH_FB_8,Shared Buffer"
hexmask.long 0x20 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x24 "SDH_FB_9,Shared Buffer"
hexmask.long 0x24 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x28 "SDH_FB_10,Shared Buffer"
hexmask.long 0x28 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x2C "SDH_FB_11,Shared Buffer"
hexmask.long 0x2C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x30 "SDH_FB_12,Shared Buffer"
hexmask.long 0x30 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x34 "SDH_FB_13,Shared Buffer"
hexmask.long 0x34 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x38 "SDH_FB_14,Shared Buffer"
hexmask.long 0x38 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x3C "SDH_FB_15,Shared Buffer"
hexmask.long 0x3C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x40 "SDH_FB_16,Shared Buffer"
hexmask.long 0x40 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x44 "SDH_FB_17,Shared Buffer"
hexmask.long 0x44 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x48 "SDH_FB_18,Shared Buffer"
hexmask.long 0x48 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x4C "SDH_FB_19,Shared Buffer"
hexmask.long 0x4C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x50 "SDH_FB_20,Shared Buffer"
hexmask.long 0x50 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x54 "SDH_FB_21,Shared Buffer"
hexmask.long 0x54 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x58 "SDH_FB_22,Shared Buffer"
hexmask.long 0x58 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x5C "SDH_FB_23,Shared Buffer"
hexmask.long 0x5C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x60 "SDH_FB_24,Shared Buffer"
hexmask.long 0x60 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x64 "SDH_FB_25,Shared Buffer"
hexmask.long 0x64 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x68 "SDH_FB_26,Shared Buffer"
hexmask.long 0x68 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x6C "SDH_FB_27,Shared Buffer"
hexmask.long 0x6C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x70 "SDH_FB_28,Shared Buffer"
hexmask.long 0x70 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x74 "SDH_FB_29,Shared Buffer"
hexmask.long 0x74 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x78 "SDH_FB_30,Shared Buffer"
hexmask.long 0x78 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
line.long 0x7C "SDH_FB_31,Shared Buffer"
hexmask.long 0x7C 0.--31. 1. "SB,SDH Shared Buffer\nSingle 128 Bytes shared buffer for data exchange between system memory and cards."
group.long 0x400++0x3
line.long 0x0 "SDH_DMACTL,DMA Control and Status Register"
bitfld.long 0x0 9. "DMABUSY,DMA Transfer Is in Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not." "0: DMA transfer is not in progress,1: DMA transfer is in progress"
bitfld.long 0x0 3. "SGEN,Scatter-gather Function Enable Bit" "0: Scatter-gather function Disabled (DMA will treat..,1: Scatter-gather function Enabled (DMA will treat.."
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bitfld.long 0x0 1. "DMARST,Software Engine Reset\nNote: The software reset DMA related registers." "0: No effect,1: Reset internal state machine and pointers. The.."
bitfld.long 0x0 0. "DMAEN,DMA Engine Enable Bit\nNote 1: If this bit is cleared  DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote 2: If target abort occurred  DMAEN will be cleared." "0: DMA Disabled,1: If this bit is cleared"
group.long 0x408++0x3
line.long 0x0 "SDH_DMASA,DMA Transfer Starting Address Register"
hexmask.long 0x0 1.--31. 1. "DMASA,DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode  this field will be interpreted as a starting.."
bitfld.long 0x0 0. "ORDER,Determined to the PAD Table Fetching Is in Order or Out of Order" "0: PAD table is fetched in order,1: PAD table is fetched out of order"
rgroup.long 0x40C++0x3
line.long 0x0 "SDH_DMABCNT,DMA Transfer Byte Count Register"
hexmask.long 0x0 0.--25. 1. "BCNT,DMA Transfer Byte Count (Read Only)\nThis field indicates the remained byte count of DMA transfer. The value of this field is valid only when DMA is busy; otherwise  it is 0."
group.long 0x410++0x3
line.long 0x0 "SDH_DMAINTEN,DMA Interrupt Enable Control Register"
bitfld.long 0x0 1. "WEOTIEN,Wrong EOT Encountered Interrupt Enable Bit" "0: Interrupt generation Disabled when wrong EOT is..,1: Interrupt generation Enabled when wrong EOT is.."
bitfld.long 0x0 0. "ABORTIEN,DMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
rgroup.long 0x414++0x3
line.long 0x0 "SDH_DMAINTSTS,DMA Interrupt Status Register"
bitfld.long 0x0 1. "WEOTIF,Wrong EOT Encountered Interrupt Flag (Read Only)\nWhen DMA Scatter-Gather function is enabled  and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD.." "0: No EOT encountered before DMA transfer finished,1: EOT encountered before DMA transfer finished"
bitfld.long 0x0 0. "ABORTIF,DMA Read/Write Target Abort Interrupt Flag (Read Only)\nNote 1: This bit is read only  but can be cleared by writing '1' to it.\nNote 2: When DMA's bus master received ERROR response  it means that target abort is happened. DMA will stop transfer.." "0: No bus ERROR response received,1: This bit is read only"
group.long 0x800++0x7
line.long 0x0 "SDH_GCTL,Global Control and Status Register"
bitfld.long 0x0 1. "SDEN,Secure Digital Functionality Enable Bit" "0: SD functionality Disabled,1: SD functionality Enabled"
bitfld.long 0x0 0. "GCTLRST,Software Engine Reset" "0: No effect,1: Reset SD host. The contents of control register.."
line.long 0x4 "SDH_GINTEN,Global Interrupt Control Register"
bitfld.long 0x4 0. "DTAIEN,DMA READ/WRITE Target Abort Interrupt Enable Bit" "0: DMA READ/WRITE target abort interrupt generation..,1: DMA READ/WRITE target abort interrupt generation.."
rgroup.long 0x808++0x3
line.long 0x0 "SDH_GINTSTS,Global Interrupt Status Register"
bitfld.long 0x0 0. "DTAIF,DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred  please reset all engine.\nNote: This bit is read only .." "0: No bus ERROR response received,1: Bus ERROR response received"
group.long 0x820++0xB
line.long 0x0 "SDH_CTL,SD Control and Status Register"
hexmask.long.byte 0x0 24.--27. 1. "SDNWR,NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1."
hexmask.long.byte 0x0 16.--23. 1. "BLKCNT,Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command  software can use this function to accelerate data transfer and improve.."
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bitfld.long 0x0 15. "DBW,SD Data Bus Width Selection" "0: Data bus width is 1-bit,1: Data bus width is 4-bit"
bitfld.long 0x0 14. "CTLRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and counters."
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hexmask.long.byte 0x0 8.--13. 1. "CMDCODE,SD Command Code\nThe bits contain the SD command code (0x00 - 0x3F)."
bitfld.long 0x0 7. "CLKKEEP,SD Clock Enable Control" "0: SD host decided when to output clock and when to..,1: SD clock always keeps free running"
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bitfld.long 0x0 6. "CLK8OEN,Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will output 8 clock cycles"
bitfld.long 0x0 5. "CLK74OEN,Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will output 74 clock cycles.."
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bitfld.long 0x0 4. "R2EN,Response R2 Input Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will wait to receive a.."
bitfld.long 0x0 3. "DOEN,Data Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will transfer block data.."
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bitfld.long 0x0 2. "DIEN,Data Input Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will wait to receive block.."
bitfld.long 0x0 1. "RIEN,Response Input Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will wait to receive a.."
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bitfld.long 0x0 0. "COEN,Command Output Enable Bit\nNote: When operation is finished  this bit will be cleared automatically  so don't write 0 to this bit (the controller will be abnormal)." "0: No effect. (Please use DMARST (SDH_CTL [0]) to..,1: Enabled. The SD host will output a command to SD.."
line.long 0x4 "SDH_CMDARG,SD Command Argument Register"
hexmask.long 0x4 0.--31. 1. "ARGUMENT,SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before trigger COEN (SDH_CTL [0])  software should fill argument in this field."
line.long 0x8 "SDH_INTEN,SD Interrupt Control Register"
bitfld.long 0x8 30. "CDSRC,SD Card Detect Source Selection" "0: From SD card's DAT3 pin,1: From GPIO pin"
bitfld.long 0x8 14. "WKIEN,Wake-up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD controller when card is inserted or removed." "0: SD Card interrupt to wake-up chip Disabled,1: SD Card interrupt to wake-up chip Enabled"
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bitfld.long 0x8 13. "DITOIEN,Data Input Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out. Time-out value is specified at TOUT register." "0: DITOIF (SDH_INTEN[13]) trigger interrupt Disabled,1: DITOIF (SDH_INTEN[13]) trigger interrupt Enabled"
bitfld.long 0x8 12. "RTOIEN,Response Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT register." "0: RTOIF (SDH_INTEN[12]) trigger interrupt Disabled,1: RTOIF (SDH_INTEN[12]) trigger interrupt Enabled"
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bitfld.long 0x8 8. "CDIEN,SD Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card is inserted or removed." "0: CDIF (SDH_INTEN[8]) trigger interrupt Disabled,1: CDIF (SDH_INTEN[8]) trigger interrupt Enabled"
bitfld.long 0x8 1. "CRCIEN,CRC7  CRC16 and CRC Status Error Interrupt Enable Bit" "0: CRCIF (SDH_INTEN[1]) trigger interrupt Disabled,1: CRCIF (SDH_INTEN[1]) trigger interrupt Enabled"
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bitfld.long 0x8 0. "BLKDIEN,Block Transfer Done Interrupt Enable Bit" "0: BLKDIF (SDH_INTEN[0]) trigger interrupt Disabled,1: BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled"
rgroup.long 0x82C++0xB
line.long 0x0 "SDH_INTSTS,SD Interrupt Status Register"
bitfld.long 0x0 18. "DAT1STS,DAT1 Pin Status of SD Card (Read Only)\nThis bit indicates the DAT1 pin status of SD card." "0,1"
bitfld.long 0x0 16. "CDSTS,Card Detect Status of SD (Read Only)\nThis bit indicates the card detect pin status of SD  and is used for card detection. When there is a card inserted in or removed from SD  software should check this bit to confirm if there is really a card.." "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
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bitfld.long 0x0 13. "DITOIF,Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only  but can be cleared by writing '1' to it." "0: Not time-out,1: Data input time-out"
bitfld.long 0x0 12. "RTOIF,Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only  but can be cleared by writing '1' to it." "0: Not time-out,1: Response time-out"
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bitfld.long 0x0 8. "CDIF,SD Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card is inserted or removed. Only when CDIEN (SDH_INTEN[8]) is set to 1  this bit is active.\nNote: This bit is read only  but can be cleared by writing '1' to it." "0: No card is inserted or removed,1: There is a card inserted in or removed from SD"
bitfld.long 0x0 7. "DAT0STS,DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port." "0,1"
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bitfld.long 0x0 4.--6. "CRCSTS,CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer." "?,?,?,?,?,?,?,?"
bitfld.long 0x0 3. "CRC16,CRC16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC16 correctness after data-in transfer." "0: Fault,1: OK"
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bitfld.long 0x0 2. "CRC7,CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in. If that response does not contain CRC7 information (ex. R3)  then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit." "0: Fault,1: OK"
bitfld.long 0x0 1. "CRCIF,CRC7  CRC16 and CRC Status Error Interrupt Flag (Read Only)\nThis bit indicates that SD host has occurred CRC error during response in  data-in or data-out (CRC status error) transfer. When CRC error is occurred  software should reset SD engine." "0: No CRC error is occurred,1: CRC error is occurred"
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bitfld.long 0x0 0. "BLKDIF,Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer  the transfer will be broken.." "0: Not finished yet,1: Done"
line.long 0x4 "SDH_RESP0,SD Receiving Response Token Register 0"
hexmask.long 0x4 0.--31. 1. "RESPTK0,SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token."
line.long 0x8 "SDH_RESP1,SD Receiving Response Token Register 1"
hexmask.long.byte 0x8 0.--7. 1. "RESPTK1,SD Receiving Response Token 1\nThe SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token."
group.long 0x838++0x7
line.long 0x0 "SDH_BLEN,SD Block Length Register"
hexmask.long.word 0x0 0.--10. 1. "BLKLEN,SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN+1.\nNote: The default SD block length is 512 bytes"
line.long 0x4 "SDH_TOUT,SD Response/Data-in Time-out Register"
hexmask.long.tbyte 0x4 0.--23. 1. "TOUT,SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached. The time period depends on SD engine clock.."
tree.end
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI0"
base ad:0x40061000
group.long 0x0++0x17
line.long 0x0 "SPIx_CTL,SPI Control Register"
bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16  24  and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode  SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode  the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode  this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock  fspi_eclk  and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode  the SPI controller can work with 3-wire interface including SPIx_CLK  SPIx_MISO and SPIx_MOSI pins. (Slave only)\nNote: The value of this register equals to control register SLAVE.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
bitfld.long 0x8 0. "SS,Slave Selection Control\nThis is Master only.\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer  if both TX and RX PDMA functions are enabled  RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error\nThis is SPI Slave mode Only." "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode  TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs  SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode  this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
line.long 0x14 "SPIx_STATUS,SPI Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs  this bit will be set to 1  the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled  this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode  if TX underflow event occurs and the slave select line goes to inactive state  this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode  when the slave select line goes to inactive state  if bit counter is mismatch with DWIDTH  this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0  and the SSLINE is 1  the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications  this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT  RXCNT  TXTHIF  TXFULL  TXEMPTY  RXTHIF  RXFULL  RXEMPTY  and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
rgroup.long 0x18++0x3
line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode. (SPI Slave mode.."
wgroup.long 0x20++0x3
line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
rgroup.long 0x30++0x3
line.long 0x0 "SPIx_RX,SPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1  the receive FIFO.."
group.long 0x60++0xB
line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1  I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode  I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode  I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit  I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL  SPIx_I2SCLK  and SPIx_FIFOCTL registers  user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock   fBCLK  is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source  which is defined in.."
hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1  I2S controller will generate master clock for external audio devices. The frequency of master clock  fMCLK  is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer  if there is more bus clock input  this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled  this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
tree.end
tree "SPI1"
base ad:0x40062000
group.long 0x0++0x17
line.long 0x0 "SPIx_CTL,SPI Control Register"
bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16  24  and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode  SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode  the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode  this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock  fspi_eclk  and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode  the SPI controller can work with 3-wire interface including SPIx_CLK  SPIx_MISO and SPIx_MOSI pins. (Slave only)\nNote: The value of this register equals to control register SLAVE.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
bitfld.long 0x8 0. "SS,Slave Selection Control\nThis is Master only.\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer  if both TX and RX PDMA functions are enabled  RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error\nThis is SPI Slave mode Only." "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode  TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs  SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode  this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
line.long 0x14 "SPIx_STATUS,SPI Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs  this bit will be set to 1  the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled  this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode  if TX underflow event occurs and the slave select line goes to inactive state  this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode  when the slave select line goes to inactive state  if bit counter is mismatch with DWIDTH  this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0  and the SSLINE is 1  the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications  this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT  RXCNT  TXTHIF  TXFULL  TXEMPTY  RXTHIF  RXFULL  RXEMPTY  and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
rgroup.long 0x18++0x3
line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode. (SPI Slave mode.."
wgroup.long 0x20++0x3
line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
rgroup.long 0x30++0x3
line.long 0x0 "SPIx_RX,SPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1  the receive FIFO.."
group.long 0x60++0xB
line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1  I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode  I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode  I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit  I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL  SPIx_I2SCLK  and SPIx_FIFOCTL registers  user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock   fBCLK  is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source  which is defined in.."
hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1  I2S controller will generate master clock for external audio devices. The frequency of master clock  fMCLK  is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer  if there is more bus clock input  this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled  this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
tree.end
tree "SPI2"
base ad:0x40063000
group.long 0x0++0x17
line.long 0x0 "SPIx_CTL,SPI Control Register"
bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16  24  and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode  SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode  the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode  this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock  fspi_eclk  and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode  the SPI controller can work with 3-wire interface including SPIx_CLK  SPIx_MISO and SPIx_MOSI pins. (Slave only)\nNote: The value of this register equals to control register SLAVE.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
bitfld.long 0x8 0. "SS,Slave Selection Control\nThis is Master only.\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer  if both TX and RX PDMA functions are enabled  RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error\nThis is SPI Slave mode Only." "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode  TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs  SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode  this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
line.long 0x14 "SPIx_STATUS,SPI Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs  this bit will be set to 1  the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled  this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode  if TX underflow event occurs and the slave select line goes to inactive state  this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode  when the slave select line goes to inactive state  if bit counter is mismatch with DWIDTH  this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0  and the SSLINE is 1  the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications  this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT  RXCNT  TXTHIF  TXFULL  TXEMPTY  RXTHIF  RXFULL  RXEMPTY  and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
rgroup.long 0x18++0x3
line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode. (SPI Slave mode.."
wgroup.long 0x20++0x3
line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
rgroup.long 0x30++0x3
line.long 0x0 "SPIx_RX,SPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1  the receive FIFO.."
group.long 0x60++0xB
line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1  I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode  I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode  I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit  I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL  SPIx_I2SCLK  and SPIx_FIFOCTL registers  user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock   fBCLK  is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source  which is defined in.."
hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1  I2S controller will generate master clock for external audio devices. The frequency of master clock  fMCLK  is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer  if there is more bus clock input  this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled  this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
tree.end
tree "SPI3"
base ad:0x40064000
group.long 0x0++0x17
line.long 0x0 "SPIx_CTL,SPI Control Register"
bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16  24  and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode  SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode  the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode  this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock  fspi_eclk  and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode  the SPI controller can work with 3-wire interface including SPIx_CLK  SPIx_MISO and SPIx_MOSI pins. (Slave only)\nNote: The value of this register equals to control register SLAVE.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
bitfld.long 0x8 0. "SS,Slave Selection Control\nThis is Master only.\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer  if both TX and RX PDMA functions are enabled  RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error\nThis is SPI Slave mode Only." "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode  TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs  SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode  this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
line.long 0x14 "SPIx_STATUS,SPI Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs  this bit will be set to 1  the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled  this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode  if TX underflow event occurs and the slave select line goes to inactive state  this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode  when the slave select line goes to inactive state  if bit counter is mismatch with DWIDTH  this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0  and the SSLINE is 1  the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications  this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT  RXCNT  TXTHIF  TXFULL  TXEMPTY  RXTHIF  RXFULL  RXEMPTY  and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
rgroup.long 0x18++0x3
line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode. (SPI Slave mode.."
wgroup.long 0x20++0x3
line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
rgroup.long 0x30++0x3
line.long 0x0 "SPIx_RX,SPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1  the receive FIFO.."
group.long 0x60++0xB
line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1  when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1  I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode  I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode  I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit  I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL  SPIx_I2SCLK  and SPIx_FIFOCTL registers  user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock   fBCLK  is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source  which is defined in.."
hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1  I2S controller will generate master clock for external audio devices. The frequency of master clock  fMCLK  is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer  if there is more bus clock input  this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled  this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
tree.end
tree.end
tree "SPIM (SPI Master Mode)"
base ad:0x40007000
group.long 0x0++0x7
line.long 0x0 "SPIM_CTL0,Control and Status Register 0"
hexmask.long.byte 0x0 24.--31. 1. "CMDCODE,Page Program Command Code\nThe Others command codes are Reserved.\nThe DTR read commands '0x0D 0xBD 0xED' improves throughput by transferring address and data on both the falling and rising edge of SPI Flash clock (SPIM_CLK). It is similar to.."
bitfld.long 0x0 22.--23. "OPMODE,SPI Function Operation Mode\nNote 1: After using Normal I/O mode of SPI Flash controller to program the content of external SPI Flash  please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).\nNote 2: In DMA write mode  hardware.." "0: Normal I/O mode. (Note1) (Note3),1: After using Normal I/O mode of SPI Flash..,2: In DMA write mode,3: For external SPI Flash with 32 Mbytes"
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bitfld.long 0x0 20.--21. "BITMODE,SPI Interface Bit Mode\nNote: Only used for normal I/O mode." "0: Standard mode,1: Dual mode,2: Quad mode,3: Reserved."
hexmask.long.byte 0x0 16.--19. 1. "SUSPITV,Suspend Interval\nNote: Only used for normal I/O mode."
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bitfld.long 0x0 15. "QDIODIR,SPI Interface Direction Select for Quad and Dual Mode Only\nNote: Only used for normal I/O mode." "0: Interface signals are input,1: Interface signals are output"
bitfld.long 0x0 13.--14. "BURSTNUM,Transmit/Receive Burst Number\nThis field specifies how many transmit/receive transactions should be executed continuously in one transfer.\nNote: Only used for normal I/O Mode." "0: Only one transmit/receive transaction will be..,1: Two successive transmit/receive transactions..,2: Three successive transmit/receive transactions..,3: Four successive transmit/receive transactions.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Transmit/Receive Bit Length\nThis specifies how many bits are transmitted/received in one transmit/receive transaction.\nNote 1: Only used for normal I/O mode.\nNote 2: Only 8  16  24  and 32 bits are allowed. Other bit length will result in.."
bitfld.long 0x0 7. "IF,Interrupt Flag\nWrite Operation:" "0: No effect.\nThe transfer has not finished yet,1: Write 1 to clear.\nThe transfer has done"
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bitfld.long 0x0 6. "IEN,Interrupt Enable Bit" "0: SPIM Interrupt Disabled,1: SPIM Interrupt Enabled"
bitfld.long 0x0 5. "B4ADDREN,4-byte Address Mode Enable Bit\nNote: Used for DMA write mode  DMA read mode  and DMM mode." "0: 4-byte address mode Disabled and 3-byte address..,1: 4-byte address mode Enabled"
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bitfld.long 0x0 2. "BALEN,Balance the AHB Control Time Between Cipher Enable and Disable Control\nWhen cipher is enabled  the AHB control signal will delay some time caused by the encoding or decoding calculation. Therefore  if setting BALEN to 1  it will make the AHB.." "0,1"
bitfld.long 0x0 0. "CIPHOFF,Cipher Disable Bit" "0: Cipher function Enabled,1: Cipher function Disabled"
line.long 0x4 "SPIM_CTL1,Control Register 1"
hexmask.long.word 0x4 16.--31. 1. "DIVIDER,Clock Divider Register\nThe value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock 'SCLK' on the output SPIM_CLK pin. The desired frequency is obtained according to the following.."
hexmask.long.byte 0x4 8.--11. 1. "IDLETIME,Idle Time Interval\nIn DMM mode  IDLETIME is set to control the minimum idle time between two SPI Flash accesses."
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bitfld.long 0x4 5. "SSACTPOL,Slave Select Active Level\nIt defines the active level of device/slave select signal (SPIM_SS)  as shown in Table 6.291." "0: The SPIM_SS slave select signal is active low,1: The SPIM_SS slave select signal is active high"
bitfld.long 0x4 4. "SS,Slave Select Active Enable Bit\nNote: This interface can only drive one device/slave at a given time. Therefore  the slave selects of the selected device must be set to its active level before starting any read or write transfer. Functional.." "0: SPIM_SS is in active level,1: SPIM_SS is in inactive level (Default)"
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bitfld.long 0x4 3. "CDINVAL,Cache Data Invalid Enable Bit\nWrite Operation:\nRead Operation: No effect\nNote: When SPI Flash memory is page erasing or whole Flash erasing  please set CDINVAL to 0x1. After using normal I/O mode or DMA write mode of SPI Flash controller to.." "0: No effect,1: Set all cache data to be invalid. This bit is.."
bitfld.long 0x4 1. "CACHEOFF,Cache Memory Function Disable Bit" "0: Cache memory function Enabled. (Default),1: Cache memory function Disabled"
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bitfld.long 0x4 0. "SPIMEN,Go and Busy Status\nWrite Operation:\nNote: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress  user should not write to any register of this peripheral." "0: No effect.\nThe transfer has done,1: Start the transfer. This bit remains set during.."
group.long 0xC++0x3
line.long 0x0 "SPIM_RXCLKDLY,RX Clock Delay Control Register"
bitfld.long 0x0 20. "RDEDGE,Sampling Clock Edge Selection of Received Data for Normal I/O Mode  DMA Read Mode  DMA Write Mode  and Direct Memory Mapping Mode Only" "0: Use SPI input clock rising edge to sample..,1: Use SPI input clock falling edge to sample.."
bitfld.long 0x0 16.--18. "RDDLYSEL,Sampling Clock Delay Selection for Received Data for Normal I/O Mode  DMA Read Mode  DMA Write Mode  and Direct Memory Mapping Mode Only\nDetermine the number of inserted delay cycles. Used to adjust the sampling clock of received data to latch.." "0: No delay,1: Delay 1 SPI Flash clock,2: Delay 2 SPI Flash clocks,3: Delay 3 SPI Flash clocks,?,?,?,7: Delay 7 SPI Flash clocks\nNote: The manufacturer.."
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hexmask.long.byte 0x0 8.--15. 1. "PHDELSEL,SPI Flash Phase Delay Time for DMA Write Mode and DMA Read Mode Only\nThe bits set phase delay time between command data phase  address data phase  and dummy cycle phase  where SPI Flash controller will send those phase data to external SPI Flash."
hexmask.long.byte 0x0 0.--7. 1. "DWDELSEL,SPI Flash Deselect Time Interval of DMA Write Mode for DMA Write Mode Only\nThe bits set the deselect time interval of SPI Flash (i.e. time interval of inactive level of SPIM_SS) when SPI Flash controller operates on DMA write mode. (Note1)"
rgroup.long 0x10++0xF
line.long 0x0 "SPIM_RX0,Data Receive Register 0"
hexmask.long 0x0 0.--31. 1. "RXDAT,Data Receive Register\nThe Data Receive Registers hold the received data of the last executed transfer. \nNumber of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  received data are held in the most significant RXDAT.."
line.long 0x4 "SPIM_RX1,Data Receive Register 1"
hexmask.long 0x4 0.--31. 1. "RXDAT,Data Receive Register\nThe Data Receive Registers hold the received data of the last executed transfer. \nNumber of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  received data are held in the most significant RXDAT.."
line.long 0x8 "SPIM_RX2,Data Receive Register 2"
hexmask.long 0x8 0.--31. 1. "RXDAT,Data Receive Register\nThe Data Receive Registers hold the received data of the last executed transfer. \nNumber of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  received data are held in the most significant RXDAT.."
line.long 0xC "SPIM_RX3,Data Receive Register 3"
hexmask.long 0xC 0.--31. 1. "RXDAT,Data Receive Register\nThe Data Receive Registers hold the received data of the last executed transfer. \nNumber of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  received data are held in the most significant RXDAT.."
group.long 0x20++0x1B
line.long 0x0 "SPIM_TX0,Data Transmit Register 0"
hexmask.long 0x0 0.--31. 1. "TXDAT,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in next transfer. \nNumber of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  data are transmitted in the most significant TXDAT register.."
line.long 0x4 "SPIM_TX1,Data Transmit Register 1"
hexmask.long 0x4 0.--31. 1. "TXDAT,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in next transfer. \nNumber of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  data are transmitted in the most significant TXDAT register.."
line.long 0x8 "SPIM_TX2,Data Transmit Register 2"
hexmask.long 0x8 0.--31. 1. "TXDAT,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in next transfer. \nNumber of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  data are transmitted in the most significant TXDAT register.."
line.long 0xC "SPIM_TX3,Data Transmit Register 3"
hexmask.long 0xC 0.--31. 1. "TXDAT,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in next transfer. \nNumber of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0  data are transmitted in the most significant TXDAT register.."
line.long 0x10 "SPIM_SRAMADDR,SRAM Memory Address Register"
hexmask.long 0x10 0.--31. 1. "ADDR,SRAM Memory Address\nFor DMA Read mode  this is the destination address for DMA transfer.\nFor DMA Write mode  this is the source address for DMA transfer.\nNote: This address must be word-aligned."
line.long 0x14 "SPIM_DMACNT,DMA Transfer Byte Count Register"
hexmask.long.tbyte 0x14 0.--23. 1. "DMACNT,DMA Transfer Byte Count Register\nIt indicates the transfer length for DMA process. \nNote 1: The unit for counting is byte.\nNote 2: The number must be the multiple of 4.\nNote 3: Please check specification of used SPI Flash to know maximum byte.."
line.long 0x18 "SPIM_FADDR,SPI Flash Address Register"
hexmask.long 0x18 0.--31. 1. "ADDR,SPI Flash Address Register\nFor DMA Read mode  this is the source address for DMA transfer.\nFor DMA Write mode  this is the destination address for DMA transfer.\nNote 1: This address must be word-aligned.\nNote 2: For external SPI Flash with 32.."
wgroup.long 0x3C++0x7
line.long 0x0 "SPIM_KEY1,Cipher Key1 Register"
hexmask.long 0x0 0.--31. 1. "KEY1,Cipher Key1 Register\nThis is the KEY1 data for cipher function.\nNote 1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000)  the cipher function will be disabled automatically.\nNote 2:.."
line.long 0x4 "SPIM_KEY2,Cipher Key2 Register"
hexmask.long 0x4 0.--31. 1. "KEY2,Cipher Key2 Register\nThis is the KEY2 data for cipher function.\nNote 1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000)  the cipher function will be disabled automatically.\nNote 2:.."
group.long 0x44++0x7
line.long 0x0 "SPIM_DMMCTL,Direct Memory Mapping Mode Control Register"
hexmask.long.byte 0x0 28.--31. 1. "ACTSCLKT,SPI Flash Active SCLK Time for Direct Memory Mapping Mode  DMA Write Mode  and DMA Read Mode Only\nThe bits set time interval between SPIM SS active edge and the position edge of the first serial SPI output clock  as shown in Figure 6.293.\nNote.."
bitfld.long 0x0 26. "UACTSCLK,User Sets SPI Flash Active SCLK Time for Direct Memory Mapping Mode  DMA Write Mode  and DMA Read Mode Only\nNote: When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually  please set UACTSCLK to 1." "0: According to DIVIDER(SPIM_CTL1[31:16])..,1: Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually"
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bitfld.long 0x0 25. "CREN,Continuous Read Mode Enable Bit for Direct Memory Mapping Mode  Read Command Codes 0xBB  0xEB  0xE7  0x0D  0xBD  and 0xED Only\nFor read operations of SPI Flash  commands of fast read quad I/O (0xEB)  word read quad I/O (0xE7)  fast read dual I/O.." "0: Continuous Read Mode Disabled. (Default),1: Continuous Read Mode Enabled"
bitfld.long 0x0 24. "BWEN,16 Bytes Burst Wrap Mode Enable Bit for Direct Memory Mapping Mode  Cache Enable  and Read Command Code 0xEB  and 0xE7 Only\nIn direct memory mapping mode  both of quad read commands '0xEB' and '0xE7' support burst wrap mode for cache application.." "0: Burst Wrap Mode Disabled. (Default),1: Burst Wrap Mode Enabled"
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hexmask.long.byte 0x0 16.--20. 1. "DESELTIM,SPI Flash Deselect Time for Direct Memory Mapping Mode Only\nSet the minimum time width of SPI Flash deselect time (i.e. Minimum SPIM_SS deselect time)  as shown in Figure 6.293.\n(1) Cache function disable:\nNote 3: Please check the used SPI.."
hexmask.long.byte 0x0 8.--15. 1. "CRMDAT,Mode Bits Data for Continuous Read Mode for Direct Memory Mapping Mode Only\nSet the mode bits data for continuous read mode (or performance enhance mode).\nWhen setting this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25])  this reduces.."
line.long 0x4 "SPIM_CTL2,Control Register 2"
hexmask.long.byte 0x4 24.--28. 1. "DCNUM,Dummy Cycle Number for Direct Memory Mapping Mode and DMA Read Mode Only\nSet number of dummy cycles\n(1) For non-DTR command codes 0x03  0x0B  0x3B  0xBB  0xEB  and 0xE7:\nFor command codes 0x0B  0x3B  0xEB  and 0xE7  user only set DCNUM to dummy.."
bitfld.long 0x4 20. "DTRMPOFF,Mode Phase OFF for DTR Command Codes 0x0D  0xBD  and 0xED for Direct Memory Mapping Mode and DMA Read Mode Only\nNote: Please check the used SPI Flash specification to know the mode cycle number (or performance enhance cycle number) for DTR.." "0: Mode cycle number (or performance enhance cycle..,1: mode cycle number (or performance enhance cycle.."
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bitfld.long 0x4 16. "USETEN,User Set Value Enable Bit for Direct Memory Mapping Mode and DMA Read Mode with Read Commands 0x03 0x0B 0x3B 0xBB 0xEB  and 0xE7 Only\nFor DTR command codes 0x0D  0xBD  and 0xED  please set USETEN to 0x1." "0: Hardware circuit of SPI Flash controller will..,1: If DCNUM(SPIM_CTL2[28:24]) and.."
tree.end
tree "SYS (System Control Registers)"
base ad:0x40000000
rgroup.long 0x0++0x3
line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used."
group.long 0x4++0xF
line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
bitfld.long 0x0 8. "CPULKRF,CPU Lockup Reset Flag\nNote 1: Write 1 to clear this bit to 0.\nNote 2: When CPU lockup happened under ICE is connected  this flag will set to 1 but chip will not reset." "0: No reset from CPU lockup happened,1: Write 1 to clear this bit to 0"
bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M4 Core and FMC are reset by software.."
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bitfld.long 0x0 6. "HRESETRF,HRESET Reset Flag\nThe HRESET reset flag is set by the 'Reset Signal' from the HRESET.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: HRESET includes: POR  Reset Pin  LVR  BOD  WDT  WWDT  CPU lockup  CHIP and MCU reset." "0: No reset from HRESET,1: Write 1 to clear this bit to 0"
bitfld.long 0x0 5. "MCURF,MCU Reset Flag\nThe MCU reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from Cortex-M4,1: The Cortex-M4 had issued the reset signal to.."
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bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
bitfld.long 0x0 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit.." "0: No reset from watchdog timer or window watchdog..,1: Write 1 to clear this bit to 0"
bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
bitfld.long 0x4 23. "CANFD3RST,CANFD3 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CANFD3 controller. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: CANFD3 controller normal operation,1: CANFD3 controller reset"
bitfld.long 0x4 22. "CANFD2RST,CANFD2 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CANFD2 controller. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: CANFD2 controller normal operation,1: CANFD2 controller reset"
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bitfld.long 0x4 21. "CANFD1RST,CANFD1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CANFD1 controller. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: CANFD1 controller normal operation,1: CANFD1 controller reset"
bitfld.long 0x4 20. "CANFD0RST,CANFD0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CANFD0 controller. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: CANFD0 controller normal operation,1: CANFD0 controller reset"
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bitfld.long 0x4 18. "PDMA1RST,PDMA1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA1 controller. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA1 controller normal operation,1: PDMA1 controller reset"
bitfld.long 0x4 17. "SDH1RST,SDH1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDH1 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: SDH1 controller normal operation,1: SDH1 controller reset"
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bitfld.long 0x4 16. "HSUSBHRST,HSUSBH Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the HSUSBH controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: HSUSBH controller normal operation,1: HSUSBH controller reset"
bitfld.long 0x4 14. "SPIMRST,SPIM Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SPIM controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: SPIM controller normal operation,1: SPIM controller reset"
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bitfld.long 0x4 13. "KSRST,Key Store Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the Key Store controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the.." "0: Key Store controller normal operation,1: Key Store controller reset"
bitfld.long 0x4 12. "CRPTRST,CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: CRYPTO controller normal operation,1: CRYPTO controller reset"
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bitfld.long 0x4 11. "HBIRST,HBI Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the HBI controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: HBI controller normal operation,1: HBI controller reset"
bitfld.long 0x4 10. "HSUSBDRST,HSUSBD Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the HSUSBD controller. User needs to set this bit to 0 to release from the reset state." "0: HSUSBD controller normal operation,1: HSUSBD controller reset"
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bitfld.long 0x4 8. "CCAPRST,CCAP Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CCAP controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CCAP controller normal operation,1: CCAP controller reset"
bitfld.long 0x4 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the.." "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x4 6. "SDH0RST,SDH0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDH0 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: SDH0 controller normal operation,1: SDH0 controller reset"
bitfld.long 0x4 5. "EMA0CRST,EMAC0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EMAC0 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: EMAC0 controller normal operation,1: EMAC0 controller reset"
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bitfld.long 0x4 3. "EBIRST,EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: EBI controller normal operation,1: EBI controller reset"
bitfld.long 0x4 2. "PDMA0RST,PDMA0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA0 controller. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA0 controller normal operation,1: PDMA0 controller reset"
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bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC)  and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset"
bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip  including Processor core and all peripherals  and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset  all the.." "0: Chip normal operation,1: Chip one-shot reset"
line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
bitfld.long 0x8 31. "TRNGRST,TRNG Controller Reset" "0: TRNG controller normal operation,1: TRNG controller reset"
bitfld.long 0x8 30. "HSOTGRST,HSOTG Controller Reset" "0: HSOTG controller normal operation,1: HSOTG controller reset"
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bitfld.long 0x8 29. "I2S0RST,I2S0 Controller Reset" "0: I2S0 controller normal operation,1: I2S0 controller reset"
bitfld.long 0x8 28. "EADC0RST,EADC0 Controller Reset" "0: EADC0 controller normal operation,1: EADC0 controller reset"
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bitfld.long 0x8 27. "USBDRST,USBD Controller Reset" "0: USBD controller normal operation,1: USBD controller reset"
bitfld.long 0x8 26. "OTGRST,OTG Controller Reset" "0: OTG controller normal operation,1: OTG controller reset"
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bitfld.long 0x8 23. "UART7RST,UART7 Controller Reset" "0: UART7 controller normal operation,1: UART7 controller reset"
bitfld.long 0x8 22. "UART6RST,UART6 Controller Reset" "0: UART6 controller normal operation,1: UART6 controller reset"
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bitfld.long 0x8 21. "UART5RST,UART5 Controller Reset" "0: UART5 controller normal operation,1: UART5 controller reset"
bitfld.long 0x8 20. "UART4RST,UART4 Controller Reset" "0: UART4 controller normal operation,1: UART4 controller reset"
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bitfld.long 0x8 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
bitfld.long 0x8 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x8 15. "SPI2RST,SPI2 Controller Reset" "0: SPI2 controller normal operation,1: SPI2 controller reset"
bitfld.long 0x8 14. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x8 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
bitfld.long 0x8 12. "QSPI0RST,QSPI0 Controller Reset" "0: QSPI0 controller normal operation,1: QSPI0 controller reset"
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bitfld.long 0x8 11. "I2C3RST,I2C3 Controller Reset" "0: I2C3 controller normal operation,1: I2C3 controller reset"
bitfld.long 0x8 10. "I2C2RST,I2C2 Controller Reset" "0: I2C2 controller normal operation,1: I2C2 controller reset"
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bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x8 7. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal operation,1: Analog Comparator 0/1 controller reset"
bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2"
bitfld.long 0xC 31. "EADC1RST,EADC1 Controller Reset" "0: EADC1 controller normal operation,1: EADC1 controller reset"
bitfld.long 0xC 29. "I2S1RST,I2S1 Controller Reset" "0: I2S1 controller normal operation,1: I2S1 controller reset"
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bitfld.long 0xC 27. "ECAP1RST,ECAP1 Controller Reset" "0: ECAP1 controller normal operation,1: ECAP1 controller reset"
bitfld.long 0xC 26. "ECAP0RST,ECAP0 Controller Reset" "0: ECAP0 controller normal operation,1: ECAP0 controller reset"
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bitfld.long 0xC 23. "EQEI1RST,EQEI1 Controller Reset" "0: EQEI1 controller normal operation,1: EQEI1 controller reset"
bitfld.long 0xC 22. "EQEI0RST,EQEI0 Controller Reset" "0: EQEI0 controller normal operation,1: EQEI0 controller reset"
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bitfld.long 0xC 21. "EQEI3RST,EQEI3 Controller Reset" "0: EQEI3 controller normal operation,1: EQEI3 controller reset"
bitfld.long 0xC 20. "EQEI2RST,EQEI2 Controller Reset" "0: EQEI2 controller normal operation,1: EQEI2 controller reset"
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bitfld.long 0xC 19. "BPWM1RST,BPWM1 Controller Reset" "0: BPWM1 controller normal operation,1: BPWM1 controller reset"
bitfld.long 0xC 18. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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bitfld.long 0xC 17. "EPWM1RST,EPWM1 Controller Reset" "0: EPWM1 controller normal operation,1: EPWM1 controller reset"
bitfld.long 0xC 16. "EPWM0RST,EPWM0 Controller Reset" "0: EPWM0 controller normal operation,1: EPWM0 controller reset"
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bitfld.long 0xC 14. "ECAP3RST,ECAP3 Controller Reset" "0: ECAP3 controller normal operation,1: ECAP3 controller reset"
bitfld.long 0xC 13. "ECAP2RST,ECAP2 Controller Reset" "0: ECAP2 controller normal operation,1: ECAP2 controller reset"
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bitfld.long 0xC 12. "DACRST,DAC Controller Reset" "0: DAC controller normal operation,1: DAC controller reset"
bitfld.long 0xC 10. "PSIORST,PSIO Controller Reset" "0: PSIO controller normal operation,1: PSIO controller reset"
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bitfld.long 0xC 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
bitfld.long 0xC 7. "SPI4RST,SPI4 Controller Reset" "0: SPI4 controller normal operation,1: SPI4 controller reset"
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bitfld.long 0xC 6. "SPI3RST,SPI3 Controller Reset" "0: SPI3 controller normal operation,1: SPI3 controller reset"
bitfld.long 0xC 4. "QSPI1RST,QSPI1 Controller Reset" "0: QSPI1 controller normal operation,1: QSPI1 controller reset"
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bitfld.long 0xC 3. "I2C4RST,I2C4 Controller Reset" "0: I2C4 controller normal operation,1: I2C4 controller reset"
bitfld.long 0xC 2. "SC2RST,SC2 Controller Reset" "0: SC2 controller normal operation,1: SC2 controller reset"
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bitfld.long 0xC 1. "SC1RST,SC1 Controller Reset" "0: SC1 controller normal operation,1: SC1 controller reset"
bitfld.long 0xC 0. "SC0RST,SC0 Controller Reset" "0: SC0 controller normal operation,1: SC0 controller reset"
group.long 0x18++0x17
line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
bitfld.long 0x0 16.--18. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Brown-Out Detector threshold voltage is 1.6V,1: Brown-Out Detector threshold voltage is 1.8V,?,?,?,?,?,?"
rbitfld.long 0x0 15. "LVRRDY,Low Voltage Reset Ready Flag (Read Only)\nWhen the LVR function first enable  need more HCLK to wait LVR ready." "0: Low Voltage Reset function not ready,1: Low Voltage Reset function ready"
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bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by LIRC clock,1: 4 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote 1: After enabling the bit  the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit"
bitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0  BOD function disabled  this bit always responds 0." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote 1: The BOD consumes about 100uA in normal mode  the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote 2: This bit is write protected. Refer to the.." "0: BOD operate in normal mode (default),1: The BOD consumes about 100uA in normal mode"
bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the AVDD is.."
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bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: While the Brown-out Detector function is enabled"
bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register"
bitfld.long 0x4 1. "VBATUGEN,VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1  the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result." "0: VBAT unity gain buffer function Disabled (default),1: VBAT unity gain buffer function Enabled"
bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
line.long 0x8 "SYS_IPRST3,Peripheral Reset Control Register 3"
bitfld.long 0x8 17. "UART9RST,UART9 Controller Reset" "0: UART9 controller normal operation,1: UART9 controller reset"
bitfld.long 0x8 16. "UART8RST,UART8 Controller Reset" "0: UART8 controller normal operation,1: UART8 controller reset"
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bitfld.long 0x8 13. "SPI10RST,SPI10 Controller Reset" "0: SPI10 controller normal operation,1: SPI10 controller reset"
bitfld.long 0x8 12. "SPI9RST,SPI9 Controller Reset" "0: SPI9 controller normal operation,1: SPI9 controller reset"
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bitfld.long 0x8 11. "SPI8RST,SPI8 Controller Reset" "0: SPI8 controller normal operation,1: SPI8 controller reset"
bitfld.long 0x8 10. "SPI7RST,SPI7 Controller Reset" "0: SPI7 controller normal operation,1: SPI7 controller reset"
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bitfld.long 0x8 9. "SPI6RST,SPI6 Controller Reset" "0: SPI6 controller normal operation,1: SPI6 controller reset"
bitfld.long 0x8 8. "SPI5RST,SPI5 Controller Reset" "0: SPI5 controller normal operation,1: SPI5 controller reset"
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bitfld.long 0x8 7. "ACMP23RST,Analog Comparator 2/3 Controller Reset" "0: Analog Comparator 2/3 controller normal operation,1: Analog Comparator 2/3 controller reset"
bitfld.long 0x8 6. "EADC2RST,EADC2 Controller Reset" "0: EADC2 controller normal operation,1: EADC2 controller reset"
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bitfld.long 0x8 0. "KPIRST,KPI Controller Reset" "0: KPI controller normal operation,1: KPI controller reset"
line.long 0xC "SYS_PORCTL,Power-On-reset Controller Register"
hexmask.long.word 0xC 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on  the POR circuit generates a reset signal to reset the whole chip function  but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
line.long 0x10 "SYS_VREFCTL,VREF Control Register"
bitfld.long 0x10 25.--26. "VBGISEL,Chip Internal Voltage Band-gap Current Selection Bits (Write Protect) \nNote 1: When ADC conversion source select band-gap voltage  suggest set VBGISEL as 10.\nNote 2: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Band-gap voltage buffer current is 4.2uA,1: When ADC conversion source select band-gap voltage,2: These bits are write protected,?"
bitfld.long 0x10 24. "VBGFEN,Chip Internal Voltage Band-gap Force Enable Bit (Write Protect) \nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Chip internal voltage band-gap controlled by..,1: Chip internal voltage band-gap force enable"
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bitfld.long 0x10 6.--7. "PRELOADSEL,Pre-load Timing Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Pre-load time is 60us for 0.1uF Capacitor,1: Pre-load time is 310us for 1uF Capacitor,?,?"
hexmask.long.byte 0x10 0.--4. 1. "VREFCTL,VREF Control Bits (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
line.long 0x14 "SYS_USBPHY,USB PHY Control Register"
bitfld.long 0x14 25. "HSUSBACT,HSUSB PHY Active Control\nThis bit is used to control HSUSB PHY at reset state or active state.\nNote: After setting HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY  user should keep HSUSB PHY at reset mode at lease 10us before changing to active.." "0: HSUSB PHY at reset state,1: HSUSB PHY at active state"
bitfld.long 0x14 24. "HSUSBEN,HSUSB PHY Enable\nThis bit is used to enable/disable HSUSB PHY." "0: HSUSB PHY Disabled,1: HSUSB PHY Enabled"
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bitfld.long 0x14 16.--17. "HSUSBROLE,HSUSB Role Option (Write Protect)\nThese two bits are used to select the role of HSUSB.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Standard HSUSB Device mode,1: Standard HSUSB Host mode,?,?"
bitfld.long 0x14 8. "USBEN,USB PHY Enable\nThis bit is used to enable/disable USB PHY." "0: USB PHY Disabled,1: USB PHY Enabled"
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bitfld.long 0x14 2. "SBO,Note: This bit must always be kept 1. If set to 0  the result is unpredictable." "0,1"
bitfld.long 0x14 0.--1. "USBROLE,USB Role Option (Write Protect)\nThese two bits are used to select the role of USB.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Standard USB Device mode,1: Standard USB Host mode,?,?"
group.long 0x80++0x27
line.long 0x0 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register"
bitfld.long 0x0 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x0 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x4 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
bitfld.long 0x4 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x4 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x8 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
bitfld.long 0x8 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x8 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0xC "SYS_GPD_MFOS,GPIOD Multiple Function Output Select Register"
bitfld.long 0xC 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0xC 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x10 "SYS_GPE_MFOS,GPIOE Multiple Function Output Select Register"
bitfld.long 0x10 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x10 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x14 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
bitfld.long 0x14 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x14 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x18 "SYS_GPG_MFOS,GPIOG Multiple Function Output Select Register"
bitfld.long 0x18 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x18 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x1C "SYS_GPH_MFOS,GPIOH Multiple Function Output Select Register"
bitfld.long 0x1C 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x1C 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x20 "SYS_GPI_MFOS,GPIOI Multiple Function Output Select Register"
bitfld.long 0x20 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x20 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x20 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
line.long 0x24 "SYS_GPJ_MFOS,GPIOJ Multiple Function Output Select Register"
bitfld.long 0x24 15. "MFOS15,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 14. "MFOS14,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 13. "MFOS13,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 12. "MFOS12,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 11. "MFOS11,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 10. "MFOS10,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 9. "MFOS9,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 8. "MFOS8,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 7. "MFOS7,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 6. "MFOS6,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 5. "MFOS5,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 4. "MFOS4,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 3. "MFOS3,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 2. "MFOS2,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x24 1. "MFOS1,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
bitfld.long 0x24 0. "MFOS0,GPIOA-J Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
group.long 0xC0++0x7
line.long 0x0 "SYS_SRAM_INTCTL,System SRAM Interrupt Enable Control Register"
bitfld.long 0x0 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
line.long 0x4 "SYS_SRAM_STATUS,System SRAM Parity Error Status Register"
bitfld.long 0x4 0. "PERRIF,SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0." "0: No System SRAM parity error,1: System SRAM parity error occur"
rgroup.long 0xC8++0x3
line.long 0x0 "SYS_SRAM_ERRADDR,System SRAM Parity Check Error Address Register"
hexmask.long 0x0 0.--31. 1. "ERRADDR,System SRAM Parity Error Address (Read Only)\nThis register shows system SRAM parity error byte address."
group.long 0xD0++0x3
line.long 0x0 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
bitfld.long 0x0 13. "RSABIST,RSA SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for RSA SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: RSA SRAM BIST Disabled,1: RSA SRAM BIST Enabled"
bitfld.long 0x0 12. "CCAPBIST,CCAP SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CCAP SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CCAP SRAM BIST Disabled,1: CCAP SRAM BIST Enabled"
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bitfld.long 0x0 11. "KSBIST,Key Store SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for Key Store SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Key Store SRAM BIST Disabled,1: Key Store SRAM BIST Enabled"
bitfld.long 0x0 10. "SRBIST2,System SRAM Bank2 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for system SRAM bank2.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System SRAM bank2 BIST Disabled,1: System SRAM bank2 BIST Enabled"
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bitfld.long 0x0 9. "HSUSBHBIST,HSUSBH SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for HSUSBH SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: HSUSBH SRAM BIST Disabled,1: HSUSBH SRAM BIST Enabled"
bitfld.long 0x0 8. "HSUSBDBIST,HSUSBD SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for HSUSBD SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: HSUSBD SRAM BIST Disabled,1: HSUSBD SRAM BIST Enabled"
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bitfld.long 0x0 6. "EMAC0BIST,EMAC0 SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for EMAC0 SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: EMAC0 SRAM BIST Disabled,1: EMAC0 SRAM BIST Enabled"
bitfld.long 0x0 5. "SPIMBIST,SPIM SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SPIM SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SPIM SRAM BIST Disabled,1: SPIM SRAM BIST Enabled"
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bitfld.long 0x0 4. "USBBIST,USB SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for USB SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: USB SRAM BIST Disabled,1: USB SRAM BIST Enabled"
bitfld.long 0x0 3. "CANBIST,CAN SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CAN SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CAN SRAM BIST Disabled,1: CAN SRAM BIST Enabled"
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bitfld.long 0x0 2. "CRBIST,CACHE SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CACHE SRAM BIST Disabled,1: CACHE SRAM BIST Enabled"
bitfld.long 0x0 1. "SRBIST1,System SRAM Bank1 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for system SRAM bank1.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System SRAM bank1 BIST Disabled,1: System SRAM bank1 BIST Enabled"
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bitfld.long 0x0 0. "SRBIST0,System SRAM Bank0 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for system SRAM bank0.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System SRAM bank0 BIST Disabled,1: System SRAM bank0 BIST Enabled"
rgroup.long 0xD4++0x3
line.long 0x0 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
bitfld.long 0x0 29. "RSABEND,RSA SRAM BIST Test Finish (Read Only)" "0: RSA SRAM BIST is active,1: RSA SRAM BIST test finish"
bitfld.long 0x0 28. "CCAPBEND,CCAP BIST Test Finish (Read Only)" "0: CCAP SRAM BIST is active,1: CCAP SRAM BIST test finish"
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bitfld.long 0x0 27. "KSBEND,Key Store SRAM BIST Test Finish (Read Only)" "0: Key Store SRAM BIST is active,1: Key Store SRAM BIST test finish"
bitfld.long 0x0 26. "SRBEND2,System SRAM Bnak2 BIST Test Finish (Read Only)" "0: System SRAM bank2 BIST is active,1: System SRAM bank2 BIST finish"
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bitfld.long 0x0 25. "HSUSBHBEND,HSUSBH SRAM BIST Test Finish (Read Only)" "0: HSUSBH SRAM BIST is active,1: HSUSBH SRAM BIST test finish"
bitfld.long 0x0 24. "HSUSBDBEND,HSUSBD SRAM BIST Test Finish (Read Only)" "0: HSUSBD SRAM BIST is active,1: HSUSBD SRAM BIST test finish"
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bitfld.long 0x0 22. "EMAC0BEND,EMAC0 SRAM BIST Test Finish (Read Only)" "0: EMAC0 SRAM BIST is active,1: EMAC0 SRAM BIST test finish"
bitfld.long 0x0 21. "SPIMBEND,SPIM SRAM BIST Test Finish (Read Only)" "0: SPIM SRAM BIST is active,1: SPIM SRAM BIST test finish"
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bitfld.long 0x0 20. "USBBEND,USB SRAM BIST Test Finish (Read Only)" "0: USB SRAM BIST is active,1: USB SRAM BIST test finish"
bitfld.long 0x0 19. "CANBEND,CAN SRAM BIST Test Finish (Read Only)\nNote: All of the CAN SRAM macros BIST finish  this flag is 1." "0: CAN SRAM BIST is active,1: CAN SRAM BIST test finish"
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bitfld.long 0x0 18. "CRBEND,CACHE SRAM BIST Test Finish (Read Only)" "0: CACHE SRAM BIST is active,1: CACHE SRAM BIST test finish"
bitfld.long 0x0 17. "SRBEND1,System SRAM Bnak1 BIST Test Finish (Read Only)" "0: System SRAM bank1 BIST is active,1: System SRAM bank1 BIST finish"
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bitfld.long 0x0 16. "SRBEND0,System SRAM Bank0 BIST Test Finish (Read Only)" "0: System SRAM bank0 BIST active,1: System SRAM bank0 BIST finish"
bitfld.long 0x0 13. "RSABISTE,RSA SRAM BIST Fail Flag (Read Only)" "0: RSA SRAM BIST test pass,1: RSA SRAM BIST test fail"
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bitfld.long 0x0 12. "CCAPBISTEF,CCAP SRAM BIST Fail Flag (Read Only)" "0: CCAP SRAM BIST test pass,1: CCAP SRAM BIST test fail"
bitfld.long 0x0 11. "KSBISTEF,Key Store SRAM BIST Fail Flag (Read Only)" "0: Key Store SRAM BIST test pass,1: Key Store SRAM BIST test fail"
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bitfld.long 0x0 10. "SRBISTEF2,System Bnak2 SRAM BIST Fail Flag (Read Only)" "0: System SRAM bank2 BIST test pass,1: System SRAM bank2 BIST test fail"
bitfld.long 0x0 9. "HSUSBHBEF,HSUSBH SRAM BIST Fail Flag (Read Only)" "0: HSUSBH SRAM BIST test pass,1: HSUSBH SRAM BIST test fail"
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bitfld.long 0x0 8. "HSUSBDBEF,HSUSBD SRAM BIST Fail Flag (Read Only)" "0: HSUSBD SRAM BIST test pass,1: HSUSBD SRAM BIST test fail"
bitfld.long 0x0 6. "EMAC0BEF,EMAC0 SRAM BIST Fail Flag (Read Only)" "0: EMAC0 SRAM BIST test pass,1: EMAC0 SRAM BIST test fail"
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bitfld.long 0x0 5. "SPIMBEF,SPIM SRAM BIST Fail Flag (Read Only)" "0: SPIM SRAM BIST test pass,1: SPIM SRAM BIST test fail"
bitfld.long 0x0 4. "USBBEF,USB SRAM BIST Fail Flag (Read Only)" "0: USB SRAM BIST test pass,1: USB SRAM BIST test fail"
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bitfld.long 0x0 3. "CANBEF,CAN SRAM BIST Fail Flag (Read Only)\nNote: Any of the CAN SRAM macros BIST fail  this flag is 1." "0: CAN SRAM BIST test pass,1: CAN SRAM BIST test fail"
bitfld.long 0x0 2. "CRBISTEF,CACHE SRAM BIST Fail Flag (Read Only)" "0: CACHE RAM BIST test pass,1: CACHE RAM BIST test fail"
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bitfld.long 0x0 1. "SRBISTEF1,System SRAM Bank1 BIST Fail Flag (Read Only)" "0: System SRAM bank1 BIST test pass,1: System SRAM bank1 BIST test fail"
bitfld.long 0x0 0. "SRBISTEF0,System SRAM Bank0 BIST Fail Flag (Read Only)" "0: System SRAM bank0 BIST test pass,1: System SRAM bank0 BIST test fail"
group.long 0xE4++0x17
line.long 0x0 "SYS_HIRCTCTL,HIRC48M Trim Control Register"
hexmask.long.byte 0x0 16.--20. 1. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x31  0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTCTL[9]) is enabled."
bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection\nNote: HIRC trim reference clock is 20 kHz in test mode." "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from internal USB.."
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bitfld.long 0x0 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked  the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example  if LOOPSEL is set as 00  auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48M) auto trim.\nDuring auto trim operation  if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
line.long 0x4 "SYS_HIRCTIEN,HIRC48M Trim Interrupt Enable Register"
bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1  and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation  an interrupt will.." "0: Disable CLKERRIF(SYS_HIRCTISTS[2]) status to..,1: Enable CLKERRIF(SYS_HIRCTISTS[2]) status to.."
bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_HIRCTISTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTISTS[1]) status to.."
line.long 0x8 "SYS_HIRCTISTS,HIRC48M Trim Interrupt Status Register"
bitfld.long 0x8 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set  if there occurs the over boundary condition  this flag will be set.\nNote: Write 1 to clear this flag." "0: Over boundary condition did not occur,1: Over boundary condition occurred"
bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC48M) is shift larger to unreasonable value  this bit will be set and to be an indicate.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set  the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically  if the frequency is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
line.long 0xC "SYS_IRCTCTL,HIRC Trim Control Register"
hexmask.long.byte 0xC 16.--20. 1. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x31  0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled."
bitfld.long 0xC 10. "REFCKSEL,Reference Clock Selection\nNote: HIRC trim reference clock is 20 kHz in test mode." "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from internal USB.."
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bitfld.long 0xC 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
bitfld.long 0xC 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0xC 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked  the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
bitfld.long 0xC 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example  if LOOPSEL is set as 00  auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0xC 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation  if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
line.long 0x10 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
bitfld.long 0x10 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1  and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation  an interrupt will be.." "0: Disable CLKERRIF(SYS_IRCTISTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTISTS[2]) status to.."
bitfld.long 0x10 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_IRCTISTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTISTS[1]) status to.."
line.long 0x14 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
bitfld.long 0x14 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set  if there occurs the over boundary condition  this flag will be set.\nNote: Write 1 to clear this flag." "0: Over boundary condition did not occur,1: Over boundary condition occurred"
bitfld.long 0x14 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value  this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x14 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set  the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
bitfld.long 0x14 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically  if the frequency is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
wgroup.long 0x100++0x3
line.long 0x0 "SYS_REGLCTL,Register Lock Control Register"
hexmask.long.byte 0x0 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h'  '16h'  '88h' to this field. After this sequence is.."
group.long 0x1EC++0x3
line.long 0x0 "SYS_PORDISAN,Analog POR Disable Control Register"
hexmask.long.word 0x0 0.--15. 1. "POROFFAN,Power-on Reset Enable Bit (Write Protect)\nAfter powered on  User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or.."
rgroup.long 0x1F4++0x3
line.long 0x0 "SYS_CSERVER,Chip Series Version Register"
hexmask.long.byte 0x0 0.--7. 1. "VERSION,Chip Series Version (Read Only)\nThese bits indicate the series version of chip."
group.long 0x1F8++0x3
line.long 0x0 "SYS_PLCTL,Power Level Control Register"
hexmask.long.byte 0x0 24.--31. 1. "LVSPRD,LDO Voltage Scaling Period (Write Protect)\nThe LVSPRD value is the period of each LDO voltage rising step.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
hexmask.long.byte 0x0 16.--21. 1. "LVSSTEP,LDO Voltage Scaling Step (Write Protect)\nThe LVSSTEP value is LDO voltage rising step.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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bitfld.long 0x0 0.--1. "PLSEL,Power Level Select (Write Protect)\nThese bits indicate the status of power level.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Power level is PL0,1: Power level is PL1,?,?"
rgroup.long 0x1FC++0x3
line.long 0x0 "SYS_PLSTS,Power Level Status Register"
bitfld.long 0x0 8.--9. "PLSTATUS,Power Level Status (Read Only)\nThis bit indicates the status of power level." "0: Power level is PL0,1: Power level is PL1,?,?"
bitfld.long 0x0 0. "PLCBUSY,Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing. After power level change is completed  this bit will be cleared automatically by hardware." "0: Core voltage change is completed,1: Core voltage change is ongoing"
group.long 0x400++0x3
line.long 0x0 "SYS_AHBMCTL,AHB Bus Matrix Priority Control Register"
bitfld.long 0x0 0. "INTACTEN,Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect)\nEnable Cortex-M4 Core with Highest AHB Bus Priority in AHB Bus Matrix.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Round-robin mode,1: Cortex-M4 CPU with highest bus priority when.."
group.long 0x500++0x9F
line.long 0x0 "SYS_GPA_MFP0,GPIOA Multiple Function Control Register 0"
hexmask.long.byte 0x0 24.--28. 1. "PA3MFP,PA.3 Multi-function Pin Selection"
hexmask.long.byte 0x0 16.--20. 1. "PA2MFP,PA.2 Multi-function Pin Selection"
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hexmask.long.byte 0x0 8.--12. 1. "PA1MFP,PA.1 Multi-function Pin Selection"
hexmask.long.byte 0x0 0.--4. 1. "PA0MFP,PA.0 Multi-function Pin Selection"
line.long 0x4 "SYS_GPA_MFP1,GPIOA Multiple Function Control Register 1"
hexmask.long.byte 0x4 24.--28. 1. "PA7MFP,PA.7 Multi-function Pin Selection"
hexmask.long.byte 0x4 16.--20. 1. "PA6MFP,PA.6 Multi-function Pin Selection"
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hexmask.long.byte 0x4 8.--12. 1. "PA5MFP,PA.5 Multi-function Pin Selection"
hexmask.long.byte 0x4 0.--4. 1. "PA4MFP,PA.4 Multi-function Pin Selection"
line.long 0x8 "SYS_GPA_MFP2,GPIOA Multiple Function Control Register 2"
hexmask.long.byte 0x8 24.--28. 1. "PA11MFP,PA.11 Multi-function Pin Selection"
hexmask.long.byte 0x8 16.--20. 1. "PA10MFP,PA.10 Multi-function Pin Selection"
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hexmask.long.byte 0x8 8.--12. 1. "PA9MFP,PA.9 Multi-function Pin Selection"
hexmask.long.byte 0x8 0.--4. 1. "PA8MFP,PA.8 Multi-function Pin Selection"
line.long 0xC "SYS_GPA_MFP3,GPIOA Multiple Function Control Register 3"
hexmask.long.byte 0xC 24.--28. 1. "PA15MFP,PA.15 Multi-function Pin Selection"
hexmask.long.byte 0xC 16.--20. 1. "PA14MFP,PA.14 Multi-function Pin Selection"
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hexmask.long.byte 0xC 8.--12. 1. "PA13MFP,PA.13 Multi-function Pin Selection"
hexmask.long.byte 0xC 0.--4. 1. "PA12MFP,PA.12 Multi-function Pin Selection"
line.long 0x10 "SYS_GPB_MFP0,GPIOB Multiple Function Control Register 0"
hexmask.long.byte 0x10 24.--28. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
hexmask.long.byte 0x10 16.--20. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
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hexmask.long.byte 0x10 8.--12. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
hexmask.long.byte 0x10 0.--4. 1. "PB0MFP,PB.0 Multi-function Pin Selection"
line.long 0x14 "SYS_GPB_MFP1,GPIOB Multiple Function Control Register 1"
hexmask.long.byte 0x14 24.--28. 1. "PB7MFP,PB.7 Multi-function Pin Selection"
hexmask.long.byte 0x14 16.--20. 1. "PB6MFP,PB.6 Multi-function Pin Selection"
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hexmask.long.byte 0x14 8.--12. 1. "PB5MFP,PB.5 Multi-function Pin Selection"
hexmask.long.byte 0x14 0.--4. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
line.long 0x18 "SYS_GPB_MFP2,GPIOB Multiple Function Control Register 2"
hexmask.long.byte 0x18 24.--28. 1. "PB11MFP,PB.11 Multi-function Pin Selection"
hexmask.long.byte 0x18 16.--20. 1. "PB10MFP,PB.10 Multi-function Pin Selection"
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hexmask.long.byte 0x18 8.--12. 1. "PB9MFP,PB.9 Multi-function Pin Selection"
hexmask.long.byte 0x18 0.--4. 1. "PB8MFP,PB.8 Multi-function Pin Selection"
line.long 0x1C "SYS_GPB_MFP3,GPIOB Multiple Function Control Register 3"
hexmask.long.byte 0x1C 24.--28. 1. "PB15MFP,PB.15 Multi-function Pin Selection"
hexmask.long.byte 0x1C 16.--20. 1. "PB14MFP,PB.14 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 8.--12. 1. "PB13MFP,PB.13 Multi-function Pin Selection"
hexmask.long.byte 0x1C 0.--4. 1. "PB12MFP,PB.12 Multi-function Pin Selection"
line.long 0x20 "SYS_GPC_MFP0,GPIOC Multiple Function Control Register 0"
hexmask.long.byte 0x20 24.--28. 1. "PC3MFP,PC.3 Multi-function Pin Selection"
hexmask.long.byte 0x20 16.--20. 1. "PC2MFP,PC.2 Multi-function Pin Selection"
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hexmask.long.byte 0x20 8.--12. 1. "PC1MFP,PC.1 Multi-function Pin Selection"
hexmask.long.byte 0x20 0.--4. 1. "PC0MFP,PC.0 Multi-function Pin Selection"
line.long 0x24 "SYS_GPC_MFP1,GPIOC Multiple Function Control Register 1"
hexmask.long.byte 0x24 24.--28. 1. "PC7MFP,PC.7 Multi-function Pin Selection"
hexmask.long.byte 0x24 16.--20. 1. "PC6MFP,PC.6 Multi-function Pin Selection"
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hexmask.long.byte 0x24 8.--12. 1. "PC5MFP,PC.5 Multi-function Pin Selection"
hexmask.long.byte 0x24 0.--4. 1. "PC4MFP,PC.4 Multi-function Pin Selection"
line.long 0x28 "SYS_GPC_MFP2,GPIOC Multiple Function Control Register 2"
hexmask.long.byte 0x28 24.--28. 1. "PC11MFP,PC.11 Multi-function Pin Selection"
hexmask.long.byte 0x28 16.--20. 1. "PC10MFP,PC.10 Multi-function Pin Selection"
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hexmask.long.byte 0x28 8.--12. 1. "PC9MFP,PC.9 Multi-function Pin Selection"
hexmask.long.byte 0x28 0.--4. 1. "PC8MFP,PC.8 Multi-function Pin Selection"
line.long 0x2C "SYS_GPC_MFP3,GPIOC Multiple Function Control Register 3"
hexmask.long.byte 0x2C 24.--28. 1. "PC15MFP,PC.15 Multi-function Pin Selection"
hexmask.long.byte 0x2C 16.--20. 1. "PC14MFP,PC.14 Multi-function Pin Selection"
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hexmask.long.byte 0x2C 8.--12. 1. "PC13MFP,PC.13 Multi-function Pin Selection"
hexmask.long.byte 0x2C 0.--4. 1. "PC12MFP,PC.12 Multi-function Pin Selection"
line.long 0x30 "SYS_GPD_MFP0,GPIOD Multiple Function Control Register 0"
hexmask.long.byte 0x30 24.--28. 1. "PD3MFP,PD.3 Multi-function Pin Selection"
hexmask.long.byte 0x30 16.--20. 1. "PD2MFP,PD.2 Multi-function Pin Selection"
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hexmask.long.byte 0x30 8.--12. 1. "PD1MFP,PD.1 Multi-function Pin Selection"
hexmask.long.byte 0x30 0.--4. 1. "PD0MFP,PD.0 Multi-function Pin Selection"
line.long 0x34 "SYS_GPD_MFP1,GPIOD Multiple Function Control Register 1"
hexmask.long.byte 0x34 24.--28. 1. "PD7MFP,PD.7 Multi-function Pin Selection"
hexmask.long.byte 0x34 16.--20. 1. "PD6MFP,PD.6 Multi-function Pin Selection"
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hexmask.long.byte 0x34 8.--12. 1. "PD5MFP,PD.5 Multi-function Pin Selection"
hexmask.long.byte 0x34 0.--4. 1. "PD4MFP,PD.4 Multi-function Pin Selection"
line.long 0x38 "SYS_GPD_MFP2,GPIOD Multiple Function Control Register 2"
hexmask.long.byte 0x38 24.--28. 1. "PD11MFP,PD.11 Multi-function Pin Selection"
hexmask.long.byte 0x38 16.--20. 1. "PD10MFP,PD.10 Multi-function Pin Selection"
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hexmask.long.byte 0x38 8.--12. 1. "PD9MFP,PD.9 Multi-function Pin Selection"
hexmask.long.byte 0x38 0.--4. 1. "PD8MFP,PD.8 Multi-function Pin Selection"
line.long 0x3C "SYS_GPD_MFP3,GPIOD Multiple Function Control Register 3"
hexmask.long.byte 0x3C 24.--28. 1. "PD15MFP,PD.15 Multi-function Pin Selection"
hexmask.long.byte 0x3C 16.--20. 1. "PD14MFP,PD.14 Multi-function Pin Selection"
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hexmask.long.byte 0x3C 8.--12. 1. "PD13MFP,PD.13 Multi-function Pin Selection"
hexmask.long.byte 0x3C 0.--4. 1. "PD12MFP,PD.12 Multi-function Pin Selection"
line.long 0x40 "SYS_GPE_MFP0,GPIOE Multiple Function Control Register 0"
hexmask.long.byte 0x40 24.--28. 1. "PE3MFP,PE.3 Multi-function Pin Selection"
hexmask.long.byte 0x40 16.--20. 1. "PE2MFP,PE.2 Multi-function Pin Selection"
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hexmask.long.byte 0x40 8.--12. 1. "PE1MFP,PE.1 Multi-function Pin Selection"
hexmask.long.byte 0x40 0.--4. 1. "PE0MFP,PE.0 Multi-function Pin Selection"
line.long 0x44 "SYS_GPE_MFP1,GPIOE Multiple Function Control Register 1"
hexmask.long.byte 0x44 24.--28. 1. "PE7MFP,PE.7 Multi-function Pin Selection"
hexmask.long.byte 0x44 16.--20. 1. "PE6MFP,PE.6 Multi-function Pin Selection"
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hexmask.long.byte 0x44 8.--12. 1. "PE5MFP,PE.5 Multi-function Pin Selection"
hexmask.long.byte 0x44 0.--4. 1. "PE4MFP,PE.4 Multi-function Pin Selection"
line.long 0x48 "SYS_GPE_MFP2,GPIOE Multiple Function Control Register 2"
hexmask.long.byte 0x48 24.--28. 1. "PE11MFP,PE.11 Multi-function Pin Selection"
hexmask.long.byte 0x48 16.--20. 1. "PE10MFP,PE.10 Multi-function Pin Selection"
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hexmask.long.byte 0x48 8.--12. 1. "PE9MFP,PE.9 Multi-function Pin Selection"
hexmask.long.byte 0x48 0.--4. 1. "PE8MFP,PE.8 Multi-function Pin Selection"
line.long 0x4C "SYS_GPE_MFP3,GPIOE Multiple Function Control Register 3"
hexmask.long.byte 0x4C 24.--28. 1. "PE15MFP,PE.15 Multi-function Pin Selection"
hexmask.long.byte 0x4C 16.--20. 1. "PE14MFP,PE.14 Multi-function Pin Selection"
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hexmask.long.byte 0x4C 8.--12. 1. "PE13MFP,PE.13 Multi-function Pin Selection"
hexmask.long.byte 0x4C 0.--4. 1. "PE12MFP,PE.12 Multi-function Pin Selection"
line.long 0x50 "SYS_GPF_MFP0,GPIOF Multiple Function Control Register 0"
hexmask.long.byte 0x50 24.--28. 1. "PF3MFP,PF.3 Multi-function Pin Selection"
hexmask.long.byte 0x50 16.--20. 1. "PF2MFP,PF.2 Multi-function Pin Selection"
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hexmask.long.byte 0x50 8.--12. 1. "PF1MFP,PF.1 Multi-function Pin Selection"
hexmask.long.byte 0x50 0.--4. 1. "PF0MFP,PF.0 Multi-function Pin Selection"
line.long 0x54 "SYS_GPF_MFP1,GPIOF Multiple Function Control Register 1"
hexmask.long.byte 0x54 24.--28. 1. "PF7MFP,PF.7 Multi-function Pin Selection"
hexmask.long.byte 0x54 16.--20. 1. "PF6MFP,PF.6 Multi-function Pin Selection"
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hexmask.long.byte 0x54 8.--12. 1. "PF5MFP,PF.5 Multi-function Pin Selection"
hexmask.long.byte 0x54 0.--4. 1. "PF4MFP,PF.4 Multi-function Pin Selection"
line.long 0x58 "SYS_GPF_MFP2,GPIOF Multiple Function Control Register 2"
hexmask.long.byte 0x58 24.--28. 1. "PF11MFP,PF.11 Multi-function Pin Selection"
hexmask.long.byte 0x58 16.--20. 1. "PF10MFP,PF.10 Multi-function Pin Selection"
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hexmask.long.byte 0x58 8.--12. 1. "PF9MFP,PF.9 Multi-function Pin Selection"
hexmask.long.byte 0x58 0.--4. 1. "PF8MFP,PF.8 Multi-function Pin Selection"
line.long 0x5C "SYS_GPF_MFP3,GPIOF Multiple Function Control Register 3"
hexmask.long.byte 0x5C 24.--28. 1. "PF15MFP,PF.15 Multi-function Pin Selection"
hexmask.long.byte 0x5C 16.--20. 1. "PF14MFP,PF.14 Multi-function Pin Selection"
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hexmask.long.byte 0x5C 8.--12. 1. "PF13MFP,PF.13 Multi-function Pin Selection"
hexmask.long.byte 0x5C 0.--4. 1. "PF12MFP,PF.12 Multi-function Pin Selection"
line.long 0x60 "SYS_GPG_MFP0,GPIOG Multiple Function Control Register 0"
hexmask.long.byte 0x60 24.--28. 1. "PG3MFP,PG.3 Multi-function Pin Selection"
hexmask.long.byte 0x60 16.--20. 1. "PG2MFP,PG.2 Multi-function Pin Selection"
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hexmask.long.byte 0x60 8.--12. 1. "PG1MFP,PG.1 Multi-function Pin Selection"
hexmask.long.byte 0x60 0.--4. 1. "PG0MFP,PG.0 Multi-function Pin Selection"
line.long 0x64 "SYS_GPG_MFP1,GPIOG Multiple Function Control Register 1"
hexmask.long.byte 0x64 24.--28. 1. "PG7MFP,PG.7 Multi-function Pin Selection"
hexmask.long.byte 0x64 16.--20. 1. "PG6MFP,PG.6 Multi-function Pin Selection"
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hexmask.long.byte 0x64 8.--12. 1. "PG5MFP,PG.5 Multi-function Pin Selection"
hexmask.long.byte 0x64 0.--4. 1. "PG4MFP,PG.4 Multi-function Pin Selection"
line.long 0x68 "SYS_GPG_MFP2,GPIOG Multiple Function Control Register 2"
hexmask.long.byte 0x68 24.--28. 1. "PG11MFP,PG.11 Multi-function Pin Selection"
hexmask.long.byte 0x68 16.--20. 1. "PG10MFP,PG.10 Multi-function Pin Selection"
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hexmask.long.byte 0x68 8.--12. 1. "PG9MFP,PG.9 Multi-function Pin Selection"
hexmask.long.byte 0x68 0.--4. 1. "PG8MFP,PG.8 Multi-function Pin Selection"
line.long 0x6C "SYS_GPG_MFP3,GPIOG Multiple Function Control Register 3"
hexmask.long.byte 0x6C 24.--28. 1. "PG15MFP,PG.15 Multi-function Pin Selection"
hexmask.long.byte 0x6C 16.--20. 1. "PG14MFP,PG.14 Multi-function Pin Selection"
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hexmask.long.byte 0x6C 8.--12. 1. "PG13MFP,PG.13 Multi-function Pin Selection"
hexmask.long.byte 0x6C 0.--4. 1. "PG12MFP,PG.12 Multi-function Pin Selection"
line.long 0x70 "SYS_GPH_MFP0,GPIOH Multiple Function Control Register 0"
hexmask.long.byte 0x70 24.--28. 1. "PH3MFP,PH.3 Multi-function Pin Selection"
hexmask.long.byte 0x70 16.--20. 1. "PH2MFP,PH.2 Multi-function Pin Selection"
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hexmask.long.byte 0x70 8.--12. 1. "PH1MFP,PH.1 Multi-function Pin Selection"
hexmask.long.byte 0x70 0.--4. 1. "PH0MFP,PH.0 Multi-function Pin Selection"
line.long 0x74 "SYS_GPH_MFP1,GPIOH Multiple Function Control Register 1"
hexmask.long.byte 0x74 24.--28. 1. "PH7MFP,PH.7 Multi-function Pin Selection"
hexmask.long.byte 0x74 16.--20. 1. "PH6MFP,PH.6 Multi-function Pin Selection"
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hexmask.long.byte 0x74 8.--12. 1. "PH5MFP,PH.5 Multi-function Pin Selection"
hexmask.long.byte 0x74 0.--4. 1. "PH4MFP,PH.4 Multi-function Pin Selection"
line.long 0x78 "SYS_GPH_MFP2,GPIOH Multiple Function Control Register 2"
hexmask.long.byte 0x78 24.--28. 1. "PH11MFP,PH.11 Multi-function Pin Selection"
hexmask.long.byte 0x78 16.--20. 1. "PH10MFP,PH.10 Multi-function Pin Selection"
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hexmask.long.byte 0x78 8.--12. 1. "PH9MFP,PH.9 Multi-function Pin Selection"
hexmask.long.byte 0x78 0.--4. 1. "PH8MFP,PH.8 Multi-function Pin Selection"
line.long 0x7C "SYS_GPH_MFP3,GPIOH Multiple Function Control Register 3"
hexmask.long.byte 0x7C 24.--28. 1. "PH15MFP,PH.15 Multi-function Pin Selection"
hexmask.long.byte 0x7C 16.--20. 1. "PH14MFP,PH.14 Multi-function Pin Selection"
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hexmask.long.byte 0x7C 8.--12. 1. "PH13MFP,PH.13 Multi-function Pin Selection"
hexmask.long.byte 0x7C 0.--4. 1. "PH12MFP,PH.12 Multi-function Pin Selection"
line.long 0x80 "SYS_GPI_MFP0,GPIOI Multiple Function Control Register 0"
hexmask.long.byte 0x80 24.--28. 1. "PI3MFP,PI.3 Multi-function Pin Selection"
hexmask.long.byte 0x80 16.--20. 1. "PI2MFP,PI.2 Multi-function Pin Selection"
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hexmask.long.byte 0x80 8.--12. 1. "PI1MFP,PI.1 Multi-function Pin Selection"
hexmask.long.byte 0x80 0.--4. 1. "PI0MFP,PI.0 Multi-function Pin Selection"
line.long 0x84 "SYS_GPI_MFP1,GPIOI Multiple Function Control Register 1"
hexmask.long.byte 0x84 24.--28. 1. "PI7MFP,PI.7 Multi-function Pin Selection"
hexmask.long.byte 0x84 16.--20. 1. "PI6MFP,PI.6 Multi-function Pin Selection"
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hexmask.long.byte 0x84 8.--12. 1. "PI5MFP,PI.5 Multi-function Pin Selection"
hexmask.long.byte 0x84 0.--4. 1. "PI4MFP,PI.4 Multi-function Pin Selection"
line.long 0x88 "SYS_GPI_MFP2,GPIOI Multiple Function Control Register 2"
hexmask.long.byte 0x88 24.--28. 1. "PI11MFP,PI.11 Multi-function Pin Selection"
hexmask.long.byte 0x88 16.--20. 1. "PI10MFP,PI.10 Multi-function Pin Selection"
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hexmask.long.byte 0x88 8.--12. 1. "PI9MFP,PI.9 Multi-function Pin Selection"
hexmask.long.byte 0x88 0.--4. 1. "PI8MFP,PI.8 Multi-function Pin Selection"
line.long 0x8C "SYS_GPI_MFP3,GPIOI Multiple Function Control Register 3"
hexmask.long.byte 0x8C 24.--28. 1. "PI15MFP,PI.15 Multi-function Pin Selection"
hexmask.long.byte 0x8C 16.--20. 1. "PI14MFP,PI.14 Multi-function Pin Selection"
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hexmask.long.byte 0x8C 8.--12. 1. "PI13MFP,PI.13 Multi-function Pin Selection"
hexmask.long.byte 0x8C 0.--4. 1. "PI12MFP,PI.12 Multi-function Pin Selection"
line.long 0x90 "SYS_GPJ_MFP0,GPIOJ Multiple Function Control Register 0"
hexmask.long.byte 0x90 24.--28. 1. "PJ3MFP,PJ.3 Multi-function Pin Selection"
hexmask.long.byte 0x90 16.--20. 1. "PJ2MFP,PJ.2 Multi-function Pin Selection"
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hexmask.long.byte 0x90 8.--12. 1. "PJ1MFP,PJ.1 Multi-function Pin Selection"
hexmask.long.byte 0x90 0.--4. 1. "PJ0MFP,PJ.0 Multi-function Pin Selection"
line.long 0x94 "SYS_GPJ_MFP1,GPIOJ Multiple Function Control Register 1"
hexmask.long.byte 0x94 24.--28. 1. "PJ7MFP,PJ.7 Multi-function Pin Selection"
hexmask.long.byte 0x94 16.--20. 1. "PJ6MFP,PJ.6 Multi-function Pin Selection"
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hexmask.long.byte 0x94 8.--12. 1. "PJ5MFP,PJ.5 Multi-function Pin Selection"
hexmask.long.byte 0x94 0.--4. 1. "PJ4MFP,PJ.4 Multi-function Pin Selection"
line.long 0x98 "SYS_GPJ_MFP2,GPIOJ Multiple Function Control Register 2"
hexmask.long.byte 0x98 24.--28. 1. "PJ11MFP,PJ.11 Multi-function Pin Selection"
hexmask.long.byte 0x98 16.--20. 1. "PJ10MFP,PJ.10 Multi-function Pin Selection"
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hexmask.long.byte 0x98 8.--12. 1. "PJ9MFP,PJ.9 Multi-function Pin Selection"
hexmask.long.byte 0x98 0.--4. 1. "PJ8MFP,PJ.8 Multi-function Pin Selection"
line.long 0x9C "SYS_GPJ_MFP3,GPIOJ Multiple Function Control Register 3"
hexmask.long.byte 0x9C 24.--28. 1. "PJ15MFP,PJ.15 Multi-function Pin Selection"
hexmask.long.byte 0x9C 16.--20. 1. "PJ14MFP,PJ.14 Multi-function Pin Selection"
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hexmask.long.byte 0x9C 8.--12. 1. "PJ13MFP,PJ.13 Multi-function Pin Selection"
hexmask.long.byte 0x9C 0.--4. 1. "PJ12MFP,PJ.12 Multi-function Pin Selection"
tree.end
tree "TIMER (Timer Controller)"
base ad:0x0
tree "TMR01"
base ad:0x40050000
group.long 0x0++0xF
line.long 0x0 "TIMER0_CTL,Timer0 Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active  user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Time-out Interrupt Enable Bit\nNote: If this bit is enabled  when the timer time-out interrupt flag TIF is set to 1  the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for event counting function enabled. \nNote: When timer is used as an event counter  this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1  while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled  the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
bitfld.long 0x0 22. "CAPSRC,Capture Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT  CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-Timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also  Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
line.long 0x4 "TIMER0_CMP,Timer0 Comparator Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value  the TIF (TIMERx_INTSTS [0] Timer Interrupt Flag) will be set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT.."
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
line.long 0xC "TIMER0_CNT,Timer0 Data Register"
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register  timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0  user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1  user can read CNT value.."
rgroup.long 0x10++0x3
line.long 0x0 "TIMER0_CAP,Timer0 Capture Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting  CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT.."
group.long 0x14++0x13
line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSC,Timer Capture Source Divider Scale\nThese bits indicate the divide scale for capture source divider. \nNote: Sets CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select capture source."
bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer Capture Edge Detect\nWhen the first capture event is generated  the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "ICAPSEL,Internal Capture Source Select\nNote: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer External Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x0 6. "CAPDBEN,Timer Capture De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection\nNote 1: When CAPFUNCS is 0 and CAPIF becomes 1  the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field.\nNote 2: When CAPFUNCS is 1 and CAPIF becomes 1  the current 24-bit timer counter value.." "0: Capture Mode Enabled,1: When CAPFUNCS is 0 and CAPIF becomes 1"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Function Enable Bit\nThis bit enables the capture input function." "0: Timer capture function Disabled,1: Timer capture function Enabled"
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clears corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag\nThis bit indicates the timer capture interrupt flag status.\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: When CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1  timer time-out interrupt or capture interrupt can be triggered DAC conversion." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
bitfld.long 0x8 1. "TRGPWM,Trigger EPWM and BPWM Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be as EPWM and BPWM counter clock source." "0: Timer interrupt signal as EPWM and BPWM counter..,1: Timer interrupt signal as EPWM and BPWM counter.."
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
line.long 0xC "TIMER0_ALTCTL,Timer0 Alternative Control Register"
bitfld.long 0xC 0. "FUNCSEL,Function Selection\nNote: When the timer is used as PWM  the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
line.long 0x10 "TIMER0_CAPNF,Timer0 Capture Input Noise Filter Register"
bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
group.long 0x40++0x1B
line.long 0x0 "TIMER0_PWMCTL,Timer0 PWM Control Register"
bitfld.long 0x0 31. "DBGNACK,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled  PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x0 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode"
bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled  CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.."
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bitfld.long 0x0 8. "CTRLD,Center Re-load\nIn up-down count type  PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1"
bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?"
bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
line.long 0x4 "TIMER0_PWMCLKSRC,Timer0 PWM Counter Clock Source Register"
bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled  the PWM counter clock source can be selected from TMR0_CLK  TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?"
line.long 0x8 "TIMER0_PWMCLKPSC,Timer0 PWM Counter Clock Pre-scale Register"
hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0  then there is no scaling in PWM counter clock source."
line.long 0xC "TIMER0_PWMCNTCLR,Timer0 PWM Clear Counter Register"
bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
line.long 0x10 "TIMER0_PWMPERIOD,Timer0 PWM Period Register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD  and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0  and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD  then.."
line.long 0x14 "TIMER0_PWMCMPDAT,Timer0 PWM Comparator Register"
hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform  interrupt events and trigger EADC to start conversion."
line.long 0x18 "TIMER0_PWMDTCTL,Timer0 PWM Dead-Time Control Register"
bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.."
bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive  the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected. Refer toSYS_REGLCTL register."
rgroup.long 0x5C++0x3
line.long 0x0 "TIMER0_PWMCNT,Timer0 PWM Counter Register"
bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
group.long 0x60++0x1B
line.long 0x0 "TIMER0_PWMMSKEN,Timer0 PWM Output Mask Enable Register"
bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
line.long 0x4 "TIMER0_PWMMSK,Timer0 PWM Output Mask Data Control Register"
bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
line.long 0x8 "TIMER0_PWMBNF,Timer0 PWM Brake Pin Noise Filter Register"
bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,?,?"
bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Value Control Bit" "0: Brake pin event will be detected if PWMx_BRAKEy..,1: Brake pin event will be detected if PWMx_BRAKEy.."
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bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields are used to control the active noise filter sample time." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
line.long 0xC "TIMER0_PWMFAILBRK,Timer0 PWM System Fail Brake Control Register"
bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
bitfld.long 0xC 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.."
line.long 0x10 "TIMER0_PWMBRKCTL,Timer0 PWM Brake Control Register"
bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy brake..,?,?"
bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy brake..,?,?"
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bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
bitfld.long 0x10 12. "BRKPLEN,Enable PWMx_BRAKEy Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Only internal ACMP0_O signal from low to high.."
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bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
bitfld.long 0x10 4. "BRKPEEN,Enable PWMx_BRAKEy Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Only internal ACMP0_O signal from low to high.."
line.long 0x14 "TIMER0_PWMPOLCTL,Timer0 PWM Pin Output Polar Control Register"
bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
line.long 0x18 "TIMER0_PWMPOEN,Timer0 PWM Pin Output Enable Register"
bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
wgroup.long 0x7C++0x3
line.long 0x0 "TIMER0_PWMSWBRK,Timer0 PWM Software Trigger Brake Control Register"
bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source  then BRKLIF0 and BRKLIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source  then BRKEIF0 and BRKEIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
group.long 0x80++0x17
line.long 0x0 "TIMER0_PWMINTEN0,Timer0 PWM Interrupt Enable Register 0"
bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type  period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
line.long 0x4 "TIMER0_PWMINTEN1,Timer0 PWM Interrupt Enable Register 1"
bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
line.long 0x8 "TIMER0_PWMINTSTS0,Timer0 PWM Interrupt Status Register 0"
bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPDIF flag in down count type.\nNote 2: This bit is cleared by.." "?,1: If CMP is equal to PERIOD"
bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPUIF flag in up count type and up-down count type.\nNote 2: This bit.." "?,1: If CMP is equal to PERIOD"
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bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote 1: In up-down count type  PIF flag means the center point flag of current PWM period.\nNote 2: This bit is cleared by writing 1 to it." "?,1: In up-down count type"
bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it." "0,1"
line.long 0xC "TIMER0_PWMINTSTS1,Timer0 PWM Interrupt Status Register 1"
rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
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bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
line.long 0x10 "TIMER0_PWMTRGCTL,Timer0 PWM Trigger Control Register"
bitfld.long 0x10 7. "TRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at zero point (ZIF),1: Trigger conversion at period point (PIF),?,?,?,?,?,?"
line.long 0x14 "TIMER0_PWMSCTL,Timer0 PWM Synchronous Control Register"
bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote 1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0  TIMER0_PWMSCTL[8]  TIMER1_PWMSCTL[8]  TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote 2: If TIMER0/1/ PWM.." "0: Counter synchronous start/clear by trigger..,1: If TIMER0/1/2/3 PWM counter synchronous source.."
bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?"
wgroup.long 0x98++0x3
line.long 0x0 "TIMER0_PWMSTRG,Timer0 PWM Synchronous Trigger Register"
bitfld.long 0x0 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (including TIMER0/1/2/3 PWM  TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according.." "0,1"
group.long 0x9C++0x3
line.long 0x0 "TIMER0_PWMSTATUS,Timer0 PWM Status Register"
bitfld.long 0x0 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
rgroup.long 0xA0++0x7
line.long 0x0 "TIMER0_PWMPBUF,Timer0 PWM Period Buffer Register"
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
line.long 0x4 "TIMER0_PWMCMPBUF,Timer0 PWM Comparator Buffer Register"
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
group.long 0xA8++0x13
line.long 0x0 "TIMER0_PWMIFA,Timer0 PWM Interrupt Flag Accumulator Register"
bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "0: Accumulate at each PWM zero point,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
line.long 0x4 "TIMER0_PWMAINTSTS,Timer0 PWM Accumulator Interrupt Flag Register"
bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set  this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER0_PWMAINTEN,Timer0 PWM Accumulator Interrupt Enable Register"
bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
line.long 0xC "TIMER0_PWMAPDMACTL,Timer0 PWM Accumulator PDMA Control Register"
bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
line.long 0x10 "TIMER0_PWMEXTETCTL,Timer0 PWM External Event Trigger Control Register"
hexmask.long.byte 0x10 8.--11. 1. "EXTTRGS,External Trigger Pin Selection"
bitfld.long 0x10 4.--5. "CNTACTS,Counter Action Selection" "0: External pin event to trigger PWM counter reset,1: External pin event to trigger PWM counter start,?,?"
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bitfld.long 0x10 0. "EXTETEN,External Pin Event Trigger Enable Bit" "0: External pin event trigger function Disabled,1: External pin event trigger function Enabled"
group.long 0x100++0xF
line.long 0x0 "TIMER1_CTL,Timer1 Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active  user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Time-out Interrupt Enable Bit\nNote: If this bit is enabled  when the timer time-out interrupt flag TIF is set to 1  the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for event counting function enabled. \nNote: When timer is used as an event counter  this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1  while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled  the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
bitfld.long 0x0 22. "CAPSRC,Capture Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT  CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-Timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also  Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
line.long 0x4 "TIMER1_CMP,Timer1 Comparator Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value  the TIF (TIMERx_INTSTS [0] Timer Interrupt Flag) will be set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT.."
line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
line.long 0xC "TIMER1_CNT,Timer1 Data Register"
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register  timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0  user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1  user can read CNT value.."
rgroup.long 0x110++0x3
line.long 0x0 "TIMER1_CAP,Timer1 Capture Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting  CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT.."
group.long 0x114++0x13
line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSC,Timer Capture Source Divider Scale\nThese bits indicate the divide scale for capture source divider. \nNote: Sets CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select capture source."
bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer Capture Edge Detect\nWhen the first capture event is generated  the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "ICAPSEL,Internal Capture Source Select\nNote: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer External Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x0 6. "CAPDBEN,Timer Capture De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection\nNote 1: When CAPFUNCS is 0 and CAPIF becomes 1  the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field.\nNote 2: When CAPFUNCS is 1 and CAPIF becomes 1  the current 24-bit timer counter value.." "0: Capture Mode Enabled,1: When CAPFUNCS is 0 and CAPIF becomes 1"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Function Enable Bit\nThis bit enables the capture input function." "0: Timer capture function Disabled,1: Timer capture function Enabled"
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clears corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag\nThis bit indicates the timer capture interrupt flag status.\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: When CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1  timer time-out interrupt or capture interrupt can be triggered DAC conversion." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
bitfld.long 0x8 1. "TRGPWM,Trigger EPWM and BPWM Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be as EPWM and BPWM counter clock source." "0: Timer interrupt signal as EPWM and BPWM counter..,1: Timer interrupt signal as EPWM and BPWM counter.."
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
line.long 0xC "TIMER1_ALTCTL,Timer1 Alternative Control Register"
bitfld.long 0xC 0. "FUNCSEL,Function Selection\nNote: When the timer is used as PWM  the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
line.long 0x10 "TIMER1_CAPNF,Timer1 Capture Input Noise Filter Register"
bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
group.long 0x140++0x1B
line.long 0x0 "TIMER1_PWMCTL,Timer1 PWM Control Register"
bitfld.long 0x0 31. "DBGNACK,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled  PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x0 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode"
bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled  CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.."
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bitfld.long 0x0 8. "CTRLD,Center Re-load\nIn up-down count type  PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1"
bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?"
bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
line.long 0x4 "TIMER1_PWMCLKSRC,Timer1 PWM Counter Clock Source Register"
bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled  the PWM counter clock source can be selected from TMR0_CLK  TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?"
line.long 0x8 "TIMER1_PWMCLKPSC,Timer1 PWM Counter Clock Pre-scale Register"
hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0  then there is no scaling in PWM counter clock source."
line.long 0xC "TIMER1_PWMCNTCLR,Timer1 PWM Clear Counter Register"
bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
line.long 0x10 "TIMER1_PWMPERIOD,Timer1 PWM Period Register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD  and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0  and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD  then.."
line.long 0x14 "TIMER1_PWMCMPDAT,Timer1 PWM Comparator Register"
hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform  interrupt events and trigger EADC to start conversion."
line.long 0x18 "TIMER1_PWMDTCTL,Timer1 PWM Dead-Time Control Register"
bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.."
bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive  the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected. Refer toSYS_REGLCTL register."
rgroup.long 0x15C++0x3
line.long 0x0 "TIMER1_PWMCNT,Timer1 PWM Counter Register"
bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
group.long 0x160++0x1B
line.long 0x0 "TIMER1_PWMMSKEN,Timer1 PWM Output Mask Enable Register"
bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
line.long 0x4 "TIMER1_PWMMSK,Timer1 PWM Output Mask Data Control Register"
bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
line.long 0x8 "TIMER1_PWMBNF,Timer1 PWM Brake Pin Noise Filter Register"
bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,?,?"
bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Value Control Bit" "0: Brake pin event will be detected if PWMx_BRAKEy..,1: Brake pin event will be detected if PWMx_BRAKEy.."
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bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields are used to control the active noise filter sample time." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
line.long 0xC "TIMER1_PWMFAILBRK,Timer1 PWM System Fail Brake Control Register"
bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
bitfld.long 0xC 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.."
line.long 0x10 "TIMER1_PWMBRKCTL,Timer1 PWM Brake Control Register"
bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy brake..,?,?"
bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy brake..,?,?"
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bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
bitfld.long 0x10 12. "BRKPLEN,Enable PWMx_BRAKEy Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Only internal ACMP0_O signal from low to high.."
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bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
bitfld.long 0x10 4. "BRKPEEN,Enable PWMx_BRAKEy Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Only internal ACMP0_O signal from low to high.."
line.long 0x14 "TIMER1_PWMPOLCTL,Timer1 PWM Pin Output Polar Control Register"
bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
line.long 0x18 "TIMER1_PWMPOEN,Timer1 PWM Pin Output Enable Register"
bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
wgroup.long 0x17C++0x3
line.long 0x0 "TIMER1_PWMSWBRK,Timer1 PWM Software Trigger Brake Control Register"
bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source  then BRKLIF0 and BRKLIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source  then BRKEIF0 and BRKEIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
group.long 0x180++0x17
line.long 0x0 "TIMER1_PWMINTEN0,Timer1 PWM Interrupt Enable Register 0"
bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type  period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
line.long 0x4 "TIMER1_PWMINTEN1,Timer1 PWM Interrupt Enable Register 1"
bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
line.long 0x8 "TIMER1_PWMINTSTS0,Timer1 PWM Interrupt Status Register 0"
bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPDIF flag in down count type.\nNote 2: This bit is cleared by.." "?,1: If CMP is equal to PERIOD"
bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPUIF flag in up count type and up-down count type.\nNote 2: This bit.." "?,1: If CMP is equal to PERIOD"
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bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote 1: In up-down count type  PIF flag means the center point flag of current PWM period.\nNote 2: This bit is cleared by writing 1 to it." "?,1: In up-down count type"
bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it." "0,1"
line.long 0xC "TIMER1_PWMINTSTS1,Timer1 PWM Interrupt Status Register 1"
rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
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bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
line.long 0x10 "TIMER1_PWMTRGCTL,Timer1 PWM Trigger Control Register"
bitfld.long 0x10 7. "TRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at zero point (ZIF),1: Trigger conversion at period point (PIF),?,?,?,?,?,?"
line.long 0x14 "TIMER1_PWMSCTL,Timer1 PWM Synchronous Control Register"
bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote 1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0  TIMER0_PWMSCTL[8]  TIMER1_PWMSCTL[8]  TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote 2: If TIMER0/1/ PWM.." "0: Counter synchronous start/clear by trigger..,1: If TIMER0/1/2/3 PWM counter synchronous source.."
bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?"
group.long 0x19C++0x3
line.long 0x0 "TIMER1_PWMSTATUS,Timer1 PWM Status Register"
bitfld.long 0x0 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
rgroup.long 0x1A0++0x7
line.long 0x0 "TIMER1_PWMPBUF,Timer1 PWM Period Buffer Register"
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
line.long 0x4 "TIMER1_PWMCMPBUF,Timer1 PWM Comparator Buffer Register"
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
group.long 0x1A8++0x13
line.long 0x0 "TIMER1_PWMIFA,Timer1 PWM Interrupt Flag Accumulator Register"
bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "0: Accumulate at each PWM zero point,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
line.long 0x4 "TIMER1_PWMAINTSTS,Timer1 PWM Accumulator Interrupt Flag Register"
bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set  this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER1_PWMAINTEN,Timer1 PWM Accumulator Interrupt Enable Register"
bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
line.long 0xC "TIMER1_PWMAPDMACTL,Timer1 PWM Accumulator PDMA Control Register"
bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
line.long 0x10 "TIMER1_PWMEXTETCTL,Timer1 PWM External Event Trigger Control Register"
hexmask.long.byte 0x10 8.--11. 1. "EXTTRGS,External Trigger Pin Selection"
bitfld.long 0x10 4.--5. "CNTACTS,Counter Action Selection" "0: External pin event to trigger PWM counter reset,1: External pin event to trigger PWM counter start,?,?"
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bitfld.long 0x10 0. "EXTETEN,External Pin Event Trigger Enable Bit" "0: External pin event trigger function Disabled,1: External pin event trigger function Enabled"
tree.end
tree "TMR23"
base ad:0x40051000
group.long 0x0++0xF
line.long 0x0 "TIMER2_CTL,Timer2 Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active  user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Time-out Interrupt Enable Bit\nNote: If this bit is enabled  when the timer time-out interrupt flag TIF is set to 1  the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for event counting function enabled. \nNote: When timer is used as an event counter  this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1  while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled  the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
bitfld.long 0x0 22. "CAPSRC,Capture Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT  CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-Timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also  Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
line.long 0x4 "TIMER2_CMP,Timer2 Comparator Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value  the TIF (TIMERx_INTSTS [0] Timer Interrupt Flag) will be set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT.."
line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
line.long 0xC "TIMER2_CNT,Timer2 Data Register"
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register  timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0  user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1  user can read CNT value.."
rgroup.long 0x10++0x3
line.long 0x0 "TIMER2_CAP,Timer2 Capture Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting  CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT.."
group.long 0x14++0x13
line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register"
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSC,Timer Capture Source Divider Scale\nThese bits indicate the divide scale for capture source divider. \nNote: Sets CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select capture source."
bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer Capture Edge Detect\nWhen the first capture event is generated  the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "ICAPSEL,Internal Capture Source Select\nNote: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer External Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x0 6. "CAPDBEN,Timer Capture De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection\nNote 1: When CAPFUNCS is 0 and CAPIF becomes 1  the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field.\nNote 2: When CAPFUNCS is 1 and CAPIF becomes 1  the current 24-bit timer counter value.." "0: Capture Mode Enabled,1: When CAPFUNCS is 0 and CAPIF becomes 1"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Function Enable Bit\nThis bit enables the capture input function." "0: Timer capture function Disabled,1: Timer capture function Enabled"
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clears corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag\nThis bit indicates the timer capture interrupt flag status.\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: When CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1  timer time-out interrupt or capture interrupt can be triggered DAC conversion." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
bitfld.long 0x8 1. "TRGPWM,Trigger EPWM and BPWM Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be as EPWM and BPWM counter clock source." "0: Timer interrupt signal as EPWM and BPWM counter..,1: Timer interrupt signal as EPWM and BPWM counter.."
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
line.long 0xC "TIMER2_ALTCTL,Timer2 Alternative Control Register"
bitfld.long 0xC 0. "FUNCSEL,Function Selection\nNote: When the timer is used as PWM  the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
line.long 0x10 "TIMER2_CAPNF,Timer2 Capture Input Noise Filter Register"
bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
group.long 0x40++0x1B
line.long 0x0 "TIMER2_PWMCTL,Timer2 PWM Control Register"
bitfld.long 0x0 31. "DBGNACK,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled  PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x0 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode"
bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled  CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.."
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bitfld.long 0x0 8. "CTRLD,Center Re-load\nIn up-down count type  PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1"
bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?"
bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
line.long 0x4 "TIMER2_PWMCLKSRC,Timer2 PWM Counter Clock Source Register"
bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled  the PWM counter clock source can be selected from TMR0_CLK  TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?"
line.long 0x8 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register"
hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0  then there is no scaling in PWM counter clock source."
line.long 0xC "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register"
bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
line.long 0x10 "TIMER2_PWMPERIOD,Timer2 PWM Period Register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD  and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0  and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD  then.."
line.long 0x14 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register"
hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform  interrupt events and trigger EADC to start conversion."
line.long 0x18 "TIMER2_PWMDTCTL,Timer2 PWM Dead-Time Control Register"
bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.."
bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive  the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected. Refer toSYS_REGLCTL register."
rgroup.long 0x5C++0x3
line.long 0x0 "TIMER2_PWMCNT,Timer2 PWM Counter Register"
bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
group.long 0x60++0x1B
line.long 0x0 "TIMER2_PWMMSKEN,Timer2 PWM Output Mask Enable Register"
bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
line.long 0x4 "TIMER2_PWMMSK,Timer2 PWM Output Mask Data Control Register"
bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
line.long 0x8 "TIMER2_PWMBNF,Timer2 PWM Brake Pin Noise Filter Register"
bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,?,?"
bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Value Control Bit" "0: Brake pin event will be detected if PWMx_BRAKEy..,1: Brake pin event will be detected if PWMx_BRAKEy.."
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bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields are used to control the active noise filter sample time." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
line.long 0xC "TIMER2_PWMFAILBRK,Timer2 PWM System Fail Brake Control Register"
bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
bitfld.long 0xC 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.."
line.long 0x10 "TIMER2_PWMBRKCTL,Timer2 PWM Brake Control Register"
bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy brake..,?,?"
bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy brake..,?,?"
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bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
bitfld.long 0x10 12. "BRKPLEN,Enable PWMx_BRAKEy Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Only internal ACMP0_O signal from low to high.."
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bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
bitfld.long 0x10 4. "BRKPEEN,Enable PWMx_BRAKEy Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Only internal ACMP0_O signal from low to high.."
line.long 0x14 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register"
bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
line.long 0x18 "TIMER2_PWMPOEN,Timer2 PWM Pin Output Enable Register"
bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
wgroup.long 0x7C++0x3
line.long 0x0 "TIMER2_PWMSWBRK,Timer2 PWM Software Trigger Brake Control Register"
bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source  then BRKLIF0 and BRKLIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source  then BRKEIF0 and BRKEIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
group.long 0x80++0x17
line.long 0x0 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0"
bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type  period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
line.long 0x4 "TIMER2_PWMINTEN1,Timer2 PWM Interrupt Enable Register 1"
bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
line.long 0x8 "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0"
bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPDIF flag in down count type.\nNote 2: This bit is cleared by.." "?,1: If CMP is equal to PERIOD"
bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPUIF flag in up count type and up-down count type.\nNote 2: This bit.." "?,1: If CMP is equal to PERIOD"
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bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote 1: In up-down count type  PIF flag means the center point flag of current PWM period.\nNote 2: This bit is cleared by writing 1 to it." "?,1: In up-down count type"
bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it." "0,1"
line.long 0xC "TIMER2_PWMINTSTS1,Timer2 PWM Interrupt Status Register 1"
rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
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bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
line.long 0x10 "TIMER2_PWMTRGCTL,Timer2 PWM Trigger Control Register"
bitfld.long 0x10 7. "TRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at zero point (ZIF),1: Trigger conversion at period point (PIF),?,?,?,?,?,?"
line.long 0x14 "TIMER2_PWMSCTL,Timer2 PWM Synchronous Control Register"
bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote 1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0  TIMER0_PWMSCTL[8]  TIMER1_PWMSCTL[8]  TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote 2: If TIMER0/1/ PWM.." "0: Counter synchronous start/clear by trigger..,1: If TIMER0/1/2/3 PWM counter synchronous source.."
bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?"
wgroup.long 0x98++0x3
line.long 0x0 "TIMER2_PWMSTRG,Timer2 PWM Synchronous Trigger Register"
bitfld.long 0x0 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (including TIMER0/1/2/3 PWM  TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according.." "0,1"
group.long 0x9C++0x3
line.long 0x0 "TIMER2_PWMSTATUS,Timer2 PWM Status Register"
bitfld.long 0x0 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
rgroup.long 0xA0++0x7
line.long 0x0 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register"
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
line.long 0x4 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register"
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
group.long 0xA8++0x13
line.long 0x0 "TIMER2_PWMIFA,Timer2 PWM Interrupt Flag Accumulator Register"
bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "0: Accumulate at each PWM zero point,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
line.long 0x4 "TIMER2_PWMAINTSTS,Timer2 PWM Accumulator Interrupt Flag Register"
bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set  this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER2_PWMAINTEN,Timer2 PWM Accumulator Interrupt Enable Register"
bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
line.long 0xC "TIMER2_PWMAPDMACTL,Timer2 PWM Accumulator PDMA Control Register"
bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
line.long 0x10 "TIMER2_PWMEXTETCTL,Timer2 PWM External Event Trigger Control Register"
hexmask.long.byte 0x10 8.--11. 1. "EXTTRGS,External Trigger Pin Selection"
bitfld.long 0x10 4.--5. "CNTACTS,Counter Action Selection" "0: External pin event to trigger PWM counter reset,1: External pin event to trigger PWM counter start,?,?"
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bitfld.long 0x10 0. "EXTETEN,External Pin Event Trigger Enable Bit" "0: External pin event trigger function Disabled,1: External pin event trigger function Enabled"
group.long 0x100++0xF
line.long 0x0 "TIMER3_CTL,Timer3 Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active  user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Time-out Interrupt Enable Bit\nNote: If this bit is enabled  when the timer time-out interrupt flag TIF is set to 1  the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for event counting function enabled. \nNote: When timer is used as an event counter  this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1  while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled  the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
bitfld.long 0x0 22. "CAPSRC,Capture Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT  CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-Timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also  Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
line.long 0x4 "TIMER3_CMP,Timer3 Comparator Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value  the TIF (TIMERx_INTSTS [0] Timer Interrupt Flag) will be set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT.."
line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
line.long 0xC "TIMER3_CNT,Timer3 Data Register"
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register  timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0  user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1  user can read CNT value.."
rgroup.long 0x110++0x3
line.long 0x0 "TIMER3_CAP,Timer3 Capture Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting  CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT.."
group.long 0x114++0x13
line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register"
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSC,Timer Capture Source Divider Scale\nThese bits indicate the divide scale for capture source divider. \nNote: Sets CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select capture source."
bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer Capture Edge Detect\nWhen the first capture event is generated  the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and ICAPSEL (TIMERx_EXTCTL[10:8]) to select.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
bitfld.long 0x0 8.--10. "ICAPSEL,Internal Capture Source Select\nNote: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer External Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x0 6. "CAPDBEN,Timer Capture De-bounce Enable Bit\nNote: If this bit is enabled  the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection\nNote 1: When CAPFUNCS is 0 and CAPIF becomes 1  the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field.\nNote 2: When CAPFUNCS is 1 and CAPIF becomes 1  the current 24-bit timer counter value.." "0: Capture Mode Enabled,1: When CAPFUNCS is 0 and CAPIF becomes 1"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Function Enable Bit\nThis bit enables the capture input function." "0: Timer capture function Disabled,1: Timer capture function Enabled"
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clears corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag\nThis bit indicates the timer capture interrupt flag status.\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: When CAPEN (TIMERx_EXTCTL[3]) bit is set  the transition on the capture source matches the CAPEDGE.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1  timer time-out interrupt or capture interrupt can be triggered DAC conversion." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
bitfld.long 0x8 1. "TRGPWM,Trigger EPWM and BPWM Enable Bit\nIf this bit is set to 1  each timer time-out event or capture event can be as EPWM and BPWM counter clock source." "0: Timer interrupt signal as EPWM and BPWM counter..,1: Timer interrupt signal as EPWM and BPWM counter.."
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
line.long 0xC "TIMER3_ALTCTL,Timer3 Alternative Control Register"
bitfld.long 0xC 0. "FUNCSEL,Function Selection\nNote: When the timer is used as PWM  the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
line.long 0x10 "TIMER3_CAPNF,Timer3 Capture Input Noise Filter Register"
bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
group.long 0x140++0x1B
line.long 0x0 "TIMER3_PWMCTL,Timer3 PWM Control Register"
bitfld.long 0x0 31. "DBGNACK,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled  PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x0 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode"
bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled  CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.."
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bitfld.long 0x0 8. "CTRLD,Center Re-load\nIn up-down count type  PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1"
bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?"
bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
line.long 0x4 "TIMER3_PWMCLKSRC,Timer3 PWM Counter Clock Source Register"
bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled  the PWM counter clock source can be selected from TMR0_CLK  TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?"
line.long 0x8 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register"
hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0  then there is no scaling in PWM counter clock source."
line.long 0xC "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register"
bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
line.long 0x10 "TIMER3_PWMPERIOD,Timer3 PWM Period Register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD  and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0  and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD  then.."
line.long 0x14 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register"
hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform  interrupt events and trigger EADC to start conversion."
line.long 0x18 "TIMER3_PWMDTCTL,Timer3 PWM Dead-Time Control Register"
bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.."
bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive  the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected. Refer toSYS_REGLCTL register."
rgroup.long 0x15C++0x3
line.long 0x0 "TIMER3_PWMCNT,Timer3 PWM Counter Register"
bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
group.long 0x160++0x1B
line.long 0x0 "TIMER3_PWMMSKEN,Timer3 PWM Output Mask Enable Register"
bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
line.long 0x4 "TIMER3_PWMMSK,Timer3 PWM Output Mask Data Control Register"
bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
line.long 0x8 "TIMER3_PWMBNF,Timer3 PWM Brake Pin Noise Filter Register"
bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,?,?"
bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Value Control Bit" "0: Brake pin event will be detected if PWMx_BRAKEy..,1: Brake pin event will be detected if PWMx_BRAKEy.."
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bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields are used to control the active noise filter sample time." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
line.long 0xC "TIMER3_PWMFAILBRK,Timer3 PWM System Fail Brake Control Register"
bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
bitfld.long 0xC 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.."
line.long 0x10 "TIMER3_PWMBRKCTL,Timer3 PWM Brake Control Register"
bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy brake..,?,?"
bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy brake..,?,?"
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bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
bitfld.long 0x10 12. "BRKPLEN,Enable PWMx_BRAKEy Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Only internal ACMP0_O signal from low to high.."
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bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
bitfld.long 0x10 4. "BRKPEEN,Enable PWMx_BRAKEy Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Only internal ACMP1_O signal from low to high.."
bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote 1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote 2: This bit is write protected. Refer toSYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Only internal ACMP0_O signal from low to high.."
line.long 0x14 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register"
bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
line.long 0x18 "TIMER3_PWMPOEN,Timer3 PWM Pin Output Enable Register"
bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
wgroup.long 0x17C++0x3
line.long 0x0 "TIMER3_PWMSWBRK,Timer3 PWM Software Trigger Brake Control Register"
bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source  then BRKLIF0 and BRKLIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source  then BRKEIF0 and BRKEIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This bit is.." "0,1"
group.long 0x180++0x17
line.long 0x0 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0"
bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type  period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
line.long 0x4 "TIMER3_PWMINTEN1,Timer3 PWM Interrupt Enable Register 1"
bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
line.long 0x8 "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0"
bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPDIF flag in down count type.\nNote 2: This bit is cleared by.." "?,1: If CMP is equal to PERIOD"
bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote 1: If CMP is equal to PERIOD  there is no CMPUIF flag in up count type and up-down count type.\nNote 2: This bit.." "?,1: If CMP is equal to PERIOD"
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bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote 1: In up-down count type  PIF flag means the center point flag of current PWM period.\nNote 2: This bit is cleared by writing 1 to it." "?,1: In up-down count type"
bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it." "0,1"
line.long 0xC "TIMER3_PWMINTSTS1,Timer3 PWM Interrupt Status Register 1"
rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released  both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
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bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event do not happened,1: This bit is cleared by writing 1 to it"
line.long 0x10 "TIMER3_PWMTRGCTL,Timer3 PWM Trigger Control Register"
bitfld.long 0x10 7. "TRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at zero point (ZIF),1: Trigger conversion at period point (PIF),?,?,?,?,?,?"
line.long 0x14 "TIMER3_PWMSCTL,Timer3 PWM Synchronous Control Register"
bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote 1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0  TIMER0_PWMSCTL[8]  TIMER1_PWMSCTL[8]  TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote 2: If TIMER0/1/ PWM.." "0: Counter synchronous start/clear by trigger..,1: If TIMER0/1/2/3 PWM counter synchronous source.."
bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?"
group.long 0x19C++0x3
line.long 0x0 "TIMER3_PWMSTATUS,Timer3 PWM Status Register"
bitfld.long 0x0 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
rgroup.long 0x1A0++0x7
line.long 0x0 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register"
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
line.long 0x4 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register"
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
group.long 0x1A8++0x13
line.long 0x0 "TIMER3_PWMIFA,Timer3 PWM Interrupt Flag Accumulator Register"
bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "0: Accumulate at each PWM zero point,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
line.long 0x4 "TIMER3_PWMAINTSTS,Timer3 PWM Accumulator Interrupt Flag Register"
bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set  this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
line.long 0x8 "TIMER3_PWMAINTEN,Timer3 PWM Accumulator Interrupt Enable Register"
bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
line.long 0xC "TIMER3_PWMAPDMACTL,Timer3 PWM Accumulator PDMA Control Register"
bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
line.long 0x10 "TIMER3_PWMEXTETCTL,Timer3 PWM External Event Trigger Control Register"
hexmask.long.byte 0x10 8.--11. 1. "EXTTRGS,External Trigger Pin Selection"
bitfld.long 0x10 4.--5. "CNTACTS,Counter Action Selection" "0: External pin event to trigger PWM counter reset,1: External pin event to trigger PWM counter start,?,?"
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bitfld.long 0x10 0. "EXTETEN,External Pin Event Trigger Enable Bit" "0: External pin event trigger function Disabled,1: External pin event trigger function Enabled"
tree.end
tree.end
tree "TRNG (True Random Number Generator)"
base ad:0x400B9000
group.long 0x0++0x3
line.long 0x0 "TRNG_CTL,TRNG Control Register and Status"
rbitfld.long 0x0 7. "READY,Random Number Generator Ready (Read Only)\nAfter ACT (TRNG_ACT[7]) bit is set  the READY bit becomes 1 after a delay of 90us~120us." "0: RNG is not ready or not activated,1: RNG is ready to be enabled"
bitfld.long 0x0 6. "DVIEN,Data Valid Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
hexmask.long.byte 0x0 2.--5. 1. "CLKPSC,Clock Prescaler\nThe CLKPSC is the peripheral clock frequency range for the selected value. The CLKPSC must be higher than or equal to the actual peripheral clock frequency (for correct random bit generation). However  if the actual peripheral.."
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rbitfld.long 0x0 1. "DVIF,Data Valid (Read Only)\nNote: This bit is cleared to '0' by reading TRNG_DATA." "0: Data is not valid. Reading from RNGD returns..,1: Data is valid. A valid random number can be read.."
bitfld.long 0x0 0. "TRNGEN,Random Number Generator Enable Bit\nThis bit can be set to 1 only after ACT (TRNG_ACT[7]) bit is set to 1 and READY (TRNG_CTL[7]) bit became 1.\nNote: TRNGEN is an enable bit of digital part. When TRNG is not required to generate random number .." "0: TRNG Disabled,1: TRNG Enabled"
rgroup.long 0x4++0x3
line.long 0x0 "TRNG_DATA,TRNG Data Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Random Number Generator Data (Read Only)\nThe DATA stores the random number generated by TRNG and can be read only once."
group.long 0xC++0x3
line.long 0x0 "TRNG_ACT,TRNG Activation Register"
bitfld.long 0x0 7. "ACT,Random Number Generator Activation\nAfter enabling the ACT bit  it will activate the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.\nNote: ACT is an enable bit of analog part. When TRNG is not required to generate random number  TRNGEN.." "0: TRNG inactive,1: TRNG active"
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART0"
base ad:0x40070000
group.long 0x0++0x4F
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
line.long 0x34 "UART_LINCTL,UART LIN Control Register"
hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware  user fill ID0~ID5 (PID [29:24])  hardware will calculate P0 (PID[30]) and P1 (PID[31])  otherwise user must filled frame ID and parity in this field.\nNote 1: User can fill any 8-bit value to this.."
bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.."
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bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break  sync and frame ID field'  it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote 1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]);.." "0: Send LIN TX header Disabled,1: This bit is shadow bit of LINTXEN"
bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in Mute Mode and LIN Exit from Mute Mode Condition section." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode  this bit should be kept cleared) \nNote 3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote 2: When operation in Automatic Resynchronization mode  the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote 3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
line.long 0x38 "UART_LINSTS,UART LIN Status Register"
bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state  hardware will monitor the bus state  if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state  BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected"
bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect  user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)'  'frame error in.." "0: LIN header error not detected,1: LIN header error detected"
bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote 3: When enable ID parity check IDPEN (UART_LINCTL [9])  if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x40 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x44 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0x48 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x48 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x4C "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x4C 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART1"
base ad:0x40071000
group.long 0x0++0x4F
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
line.long 0x34 "UART_LINCTL,UART LIN Control Register"
hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware  user fill ID0~ID5 (PID [29:24])  hardware will calculate P0 (PID[30]) and P1 (PID[31])  otherwise user must filled frame ID and parity in this field.\nNote 1: User can fill any 8-bit value to this.."
bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.."
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bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break  sync and frame ID field'  it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote 1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]);.." "0: Send LIN TX header Disabled,1: This bit is shadow bit of LINTXEN"
bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in Mute Mode and LIN Exit from Mute Mode Condition section." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode  this bit should be kept cleared) \nNote 3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote 2: When operation in Automatic Resynchronization mode  the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote 3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
line.long 0x38 "UART_LINSTS,UART LIN Status Register"
bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state  hardware will monitor the bus state  if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state  BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected"
bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect  user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)'  'frame error in.." "0: LIN header error not detected,1: LIN header error detected"
bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote 3: When enable ID parity check IDPEN (UART_LINCTL [9])  if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x40 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x44 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0x48 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x48 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x4C "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x4C 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART2"
base ad:0x40072000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART3"
base ad:0x40073000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART4"
base ad:0x40074000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART5"
base ad:0x40075000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART6"
base ad:0x40076000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART7"
base ad:0x40077000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART8"
base ad:0x40078000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree "UART9"
base ad:0x40079000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit  the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set  the UART controller will send out this bit follow the DAT.." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register  the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit  the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1  the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6])  Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled  the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled  if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16])  the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL  the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled  and an interrupt will be generated)."
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set  all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set  all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0  the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1  the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1  the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode.\nNote 2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not  and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled  and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state  and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state  this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full  an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT  TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register  TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16  otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device  RXPTR increases one. When one byte of RX FIFO is read by CPU  RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes  this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled  the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF (UART_FIFOSTS[6])  FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0])  BRKDETF(UART_LINSTS[8])  BITEF(UART_LINSTS[9])  SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4])  RS485WKF (UART_WKSTS[3])  RFRTWKF (UART_WKSTS[2])  DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set  the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled  the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error  frame error or break error (at least one of 3 bits  BIF(UART_FIFOSTS[6])  FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4])  is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled  the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled  the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
line.long 0x20 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.234."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detailed description is shown in Table 6.234."
line.long 0x28 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit  TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done  clear TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation is finished  this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled  the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
group.long 0x3C++0x13
line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8])."
line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode  RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode  Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode  incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode  an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled  the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled  the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled  the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled  the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled  the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
tree.end
tree.end
tree "USBD (USB Device Controller)"
base ad:0x0
tree "HSUSBD"
base ad:0x40019000
rgroup.long 0x0++0x3
line.long 0x0 "HSUSBD_GINTSTS,Global Interrupt Status Register"
bitfld.long 0x0 13. "EPLIF,Endpoint L Interrupt\nWhen set  the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 12. "EPKIF,Endpoint K Interrupt\nWhen set  the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 11. "EPJIF,Endpoint J Interrupt\nWhen set  the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 10. "EPIIF,Endpoint I Interrupt\nWhen set  the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 9. "EPHIF,Endpoint H Interrupt\nWhen set  the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 8. "EPGIF,Endpoint G Interrupt\nWhen set  the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 7. "EPFIF,Endpoint F Interrupt\nWhen set  the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 6. "EPEIF,Endpoint E Interrupt\nWhen set  the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 5. "EPDIF,Endpoint D Interrupt\nWhen set  the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 4. "EPCIF,Endpoint C Interrupt\nWhen set  the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 3. "EPBIF,Endpoint B Interrupt\nWhen set  the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 2. "EPAIF,Endpoint A Interrupt\nWhen set  the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 1. "CEPIF,Control Endpoint Interrupt \nThis bit conveys the interrupt status for control endpoint. When set  Control-ep's interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
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bitfld.long 0x0 0. "USBIF,USB Interrupt \nThis bit conveys the interrupt status for USB specific events endpoint. When set  USB interrupt status register should be read to determine the cause of the interrupt." "0: No interrupt event occurred,1: The related interrupt event occurred"
group.long 0x8++0x3
line.long 0x0 "HSUSBD_GINTEN,Global Interrupt Enable Register"
bitfld.long 0x0 13. "EPLIEN,Interrupt Enable Control for Endpoint L \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 12. "EPKIEN,Interrupt Enable Control for Endpoint K \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 11. "EPJIEN,Interrupt Enable Control for Endpoint J \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 10. "EPIIEN,Interrupt Enable Control for Endpoint I \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 9. "EPHIEN,Interrupt Enable Control for Endpoint H \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 8. "EPGIEN,Interrupt Enable Control for Endpoint G\nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 7. "EPFIEN,Interrupt Enable Control for Endpoint F \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 6. "EPEIEN,Interrupt Enable Control for Endpoint E \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 5. "EPDIEN,Interrupt Enable Control for Endpoint D \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 4. "EPCIEN,Interrupt Enable Control for Endpoint C \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 3. "EPBIEN,Interrupt Enable Control for Endpoint B \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 2. "EPAIEN,Interrupt Enable Control for Endpoint A \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A." "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 1. "CEPIEN,Control Endpoint Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint." "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x0 0. "USBIEN,USB Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be generated when a USB event occurs on the bus." "0: The related interrupt Disabled,1: The related interrupt Enabled"
group.long 0x10++0xB
line.long 0x0 "HSUSBD_BUSINTSTS,USB Bus Interrupt Status Register"
bitfld.long 0x0 9. "LPMTKNIF,LPM Token Interrupt\nNote : Write 1 to clear this bit to 0." "0: No LPM token has been received from the host,1: A LPM token has been received from the host"
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bitfld.long 0x0 8. "VBUSDETIF,VBUS Detection Interrupt \nNote: Write 1 to clear this bit to 0." "0: No VBUS is plug-in,1: VBUS is plug-in"
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bitfld.long 0x0 6. "PHYCLKVLDIF,Usable Clock Interrupt \nNote: Write 1 to clear this bit to 0." "0: Usable clock is not available,1: Usable clock is available from the transceiver"
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bitfld.long 0x0 5. "DMADONEIF,DMA Completion Interrupt \nNote: Write 1 to clear this bit to 0." "0: No DMA transfer over,1: DMA transfer is over"
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bitfld.long 0x0 4. "HISPDIF,High-speed Settle Interrupt\nNote: Write 1 to clear this bit to 0." "0: No valid high-speed reset protocol is detected,1: Valid high-speed reset protocol is over and the.."
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bitfld.long 0x0 3. "SUSPENDIF,Suspend Request Interrupt\nThis bit is set as default and it has to be cleared by writing '1' before the USB reset. This bit is also set when a USB Suspend request is detected from the host. \nNote: Write 1 to clear this bit to 0." "0: No USB Suspend request is detected from the host,1: USB Suspend request is detected from the host"
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bitfld.long 0x0 2. "RESUMEIF,Resume Interrupt\nWhen set  this bit indicates that a device resume has occurred.\nNote: Write 1 to clear this bit to 0." "0: No device resume has occurred,1: Device resume has occurred"
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bitfld.long 0x0 1. "RSTIF,Reset Interrupt \nWhen set  this bit indicates that either the USB root port reset is end.\nNote: Write 1 to clear this bit to 0." "0: No USB root port reset is end,1: USB root port reset is end"
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bitfld.long 0x0 0. "SOFIF,SOF Receive Control Interrupt\nThis bit indicates when a start-of-frame packet has been received. \nNote: Write 1 to clear this bit to 0." "0: No start-of-frame packet has been received,1: Start-of-frame packet has been received"
line.long 0x4 "HSUSBD_BUSINTEN,USB Bus Interrupt Enable Register"
bitfld.long 0x4 9. "LPMTKNIEN,LPM Token Interrupt Enable Bit" "0: The LPM token interrupt Disabled,1: The LPM token interrupt Enabled"
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bitfld.long 0x4 8. "VBUSDETIEN,VBUS Detection Interrupt Enable Bit\nThis bit enables the VBUS floating detection interrupt." "0: VBUS floating detection interrupt Disabled,1: VBUS floating detection interrupt Enabled"
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bitfld.long 0x4 6. "PHYCLKVLDIEN,Usable Clock Interrupt Enable Bit\nThis bit enables the usable clock interrupt." "0: Usable clock interrupt Disabled,1: Usable clock interrupt Enabled"
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bitfld.long 0x4 5. "DMADONEIEN,DMA Completion Interrupt Enable Bit\nThis bit enables the DMA completion interrupt" "0: DMA completion interrupt Disabled,1: DMA completion interrupt Enabled"
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bitfld.long 0x4 4. "HISPDIEN,High-speed Settle Interrupt Enable Bit\nThis bit enables the high-speed settle interrupt." "0: High-speed settle interrupt Disabled,1: High-speed settle interrupt Enabled"
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bitfld.long 0x4 3. "SUSPENDIEN,Suspend Request Interrupt Enable Bit\nThis bit enables the Suspend interrupt." "0: Suspend interrupt Disabled,1: Suspend interrupt Enabled"
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bitfld.long 0x4 2. "RESUMEIEN,Resume Interrupt Enable Bit\nThis bit enables the Resume interrupt." "0: Resume interrupt Disabled,1: Resume interrupt Enabled"
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bitfld.long 0x4 1. "RSTIEN,Reset Interrupt Enable Bit\nThis bit enables the USB-Reset interrupt." "0: USB-Reset interrupt Disabled,1: USB-Reset interrupt Enabled"
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bitfld.long 0x4 0. "SOFIEN,SOF Interrupt Enable Bit\nThis bit enables the SOF interrupt." "0: SOF interrupt Disabled,1: SOF interrupt Enabled"
line.long 0x8 "HSUSBD_OPER,USB Operational Register"
bitfld.long 0x8 2. "CURSPD,USB Current Speed" "0: The device has settled in full-speed,1: The USB device controller has settled in.."
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bitfld.long 0x8 1. "HISPDEN,USB High-speed" "0: The USB device controller to suppress the..,1: The USB device controller to initiate a.."
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bitfld.long 0x8 0. "RESUMEEN,Generate Resume" "0: No Resume sequence to be initiated to the host,1: A Resume sequence to be initiated to the host if.."
rgroup.long 0x1C++0x3
line.long 0x0 "HSUSBD_FRAMECNT,USB Frame Count Register"
hexmask.long.word 0x0 3.--13. 1. "FRAMECNT,Frame Counter\nThis field contains the frame count from the most recent start-of-frame packet."
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bitfld.long 0x0 0.--2. "MFRAMECNT,Micro-frame Counter\nThis field contains the micro-frame number for the frame number in the frame counter field." "0,1,2,3,4,5,6,7"
group.long 0x20++0x1B
line.long 0x0 "HSUSBD_FADDR,USB Function Address Register"
hexmask.long.byte 0x0 0.--6. 1. "FADDR,USB Function Address\nThis field contains the current USB address of the device. This field is cleared when a root port reset is detected."
line.long 0x4 "HSUSBD_TEST,USB Test Mode Register"
bitfld.long 0x4 0.--2. "TESTMODE,Test Mode Selection\nNote: This field is cleared when root port reset is detected." "0: Normal Operation,1: Test_J,?,?,?,?,?,?"
line.long 0x8 "HSUSBD_CEPDAT,Control-endpoint Data Buffer"
hexmask.long 0x8 0.--31. 1. "DAT,Control-endpoint Data Buffer \nControl endpoint data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0xC "HSUSBD_CEPCTL,Control-endpoint Control Register"
bitfld.long 0xC 3. "FLUSH,CEP-flush Bit" "0: No the packet buffer and its corresponding..,1: The packet buffer and its corresponding.."
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bitfld.long 0xC 2. "ZEROLEN,Zero Packet Length\nThis bit is valid for Auto Validation mode only." "0: No zero length packet to the host during Data..,1: USB device controller can send a zero length.."
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bitfld.long 0xC 1. "STALLEN,Stall Enable Bit\nWhen this stall bit is set  the control endpoint sends a stall handshake in response to any in or out token thereafter. This is typically used for response to invalid/unsupported requests. When this bit is being set the NAK.." "0: No sends a stall handshake in response to any in..,1: The control endpoint sends a stall handshake in.."
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bitfld.long 0xC 0. "NAKCLR,No Acknowledge Control\nThis bit plays a crucial role in any control transfer. \nNote: Only when CPU writes data[1:0] is 2'b10 or 2'b00  this bit can be updated." "0: The bit is being cleared by the local CPU by..,1: This bit is set to one by the USB device.."
line.long 0x10 "HSUSBD_CEPINTEN,Control-endpoint Interrupt Enable"
bitfld.long 0x10 12. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit" "0: The buffer empty interrupt in Control Endpoint..,1: The buffer empty interrupt in Control Endpoint.."
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bitfld.long 0x10 11. "BUFFULLIEN,Buffer Full Interrupt Enable Bit" "0: The buffer full interrupt in Control Endpoint..,1: The buffer full interrupt in Control Endpoint.."
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bitfld.long 0x10 10. "STSDONEIEN,Status Completion Interrupt Enable Bit" "0: The Status Completion interrupt in Control..,1: The Status Completion interrupt in Control.."
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bitfld.long 0x10 9. "ERRIEN,USB Error Interrupt Enable Bit" "0: The USB Error interrupt in Control Endpoint..,1: The USB Error interrupt in Control Endpoint.."
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bitfld.long 0x10 8. "STALLIEN,STALL Sent Interrupt Enable Bit" "0: The STALL sent interrupt in Control Endpoint..,1: The STALL sent interrupt in Control Endpoint.."
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bitfld.long 0x10 7. "NAKIEN,NAK Sent Interrupt Enable Bit" "0: The NAK sent interrupt in Control Endpoint..,1: The NAK sent interrupt in Control Endpoint Enabled"
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bitfld.long 0x10 6. "RXPKIEN,Data Packet Received Interrupt Enable Bit" "0: The data received interrupt in Control Endpoint..,1: The data received interrupt in Control Endpoint.."
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bitfld.long 0x10 5. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit" "0: The data packet transmitted interrupt in Control..,1: The data packet transmitted interrupt in Control.."
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bitfld.long 0x10 4. "PINGIEN,Ping Token Interrupt Enable Bit" "0: The ping token interrupt in Control Endpoint..,1: The ping token interrupt Control Endpoint Enabled"
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bitfld.long 0x10 3. "INTKIEN,In Token Interrupt Enable Bit" "0: The IN token interrupt in Control Endpoint..,1: The IN token interrupt in Control Endpoint Enabled"
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bitfld.long 0x10 2. "OUTTKIEN,Out Token Interrupt Enable Bit" "0: The OUT token interrupt in Control Endpoint..,1: The OUT token interrupt in Control Endpoint.."
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bitfld.long 0x10 1. "SETUPPKIEN,Setup Packet Interrupt Enable Bit" "0: The SETUP packet interrupt in Control Endpoint..,1: The SETUP packet interrupt in Control Endpoint.."
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bitfld.long 0x10 0. "SETUPTKIEN,Setup Token Interrupt Enable Bit" "0: The SETUP token interrupt in Control Endpoint..,1: The SETUP token interrupt in Control Endpoint.."
line.long 0x14 "HSUSBD_CEPINTSTS,Control-endpoint Interrupt Status"
bitfld.long 0x14 12. "BUFEMPTYIF,Buffer Empty Interrupt \nNote: Write 1 to clear this bit to 0." "0: The control-endpoint buffer is not empty,1: The control-endpoint buffer is empty"
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bitfld.long 0x14 11. "BUFFULLIF,Buffer Full Interrupt \nNote: Write 1 to clear this bit to 0." "0: The control-endpoint buffer is not full,1: The control-endpoint buffer is full"
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bitfld.long 0x14 10. "STSDONEIF,Status Completion Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a USB transaction has completed successfully,1: The status stage of a USB transaction has.."
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bitfld.long 0x14 9. "ERRIF,USB Error Interrupt\nNote: Write 1 to clear this bit to 0." "0: No error had occurred during the transaction,1: An error had occurred during the transaction"
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bitfld.long 0x14 8. "STALLIF,STALL Sent Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a stall-token is sent in response to an..,1: A stall-token is sent in response to an IN/OUT.."
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bitfld.long 0x14 7. "NAKIF,NAK Sent Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a NAK-token is sent in response to an IN/OUT..,1: A NAK-token is sent in response to an IN/OUT token"
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bitfld.long 0x14 6. "RXPKIF,Data Packet Received Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is successfully received from..,1: A data packet is successfully received from the.."
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bitfld.long 0x14 5. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is successfully transmitted to..,1: A data packet is successfully transmitted to the.."
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bitfld.long 0x14 4. "PINGIF,Ping Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: The control-endpoint does not receive a ping..,1: The control-endpoint receives a ping token from.."
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bitfld.long 0x14 3. "INTKIF,In Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: The control-endpoint does not receive an IN..,1: The control-endpoint receives an IN token from.."
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bitfld.long 0x14 2. "OUTTKIF,Out Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: The control-endpoint does not receive an OUT..,1: The control-endpoint receives an OUT token from.."
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bitfld.long 0x14 1. "SETUPPKIF,Setup Packet Interrupt \nThis bit must be cleared (by writing 1) before the next setup packet can be received. If the bit is not cleared  then the successive setup packets will be overwritten in the setup packet buffer.\nNote: Write 1 to clear.." "0: Not a Setup packet has been received from the host,1: A Setup packet has been received from the host"
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bitfld.long 0x14 0. "SETUPTKIF,Setup Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a Setup token is received,1: A Setup token is received. Writing 1 clears this.."
line.long 0x18 "HSUSBD_CEPTXCNT,Control-endpoint In-transfer Data Count"
hexmask.long.byte 0x18 0.--7. 1. "TXCNT,In-transfer Data Count\nThere is no mode selection for the control endpoint (but it operates like manual mode). The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this.."
rgroup.long 0x3C++0x17
line.long 0x0 "HSUSBD_CEPRXCNT,Control-endpoint Out-transfer Data Count"
hexmask.long.byte 0x0 0.--7. 1. "RXCNT,Out-transfer Data Count \nThe USB device controller maintains the count of the data received in case of an out transfer  during the control transfer."
line.long 0x4 "HSUSBD_CEPDATCNT,Control-endpoint Data Count"
hexmask.long.word 0x4 0.--15. 1. "DATCNT,Control-endpoint Data Count \nThe USB device controller maintains the count of the data of control-endpoint."
line.long 0x8 "HSUSBD_SETUP1_0,Setup1 Setup0 Bytes"
hexmask.long.byte 0x8 8.--15. 1. "SETUP1,Setup Byte 1[15:8]\nThis register provides byte 1 of the last setup packet received. For a Standard Device Request  the following bRequest Code information is returned."
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hexmask.long.byte 0x8 0.--7. 1. "SETUP0,Setup Byte 0[7:0]\nThis register provides byte 0 of the last setup packet received. For a Standard Device Request  the following bmRequestType information is returned.\nBit 7 (Direction):"
line.long 0xC "HSUSBD_SETUP3_2,Setup3 Setup2 Bytes"
hexmask.long.byte 0xC 8.--15. 1. "SETUP3,Setup Byte 3[15:8]\nThis register provides byte 3 of the last setup packet received. For a Standard Device Request  the most significant byte of the wValue field is returned."
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hexmask.long.byte 0xC 0.--7. 1. "SETUP2,Setup Byte 2[7:0]\nThis register provides byte 2 of the last setup packet received. For a Standard Device Request  the least significant byte of the wValue field is returned."
line.long 0x10 "HSUSBD_SETUP5_4,Setup5 Setup4 Bytes"
hexmask.long.byte 0x10 8.--15. 1. "SETUP5,Setup Byte 5[15:8] \nThis register provides byte 5 of the last setup packet received. For a Standard Device Request  the most significant byte of the wIndex field is returned."
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hexmask.long.byte 0x10 0.--7. 1. "SETUP4,Setup Byte 4[7:0] \nThis register provides byte 4 of the last setup packet received. For a Standard Device Request  the least significant byte of the wIndex field is returned."
line.long 0x14 "HSUSBD_SETUP7_6,Setup7 Setup6 Bytes"
hexmask.long.byte 0x14 8.--15. 1. "SETUP7,Setup Byte 7[15:8] \nThis register provides byte 7 of the last setup packet received. For a Standard Device Request  the most significant byte of the wLength field is returned."
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hexmask.long.byte 0x14 0.--7. 1. "SETUP6,Setup Byte 6[7:0] \nThis register provides byte 6 of the last setup packet received. For a Standard Device Request  the least significant byte of the wLength field is returned."
group.long 0x54++0x1B
line.long 0x0 "HSUSBD_CEPBUFSTART,Control Endpoint RAM Start Address Register"
hexmask.long.word 0x0 0.--11. 1. "SADDR,Control-endpoint Start Address\nThis is the start-address of the RAM space allocated for the control-endpoint."
line.long 0x4 "HSUSBD_CEPBUFEND,Control Endpoint RAM End Address Register"
hexmask.long.word 0x4 0.--11. 1. "EADDR,Control-endpoint End Address\nThis is the end-address of the RAM space allocated for the control-endpoint."
line.long 0x8 "HSUSBD_DMACTL,DMA Control Status Register"
bitfld.long 0x8 8. "SVINEP,Serve IN Endpoint\nThis bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint." "0: DMA serves OUT endpoint,1: DMA serves IN endpoint"
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bitfld.long 0x8 7. "DMARST,Reset DMA State Machine" "0: No reset the DMA state machine,1: Reset the DMA state machine"
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bitfld.long 0x8 6. "SGEN,Scatter Gather Function Enable Bit" "0: Scatter gather function Disabled,1: Scatter gather function Enabled"
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bitfld.long 0x8 5. "DMAEN,DMA Enable Bit" "0: DMA function Disabled,1: DMA function Enabled"
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bitfld.long 0x8 4. "DMARD,DMA Operation" "0: The operation is a DMA write (read from USB..,1: The operation is a DMA read (write to USB buffer)"
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hexmask.long.byte 0x8 0.--3. 1. "EPNUM,DMA Endpoint Address Bits\nUsed to define the Endpoint Address"
line.long 0xC "HSUSBD_DMACNT,DMA Count Register"
hexmask.long.tbyte 0xC 0.--19. 1. "DMACNT,DMA Transfer Count\nThe transfer count of the DMA operation to be performed is written to this register."
line.long 0x10 "HSUSBD_EPADAT,Endpoint A Data Register"
hexmask.long 0x10 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x14 "HSUSBD_EPAINTSTS,Endpoint A Interrupt Status Register"
bitfld.long 0x14 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x14 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x14 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x14 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x14 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x14 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x14 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x14 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x14 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x14 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x14 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x14 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x14 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x18 "HSUSBD_EPAINTEN,Endpoint A Interrupt Enable Control Register"
bitfld.long 0x18 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x18 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x18 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x18 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x18 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x18 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x18 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x18 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x18 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x18 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x18 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x18 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x18 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x70++0x3
line.long 0x0 "HSUSBD_EPADATCNT,Endpoint A Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x74++0x23
line.long 0x0 "HSUSBD_EPARSPCTL,Endpoint A Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPAMPS,Endpoint A Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPATXCNT,Endpoint A Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPACFG,Endpoint A Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPABUFSTART,Endpoint A RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPABUFEND,Endpoint A RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPBDAT,Endpoint B Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPBINTSTS,Endpoint B Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPBINTEN,Endpoint B Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x98++0x3
line.long 0x0 "HSUSBD_EPBDATCNT,Endpoint B Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x9C++0x23
line.long 0x0 "HSUSBD_EPBRSPCTL,Endpoint B Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPBMPS,Endpoint B Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPBTXCNT,Endpoint B Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPBCFG,Endpoint B Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPBBUFSTART,Endpoint B RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPBBUFEND,Endpoint B RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPCDAT,Endpoint C Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPCINTSTS,Endpoint C Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPCINTEN,Endpoint C Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0xC0++0x3
line.long 0x0 "HSUSBD_EPCDATCNT,Endpoint C Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0xC4++0x23
line.long 0x0 "HSUSBD_EPCRSPCTL,Endpoint C Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPCMPS,Endpoint C Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPCTXCNT,Endpoint C Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPCCFG,Endpoint C Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPCBUFSTART,Endpoint C RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPCBUFEND,Endpoint C RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPDDAT,Endpoint D Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPDINTSTS,Endpoint D Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPDINTEN,Endpoint D Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0xE8++0x3
line.long 0x0 "HSUSBD_EPDDATCNT,Endpoint D Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0xEC++0x23
line.long 0x0 "HSUSBD_EPDRSPCTL,Endpoint D Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPDMPS,Endpoint D Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPDTXCNT,Endpoint D Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPDCFG,Endpoint D Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPDBUFSTART,Endpoint D RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPDBUFEND,Endpoint D RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPEDAT,Endpoint E Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPEINTSTS,Endpoint E Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPEINTEN,Endpoint E Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x110++0x3
line.long 0x0 "HSUSBD_EPEDATCNT,Endpoint E Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x114++0x23
line.long 0x0 "HSUSBD_EPERSPCTL,Endpoint E Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPEMPS,Endpoint E Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPETXCNT,Endpoint E Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPECFG,Endpoint E Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPEBUFSTART,Endpoint E RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPEBUFEND,Endpoint E RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPFDAT,Endpoint F Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPFINTSTS,Endpoint F Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPFINTEN,Endpoint F Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x138++0x3
line.long 0x0 "HSUSBD_EPFDATCNT,Endpoint F Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x13C++0x23
line.long 0x0 "HSUSBD_EPFRSPCTL,Endpoint F Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPFMPS,Endpoint F Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPFTXCNT,Endpoint F Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPFCFG,Endpoint F Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPFBUFSTART,Endpoint F RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPFBUFEND,Endpoint F RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPGDAT,Endpoint G Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPGINTSTS,Endpoint G Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPGINTEN,Endpoint G Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x160++0x3
line.long 0x0 "HSUSBD_EPGDATCNT,Endpoint G Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x164++0x23
line.long 0x0 "HSUSBD_EPGRSPCTL,Endpoint G Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPGMPS,Endpoint G Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPGTXCNT,Endpoint G Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPGCFG,Endpoint G Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPGBUFSTART,Endpoint G RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPGBUFEND,Endpoint G RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPHDAT,Endpoint H Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPHINTSTS,Endpoint H Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPHINTEN,Endpoint H Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x188++0x3
line.long 0x0 "HSUSBD_EPHDATCNT,Endpoint H Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x18C++0x23
line.long 0x0 "HSUSBD_EPHRSPCTL,Endpoint H Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPHMPS,Endpoint H Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPHTXCNT,Endpoint H Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPHCFG,Endpoint H Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPHBUFSTART,Endpoint H RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPHBUFEND,Endpoint H RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPIDAT,Endpoint I Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPIINTSTS,Endpoint I Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPIINTEN,Endpoint I Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x1B0++0x3
line.long 0x0 "HSUSBD_EPIDATCNT,Endpoint I Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x1B4++0x23
line.long 0x0 "HSUSBD_EPIRSPCTL,Endpoint I Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPIMPS,Endpoint I Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPITXCNT,Endpoint I Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPICFG,Endpoint I Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPIBUFSTART,Endpoint I RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPIBUFEND,Endpoint I RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPJDAT,Endpoint J Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPJINTSTS,Endpoint J Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPJINTEN,Endpoint J Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x1D8++0x3
line.long 0x0 "HSUSBD_EPJDATCNT,Endpoint J Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x1DC++0x23
line.long 0x0 "HSUSBD_EPJRSPCTL,Endpoint J Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPJMPS,Endpoint J Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPJTXCNT,Endpoint J Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPJCFG,Endpoint J Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPJBUFSTART,Endpoint J RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPJBUFEND,Endpoint J RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPKDAT,Endpoint K Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPKINTSTS,Endpoint K Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPKINTEN,Endpoint K Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x200++0x3
line.long 0x0 "HSUSBD_EPKDATCNT,Endpoint K Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x204++0x23
line.long 0x0 "HSUSBD_EPKRSPCTL,Endpoint K Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPKMPS,Endpoint K Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPKTXCNT,Endpoint K Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPKCFG,Endpoint K Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPKBUFSTART,Endpoint K RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPKBUFEND,Endpoint K RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
line.long 0x18 "HSUSBD_EPLDAT,Endpoint L Data Register"
hexmask.long 0x18 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported."
line.long 0x1C "HSUSBD_EPLINTSTS,Endpoint L Interrupt Status Register"
bitfld.long 0x1C 12. "SHORTRXIF,Bulk Out Short Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No bulk out short packet is received,1: Received bulk out short packet (including zero.."
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bitfld.long 0x1C 11. "ERRIF,ERR Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x1C 10. "NYETIF,NYET Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The space available in the RAM is sufficient to..,1: The space available in the RAM is not sufficient.."
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bitfld.long 0x1C 9. "STALLIF,USB STALL Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x1C 8. "NAKIF,USB NAK Sent Interrupt\nNote: Write 1 to clear this bit to 0." "0: The last USB IN packet could be provided and was..,1: The last USB IN packet could not be provided and.."
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bitfld.long 0x1C 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: A Data PING token has not been received from the..,1: A Data PING token has been received from the host"
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bitfld.long 0x1C 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not Data IN token has been received from the host,1: A Data IN token has been received from the host"
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bitfld.long 0x1C 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0." "0: A Data OUT token has not been received from the..,1: A Data OUT token has been received from the.."
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bitfld.long 0x1C 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0." "0: No data packet is received from the host by the..,1: A data packet is received from the host by the.."
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bitfld.long 0x1C 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0." "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the endpoint.."
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bitfld.long 0x1C 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0." "0: The length of the last packet was not less than..,1: The length of the last packet was less than the.."
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bitfld.long 0x1C 1. "BUFEMPTYIF,Buffer Empty Interrupt\nFor an IN endpoint  a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only." "0: The endpoint buffer is not empty.\nThe currently..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x1C 0. "BUFFULLIF,Buffer Full Interrupt\nFor an IN endpoint  the currently selected buffer is full  or no buffer is available to the local side for writing (no space to write). For an OUT endpoint  there is a buffer available on the local side  and there are.." "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
line.long 0x20 "HSUSBD_EPLINTEN,Endpoint L Interrupt Enable Control Register"
bitfld.long 0x20 12. "SHORTRXIEN,Bulk Out Short Packet Received Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint." "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x20 11. "ERRIEN,ERR Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint." "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x20 10. "NYETIEN,NYET Sent Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint." "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x20 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a stall token is sent to the host." "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x20 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a NAK token is sent to the host." "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x20 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a PING token has been received from the host." "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x20 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a Data IN token has been received from the host." "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x20 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a Data OUT token has been received from the host." "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x20 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been received from the host." "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x20 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a data packet has been transmitted to the host." "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x20 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host." "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x20 1. "BUFEMPTYIEN,Buffer Empty Interrupt Enable Bit\nWhen set  this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus." "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x20 0. "BUFFULLIEN,Buffer Full Interrupt Enable Bit \nWhen set  this bit enables a local interrupt to be set when a buffer full condition is detected on the bus." "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x228++0x3
line.long 0x0 "HSUSBD_EPLDATCNT,Endpoint L Data Available Count Register"
hexmask.long.word 0x0 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer."
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hexmask.long.word 0x0 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR (HSUSBD_EPxCFG[3] is high.)  this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR (HSUSBD_EPxCFG[3] is low.)  this register returns the number of.."
group.long 0x22C++0x17
line.long 0x0 "HSUSBD_EPLRSPCTL,Endpoint L Response Control Register"
bitfld.long 0x0 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference HSUSBD_EPxDATCNT register." "0: Buffer not disabled when Bulk-OUT short packet..,1: Buffer disabled when Bulk-OUT short packet is.."
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bitfld.long 0x0 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint  and happens to be the last transfer. This.." "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer which.."
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bitfld.long 0x0 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set  a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent." "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on reception.."
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bitfld.long 0x0 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU  it must write a '1' to this bit." "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the token.."
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bitfld.long 0x0 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.\nThe local CPU may use this bit to initialize the end-point's toggle in case of reception of a.." "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x0 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint. \nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected." "0: Auto-Validate Mode,1: Manual-Validate Mode,?,?"
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bitfld.long 0x0 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after a configuration event." "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
line.long 0x4 "HSUSBD_EPLMPS,Endpoint L Maximum Packet Size Register"
hexmask.long.word 0x4 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint."
line.long 0x8 "HSUSBD_EPLTXCNT,Endpoint L Transfer Count Register"
hexmask.long.word 0x8 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints  this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints  this field has no effect."
line.long 0xC "HSUSBD_EPLCFG,Endpoint L Configuration Register"
hexmask.long.byte 0xC 4.--7. 1. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number."
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bitfld.long 0xC 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number." "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0xC 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type." "0: Reserved.,1: Bulk,?,?"
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bitfld.long 0xC 0. "EPEN,Endpoint Valid\nWhen set  this bit enables this endpoint. This bit has no effect on Endpoint 0  which is always enabled." "0: The endpoint Disabled,1: The endpoint Enabled"
line.long 0x10 "HSUSBD_EPLBUFSTART,Endpoint L RAM Start Address Register"
hexmask.long.word 0x10 0.--12. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L."
line.long 0x14 "HSUSBD_EPLBUFEND,Endpoint L RAM End Address Register"
hexmask.long.word 0x14 0.--12. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L."
group.long 0x6F8++0xF
line.long 0x0 "HSUSBD_BCDC,Battery Charge Detect Control Register"
bitfld.long 0x0 31. "BCDIF,Battery Charge Detect Interrupt Status\nIt supports VBUSOK and DCD interrupt status \nNote: Write 1 to clear this bit to 0." "0: BCD event did not occur,1: BCD event occurred"
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bitfld.long 0x0 30. "BCDIEN,Battery Charge Detect Interrupt Enable Bit" "0: BCD Interrupt Disabled,1: BCD Interrupt Enabled"
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rbitfld.long 0x0 5. "USP,USB Special Port (Read Only)" "0: USB support port,1: Special port. (PS/2 or proprietary charger)"
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rbitfld.long 0x0 4. "DETSTS,Detect Status (Read Only)" "0: VBUS is less than threshold voltage.\nData pin..,1: VBUS is greater than threshold voltage.\nData.."
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bitfld.long 0x0 1.--3. "DETMOD,Detect Mode" "0: Idle nothing to detect,1: VBUS detect detect USB VBUS whether great than..,?,?,?,?,?,?"
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bitfld.long 0x0 0. "BCDEN,Battery Charge Detect Enable\nEnable battery charge detect  select DETMOD and then observer DETSTS to decide contact port." "0: Normal operation,1: Battery charge detect operation"
line.long 0x4 "HSUSBD_LPMCSR,LPM Control and Status Register"
bitfld.long 0x4 14. "LPMSENDNYET,LPM Send NYET Response" "0: Not send a NYET handshake as response to the LPM..,1: Send a NYET handshake as response to the LPM token"
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bitfld.long 0x4 13. "LPMSLEEPEN,LPM Sleep Function Enable Bit" "0: The LPM sleep function Disabled,1: The LPM sleep function Enabled"
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bitfld.long 0x4 12. "LPMEN,LPM Function Enable Bit" "0: The LPM function Disabled,1: The LPM function Enabled"
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hexmask.long.word 0x4 0.--10. 1. "bmAttributes,The LPM Token bmAttributes Field Definition (Read Only)\nBit 10-9 (Reserved)\nBit 8 (bRemoteWake)\nBit 7-4 (HIRD)\nBit 3-0 (bLinkState):"
line.long 0x8 "HSUSBD_DMAADDR,AHB DMA Address Register"
hexmask.long 0x8 0.--31. 1. "DMAADDR,DMAADDR\nThe register specifies the address from which the DMA has to read / write. The address must WORD (32-bit) aligned."
line.long 0xC "HSUSBD_PHYCTL,USB PHY Control Register"
bitfld.long 0xC 31. "VBUSDET,VBUS Status" "0: The VBUS is not detected yet,1: The VBUS is detected"
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bitfld.long 0xC 27. "PHYCLKSTB,PHY Clock Stable Flag" "0: The PHY clock is not stable for USB device usage,1: The PHY clock is stable for USB device usage"
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bitfld.long 0xC 26. "STALLREVERT,Stall Revert Write Pointer Enable Bit" "0: The Stall revert write pointer function Disabled,1: The Stall revert write pointer function Enabled"
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bitfld.long 0xC 25. "LINESTATEWKEN,Line State Wake-up Enable Bit" "0: The Line State wake-up function Disabled,1: The Line State wake-up function Enabled"
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bitfld.long 0xC 24. "VBUSWKEN,VBUS Wake-up Enable Bit" "0: The wake-up function Disabled,1: The wake-up function Enabled"
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bitfld.long 0xC 9. "PHYEN,PHY Suspend Enable Bit" "0: The USB PHY is suspend,1: The USB PHY is not suspend"
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bitfld.long 0xC 8. "DPPUEN,DP Pull-up Enable Bit" "0: Pull-up resistor on D+ Disabled,1: Pull-up resistor on D+ Enabled"
tree.end
tree "USBD"
base ad:0x400C0000
group.long 0x0++0xB
line.long 0x0 "USBD_INTEN,USB Device Interrupt Enable Register"
bitfld.long 0x0 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS0 and.."
bitfld.long 0x0 8. "WKEN,Wake-up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
newline
bitfld.long 0x0 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
bitfld.long 0x0 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x0 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
bitfld.long 0x0 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
newline
bitfld.long 0x0 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
line.long 0x4 "USBD_INTSTS,USB Device Interrupt Event Status Register"
bitfld.long 0x4 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by writing 1 to.."
bitfld.long 0x4 27. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11. Check.."
newline
bitfld.long 0x4 26. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10. Check.."
bitfld.long 0x4 25. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9. Check.."
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bitfld.long 0x4 24. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8. Check.."
bitfld.long 0x4 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7. Check.."
newline
bitfld.long 0x4 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6. Check.."
bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5. Check.."
newline
bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4. Check.."
bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3. Check.."
newline
bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2. Check.."
bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1. Check.."
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bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0. Check.."
bitfld.long 0x4 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event did not occur,1: SOF event occurred cleared by writing 1 to.."
newline
bitfld.long 0x4 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event did not occur,1: No-event-wake-up event occurred cleared by.."
bitfld.long 0x4 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.."
newline
bitfld.long 0x4 1. "USBIF,USB Event Interrupt Status\nThe USB event includes the SETUP Token  IN Token  OUT ACK  ISO IN  or ISO OUT events in the bus." "0: No USB event occurred,1: USB event occurred. Check EPSTS0~25 in.."
bitfld.long 0x4 0. "BUSIF,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus." "0: No BUS event occurred,1: Bus event occurred; check USBD_ATTR[3:0] to know.."
line.long 0x8 "USBD_FADDR,USB Device Function Address Register"
hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB device function address"
rgroup.long 0xC++0x3
line.long 0x0 "USBD_EPSTS,USB Device Endpoint Status Register"
bitfld.long 0x0 7. "OV,Overrun\nIt indicates that the received data is over the maximum payload number or not." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.."
group.long 0x10++0x3
line.long 0x0 "USBD_ATTR,USB Device Bus Status and Attribution Register"
rbitfld.long 0x0 13. "L1RESUME,LPM L1 Resume (Read Only)" "0: Bus no LPM L1 state resume,1: LPM L1 state resume from LPM L1 state suspend"
rbitfld.long 0x0 12. "L1SUSPEND,LPM L1 Suspend (Read Only)" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM command.."
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bitfld.long 0x0 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: The valid LPM Token will be NYET,1: The valid LPM Token will be ACK"
bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.."
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bitfld.long 0x0 9. "PWRDN,Power-down PHY Transceiver  Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
bitfld.long 0x0 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
newline
bitfld.long 0x0 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
bitfld.long 0x0 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D- high).."
newline
bitfld.long 0x0 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
rbitfld.long 0x0 3. "TOUT,Time-out Status (Read Only)" "0: No time-out,1: No Bus response more than 18 bits time"
newline
rbitfld.long 0x0 2. "RESUME,Resume Status (Read Only)" "0: No bus resume,1: Resume from suspend"
rbitfld.long 0x0 1. "SUSPEND,Suspend Status (Read Only)" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
newline
rbitfld.long 0x0 0. "USBRST,USB Reset Status (Read Only)" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
rgroup.long 0x14++0x3
line.long 0x0 "USBD_VBUSDET,USB Device VBUS Detection Register"
bitfld.long 0x0 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
group.long 0x18++0x3
line.long 0x0 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
hexmask.long.byte 0x0 3.--10. 1. "STBUFSEG,SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address. The effective starting address is\nUSBD_SRAM address + {STBUFSE.G. 3'b000} \nNote: It is used for SETUP.."
rgroup.long 0x20++0xF
line.long 0x0 "USBD_EPSTS0,USB Device Endpoint Status Register 0"
hexmask.long.byte 0x0 28.--31. 1. "EPSTS7,Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x0 24.--27. 1. "EPSTS6,Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x0 20.--23. 1. "EPSTS5,Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint."
line.long 0x4 "USBD_EPSTS1,USB Device Endpoint Status Register 1"
hexmask.long.byte 0x4 28.--31. 1. "EPSTS15,Endpoint 15 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x4 24.--27. 1. "EPSTS14,Endpoint 14 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 20.--23. 1. "EPSTS13,Endpoint 13 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x4 16.--19. 1. "EPSTS12,Endpoint 12 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 12.--15. 1. "EPSTS11,Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x4 8.--11. 1. "EPSTS10,Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 4.--7. 1. "EPSTS9,Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x4 0.--3. 1. "EPSTS8,Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint."
line.long 0x8 "USBD_EPSTS2,USB Device Endpoint Status Register 2"
hexmask.long.byte 0x8 28.--31. 1. "EPSTS23,Endpoint 23 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x8 24.--27. 1. "EPSTS22,Endpoint 22 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x8 20.--23. 1. "EPSTS21,Endpoint 21 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x8 16.--19. 1. "EPSTS20,Endpoint 20 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x8 12.--15. 1. "EPSTS19,Endpoint 19 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x8 8.--11. 1. "EPSTS18,Endpoint 18 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x8 4.--7. 1. "EPSTS17,Endpoint 17 Status\nThese bits are used to indicate the current status of this endpoint."
hexmask.long.byte 0x8 0.--3. 1. "EPSTS16,Endpoint 16 Status\nThese bits are used to indicate the current status of this endpoint."
line.long 0xC "USBD_EPSTS3,USB Device Endpoint Status Register 3"
hexmask.long.byte 0xC 0.--3. 1. "EPSTS24,Endpoint 24 Status\nThese bits are used to indicate the current status of this endpoint."
group.long 0x30++0x3
line.long 0x0 "USBD_EPINTSTS,USB Device Endpoint Interrupt Event Status Register"
bitfld.long 0x0 24. "EPEVT24,Endpoint 24's USB Event Status" "0: No event occurred in endpoint 24,1: USB event occurred on Endpoint 24. Check.."
bitfld.long 0x0 23. "EPEVT23,Endpoint 23's USB Event Status" "0: No event occurred in endpoint 23,1: USB event occurred on Endpoint 23. Check.."
newline
bitfld.long 0x0 22. "EPEVT22,Endpoint 22's USB Event Status" "0: No event occurred in endpoint 22,1: USB event occurred on Endpoint 22. Check.."
bitfld.long 0x0 21. "EPEVT21,Endpoint 21's USB Event Status" "0: No event occurred in endpoint 21,1: USB event occurred on Endpoint 21. Check.."
newline
bitfld.long 0x0 20. "EPEVT20,Endpoint 20's USB Event Status" "0: No event occurred in endpoint 20,1: USB event occurred on Endpoint 20. Check.."
bitfld.long 0x0 19. "EPEVT19,Endpoint 19's USB Event Status" "0: No event occurred in endpoint 19,1: USB event occurred on Endpoint 19. Check.."
newline
bitfld.long 0x0 18. "EPEVT18,Endpoint 18's USB Event Status" "0: No event occurred in endpoint 18,1: USB event occurred on Endpoint 18. Check.."
bitfld.long 0x0 17. "EPEVT17,Endpoint 17's USB Event Status" "0: No event occurred in endpoint 17,1: USB event occurred on Endpoint 17. Check.."
newline
bitfld.long 0x0 16. "EPEVT16,Endpoint 16's USB Event Status" "0: No event occurred in endpoint 16,1: USB event occurred on Endpoint 16. Check.."
bitfld.long 0x0 15. "EPEVT15,Endpoint 15's USB Event Status" "0: No event occurred in endpoint 15,1: USB event occurred on Endpoint 15. Check.."
newline
bitfld.long 0x0 14. "EPEVT14,Endpoint 14's USB Event Status" "0: No event occurred in endpoint 14,1: USB event occurred on Endpoint 14. Check.."
bitfld.long 0x0 13. "EPEVT13,Endpoint 13's USB Event Status" "0: No event occurred in endpoint 13,1: USB event occurred on Endpoint 13. Check.."
newline
bitfld.long 0x0 12. "EPEVT12,Endpoint 12's USB Event Status" "0: No event occurred in endpoint 12,1: USB event occurred on Endpoint 12. Check.."
bitfld.long 0x0 11. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11. Check.."
newline
bitfld.long 0x0 10. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10. Check.."
bitfld.long 0x0 9. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9. Check.."
newline
bitfld.long 0x0 8. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8. Check.."
bitfld.long 0x0 7. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7. Check.."
newline
bitfld.long 0x0 6. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6. Check.."
bitfld.long 0x0 5. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5. Check.."
newline
bitfld.long 0x0 4. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4. Check.."
bitfld.long 0x0 3. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3. Check.."
newline
bitfld.long 0x0 2. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2. Check.."
bitfld.long 0x0 1. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1. Check.."
newline
bitfld.long 0x0 0. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0. Check.."
rgroup.long 0x88++0x7
line.long 0x0 "USBD_LPMATTR,USB LPM Attribution Register"
bitfld.long 0x0 8. "LPMRWAKUP,LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "LPMBESL,LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token"
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hexmask.long.byte 0x0 0.--3. 1. "LPMLINKSTS,LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token"
line.long 0x4 "USBD_FN,USB Frame Number Register"
hexmask.long.word 0x4 0.--10. 1. "FN,Frame Number\nThese bits contain the 11 bits frame number in the last received SOF packet."
group.long 0x90++0x3
line.long 0x0 "USBD_SE0,USB Device Drive SE0 Control Register"
bitfld.long 0x0 0. "SE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low." "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
group.long 0x500++0x18F
line.long 0x0 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
hexmask.long.byte 0x0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x4 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
hexmask.long.word 0x4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x8 "USBD_CFG0,Endpoint 0 Configuration Register"
bitfld.long 0x8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
newline
bitfld.long 0x8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
newline
bitfld.long 0x8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
newline
hexmask.long.byte 0x8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xC "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x10 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
hexmask.long.byte 0x10 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x14 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
hexmask.long.word 0x14 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x18 "USBD_CFG1,Endpoint 1 Configuration Register"
bitfld.long 0x18 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x18 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
newline
bitfld.long 0x18 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x18 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
newline
bitfld.long 0x18 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
newline
hexmask.long.byte 0x18 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x1C "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x1C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x1C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x20 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
hexmask.long.byte 0x20 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x24 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
hexmask.long.word 0x24 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x28 "USBD_CFG2,Endpoint 2 Configuration Register"
bitfld.long 0x28 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x28 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
newline
bitfld.long 0x28 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x28 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
newline
bitfld.long 0x28 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
newline
hexmask.long.byte 0x28 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x2C "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x2C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x2C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x30 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
hexmask.long.byte 0x30 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x34 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
hexmask.long.word 0x34 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x38 "USBD_CFG3,Endpoint 3 Configuration Register"
bitfld.long 0x38 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x38 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x38 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x38 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
newline
bitfld.long 0x38 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
newline
hexmask.long.byte 0x38 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x3C "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x3C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x3C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x40 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
hexmask.long.byte 0x40 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x44 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
hexmask.long.word 0x44 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x48 "USBD_CFG4,Endpoint 4 Configuration Register"
bitfld.long 0x48 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x48 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x48 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x48 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x48 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x48 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x4C "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x4C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x4C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x50 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
hexmask.long.byte 0x50 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x54 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
hexmask.long.word 0x54 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x58 "USBD_CFG5,Endpoint 5 Configuration Register"
bitfld.long 0x58 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x58 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x58 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x58 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x58 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x58 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x5C "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x5C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x5C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x60 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
hexmask.long.byte 0x60 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x64 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
hexmask.long.word 0x64 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x68 "USBD_CFG6,Endpoint 6 Configuration Register"
bitfld.long 0x68 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x68 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x68 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x68 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x68 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x68 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x68 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x6C "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x6C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x6C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x70 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
hexmask.long.byte 0x70 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x74 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
hexmask.long.word 0x74 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x78 "USBD_CFG7,Endpoint 7 Configuration Register"
bitfld.long 0x78 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x78 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x78 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x78 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x78 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x78 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x78 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x7C "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x7C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x7C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x80 "USBD_BUFSEG8,Endpoint 8 Buffer Segmentation Register"
hexmask.long.byte 0x80 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x84 "USBD_MXPLD8,Endpoint 8 Maximal Payload Register"
hexmask.long.word 0x84 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x88 "USBD_CFG8,Endpoint 8 Configuration Register"
bitfld.long 0x88 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x88 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x88 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x88 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x88 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x88 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x88 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x8C "USBD_CFGP8,Endpoint 8 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x8C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x8C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x90 "USBD_BUFSEG9,Endpoint 9 Buffer Segmentation Register"
hexmask.long.byte 0x90 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x94 "USBD_MXPLD9,Endpoint 9 Maximal Payload Register"
hexmask.long.word 0x94 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x98 "USBD_CFG9,Endpoint 9 Configuration Register"
bitfld.long 0x98 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x98 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x98 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x98 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x98 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x98 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x98 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x9C "USBD_CFGP9,Endpoint 9 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x9C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x9C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0xA0 "USBD_BUFSEG10,Endpoint 10 Buffer Segmentation Register"
hexmask.long.byte 0xA0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0xA4 "USBD_MXPLD10,Endpoint 10 Maximal Payload Register"
hexmask.long.word 0xA4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0xA8 "USBD_CFG10,Endpoint 10 Configuration Register"
bitfld.long 0xA8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0xA8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xA8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0xA8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xA8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0xA8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xA8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xAC "USBD_CFGP10,Endpoint 10 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xAC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xAC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0xB0 "USBD_BUFSEG11,Endpoint 11 Buffer Segmentation Register"
hexmask.long.byte 0xB0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0xB4 "USBD_MXPLD11,Endpoint 11 Maximal Payload Register"
hexmask.long.word 0xB4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0xB8 "USBD_CFG11,Endpoint 11 Configuration Register"
bitfld.long 0xB8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0xB8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xB8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0xB8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xB8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0xB8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xB8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xBC "USBD_CFGP11,Endpoint 11 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xBC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xBC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0xC0 "USBD_BUFSEG12,Endpoint 12 Buffer Segmentation Register"
hexmask.long.byte 0xC0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0xC4 "USBD_MXPLD12,Endpoint 12 Maximal Payload Register"
hexmask.long.word 0xC4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0xC8 "USBD_CFG12,Endpoint 12 Configuration Register"
bitfld.long 0xC8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0xC8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xC8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0xC8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xC8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0xC8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xC8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xCC "USBD_CFGP12,Endpoint 12 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xCC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xCC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0xD0 "USBD_BUFSEG13,Endpoint 13 Buffer Segmentation Register"
hexmask.long.byte 0xD0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0xD4 "USBD_MXPLD13,Endpoint 13 Maximal Payload Register"
hexmask.long.word 0xD4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0xD8 "USBD_CFG13,Endpoint 13 Configuration Register"
bitfld.long 0xD8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0xD8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xD8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0xD8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xD8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0xD8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xD8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xDC "USBD_CFGP13,Endpoint 13 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xDC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xDC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0xE0 "USBD_BUFSEG14,Endpoint 14 Buffer Segmentation Register"
hexmask.long.byte 0xE0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0xE4 "USBD_MXPLD14,Endpoint 14 Maximal Payload Register"
hexmask.long.word 0xE4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0xE8 "USBD_CFG14,Endpoint 14 Configuration Register"
bitfld.long 0xE8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0xE8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xE8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0xE8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xE8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0xE8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xE8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xEC "USBD_CFGP14,Endpoint 14 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xEC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xEC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0xF0 "USBD_BUFSEG15,Endpoint 15 Buffer Segmentation Register"
hexmask.long.byte 0xF0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0xF4 "USBD_MXPLD15,Endpoint 15 Maximal Payload Register"
hexmask.long.word 0xF4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0xF8 "USBD_CFG15,Endpoint 15 Configuration Register"
bitfld.long 0xF8 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0xF8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xF8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0xF8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xF8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0xF8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xF8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0xFC "USBD_CFGP15,Endpoint 15 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0xFC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0xFC 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x100 "USBD_BUFSEG16,Endpoint 16 Buffer Segmentation Register"
hexmask.long.byte 0x100 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x104 "USBD_MXPLD16,Endpoint 16 Maximal Payload Register"
hexmask.long.word 0x104 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x108 "USBD_CFG16,Endpoint 16 Configuration Register"
bitfld.long 0x108 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x108 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x108 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x108 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x108 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x108 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x108 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x10C "USBD_CFGP16,Endpoint 16 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x10C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x10C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x110 "USBD_BUFSEG17,Endpoint 17 Buffer Segmentation Register"
hexmask.long.byte 0x110 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x114 "USBD_MXPLD17,Endpoint 17 Maximal Payload Register"
hexmask.long.word 0x114 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x118 "USBD_CFG17,Endpoint 17 Configuration Register"
bitfld.long 0x118 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x118 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x118 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x118 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x118 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x118 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x118 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x11C "USBD_CFGP17,Endpoint 17 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x11C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x11C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x120 "USBD_BUFSEG18,Endpoint 18 Buffer Segmentation Register"
hexmask.long.byte 0x120 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x124 "USBD_MXPLD18,Endpoint 18 Maximal Payload Register"
hexmask.long.word 0x124 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x128 "USBD_CFG18,Endpoint 18 Configuration Register"
bitfld.long 0x128 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x128 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x128 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x128 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x128 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x128 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x128 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x12C "USBD_CFGP18,Endpoint 18 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x12C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x12C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x130 "USBD_BUFSEG19,Endpoint 19 Buffer Segmentation Register"
hexmask.long.byte 0x130 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x134 "USBD_MXPLD19,Endpoint 19 Maximal Payload Register"
hexmask.long.word 0x134 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x138 "USBD_CFG19,Endpoint 19 Configuration Register"
bitfld.long 0x138 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x138 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x138 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x138 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x138 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x138 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x138 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x13C "USBD_CFGP19,Endpoint 19 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x13C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x13C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x140 "USBD_BUFSEG20,Endpoint 20 Buffer Segmentation Register"
hexmask.long.byte 0x140 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x144 "USBD_MXPLD20,Endpoint 20 Maximal Payload Register"
hexmask.long.word 0x144 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x148 "USBD_CFG20,Endpoint 20 Configuration Register"
bitfld.long 0x148 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x148 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x148 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x148 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x148 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x148 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x148 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x14C "USBD_CFGP20,Endpoint 20 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x14C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x14C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x150 "USBD_BUFSEG21,Endpoint 21 Buffer Segmentation Register"
hexmask.long.byte 0x150 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x154 "USBD_MXPLD21,Endpoint 21 Maximal Payload Register"
hexmask.long.word 0x154 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x158 "USBD_CFG21,Endpoint 21 Configuration Register"
bitfld.long 0x158 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x158 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x158 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x158 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x158 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x158 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x158 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x15C "USBD_CFGP21,Endpoint 21 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x15C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x15C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x160 "USBD_BUFSEG22,Endpoint 22 Buffer Segmentation Register"
hexmask.long.byte 0x160 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x164 "USBD_MXPLD22,Endpoint 22 Maximal Payload Register"
hexmask.long.word 0x164 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x168 "USBD_CFG22,Endpoint 22 Configuration Register"
bitfld.long 0x168 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x168 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x168 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x168 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x168 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x168 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x168 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x16C "USBD_CFGP22,Endpoint 22 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x16C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x16C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x170 "USBD_BUFSEG23,Endpoint 23 Buffer Segmentation Register"
hexmask.long.byte 0x170 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x174 "USBD_MXPLD23,Endpoint 23 Maximal Payload Register"
hexmask.long.word 0x174 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x178 "USBD_CFG23,Endpoint 23 Configuration Register"
bitfld.long 0x178 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x178 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x178 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x178 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x178 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x178 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x178 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x17C "USBD_CFGP23,Endpoint 23 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x17C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x17C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
line.long 0x180 "USBD_BUFSEG24,Endpoint 24 Buffer Segmentation Register"
hexmask.long.byte 0x180 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSE.G. 3'b000}\nRefer to the section 6.33.5.7.."
line.long 0x184 "USBD_MXPLD24,Endpoint 24 Maximal Payload Register"
hexmask.long.word 0x184 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
line.long 0x188 "USBD_CFG24,Endpoint 24 Configuration Register"
bitfld.long 0x188 11. "DBEN,Double Buffer Enable" "0: Single buffer mode,1: Double buffer mode"
bitfld.long 0x188 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x188 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
bitfld.long 0x188 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x188 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
bitfld.long 0x188 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint  no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x188 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
line.long 0x18C "USBD_CFGP24,Endpoint 24 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x18C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x18C 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~24 register is set by user  it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start  users can set this bit to 1 to disable it.." "0,1"
tree.end
tree.end
tree "USBH (USB 1.1 Host Controller)"
base ad:0x0
tree "HSUSBH"
base ad:0x4001A000
rgroup.long 0x0++0xB
line.long 0x0 "EHCVNR,EHCI Version Number Register"
hexmask.long.word 0x0 16.--31. 1. "VERSION,Host Controller Interface Version Number\nThis is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least.."
hexmask.long.byte 0x0 0.--7. 1. "CRLEN,Capability Registers Length\nThis register is used as an offset to add to register base to find the beginning of the Operational Register Space."
line.long 0x4 "EHCSPR,EHCI Structural Parameters Register"
hexmask.long.byte 0x4 12.--15. 1. "N_CC,Number of Companion Controller\nThis field indicates the number of companion controllers associated with this USB 2.0 host controller.\nA 0 in this field indicates there are no companion host controllers. Port-ownership hand-off is not supported."
hexmask.long.byte 0x4 8.--11. 1. "N_PCC,Number of Ports Per Companion Controller\nThis field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software.\nFor example  if N_PORTS has a value of 6 and N_CC.."
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bitfld.long 0x4 4. "PPC,Port Power Control\nThis field indicates whether the host controller implementation includes port power control. A 1 in this bit indicates the ports have port power switches. A 0 in this bit indicates the port do not have port power stitches. The.." "0,1"
hexmask.long.byte 0x4 0.--3. 1. "N_PORTS,Number of Physical Downstream Ports\nThis field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space.."
line.long 0x8 "EHCCPR,EHCI Capability Parameters Register"
hexmask.long.byte 0x8 8.--15. 1. "EECP,EHCI Extended Capabilities Pointer"
hexmask.long.byte 0x8 4.--7. 1. "IST,Isochronous Scheduling Threshold\nThis field indicates  relative to the current position of the executing host controller  where software can reliably update the isochronous schedule.\nWhen bit [7] is 0  the value of the least significant 3 bits.."
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bitfld.long 0x8 2. "ASPC,Asynchronous Schedule Park Capability" "0: This EHCI host controller doesn't support park..,?"
bitfld.long 0x8 1. "PFLF,Programmable Frame List Flag" "0: System software must use a frame list length of..,?"
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bitfld.long 0x8 0. "AC64,64-bit Addressing Capability" "0: Data structure using 32-bit address memory..,?"
group.long 0x20++0xF
line.long 0x0 "UCMDR,USB Command Register"
hexmask.long.byte 0x0 16.--23. 1. "ITC,Interrupt Threshold Control (Read/Write)\nThis field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this.."
bitfld.long 0x0 6. "IAAD,Interrupt on Asynchronous Advance Doorbell (Read/Write)\nThis bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the.." "0,1"
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bitfld.long 0x0 5. "ASEN,Asynchronous Schedule Enable (Read/Write)\nThis bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:" "0: Do not process the Asynchronous Schedule,1: Use the ASYNCLISTADDR register to access the.."
bitfld.long 0x0 4. "PSEN,Periodic Schedule Enable (Read/Write)\nThis bit controls whether the host controller skips processing the Periodic Schedule. Values mean:" "0: Do not process the Periodic Schedule,1: Use the PERIODICLISTBASE register to access the.."
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rbitfld.long 0x0 2.--3. "FLSZ,Frame List Size (Read Only)\nThis field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a 1. This field specifies the size of the frame list. The size the frame list controls which bits in the Frame Index Register.." "0: 1024 elements (4096 bytes) Default value,1: 512 elements (2048 bytes),?,?"
bitfld.long 0x0 1. "HCRST,Host Controller Reset (Read/Write)\nThis control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.\nWhen software writes a 1 to this bit  the Host Controller resets.." "0,1"
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bitfld.long 0x0 0. "RUN,Run/Stop (Read/Write)\nWhen set to a 1  the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0  the Host Controller completes the current and.." "0: Stop,1: Run"
line.long 0x4 "USTSR,USB Status Register"
rbitfld.long 0x4 15. "ASS,Asynchronous Schedule Status (Read Only)\nThe bit reports the current real status of the Asynchronous Schedule. If this bit is 0 then the status of them Asynchronous Schedule is disabled. If this bit is a 1 then the status of the Asynchronous.." "0,1"
rbitfld.long 0x4 14. "PSS,Periodic Schedule Status (Read Only)\nThe bit reports the current real status of the Periodic Schedule. If this bit is 0 then the status of the Periodic Schedule is disabled. If this bit is a 1 then the status of the Periodic Schedule is enabled. The.." "0,1"
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rbitfld.long 0x4 13. "RECLA,Reclamation (Read Only)\nThis is a read-only status bit  which is used to detect an empty asynchronous schedule." "0,1"
rbitfld.long 0x4 12. "HCHalted,HCHalted (Read Only)\nThis bit is 0 whenever the Run/Stop bit is a 1. The Host Controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit being set to 0  either by software or by the Host Controller hardware.." "0,1"
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bitfld.long 0x4 5. "IAA,Interrupt on Asynchronous Advance\nSystem software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the Interrupt on Asynchronous Advance Doorbell bit in the.." "0,1"
bitfld.long 0x4 4. "HSERR,Host System Error\nThe Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.\nNote: This bit is cleared by writing 1 to it." "0,1"
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bitfld.long 0x4 3. "FLR,Frame List Rollover\nThe Host Controller sets this bit to a 1 when the Frame List Index rolls over from its maximum value to 0. The exact value at which the rollover occurs depends on the frame list size. For example  if the frame list size (as.." "0,1"
bitfld.long 0x4 2. "PCD,Port Change Detect\nThe Host Controller sets this bit to a 1 when any port for which the Port Owner bit is set to 0 has a change bit transition from 0 to 1 or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected.." "0,1"
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bitfld.long 0x4 1. "UERRINT,USB Error Interrupt\nThe Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g.  error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set  both this.." "0,1"
bitfld.long 0x4 0. "USBINT,USB Interrupt\nThe Host Controller sets this bit to 1 on the completion of a USB transaction  which results in the retirement of a Transfer Descriptor that had its IOC bit set.\nThe Host Controller also sets this bit to 1 when a short packet is.." "0,1"
line.long 0x8 "UIENR,USB Interrupt Enable Register"
bitfld.long 0x8 5. "IAAEN,Interrupt on Asynchronous Advance Enable or Disable Bit\nWhen this bit is a 1  and the Interrupt on Asynchronous Advance bit in the USTSR register is a 1  the host controller will issue an interrupt at the next interrupt threshold. The interrupt is.." "0: Interrupt on Asynchronous Advance Disabled,1: Interrupt on Asynchronous Advance Enabled"
bitfld.long 0x8 4. "HSERREN,Host System Error Enable or Disable Bit\nWhen this bit is a 1  and the Host System Error Status bit in the USTSR register is a 1  the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System.." "0: Host System Error interrupt Disabled,1: Host System Error interrupt Enabled"
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bitfld.long 0x8 3. "FLREN,Frame List Rollover Enable or Disable Bit\nWhen this bit is a 1  and the Frame List Rollover bit in the USTSR register is a 1  the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover.." "0: Frame List Rollover interrupt Disabled,1: Frame List Rollover interrupt Enabled"
bitfld.long 0x8 2. "PCIEN,Port Change Interrupt Enable or Disable Bit\nWhen this bit is a 1  and the Port Change Detect bit in the USTSR register is a 1  the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect.." "0: Port Change interrupt Disabled,1: Port Change interrupt Enabled"
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bitfld.long 0x8 1. "UERRIEN,USB Error Interrupt Enable or Disable Bit\nWhen this bit is a 1  and the UERRINT bit in the USTSR register is a 1  the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the.." "0: USB Error interrupt Disabled,1: USB Error interrupt Enabled"
bitfld.long 0x8 0. "USBIEN,USB Interrupt Enable or Disable Bit\nWhen this bit is a 1  and the USBINT bit in the USTSR register is a 1  the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT.." "0: USB interrupt Disabled,1: USB interrupt Enabled"
line.long 0xC "UFINDR,USB Frame Index Register"
hexmask.long.word 0xC 0.--13. 1. "FI,Frame Index\nThe value in this register increment at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames).."
group.long 0x34++0xB
line.long 0x0 "UPFLBAR,USB Periodic Frame List Base Address Register"
hexmask.long.tbyte 0x0 12.--31. 1. "BADDR,Base Address\nThese bits correspond to memory address signals [31:12]  respectively."
line.long 0x4 "UCALAR,USB Current Asynchronous List Address Register"
hexmask.long 0x4 5.--31. 1. "LPL,Link Pointer Low\nThese bits correspond to memory address signals [31:5]  respectively. This field may only reference a Queue Head (QH)."
line.long 0x8 "UASSTR,USB Asynchronous Schedule Sleep Timer Register"
hexmask.long.word 0x8 0.--11. 1. "ASSTMR,Asynchronous Schedule Sleep Timer\nThis field defines the AsyncSchedSleepTime of EHCI spec.\nThe asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the.."
group.long 0x60++0xB
line.long 0x0 "UCFGR,USB Configure Flag Register"
bitfld.long 0x0 0. "CF,Configure Flag\nHost software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below." "0: Port routing control logic default-routes each..,1: Port routing control logic default-routes all.."
line.long 0x4 "UPSCR0,USB Port 0 Status and Control Register"
hexmask.long.byte 0x4 16.--19. 1. "PTC,Port Test Control (Read/Write)\nWhen this field is 0  the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode.."
bitfld.long 0x4 13. "PO,Port Owner (Read/Write)\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is 0.\nSystem software uses this field to.." "0,1"
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bitfld.long 0x4 12. "PP,Port Power\nWhen an overcurrent condition is detected on a powered port and PPC is a 1  the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port)." "0,1"
rbitfld.long 0x4 10.--11. "LSTS,Line Status (Read Only)\nThese bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only.." "0: SE0 Not Low-speed device perform EHCI reset,1: K-state Low-speed device release ownership of port,?,?"
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bitfld.long 0x4 8. "PRST,Port Reset (Read/Write)\nWhen software writes a 1 to this bit (from a 0)  the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep.." "0: Port is not in Reset,1: Port is in Reset"
bitfld.long 0x4 7. "SUSPEND,Suspend (Read/Write)\nPort Enabled Bit and Suspend bit of this register define the port states as follows:" "0: Port Disable.\nPort not in suspend state,1: Port Disable.\nPort in suspend state"
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bitfld.long 0x4 6. "FPR,Force Port Resume (Read/Write)\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example  if the port is not suspended (Suspend and Enabled bits are a 1) and software transitions this bit to a 1  then.." "0: No resume (K-state) detected/driven on port,1: Resume detected/driven on port"
bitfld.long 0x4 5. "OCC,Overcurrent Change\nNote: This bit is cleared by writing 1 to it." "?,1: This bit gets set to a 1 when there is a change.."
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rbitfld.long 0x4 4. "OCA,Overcurrent Active (Read Only)\nThis bit will automatically transition from a 1 to a 0 when the overcurrent condition is removed." "0: This port does not have an overcurrent condition,1: This port currently has an overcurrent condition"
bitfld.long 0x4 3. "PEC,Port Enable/Disable Change\nFor the root hub  this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software.." "0: No change,1: Port enabled/disabled status has changed"
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bitfld.long 0x4 2. "PE,Port Enabled/Disabled (Read/Write)\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this field. The host controller will only set this bit to a 1 when the reset.." "0: Port Disabled,1: Port Enabled"
bitfld.long 0x4 1. "CSC,Connect Status Change (Read/Write)\nIndicate a change has occurred in the port's Current Connect Status. The host controller sets this bit for all changes to the port device connect status  even if system software has not cleared an existing connect.." "0: No change,1: Change in Current Connect Status"
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rbitfld.long 0x4 0. "CCS,Current Connect Status (Read Only)\nThis value reflects the current state of the port  and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.\nThis field is 0 if Port Power is 0." "0: No device is present,1: Device is present on port"
line.long 0x8 "UPSCR1,USB Port 1 Status and Control Register"
hexmask.long.byte 0x8 16.--19. 1. "PTC,Port Test Control (Read/Write)\nWhen this field is 0  the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode.."
bitfld.long 0x8 13. "PO,Port Owner (Read/Write)\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is 0.\nSystem software uses this field to.." "0,1"
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bitfld.long 0x8 12. "PP,Port Power\nWhen an overcurrent condition is detected on a powered port and PPC is a 1  the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port)." "0,1"
rbitfld.long 0x8 10.--11. "LSTS,Line Status (Read Only)\nThese bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only.." "0: SE0 Not Low-speed device perform EHCI reset,1: K-state Low-speed device release ownership of port,?,?"
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bitfld.long 0x8 8. "PRST,Port Reset (Read/Write)\nWhen software writes a 1 to this bit (from a 0)  the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep.." "0: Port is not in Reset,1: Port is in Reset"
bitfld.long 0x8 7. "SUSPEND,Suspend (Read/Write)\nPort Enabled Bit and Suspend bit of this register define the port states as follows:" "0: Port Disable.\nPort not in suspend state,1: Port Disable.\nPort in suspend state"
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bitfld.long 0x8 6. "FPR,Force Port Resume (Read/Write)\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example  if the port is not suspended (Suspend and Enabled bits are a 1) and software transitions this bit to a 1  then.." "0: No resume (K-state) detected/driven on port,1: Resume detected/driven on port"
bitfld.long 0x8 5. "OCC,Overcurrent Change\nNote: This bit is cleared by writing 1 to it." "?,1: This bit gets set to a 1 when there is a change.."
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rbitfld.long 0x8 4. "OCA,Overcurrent Active (Read Only)\nThis bit will automatically transition from a 1 to a 0 when the overcurrent condition is removed." "0: This port does not have an overcurrent condition,1: This port currently has an overcurrent condition"
bitfld.long 0x8 3. "PEC,Port Enable/Disable Change\nFor the root hub  this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software.." "0: No change,1: Port enabled/disabled status has changed"
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bitfld.long 0x8 2. "PE,Port Enabled/Disabled (Read/Write)\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this field. The host controller will only set this bit to a 1 when the reset.." "0: Port Disabled,1: Port Enabled"
bitfld.long 0x8 1. "CSC,Connect Status Change (Read/Write)\nIndicate a change has occurred in the port's Current Connect Status. The host controller sets this bit for all changes to the port device connect status  even if system software has not cleared an existing connect.." "0: No change,1: Change in Current Connect Status"
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rbitfld.long 0x8 0. "CCS,Current Connect Status (Read Only)\nThis value reflects the current state of the port  and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.\nThis field is 0 if Port Power is 0." "0: No device is present,1: Device is present on port"
group.long 0xC4++0x7
line.long 0x0 "USBPCR0,USB PHY 0 Control Register"
bitfld.long 0x0 13. "FDISCEN,Force Disconnection Function Enable Bit\nThis bit is used to enable Force Disconnection Function (FDISC)." "0: Force Disconnection Function Disabled,1: Force Disconnection Function Enabled"
bitfld.long 0x0 12. "FDISC,Force Disconnection Function\nThis bit is used to force the device to disconnect without really removing the device from the port. This bit is valid only if FDISCEN is asserted." "0: The device is not forced to be disconnected,1: The device is forced to disconnected"
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bitfld.long 0x0 11. "CLKVALID,UTMI Clock Valid\nThis bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready. Software program must prevent to write other control registers before this UTMI clock valid flag is active." "0: UTMI clock is not valid,1: UTMI clock is valid"
bitfld.long 0x0 8. "SUSPEND,Suspend Assertion\nThis bit controls the suspend mode of USB PHY 0.\nWhile PHY was suspended  all circuits of PHY were powered down and outputs are tri-state.\nThis bit is 1'b0 by default. This means the USB PHY 0 is suspended by default. It is.." "0: USB PHY 0 was suspended,1: USB PHY 0 was not suspended"
line.long 0x4 "USBPCR1,USB PHY 1 Control Register"
bitfld.long 0x4 13. "FDISCEN,Force Disconnection Function Enable\nThis bit is used to enable Force Disconnection Function (FDISC)." "0: Force Disconnection Function Disabled,1: Force Disconnection Function Enabled"
bitfld.long 0x4 12. "FDISC,Force Disconnection Function\nThis bit is used to force the device to disconnect without really removing the device from the port. This bit is valid only if FDISCEN is asserted." "0: The device is not forced to disconnect,1: The device is forced to disconnect"
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bitfld.long 0x4 8. "SUSPEND,Suspend Assertion\nThis bit controls the suspend mode of USB PHY 1.\nWhile PHY was suspended  all circuits of PHY were powered down and outputs are tri-state.\nThis bit is 1'b0 by default. This means the USB PHY 0 is suspended by default. It is.." "0: USB PHY 1 suspended,1: USB PHY 1 not suspended"
tree.end
tree "USBH"
base ad:0x40009000
rgroup.long 0x0++0x3
line.long 0x0 "HcRevision,Host Controller Revision Register"
hexmask.long.byte 0x0 0.--7. 1. "REV,Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification."
group.long 0x4++0x17
line.long 0x0 "HcControl,Host Controller Control Register"
bitfld.long 0x0 6.--7. "HCFS,Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are:" "0: USBRESET,1: USBRESUME,?,?"
bitfld.long 0x0 5. "BLE,Bulk List Enable Bit" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
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bitfld.long 0x0 4. "CLE,Control List Enable Bit" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next frame.."
bitfld.long 0x0 3. "IE,Isochronous List Enable Bit\nBoth IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list." "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the next.."
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bitfld.long 0x0 2. "PLE,Periodic List Enable Bit\nWhen set  this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.\nNote: To enable the processing of the.." "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
bitfld.long 0x0 0.--1. "CBSR,Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists  HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been.." "0: Number of Control EDs over Bulk EDs served is 1:1,1: Number of Control EDs over Bulk EDs served is 2:1,?,?"
line.long 0x4 "HcCommandStatus,Host Controller Command Status Register"
bitfld.long 0x4 16.--17. "SOC,Schedule Overrun Count\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been.." "0,1,2,3"
bitfld.long 0x4 2. "BLF,Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list." "0: No active TD found or Host Controller begins to..,1: An active TD added or found on the Bulk list"
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bitfld.long 0x4 1. "CLF,Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List." "0: No active TD found or Host Controller begins to..,1: An active TD added or found on the Control list"
bitfld.long 0x4 0. "HCR,Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller  upon completed of the reset operation.\nThis bit  when set  didn't reset the Root Hub and no subsequent reset.." "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
line.long 0x8 "HcInterruptStatus,Host Controller Interrupt Status Register"
bitfld.long 0x8 6. "RHSC,Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed." "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
bitfld.long 0x8 5. "FNO,Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1." "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to 0.."
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bitfld.long 0x8 3. "RD,Resume Detected\nSet when Host Controller detects resume signaling on a downstream port." "0: No resume signaling detected on a downstream port,1: Resume signaling detected on a downstream port"
bitfld.long 0x8 2. "SF,Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time." "0: Not the start of a frame,1: Indicate the start of a frame and Host.."
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bitfld.long 0x8 1. "WDH,Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared." "0: Host Controller didn't update HccaDoneHead,1: Host Controller has written HcDoneHead to.."
bitfld.long 0x8 0. "SO,Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred." "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
line.long 0xC "HcInterruptEnable,Host Controller Interrupt Enable Register"
bitfld.long 0xC 31. "MIE,Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
bitfld.long 0xC 6. "RHSC,Root Hub Status Change Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0xC 5. "FNO,Frame Number Overflow Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
bitfld.long 0xC 3. "RD,Resume Detected Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
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bitfld.long 0xC 2. "SF,Start of Frame Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
bitfld.long 0xC 1. "WDH,Write Back Done Head Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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bitfld.long 0xC 0. "SO,Scheduling Overrun Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
line.long 0x10 "HcInterruptDisable,Host Controller Interrupt Disable Register"
bitfld.long 0x10 31. "MIE,Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
bitfld.long 0x10 6. "RHSC,Root Hub Status Change Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0x10 5. "FNO,Frame Number Overflow Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
bitfld.long 0x10 3. "RD,Resume Detected Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
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bitfld.long 0x10 2. "SF,Start of Frame Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
bitfld.long 0x10 1. "WDH,Write Back Done Head Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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bitfld.long 0x10 0. "SO,Scheduling Overrun Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
line.long 0x14 "HcHCCA,Host Controller Communication Area Register"
hexmask.long.tbyte 0x14 8.--31. 1. "HCCA,Host Controller Communication Area\nPointer to indicate the base address of the Host Controller Communication Area (HCCA)."
rgroup.long 0x1C++0x3
line.long 0x0 "HcPeriodCurrentED,Host Controller Period Current ED Register"
hexmask.long 0x0 4.--31. 1. "PCED,Periodic Current ED\nPointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor."
group.long 0x20++0x17
line.long 0x0 "HcControlHeadED,Host Controller Control Head ED Register"
hexmask.long 0x0 4.--31. 1. "CHED,Control Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Control list."
line.long 0x4 "HcControlCurrentED,Host Controller Control Current ED Register"
hexmask.long 0x4 4.--31. 1. "CCED,Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list."
line.long 0x8 "HcBulkHeadED,Host Controller Bulk Head ED Register"
hexmask.long 0x8 4.--31. 1. "BHED,Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list."
line.long 0xC "HcBulkCurrentED,Host Controller Bulk Current ED Register"
hexmask.long 0xC 4.--31. 1. "BCED,Bulk Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Bulk list."
line.long 0x10 "HcDoneHead,Host Controller Done Head Register"
hexmask.long 0x10 4.--31. 1. "DH,Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue."
line.long 0x14 "HcFmInterval,Host Controller Frame Interval Register"
bitfld.long 0x14 31. "FIT,Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0])." "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into FI.."
hexmask.long.word 0x14 16.--29. 1. "FSMPS,FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame."
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hexmask.long.word 0x14 0.--13. 1. "FI,Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12 000 bit times in a frame  a value of 11 999 is stored here."
rgroup.long 0x38++0x7
line.long 0x0 "HcFmRemaining,Host Controller Frame Remaining Register"
bitfld.long 0x0 31. "FRT,Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0." "0,1"
hexmask.long.word 0x0 0.--13. 1. "FR,Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state  this 14-bit field decrements each 12 MHz clock period. When the count reaches 0  (end of frame) the counter reloads with Frame Interval. In addition  the counter loads when the.."
line.long 0x4 "HcFmNumber,Host Controller Frame Number Register"
hexmask.long.word 0x4 0.--15. 1. "FN,Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.'"
group.long 0x40++0x13
line.long 0x0 "HcPeriodicStart,Host Controller Periodic Start Register"
hexmask.long.word 0x0 0.--13. 1. "PS,Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin."
line.long 0x4 "HcLSThreshold,Host Controller Low-speed Threshold Register"
hexmask.long.word 0x4 0.--11. 1. "LST,Low-speed Threshold"
line.long 0x8 "HcRhDescriptorA,Host Controller Root Hub Descriptor A Register"
bitfld.long 0x8 12. "NOCP,No Overcurrent Protection\nThis bit describes how the overcurrent status for the Root Hub ports reported." "0: Overcurrent status is reported,1: Overcurrent status is not reported"
bitfld.long 0x8 11. "OCPM,Overcurrent Protection Mode\nThis bit describes how the overcurrent status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared." "0: Global overcurrent,1: Individual overcurrent"
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bitfld.long 0x8 8. "PSM,Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled." "0: Global switching,1: Individual switching"
hexmask.long.byte 0x8 0.--7. 1. "NDP,Number Downstream Ports\nUSB host control supports two downstream ports in this series of chip."
line.long 0xC "HcRhDescriptorB,Host Controller Root Hub Descriptor B Register"
hexmask.long.word 0xC 16.--31. 1. "PPCM,Port Power Control Mask\nGlobal power switching. This field is only valid if Power Switching Mode is set (individual port switching). When set  the port only responds to individual port power switching commands (Set/Clear Port Power). When cleared .."
line.long 0x10 "HcRhStatus,Host Controller Root Hub Status Register"
bitfld.long 0x10 31. "CRWE,Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always reads as 0.\nWrite Operation:" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
bitfld.long 0x10 17. "OCIC,Overcurrent Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to 0." "0: OCI (HcRhStatus[1]) didn't change,1: OCI (HcRhStatus[1]) changed"
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bitfld.long 0x10 16. "LPSC,Set Global Power" "0: No effect,1: Set global power"
bitfld.long 0x10 15. "DRWE,Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nRemote wake-up can only be triggered while port is in suspend state.\nWrite Operation:" "0: No effect.\nConnect Status Change as a remote..,1: Connect Status Change as a remote wake-up event.."
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bitfld.long 0x10 1. "OCI,overcurrent Indicator\nThis bit reflects the state of the overcurrent status pin. This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared." "0: No overcurrent condition,1: Overcurrent condition"
bitfld.long 0x10 0. "LPS,Clear Global Power" "0: No effect,1: Clear global power"
group.long 0x58++0x3
line.long 0x0 "HcRhPortStatus1,Host Controller Root Hub Port Status [1]"
bitfld.long 0x0 20. "PRSC,Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to 0." "0: Port reset is not complete,1: Port reset is complete"
bitfld.long 0x0 19. "OCIC,Port Overcurrent Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to 0." "0: POCI (HcRhPortStatus1[3]) didn't change,1: POCI (HcRhPortStatus1[3]) changed"
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bitfld.long 0x0 18. "PSSC,Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to 0." "0: Port resume is not complete,1: Port resume is complete"
bitfld.long 0x0 17. "PESC,Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to 0." "0: PES (HcRhPortStatus1[1]) didn't change,1: PES (HcRhPortStatus1[1]) changed"
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bitfld.long 0x0 16. "CSC,Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to 0." "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect event.."
bitfld.long 0x0 9. "LSDA,Low Speed Device Attached or Clear Port Power (Read/Write)\nThis bit defines the speed (and bus idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation:" "0: No effect.\nFull Speed device,1: Clear PPS (HcRhPortStatus1[8]).\nLow-speed device"
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bitfld.long 0x0 8. "PPS,Port Power Status or Set Port Power (Read/Write)\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:" "0: No effect.\nPort power is Disabled,1: Port Power Enabled.\nPort power is Enabled"
bitfld.long 0x0 4. "PRS,Port Reset Status or Set Port Reset (Read/Write)\nThis bit reflects the reset state of the port.\nWrite Operation:" "0: No effect.\nPort reset signal is not active,1: Set port reset.\nPort reset signal is active"
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bitfld.long 0x0 3. "POCI,Port Overcurrent Indicator or Clear Port Suspend (Read/Write)\nThis bit reflects the state of the overcurrent status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is.." "0: No effect.\nNo overcurrent condition,1: Clear port suspend.\nOvercurrent condition"
bitfld.long 0x0 2. "PSS,Port Suspend Status or Set Port Suspend (Read/Write)\nThis bit indicates the port is suspended\nWrite Operation:" "0: No effect.\nPort is not suspended,1: Set port suspend.\nPort is selectively suspended"
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bitfld.long 0x0 1. "PES,Port Enable Status or Set Port Enable (Read/Write)\nWrite Operation:" "0: No effect.\nPort Disabled,1: Set port enable.\nPort Enabled"
bitfld.long 0x0 0. "CCS,Current Connect Status or Clear Port Enable (Read/Write)\nWrite Operation:" "0: No effect.\nNo device connected,1: Clear port enable.\nDevice connected"
group.long 0x200++0x7
line.long 0x0 "HcPhyControl,Host Controller PHY Control Register"
bitfld.long 0x0 27. "STBYEN,USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption." "0: The USB transceiver would never enter the..,1: The USB transceiver will enter standby mode.."
line.long 0x4 "HcMiscControl,Host Controller Miscellaneous Control Register"
bitfld.long 0x4 16. "DPRT1,Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled  the USB host controller will not recognize any event of USB bus.\nSet this bit high  the.." "0: The connection between USB host controller and..,1: The connection between USB host controller and.."
bitfld.long 0x4 3. "OCAL,Overcurrent Active Low\nThis bit controls the polarity of overcurrent flag from external power IC." "0: Overcurrent flag is high active,1: Overcurrent flag is low active"
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bitfld.long 0x4 1. "ABORT,AHB Bus Error Response\nThis bit indicates there is an Error response received in AHB bus." "0: No Error response received,1: Error response received"
tree.end
tree.end
tree "USCI (Universal Serial Control Interface Controller)"
base ad:0x0
tree "UI2C (Inter-Integrated Circuit)"
base ad:0x400D0000
group.long 0x0++0x3
line.long 0x0 "UI2C_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols  the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
group.long 0x8++0x3
line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider"
hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
group.long 0x2C++0x3
line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
rgroup.long 0x34++0x3
line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol  RXDAT[12:8] indicate the different transmission conditions which defined in I2C."
group.long 0x44++0x23
line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol  this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB  the AA bits are compared to the bits DEVADDR [9:8] to check for address match  where the X is R/W bit. Then.."
line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1"
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol  this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB  the AA bits are compared to the bits DEVADDR [9:8] to check for address match  where the X is R/W bit. Then.."
line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set to zero .."
line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one  it means the received corresponding address bit is don't-care. If the bit is set to zero .."
line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according to START signal,1: The chip is woken up according to address match"
bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x14 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode  this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the.." "0: The monitor mode Disabled,1: The monitor mode Enabled"
bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.."
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bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register  if the related interrupt enable bits are set  the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags.." "0: I2C 's stretch disabled and the I2C protocol..,1: I2C 's stretch is active"
bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x18 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1"
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bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1"
bitfld.long 0x18 0. "GCFUNC,General Call Function\nNote: When ADDR10EN (UI2C_PROTCTL [4]) is set  don't set this bit." "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))." "0: The error interrupt Disabled,1: The error interrupt Enabled"
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bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master." "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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bitfld.long 0x1C 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
bitfld.long 0x1C 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol  this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register"
bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
bitfld.long 0x20 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x20 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal  and it will be cleared automatically by hardware." "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
bitfld.long 0x20 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal  and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag\nNote 1: This bit is cleared by software writing 1 into this bit.\nNote 2: This bit is set for slave mode  and user must write 1 into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: This bit is cleared by software writing 1 into.."
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bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: An arbitration has not been lost,1: An arbitration has been lost"
bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A stop condition has not yet been detected,1: A stop condition has been detected"
bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However  this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x20 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
group.long 0x8C++0x3
line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x0 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode."
hexmask.long.word 0x0 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.."
tree.end
tree "USPI (Serial Peripheral Interface)"
base ad:0x400D0000
group.long 0x0++0xB
line.long 0x0 "USPI_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols  the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode  the receive start event happens when SPI master sends slave select active and spi clock to the external.." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider"
bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
group.long 0x10++0x3
line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol  it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal  which is synchronized with PCLK  can be used as input for the data shift.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x3
line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal  which is synchronized with PCLK  can be used as input for the data shift.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x7
line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal  which is synchronized with PCLK  can be used as input for the data shift unit.\nNote: In SPI.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol  the control.." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins." "0: Data output values of USCIx_DAT0/1 pins are not..,1: Data output values of USCIx_DAT0/1 pins are.."
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data  user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
rgroup.long 0x34++0x3
line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
group.long 0x38++0x3
line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
bitfld.long 0x0 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under Run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
rgroup.long 0x3C++0x3
line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6])  the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled  the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x40++0x3
line.long 0x0 "USPI_PDMACTL,USCI PDMA Control Register"
bitfld.long 0x0 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
bitfld.long 0x0 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
bitfld.long 0x0 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
group.long 0x54++0x13
line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode  this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity for Slave\nThis bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring." "0: The output data value is 0 if TX under run event..,1: The output data value is 1 if TX under run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period for Slave Only\nIn Slave mode  this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC  USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval for Master Only\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of.."
bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status  data transmit  and data receive edge." "0,1,2,3"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable for Master Only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
bitfld.long 0x8 2. "SS,Slave Select Control for Master Only\nIf AUTOSS bit is cleared  setting this bit to 1 will set the slave select signal to active state  and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol  the internal.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection for Slave Only\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode  so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: The Slave mode bit count error interrupt Disabled,1: The Slave mode bit count error interrupt Enabled"
bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol  this bit enables the interrupt generation in case of a Slave time-out event." "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode  if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock  this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under run event does not occur,1: Slave transmit under run event occurs"
rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])  bit count error event occurs." "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit." "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode  the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode  the.." "0: Receive start event did not occur,1: Receive start event occurred"
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit." "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit." "0: Transmit start event did not occur,1: Transmit start event occurred"
tree.end
tree "UUART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x400D0000
group.long 0x0++0xB
line.long 0x0 "UUART_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols  the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function  it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
group.long 0x10++0x3
line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode  it is suggested to set this bit field as 0x2." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x3
line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x7
line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART.."
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol  the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
rgroup.long 0x34++0x3
line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK  FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
group.long 0x38++0x3
line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
rgroup.long 0x3C++0x3
line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled  the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x40++0x3
line.long 0x0 "UUART_PDMACTL,USCI PDMA Control Register"
bitfld.long 0x0 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
bitfld.long 0x0 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
bitfld.long 0x0 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
group.long 0x54++0x13
line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode  this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
bitfld.long 0x8 30. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1  any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1  the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information." "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is wake-up from Power-down mode."
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bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes  hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled  if the transmitted bytes in the TX buffer is empty  the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2:.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.."
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bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled  the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame." "0: The PARITY bit Disabled,1: The PARITY bit Enabled"
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bitfld.long 0x8 0. "STOPB,STOP bits\nThis bit defines the number of STOP bits in an UART frame." "0: The number of STOP bits is 1,1: The number of STOP bits is 2"
line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun  the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set  the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is  the total time of 'START bit' + data bits + parity + STOP bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is  the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK  FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
tree.end
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40040000
group.long 0x0++0x7
line.long 0x0 "WDT_CTL,WDT Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
rbitfld.long 0x0 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7])  this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 4 * WDT_CLK.." "0: Setting WDTEN bit is completed and WDT is ready,1: Setting WDTEN bit is synchronizing and not.."
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hexmask.long.byte 0x0 8.--11. 1. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register."
bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111  this bit is forced as 1 and user cannot change.." "0: WDT Disabled (This action will reset the..,1: This bit is write protected"
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bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled  the WDT time-out interrupt signal is generated and inform to CPU.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
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bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1  while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled  the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT time-out..,1: This bit is write protected"
bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened  user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
wgroup.long 0x8++0x3
line.long 0x0 "WDT_RSTCNT,WDT Reset Counter Register"
hexmask.long 0x0 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active."
tree.end
tree "WWDT (Window Watchdog Timer)"
base ad:0x40040100
wgroup.long 0x0++0x3
line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
group.long 0x4++0x7
line.long 0x0 "WWDT_CTL,WWDT Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when.."
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hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection"
bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled  the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: Enable WWDT counter starts counting"
line.long 0x4 "WWDT_STATUS,WWDT Status Register"
bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches CMPDAT"
rgroup.long 0xC++0x3
line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value."
tree.end
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