; --------------------------------------------------------------------------------
; @Title: M2S005 M2S010 M2S025 M2S050 M2S080 M2S120 On-Chip Peripherals
; @Props: Released
; @Author: EMK
; @Changelog: 2013-01-28 EMK
; @Manufacturer: MICROSEMI - Microsemi Corp.
; @Doc: SmartFusion2_CortexM3_UG.pdf
; @Core: Cortex-M3
; @Chip: M2S005, M2S010, M2S025, M2S050, M2S080, M2S120
; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perm2s.per 17736 2024-04-08 09:26:07Z kwisniewski $

width 0x0b
tree.close "Core Registers (Cortex-M3)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
group 0x10--0x1b
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "      CLKSOURCE       ,Clock Source" "External,Core"
bitfld.long 0x00 1. "                  TICKINT        ,SysTick Handler" "Not SysTick,SysTick"
textline "                    "
bitfld.long 0x00 0. " ENABLE       ,Counter Enable" "Disabled,Enabled"
;group 0x14++0x03
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,The value to load into the SYST_CVR when the counter reaches 0"
;group 0x18++0x03
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Current Value"
rgroup 0x1c++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW            ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "                   TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
textline "                    "
rgroup 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer Code"
bitfld.long 0x00 20.--23. "               VARIANT         ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                        CONSTANT       ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.word 0x00 4.--15. 1. " PARTNO       ,Number of Processor"
bitfld.long 0x00 0.--3. "             REVISION        ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group 0xd04--0xd17
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Set Pending NMI Bit" "Not set,Set"
bitfld.long 0x00 28. "          PENDSVSET       ,Set Pending pendSV Bit" "Not set,Set"
bitfld.long 0x00 27. "                   PENDSVCLR      ,Clear Pending pendSV Bit" "Not cleared,Cleared"
textline "                    "
bitfld.long 0x00 26. " PENDSTSET    ,Set Pending SysTick Bit" "Not set,Set"
bitfld.long 0x00 25. "          PENDSTCLR       ,Clear Pending SysTick Bit" "Not cleared,Cleared"
bitfld.long 0x00 23. "               ISRPREEMPT     ,Use Only at Debug Time" "Not active,Active"
textline "                    "
bitfld.long 0x00 22. " ISRPENDING   ,Interrupt Pending Flag" "Not pending,Pending"
hexmask.long.word 0x00 12.--21. 1. "      VECTPENDING     ,Pending ISR Number Field"
bitfld.long 0x00 11. "                      RETTOBASE      ,Interrupt Exception" "Active,Not active"
textline "                    "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE   ,Active ISR Number Field"
;group 0xd08++0x03
line.long 0x04 "VTOR,Vector Table Offset Register"
bitfld.long 0x04 29. " TBLBASE      ,Table Base" "Code,RAM"
hexmask.long.tbyte 0x04 7.--28. 1. "             TBLOFF          ,Vector Table Base Offset Field"
;group 0xd0c++0x03
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY      ,Register Key"
rbitfld.long 0x08 15. "             ENDIANESS       ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "                    PRIGROUP       ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                    "
bitfld.long 0x08 2. " SYSRESETREQ  ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "    VECTCLRACTIVE   ,Clear Active Vector Bit" "Not cleared,Cleared all"
bitfld.long 0x08 0. "               VECTRESET      ,System Reset" "No reset,Reset"
;group 0xd10++0x03
line.long 0x0c "SCR,System Control Register"
bitfld.long 0x0c 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0c 2. "       SLEEPDEEP       ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                    "
bitfld.long 0x0c 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
;group 0xd14++0x03
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 9. " STKALIGN     ,8-byte Stack Frame Alignment" "4-byte,8-byte"
bitfld.long 0x10 8. "           BFHFNMIGN       ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
textline "                    "
bitfld.long 0x10 4. " DIV_0_TRP    ,Trap Divide by Zero" "Disabled,Enabled"
bitfld.long 0x10 3. "         UNALIGN_TRP     ,Trap for Unaligned Access" "Disabled,Enabled"
textline "                    "
bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
bitfld.long 0x10 0. "         NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
group 0xd18--0xd23
line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " PRI_7        ,Priority of System Handler 7"
hexmask.long.byte 0x00 16.--23. 1. "               PRI_6           ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x00 8.--15. 1. "                        PRI_5          ,Priority of system handler 5(BusFault)"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " PRI_4        ,Priority of system handler 4(MemManage)"
line.long 0x04 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x04 24.--31. 1. " PRI_11       ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x04 16.--23. 1. "               PRI_10          ,Priority of System Handler 10"
hexmask.long.byte 0x04 8.--15. 1. "                        PRI_9          ,Priority of System Handler 9"
textline "                    "
hexmask.long.byte 0x04 0.--7. 1. " PRI_8        ,Priority of System Handler 8"
line.long 0x08 "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x08 24.--31. 1. " PRI_15       ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x08 16.--23. 1. "               PRI_14          ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x08 8.--15. 1. "                        PRI_13         ,Priority of System Handler 13"
textline "                    "
hexmask.long.byte 0x08 0.--7. 1. " PRI_12       ,Priority of System Handler 12(DebugMonitor)"
group 0xd24++0x3
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 18. " USGFAULTENA  ,USGFAULTENA" "Disabled,Enabled"
bitfld.long 0x00 17. "         BUSFAULTENA     ,BUSFAULTENA" "Disabled,Enabled"
bitfld.long 0x00 16. "                  MEMFAULTENA    ,MEMFAULTENA" "Disabled,Enabled"
textline "                    "
bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
bitfld.long 0x00 14. "     BUSFAULTPENDED  ,BusFault is Pended Started" "Not replaced,Replaced"
bitfld.long 0x00 13. "              MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
textline "                    "
bitfld.long 0x00 11. " SYSTICKACT   ,SysTick is Active" "Not active,Active"
bitfld.long 0x00 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
bitfld.long 0x00 8. "                MONITORACT     ,Monitor is Active" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " SVCALLACT    ,SVCall is Active" "Not active,Active"
bitfld.long 0x00 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
bitfld.long 0x00 1. "                BUSFAULTACT    ,BusFault is Active" "Not active,Active"
textline "                    "
bitfld.long 0x00 0. " MEMFAULTACT  ,MemManage is Active" "Not active,Active"
group 0xd28--0xd3b
line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
bitfld.byte 0x0 7. "       MMARVALID    ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x0 4. "        MSTKERR         ,Stacking Access Violations" "No error,Error"
bitfld.byte 0x0 3. "                  MUNSTKERR      ,Unstack Access Violations" "No error,Error"
textline "                    "
bitfld.byte 0x0 1. " DACCVIOL     ,Data Access Violation" "No error,Error"
bitfld.byte 0x0 0. "         IACCVIOL        ,Instruction Access Violation" "No error,Error"
;group 0xd29++0x00
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID    ,Address Valid" "Not valid,Valid"
bitfld.byte 0x01 4. "        STKERR          ,Stacking from Exception has Caused Bus Faults" "No error,Error"
bitfld.byte 0x01 3. "                  UNSTKERR       ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
textline "                    "
bitfld.byte 0x01 2. " IMPRECISERR  ,Imprecise Data Bus Error" "No error,Error"
bitfld.byte 0x01 1. "         PRECISERR       ,Precise Data Bus Error Return" "No error,Error"
bitfld.byte 0x01 0. "                  IBUSERR        ,Instruction Bus Error Flag" "No error,Error"
;group 0xd2a++0x01
line.word 0x02 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x02 9. "     DIVBYZERO    ,Illegal PC Load" "No error,Error"
bitfld.word 0x02 8. "         UNALIGNED       ,Illegal Unaligned Access" "No error,Error"
bitfld.word 0x02 3. "                  NOCP           ,Attempt to use a coprocessor instruction" "No error,Error"
textline "                    "
bitfld.word 0x02 2. " INVPC        ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
bitfld.word 0x02 1. "         INVSTATE        , Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x02 0. "                  UNDEFINSTR     ,Illegal Processor State" "No error,Error"
;group 0xd2c++0x03
line.long 0x04 "HFSR,Hard Fault Status Register"
bitfld.long 0x04 31. " DEBUGEVT     ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
bitfld.long 0x04 30. "         FORCED          ,Hard Fault Activated" "No error,Error"
bitfld.long 0x04 1. "                  VECTTBL        ,Bus Fault" "No error,Error"
;group 0xd30++0x03
line.long 0x08 "DFSR,Debug Fault Status Register"
bitfld.long 0x08 4. " EXTERNAL     ,External Debug Request Flag" "Not asserted,Asserted"
bitfld.long 0x08 3. "     VCATCH          ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x08 2. "              DWTTRAP        ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
textline "                    "
bitfld.long 0x08 1. " BKPT         ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x08 0. "     HALTED          ,Halt Request Flag" "Not requested,Requested"
;group 0xd34++0x03
line.long 0xc "MMFAR,Memory Manage Fault Address Register"
;group 0xd38++0x03
line.long 0x10 "BFAR,Bus Fault Address Register"
wgroup 0xf00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID        ,Indicates the interrupt to be triggered"
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
tree "CoreSight Identification Registers"
width 6.
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 1. "   C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 5. " C_SNAPSTALL       ,Halting debug to gain control of the core" "Disabled,Enabled"
bitfld.long 0x00 3. "     C_MASKINTS         ,Interrupts Mask" "Not masked,Masked"
textline "                "
bitfld.long 0x00 2. " C_STEP            ,Core Step" "No step,Step"
bitfld.long 0x00 1. "      C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 2. " C_STEP            ,Core Step" "No step,Step"
bitfld.long 0x00 1. "      C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
endif
wgroup 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "        REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
group 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "     MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "         MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
textline "                "
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "  MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "  VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "     VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "  VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "     VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "  VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "     MON_REQ    ,DebugMonitor semaphore bit" "0,1"
textline "                "
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "  MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "  VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "     VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "  VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "     VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "  VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group 0x00--0x27
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "  NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "  KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. "  ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
;group 0x04++0x03
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP   ,Remap Base Address Field"
;group 0x08++0x03
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x8 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x8 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0xC 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0xC 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x10 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x10 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x14 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x14 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x18 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x18 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x1C 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x1C 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x20 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x20 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x24 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x24 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
tree "Coresight Management Registers"
rgroup 0xfd0--0xfff
line.long 0x00 "PID4,Peripheral ID4"
line.long 0x04 "PID5,Peripheral ID5"
line.long 0x08 "PID6,Peripheral ID6"
line.long 0x0c "PID7,Peripheral ID7"
line.long 0x10 "PID0,Peripheral ID0"
line.long 0x14 "PID1,Peripheral ID1"
line.long 0x18 "PID2,Peripheral ID2"
line.long 0x1c "PID3,Peripheral ID3"
line.long 0x20 "CID0,Component ID0"
line.long 0x24 "CID1,Component ID1"
line.long 0x28 "CID2,Component ID2"
line.long 0x2c "CID3,Component ID3"
tree.end
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group 0x00--0x1B
line.long 0x00 "DWT_CTRL,DWT Control Register"
bitfld.long 0x00 28.--31. " NUMCOMP    ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22. "        CYCEVTENA   ,Enables Cycle Count Event" "Disabled,Enabled"
bitfld.long 0x00 21. "  FOLDEVTENA  ,Enables Folded Instruction Count Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 20. " LSUEVTENA  ,Enables LSU Count Event" "Disabled,Enabled"
bitfld.long 0x00 19. "  SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
bitfld.long 0x00 18. "  EXCEVTENA   ,Enables Interrupt Overhead Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 17. " CPIEVTENA  ,Enables CPI Count Event" "Disabled,Enabled"
bitfld.long 0x00 16. "  EXCTRCENA   ,Enables Interrupt Event Tracing" "Disabled,Enabled"
bitfld.long 0x00 12. "  PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 10.--11. " SYNCTAP    ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
bitfld.long 0x00 9. "  CYCTAP      ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
bitfld.long 0x00 5.--8. "    POSTCNT     ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        CYCCNTENA   ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
;group 0x04++0x03
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
;group 0x08++0x03
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT     ,The base CPI counter"
;group 0x0c++0x03
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT     ,The exception overhead counter"
;group 0x10++0x03
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT   ,Sleep Counter"
;group 0x14++0x03
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT     ,Load-store counter"
;group 0x18++0x03
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT    ,Folded-instruction counter"
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
group.long 0x24++0x03
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x03
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x03
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
group.long 0x38++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x38++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
group.long 0x48++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x48++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
group.long 0x58++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x58++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
tree "Coresight Management Registers"
rgroup 0xfd0--0xfff
line.long 0x00 "PID4,Peripheral ID4"
line.long 0x04 "PID5,Peripheral ID5"
line.long 0x08 "PID6,Peripheral ID6"
line.long 0x0c "PID7,Peripheral ID7"
line.long 0x10 "PID0,Peripheral ID1"
line.long 0x14 "PID1,Peripheral ID2"
line.long 0x18 "PID2,Peripheral ID3"
line.long 0x1c "PID3,Peripheral ID4"
line.long 0x20 "CID0,Component ID0"
line.long 0x24 "CID1,Component ID1"
line.long 0x28 "CID2,Component ID2"
line.long 0x2c "CID3,Component ID3"
tree.end
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
config 16. 8.
tree "HPDMA (High Performance DMA Controller)"
base ad:0x40014000
width 16.
rgroup.long 0x00++0x3
line.long 0x00 "HPDMAEDR_REG,HPDMA Empty Descriptor register"
bitfld.long 0x00 15. " HPDMAEDR_DCP_NON_WORD_ERR[3] ,Descriptor 3 non-word aligned transfer size error" "No error,Error"
bitfld.long 0x00 14. "       HPDMAEDR_DCP_NON_WORD_ERR[2] ,Descriptor 2 non word aligned transfer size error" "No error,Error"
bitfld.long 0x00 13. "       HPDMAEDR_DCP_NON_WORD_ERR[1] ,Descriptor 1 non-word aligned transfer size error" "No error,Error"
textline "                         "
bitfld.long 0x00 12. " HPDMAEDR_DCP_NON_WORD_ERR[0] ,Descriptor 0 non-word aligned transfer size error" "No error,Error"
bitfld.long 0x00 11. "       HPDMAEDR_DCP_ERR[3]          ,Descriptor 3 transfer error" "No error,Error"
bitfld.long 0x00 10. "       HPDMAEDR_DCP_ERR[2]          ,Descriptor 2 transfer error" "No error,Error"
textline "                         "
bitfld.long 0x00 9. " HPDMAEDR_DCP_ERR[1]          ,Descriptor 1 transfer error" "No error,Error"
bitfld.long 0x00 8. "       HPDMAEDR_DCP_ERR[0]          ,Descriptor 0 transfer error" "No error,Error"
bitfld.long 0x00 7. "       HPDMAEDR_DCP_CMPLET[3]       ,Descriptor 3 transfer complete" "Not completed,Completed"
textline "                         "
bitfld.long 0x00 6. " HPDMAEDR_DCP_CMPLET[2]       ,Descriptor 2 transfer complete" "Not completed,Completed"
bitfld.long 0x00 5. "  HPDMAEDR_DCP_CMPLET[1]       ,Descriptor 1 transfer complete" "Not completed,Completed"
bitfld.long 0x00 4. "  HPDMAEDR_DCP_CMPLET[0]       ,Descriptor 0 transfer complete" "Not completed,Completed"
textline "                         "
bitfld.long 0x00 3. " HPDMAEDR_DCP_EMPTY[3]        ,Descriptor 3 is empty and ready for software configuration" "Not ready,Ready"
bitfld.long 0x00 2. "      HPDMAEDR_DCP_EMPTY[2]        ,Descriptor 2 is empty and ready for software configuration" "Not ready,Ready"
bitfld.long 0x00 1. "      HPDMAEDR_DCP_EMPTY[1]        ,Descriptor 1 is empty and ready for software configuration" "Not ready,Ready"
textline "                         "
bitfld.long 0x00 0. " HPDMAEDR_DCP_EMPTY[0]        ,Descriptor 0 is empty and ready for software configuration" "Not ready,Ready"
group.long (0x0+0x04)++0xb
line.long 0x00 "HPDMAD0SAR_REG,Descriptor 0 source memory start address"
line.long 0x04 "HPDMAD0DAR_REG,Descriptor 0 destination memory start address"
line.long 0x08 "HPDMAD0CR_REG,Descriptor 0 Control register"
bitfld.long 0x08 22. " HPDMACR_NON_WORD_INT[0]     ,Non-word interrupt enable" "Disbaled,Enabled"
bitfld.long 0x08 21. "       HPDMACR_XFR_ERR_INT[0]      ,HPDMA asserts transfer error interrupt on error during descriptor 0 transfers" "Not asserted,Asserted"
bitfld.long 0x08 20. "   HPDMACR_XFR_CMP_INT[0]      ,HPDMA asserts interrupt on completion of descriptor 0 transfers without error" "Not asserted,Asserted"
textline "                         "
bitfld.long 0x08 19. " HPDMACR_DCP_PAUSE[0]        ,HPDMA pauses descriptor 0 transfers, does idle transfe" "Resumed,Paused"
bitfld.long 0x08 18. "        HPDMACR_DCP_CLR[0]          ,When this bit is set, HPDMA clears the descriptor 0 fields" "No effect,Cleared"
bitfld.long 0x08 17. "      HPDMACR_XFR_DIR[0]          ,Descriptor 0 data transfer direction" "AHB to MSS DDR,MSS DDR to AHB"
textline "                         "
bitfld.long 0x08 16. " HPDMACR_DCP_VALID[0]        ,Indicates the descriptor 0 is valid and ready to transfer" "Invalid,Valid"
hexmask.long.word 0x08 0.--15. 1. "        HPDMACR_DCP0_XFR_SIZE       ,Descriptor 0 transfer size in bytes"
rgroup.long (0x0+0x10)++0x7
line.long 0x00 "HPDMAD0SR_REG,Descriptor 0 Status register"
bitfld.long 0x00 3. " HPDMASR_DCP_DERR[0]         ,Descriptor 0 destination transfer error" "No error,Error"
bitfld.long 0x00 2. "       HPDMASR_DCP_SERR[0]         ,Descriptor 0 source transfer error" "Not occurred,Occurred"
bitfld.long 0x00 1. "   HPDMASR_DCP_CMPLET[0]       ,Descriptor 0 transfer complete" "Not completed,Completed"
textline "                         "
bitfld.long 0x00 0. " HPDMASR_DCP_ACTIVE[0]       ,Descriptor 0 transfer in progress" "In queue,In progress"
line.long 0x04 "HPDMAD0PTR_REG,Descriptor 0 Pending Transfer register"
hexmask.long.word 0x04 16.--31. 1. " HPDMAPTR_D0_DST_PNDNG       ,Descriptor 0 destination pending transfers in words"
hexmask.long.word 0x04 0.--15. 1. "           HPDMAPTR_D0_SRC_PNDNG       ,Descriptor 0 source pending transfers in words"
group.long (0x14+0x04)++0xb
line.long 0x00 "HPDMAD1SAR_REG,Descriptor 1 source memory start address"
line.long 0x04 "HPDMAD1DAR_REG,Descriptor 1 destination memory start address"
line.long 0x08 "HPDMAD1CR_REG,Descriptor 1 Control register"
bitfld.long 0x08 22. " HPDMACR_NON_WORD_INT[1]     ,Non-word interrupt enable" "Disbaled,Enabled"
bitfld.long 0x08 21. "       HPDMACR_XFR_ERR_INT[1]      ,HPDMA asserts transfer error interrupt on error during descriptor 1 transfers" "Not asserted,Asserted"
bitfld.long 0x08 20. "   HPDMACR_XFR_CMP_INT[1]      ,HPDMA asserts interrupt on completion of descriptor 1 transfers without error" "Not asserted,Asserted"
textline "                         "
bitfld.long 0x08 19. " HPDMACR_DCP_PAUSE[1]        ,HPDMA pauses descriptor 1 transfers, does idle transfe" "Resumed,Paused"
bitfld.long 0x08 18. "        HPDMACR_DCP_CLR[1]          ,When this bit is set, HPDMA clears the descriptor 1 fields" "No effect,Cleared"
bitfld.long 0x08 17. "      HPDMACR_XFR_DIR[1]          ,Descriptor 1 data transfer direction" "AHB to MSS DDR,MSS DDR to AHB"
textline "                         "
bitfld.long 0x08 16. " HPDMACR_DCP_VALID[1]        ,Indicates the descriptor 1 is valid and ready to transfer" "Invalid,Valid"
hexmask.long.word 0x08 0.--15. 1. "        HPDMACR_DCP1_XFR_SIZE       ,Descriptor 1 transfer size in bytes"
rgroup.long (0x14+0x10)++0x7
line.long 0x00 "HPDMAD1SR_REG,Descriptor 1 Status register"
bitfld.long 0x00 3. " HPDMASR_DCP_DERR[1]         ,Descriptor 1 destination transfer error" "No error,Error"
bitfld.long 0x00 2. "       HPDMASR_DCP_SERR[1]         ,Descriptor 1 source transfer error" "Not occurred,Occurred"
bitfld.long 0x00 1. "   HPDMASR_DCP_CMPLET[1]       ,Descriptor 1 transfer complete" "Not completed,Completed"
textline "                         "
bitfld.long 0x00 0. " HPDMASR_DCP_ACTIVE[1]       ,Descriptor 1 transfer in progress" "In queue,In progress"
line.long 0x04 "HPDMAD1PTR_REG,Descriptor 1 Pending Transfer register"
hexmask.long.word 0x04 16.--31. 1. " HPDMAPTR_D1_DST_PNDNG       ,Descriptor 1 destination pending transfers in words"
hexmask.long.word 0x04 0.--15. 1. "           HPDMAPTR_D1_SRC_PNDNG       ,Descriptor 1 source pending transfers in words"
group.long (0x28+0x04)++0xb
line.long 0x00 "HPDMAD2SAR_REG,Descriptor 2 source memory start address"
line.long 0x04 "HPDMAD2DAR_REG,Descriptor 2 destination memory start address"
line.long 0x08 "HPDMAD2CR_REG,Descriptor 2 Control register"
bitfld.long 0x08 22. " HPDMACR_NON_WORD_INT[2]     ,Non-word interrupt enable" "Disbaled,Enabled"
bitfld.long 0x08 21. "       HPDMACR_XFR_ERR_INT[2]      ,HPDMA asserts transfer error interrupt on error during descriptor 2 transfers" "Not asserted,Asserted"
bitfld.long 0x08 20. "   HPDMACR_XFR_CMP_INT[2]      ,HPDMA asserts interrupt on completion of descriptor 2 transfers without error" "Not asserted,Asserted"
textline "                         "
bitfld.long 0x08 19. " HPDMACR_DCP_PAUSE[2]        ,HPDMA pauses descriptor 2 transfers, does idle transfe" "Resumed,Paused"
bitfld.long 0x08 18. "        HPDMACR_DCP_CLR[2]          ,When this bit is set, HPDMA clears the descriptor 2 fields" "No effect,Cleared"
bitfld.long 0x08 17. "      HPDMACR_XFR_DIR[2]          ,Descriptor 2 data transfer direction" "AHB to MSS DDR,MSS DDR to AHB"
textline "                         "
bitfld.long 0x08 16. " HPDMACR_DCP_VALID[2]        ,Indicates the descriptor 2 is valid and ready to transfer" "Invalid,Valid"
hexmask.long.word 0x08 0.--15. 1. "        HPDMACR_DCP2_XFR_SIZE       ,Descriptor 2 transfer size in bytes"
rgroup.long (0x28+0x10)++0x7
line.long 0x00 "HPDMAD2SR_REG,Descriptor 2 Status register"
bitfld.long 0x00 3. " HPDMASR_DCP_DERR[2]         ,Descriptor 2 destination transfer error" "No error,Error"
bitfld.long 0x00 2. "       HPDMASR_DCP_SERR[2]         ,Descriptor 2 source transfer error" "Not occurred,Occurred"
bitfld.long 0x00 1. "   HPDMASR_DCP_CMPLET[2]       ,Descriptor 2 transfer complete" "Not completed,Completed"
textline "                         "
bitfld.long 0x00 0. " HPDMASR_DCP_ACTIVE[2]       ,Descriptor 2 transfer in progress" "In queue,In progress"
line.long 0x04 "HPDMAD2PTR_REG,Descriptor 2 Pending Transfer register"
hexmask.long.word 0x04 16.--31. 1. " HPDMAPTR_D2_DST_PNDNG       ,Descriptor 2 destination pending transfers in words"
hexmask.long.word 0x04 0.--15. 1. "           HPDMAPTR_D2_SRC_PNDNG       ,Descriptor 2 source pending transfers in words"
group.long (0x3C+0x04)++0xb
line.long 0x00 "HPDMAD3SAR_REG,Descriptor 3 source memory start address"
line.long 0x04 "HPDMAD3DAR_REG,Descriptor 3 destination memory start address"
line.long 0x08 "HPDMAD3CR_REG,Descriptor 3 Control register"
bitfld.long 0x08 22. " HPDMACR_NON_WORD_INT[3]     ,Non-word interrupt enable" "Disbaled,Enabled"
bitfld.long 0x08 21. "       HPDMACR_XFR_ERR_INT[3]      ,HPDMA asserts transfer error interrupt on error during descriptor 3 transfers" "Not asserted,Asserted"
bitfld.long 0x08 20. "   HPDMACR_XFR_CMP_INT[3]      ,HPDMA asserts interrupt on completion of descriptor 3 transfers without error" "Not asserted,Asserted"
textline "                         "
bitfld.long 0x08 19. " HPDMACR_DCP_PAUSE[3]        ,HPDMA pauses descriptor 3 transfers, does idle transfe" "Resumed,Paused"
bitfld.long 0x08 18. "        HPDMACR_DCP_CLR[3]          ,When this bit is set, HPDMA clears the descriptor 3 fields" "No effect,Cleared"
bitfld.long 0x08 17. "      HPDMACR_XFR_DIR[3]          ,Descriptor 3 data transfer direction" "AHB to MSS DDR,MSS DDR to AHB"
textline "                         "
bitfld.long 0x08 16. " HPDMACR_DCP_VALID[3]        ,Indicates the descriptor 3 is valid and ready to transfer" "Invalid,Valid"
hexmask.long.word 0x08 0.--15. 1. "        HPDMACR_DCP3_XFR_SIZE       ,Descriptor 3 transfer size in bytes"
rgroup.long (0x3C+0x10)++0x7
line.long 0x00 "HPDMAD3SR_REG,Descriptor 3 Status register"
bitfld.long 0x00 3. " HPDMASR_DCP_DERR[3]         ,Descriptor 3 destination transfer error" "No error,Error"
bitfld.long 0x00 2. "       HPDMASR_DCP_SERR[3]         ,Descriptor 3 source transfer error" "Not occurred,Occurred"
bitfld.long 0x00 1. "   HPDMASR_DCP_CMPLET[3]       ,Descriptor 3 transfer complete" "Not completed,Completed"
textline "                         "
bitfld.long 0x00 0. " HPDMASR_DCP_ACTIVE[3]       ,Descriptor 3 transfer in progress" "In queue,In progress"
line.long 0x04 "HPDMAD3PTR_REG,Descriptor 3 Pending Transfer register"
hexmask.long.word 0x04 16.--31. 1. " HPDMAPTR_D3_DST_PNDNG       ,Descriptor 3 destination pending transfers in words"
hexmask.long.word 0x04 0.--15. 1. "           HPDMAPTR_D3_SRC_PNDNG       ,Descriptor 3 source pending transfers in words"
wgroup.long 0x54++0x3
line.long 0x00 "HPDMAICR_REG,HPDMA Interrupt Clear register"
bitfld.long 0x00 7. " HPDMAICR_NON_WORD_INT[3]     , HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR3] Clear" "No effect,Clear"
bitfld.long 0x00 6. "      HPDMAICR_NON_WORD_INT[2]     , HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR2] Clear" "No effect,Clear"
bitfld.long 0x00 5. "      HPDMAICR_NON_WORD_INT[1]     , HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR1] Clear" "No effect,Clear"
textline "                         "
bitfld.long 0x00 4. " HPDMAICR_NON_WORD_INT[0]      , HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR0] Clear" "No effect,Clear"
bitfld.long 0x00 3. "     HPDMAICR_CLR_XFR_INT[3]       , HPDMAD3SR_REG & HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR3] Clear" "No effect,Clear"
bitfld.long 0x00 2. "     HPDMAICR_CLR_XFR_INT[2]     ,HPDMAD3SR_REG & HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR2] Clear" "No effect,Clear"
textline "                         "
bitfld.long 0x00 1. " HPDMAICR_CLR_XFR_INT[1]      ,HPDMAD3SR_REG & HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR1] Clear" "No effect,Clear"
bitfld.long 0x00 0. "      HPDMAICR_CLR_XFR_INT[0]      , HPDMAD3SR_REG & HPDMAEDR_REG[HPDMAEDR_DCP_NON_WORD_ERR0] Clear" "No effect,Clear"
rgroup.long 0x58++0x3
line.long 0x00 "HPDMADR_REG,HPDMA Debug Register"
bitfld.long 0x00 26.--27. " HPDMADR_DMA_CST_DBG[1:0]     ,DMA controller FSM current state" "0,1,2,3"
bitfld.long 0x00 22.--25. "              HPDMADR_RRBN_CST_DBG[3:0]    ,Round robin FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--21. "             HPDMADR_RBC_CST_DBG[2:0]     ,Read buffer controller current state" "0,1,2,3,4,5,6,7"
textline "                         "
bitfld.long 0x00 16.--18. " HPDMADR_WBC_CST_DBG[2:0]     ,Write buffer controller current state" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--15. "              HPDMADR_AHM2_CST_DBG[3:0]    ,Master 2 (MSS DDR bridge) current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "             HPDMADR_AHM1_CST_DBG[3:0]    ,Master 1 (AHB bus matrix) current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 5.--7. " HPDMADR_BFR_WR_PNTR[2:0]     ,HPDMA data buffer write pointer" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2.--4. "              HPDMADR_BFR_RD_PNTR[2:0]     ,HPDMA data buffer read pointer" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "              HPDMADR_BFR_FULL             ,Data buffer is full" "Not full,Full"
textline "                         "
bitfld.long 0x00 0. " HPDMADR_BFR_EMPTY            ,Data buffer is empty" "Not empty,Empty"
width 0xb
tree.end
tree "PDMA (Peripheral DMA)"
base ad:0x40003000
width 18.
group.long 0x00++0x3
line.long 0x00 "RATIO_HIGH_LOW,Ratio of high priority transfers versus low priority transfers"
hexmask.long.byte 0x00 0.--7. 1. " RATIOHILO ,This field indicates the ratio of high priority to low priority for DMA access opportunities"
rgroup.long 0x04++0x3
line.long 0x00 "BUFFER_STATUS,Indicates when buffers have drained"
bitfld.long 0x00 15. " CH7BUFB   ,If CH_COMP_B for channel 7 is set and if BUF_B_SEL for channel 7 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 14. "  CH7BUA  , If CH_COMP_A for channel 7 is set and if BUF_A_SEL for channel 7 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 13. "  CH6BUFB , If CH_COMP_B for channel 6 is set and if BUF_B_SEL for channel 6 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 12. "  CH6BUFA , If CH_COMP_A for channel 6 is set and if BUF_A_SEL for channel 6 is clear,this bit is asserted" "Not asserted,Asserted"
textline "                           "
bitfld.long 0x00 11. " CH5BUFB   , If CH_COMP_B for channel 5 is set and if BUF_B_SEL for channel 5 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 10. "  CH5BUFA , If CH_COMP_A for channel 5 is set and if BUF_A_SEL for channel 5 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 9. "  CH4BUFB , If CH_COMP_B for channel 4 is set and if BUF_B_SEL for channel 4 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 8. "  CH4BUFA ,If CH_COMP_A for channel 4 is set and if BUF_A_SEL for channel 4 is clear, this bit is asserted" "Not asserted,Asserted"
textline "                           "
bitfld.long 0x00 7. " CH3BUFB   , If CH_COMP_B for channel 3 is set and if BUF_B_SEL for channel 3 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 6. "  CH3BUFA , If CH_COMP_A for channel 3 is set and if BUF_A_SEL for channel 3 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 5. "  CH2BUFB , If CH_COMP_B for channel 2 is set and if BUF_B_SEL for channel 2 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 4. "  CH2BUFA ,If CH_COMP_A for channel 2 is set and if BUF_A_SEL for channel 2 is clear, this bit is asserted" "Not asserted,Asserted"
textline "                           "
bitfld.long 0x00 3. " CH1BUFB   , If CH_COMP_B for channel 1 is set and if BUF_B_SEL for channel 1 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 2. "  CH1BUFA ,If CH_COMP_A for channel 1 is set and if BUF_A_SEL for channel 1 is clear, this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 1. "  CH0BUFB , If CH_COMP_B for channel 0 is set and if BUF_B_SEL for channel 0 is clear,this bit is asserted" "Not asserted,Asserted"
bitfld.long 0x00 0. "  CH0BUFA , If CH_COMP_A for channel 0 is set and if BUF_A_SEL for channel 0 is clear,this bit is asserted" "Not asserted,Asserted"
tree "Channel 0"
group.long 0x20++0x3
line.long 0x00 "PDMA_CSR0,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0x20+0x4)++0x3
line.long 0x00 "CHANNEL_0_STATUS,Channel 0 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0x20+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR0,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR0,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR0,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0x20+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR0,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR0,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR0,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 1"
group.long 0x40++0x3
line.long 0x00 "PDMA_CSR1,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0x40+0x4)++0x3
line.long 0x00 "CHANNEL_1_STATUS,Channel 1 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0x40+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR1,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR1,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR1,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0x40+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR1,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR1,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR1,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 2"
group.long 0x60++0x3
line.long 0x00 "PDMA_CSR2,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0x60+0x4)++0x3
line.long 0x00 "CHANNEL_2_STATUS,Channel 2 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0x60+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR2,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR2,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR2,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0x60+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR2,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR2,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR2,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 3"
group.long 0x80++0x3
line.long 0x00 "PDMA_CSR3,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0x80+0x4)++0x3
line.long 0x00 "CHANNEL_3_STATUS,Channel 3 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0x80+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR3,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR3,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR3,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0x80+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR3,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR3,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR3,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 4"
group.long 0xA0++0x3
line.long 0x00 "PDMA_CSR4,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0xA0+0x4)++0x3
line.long 0x00 "CHANNEL_4_STATUS,Channel 4 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0xA0+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR4,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR4,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR4,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0xA0+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR4,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR4,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR4,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 5"
group.long 0xC0++0x3
line.long 0x00 "PDMA_CSR5,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0xC0+0x4)++0x3
line.long 0x00 "CHANNEL_5_STATUS,Channel 5 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0xC0+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR5,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR5,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR5,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0xC0+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR5,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR5,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR5,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 6"
group.long 0xE0++0x3
line.long 0x00 "PDMA_CSR6,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0xE0+0x4)++0x3
line.long 0x00 "CHANNEL_6_STATUS,Channel 6 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0xE0+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR6,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR6,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR6,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0xE0+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR6,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR6,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR6,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
tree "Channel 7"
group.long 0x100++0x3
line.long 0x00 "PDMA_CSR7,PDMA Control Register"
bitfld.long 0x00 23.--26. " PERIPHERAL_SEL ,Selects the peripheral assigned to this channel" "UART_0 receive to MSS,MSS to UART_0 transmit,UART_1 receive to MSS,MSS to UART_1 transmit,SPI_0 receive to MSS,MSS to SPI_0 transmit,SPI_1 receive to MSS,MSS to SPI_1 transmit,To/from FPGA fabric DMAREADY1,To/from FPGA fabric DMAREADY0,From MSS to the ACE,From the ACE to MSS,To/from FPGA fabric (DMAREADY_1[1]),To/from FPGA fabric (DMAREADY_1[0]),COMM_BLK receive to MSS,MSS to COMM_BLK transmit"
textline "                           "
hexmask.long.byte 0x00 14.--21. 1. " WRITE_ADJ      ,indicating the number of FCLK periods"
bitfld.long 0x00 12.--13. "        DSTADDRINC ,This field controls the destination address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
bitfld.long 0x00 10.--11. "        SRCADDRINC    ,This field controls the source address increment for the DMA transfer" "0 byte,1 byte,2 bytes,4 bytes"
textline "                           "
bitfld.long 0x00 9. " HI_PRIORITY    ,High priority enable" "Disable,Enable"
bitfld.long 0x00 8. "   CLR_COMP_B ,Clears the CH_COMP_B" "Not cleared,Cleared"
bitfld.long 0x00 7. "    CLR_COMP_A    ,Clears the CH_COMP_A" "Not cleared,Cleared"
bitfld.long 0x00 6. "    INTEN ,Interrupt enable" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 5. " RESET          ,Resets this channel" "No reset,Reset"
bitfld.long 0x00 4. "  PAUSE      ,Pauses the transfer for this channel" "No pause,Pause"
bitfld.long 0x00 2.--3. "       TRANSFER_SIZE ,This field determines the data width" "Byte,Half Word,Word,?..."
bitfld.long 0x00 1. "      DIR   ,Direct data transfer" "Peripheral to memory,Memory to peripheral"
textline "                           "
bitfld.long 0x00 0. " PERIPHERAL_DMA ,Memory to memory mode enable" "Disabled,Enabled"
rgroup.long (0x100+0x4)++0x3
line.long 0x00 "CHANNEL_7_STATUS,Channel 7 status register"
bitfld.long 0x00 2. " BUF_SEL        ,Buffer A/B select" "Buffer A,Buffer B"
bitfld.long 0x00 1. "  CH_COMP_B  ,Asserts when this channel completes its DMA" "Not completed,Completed"
bitfld.long 0x00 0. "  CH_COMP_A     ,Asserts when this channel completes its DMA" "Not completed,Completed"
group.long (0x100+0x8)++0xb
line.long 0x0 "BUFFER_A_SAR7,Buffer A Source Address Register"
line.long 0x04 "BUFFER_A_DAR7,Buffer A Destination Address Register"
line.long 0x08 "BUFFER_A_BCR7,Buffer A Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_A_BCR   ,Buffer A Transfer Byte Count Register"
group.long (0x100+0x14)++0xb
line.long 0x0 "BUFFER_B_SAR7,Buffer B Source Address Register"
line.long 0x04 "BUFFER_B_DAR7,Buffer B Destination Address Register"
line.long 0x08 "BUFFER_B_BCR7,Buffer B Transfer Byte Count Register"
hexmask.long.word 0x08 0.--15. 1. " BUFFER_B_BCR   ,Buffer B Transfer Byte Count Register"
tree.end
width 0xB
tree.end
tree "USB (Universal Serial Bus)"
base ad:0x40043000
width 15.
if ((d.l(ad:0x40043000+0x60)&0x4)==0x4)
hgroup.byte 0x00++0x00
hide.byte 0x00 "FADDR_REG,Function Address"
else
group.byte 0x00++0x00
line.byte 0x00 "FADDR_REG,Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNC_ADDR     ,Function Address"
endif
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)
rgroup.byte 0x01++0x00
line.byte 0x00 "POWER_REG,Power Register"
bitfld.byte 0x00 7. " ISO_UPDATE    ,ISO update" "Not updated,Updated"
bitfld.byte 0x00 6. "       SOFT_CONN   ,Soft Connect/Disconnect" "Disabled,Enabled"
bitfld.byte 0x00 5. "          HS_ENAB      ,High speed mode enabled" "Disabled,Enabled"
bitfld.byte 0x00 4. "      HS_MODE      ,High-speed mode successfully negotiated during USB reset" "Not successfully,Successfully"
textline "                    "
bitfld.byte 0x00 3. " RESET         ,This bit is set when reset signaling is present on the bus" "Not reset,Reset"
bitfld.byte 0x00 2. "         RESUME      ,Resume Signaling" "Not generated,Generated"
bitfld.byte 0x00 1. "     SUSPEND_MODE ,Suspend Mode" "Disabled,Enabled"
bitfld.byte 0x00 0. "      ENABLE_SM    ,SUSPENDM output enabled" "Disabled,Enabled"
else
rgroup.byte 0x01++0x00
line.byte 0x00 "POWER_REG,Power Register"
bitfld.byte 0x00 5. " HS_ENAB       ,High speed mode enabled" "Disabled,Enabled"
bitfld.byte 0x00 4. "          HS_MODE     ,High-speed mode successfully negotiated during USB reset" "Not successfully,Successfully"
bitfld.byte 0x00 3. "  RESET        ,This bit is set when reset signaling is present on the bus" "Not reset,Reset"
bitfld.byte 0x00 2. "     RESUME       ,Resume Signaling" "Not generated,Generated"
textline "                    "
bitfld.byte 0x00 1. " SUSPEND_MODE  ,Suspend Mode" "Disabled,Enabled"
bitfld.byte 0x00 0. "          ENABLE_SM   ,SUSPENDM output enabled" "Disabled,Enabled"
endif
rgroup.word 0x02++0x3
line.word 0x00 "TX_IRQ_REG,Transmit Interrupt Status"
bitfld.word 0x00 4. " EP4_Tx        ,Transmit endpoint 4 interrupt" "Not occurred,Occurred"
bitfld.word 0x00 3. "      EP3_Tx      ,Transmit endpoint 3 interrupt" "Not occurred,Occurred"
bitfld.word 0x00 2. "      EP2_Tx       ,Transmit endpoint 2 interrupt" "Not occurred,Occurred"
bitfld.word 0x00 1. "  EP1_Tx       ,Transmit endpoint 1 interrupt" "Not occurred,Occurred"
textline "                    "
bitfld.word 0x00 0. " EP0           ,Endpoint 0 interrupt" "Not occurred,Occurred"
line.word 0x02 "RX_IRQ_REG,Receive Interrupt Status"
bitfld.word 0x02 4. " EP4_Rx        ,Receive endpoint 4 interrupt" "Not occurred,Occurred"
bitfld.word 0x02 3. "      EP3_Rx      ,Receive endpoint 3 interrupt" "Not occurred,Occurred"
bitfld.word 0x02 2. "      EP2_Rx       ,Receive endpoint 2 interrupt" "Not occurred,Occurred"
bitfld.word 0x02 1. "  EP1_Rx       ,Receive endpoint 1 interrupt" "Not occurred,Occurred"
textline "                    "
bitfld.word 0x02 0. " EP0           ,Endpoint 0 interrupt" "Not occurred,Occurred"
group.word 0x06++0x3
line.word 0x00 "TX_IRQ_EN_REG,Transmit Interrupt Enable"
bitfld.word 0x00 4. " EP4_TXEN      ,Transmit endpoint 4 interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 3. "          EP3_TXEN    ,Transmit endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 2. "          EP2_TXEN     ,Transmit endpoint 2 interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 1. "      EP1_TXEN     ,Transmit endpoint 1 interrupt enable" "Disabled,Enabled"
textline "                    "
bitfld.word 0x00 0. " EP0           ,Endpoint 0 interrupt enable" "Disabled,Enabled"
line.word 0x02 "RX_IRQ_EN_REG,Receive Interrupt Enable"
bitfld.word 0x02 4. " EP4_RXEN      ,Receive endpoint 4 interrupt enable" "Disabled,Enabled"
bitfld.word 0x02 3. "          EP3_RXEN    ,Receive endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.word 0x02 2. "          EP2_RXEN     ,Receive endpoint 2 interrupt enable" "Disabled,Enabled"
bitfld.word 0x02 1. "      EP1_RXEN     ,Receive endpoint 1 interrupt enable" "Disabled,Enabled"
textline "                    "
bitfld.word 0x02 0. " EP0           ,Endpoint 0 interrupt enable" "Disabled,Enabled"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)&&((d.l(ad:0x40043000+0x60)&0x80)==0x0)
rgroup.byte 0xA++0x00
line.byte 0x00 "USB_IRQ_REG,Interrupt Status"
bitfld.byte 0x00 7. " VBUS_ERROR    ,Set when VBus drops below the VBus valid threshold during a session" "Not dropped,Dropped"
bitfld.byte 0x00 6. "       SESS_REQ    ,Set when session request signaling has been detected" "Not detected,Detected"
bitfld.byte 0x00 5. "      DISCON       ,Set in Host mode when a device disconnection is detected" "Not detected,Detected"
bitfld.byte 0x00 4. "  CONN         ,Set when a device connection is detected" "Not detected,Detected"
textline "                    "
bitfld.byte 0x00 3. " SOF           ,Set when a new frame starts" "Not started,Started"
bitfld.byte 0x00 2. "       BABBLE      ,Set in Host mode when babble is detected" "Not detected,Detected"
bitfld.byte 0x00 1. "      RESUME       ,Set when resume signaling is detected on the bus while the USB controller is in Suspend mode" "Not detected,Detected"
elif ((d.l(ad:0x40043000+0x60)&0x4)==0x0)&&((d.l(ad:0x40043000+0x60)&0x80)==0x80)
rgroup.byte 0xA++0x00
line.byte 0x00 "USB_IRQ_REG,Interrupt Status"
bitfld.byte 0x00 5. " DISCON        ,Set in Host mode when a device disconnection is detected" "Not detected,Detected"
bitfld.byte 0x00 4. "      CONN        ,Set when a device connection is detected" "Not detected,Detected"
textline "                    "
bitfld.byte 0x00 3. " SOF           ,Set when a new frame starts" "Not started,Started"
bitfld.byte 0x00 2. "       BABBLE      ,Set in Host mode when babble is detected" "Not detected,Detected"
bitfld.byte 0x00 1. "      RESUME       ,Set when resume signaling is detected on the bus while the USB controller is in Suspend mode" "Not detected,Detected"
elif ((d.l(ad:0x40043000+0x60)&0x4)==0x4)&&((d.l(ad:0x40043000+0x60)&0x80)==0x0)
rgroup.byte 0xA++0x00
line.byte 0x00 "USB_IRQ_REG,Interrupt Status"
bitfld.byte 0x00 7. " VBUS_ERROR    ,Set when VBus drops below the VBus valid threshold during a session" "Not dropped,Dropped"
bitfld.byte 0x00 6. "       SESS_REQ    ,Set when session request signaling has been detected" "Not detected,Detected"
bitfld.byte 0x00 5. "      DISCON       ,Set in Host mode when a device disconnection is detected" "Not detected,Detected"
bitfld.byte 0x00 3. "  SOF          ,Set when a new frame starts" "Not started,Started"
textline "                    "
bitfld.byte 0x00 2. " RESET         ,Set in Peripheral mode when reset signaling is detected on the bus" "Not detected,Detected"
bitfld.byte 0x00 1. "      RESUME      ,Set when resume signaling is detected on the bus while the USB controller is in Suspend mode" "Not detected,Detected"
bitfld.byte 0x00 0. "      SUSPEND      ,Set when suspend signaling is detected on the bus" "Not detected,Detected"
elif ((d.l(ad:0x40043000+0x60)&0x4)==0x4)&&((d.l(ad:0x40043000+0x60)&0x80)==0x80)
rgroup.byte 0xA++0x00
line.byte 0x00 "USB_IRQ_REG,Interrupt Status"
bitfld.byte 0x00 5. " DISCON        ,Set in Host mode when a device disconnection is detected" "Not detected,Detected"
bitfld.byte 0x00 3. "      SOF         ,Set when a new frame starts" "Not started,Started"
bitfld.byte 0x00 2. "       RESET        ,Set in Peripheral mode when reset signaling is detected on the bus" "Not detected,Detected"
bitfld.byte 0x00 1. "  RESUME       ,Set when resume signaling is detected on the bus while the USB controller is in Suspend mode" "Not detected,Detected"
textline "                    "
bitfld.byte 0x00 0. " SUSPEND       ,Set when suspend signaling is detected on the bus" "Not detected,Detected"
endif
group.byte 0xB++0x00
line.byte 0x00 "USB_IRQ_EN_REG,Interrupt Enable"
bitfld.byte 0x00 7. " VB_EN         ,VBus Error in USB_IRQ_REG" "Disabled,Enabled"
bitfld.byte 0x00 6. "          SR_EN       ,Sess Req in USB_IRQ_REG" "Disabled,Enabled"
bitfld.byte 0x00 5. "          DC_EN        ,Discon in USB_IRQ_REG" "Disabled,Enabled"
bitfld.byte 0x00 4. "      CO_EN        ,Conn in USB_IRQ_REG" "Disabled,Enabled"
textline "                    "
bitfld.byte 0x00 3. " SOF_EN        ,SOF in USB_IRQ_REG" "Disabled,Enabled"
bitfld.byte 0x00 2. "          RES/BA_EN   ,Reset/Babble in USB_IRQ_REG" "Disabled,Enabled"
bitfld.byte 0x00 1. "          RE_EN        ,Resume in USB_IRQ_REG" "Disabled,Enabled"
bitfld.byte 0x00 0. "      SU_EN        ,Suspend in USB_IRQ_REG" "Disabled,Enabled"
rgroup.word 0xC++0x1
line.word 0x00 "FRAME_REG,Frame Number "
hexmask.word 0x00 0.--10. 1. " FRAME_NUMBER  ,This is the 11-bit frame number"
group.byte 0xE++0x00
line.byte 0x00 "INDEX_REG,Endpoint Index"
bitfld.byte 0x00 0.--3. " SELECTED_ENDP ,This is the index into the selected endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xF++0x00
line.byte 0x00 "TEST_MODE_REG,Test mode"
bitfld.byte 0x00 7. " FORCE_HOST    ,Forced Host mode" "Disabled,Enabled"
bitfld.byte 0x00 6. "          FIFO_ACCESS ,FIFO access" "No access,FIFO access"
bitfld.byte 0x00 5. "       FORCE_FS     ,Full speed mode forces" "Disabled,Enabled"
bitfld.byte 0x00 4. "      FORCE_HS     ,High speed mode forces" "Disabled,Enabled"
textline "                    "
bitfld.byte 0x00 3. " TEST_PACKET   ,Test_Packet test mode" "No effect,Test packet mode"
bitfld.byte 0x00 2. "  TEST_K      ,TEST K mode" "No effect,Test K mode"
bitfld.byte 0x00 1. "       TEST_J       ,TEST J mode" "No effect,Test J mode"
bitfld.byte 0x00 0. "   Test_SE0_NAK ,Test_SE0_NAK test mode" "No effect,Test_SE0_NAK"
width 17.
tree "Indexed Registers"
group.word 0x10++0x1
line.word 0x00 "TX_MAX_P_REG,Maximum packet size for host transmit endpoint"
bitfld.word 0x00 11.--15. " M-1                           ,Multiplier M" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
hexmask.word 0x00 0.--10. 1. "                    TXMAXP               ,Maximum payload/transaction"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)
group.byte 0x12++0x00
line.byte 0x00 "CSR0L_REG,Select endpoint 0"
bitfld.byte 0x00 7. " SERVICEDSETUPEND              ,SetupEnd bit clear" "No action,Clear"
bitfld.byte 0x00 6. "             SERVICEDRXPKTRDY     ,RxPktRdy bit clear" "No action,Clear"
bitfld.byte 0x00 5. "        SENDSTALL              ,Terminate the current transaction" "No action,Terminate"
bitfld.byte 0x00 4. "          SETUPEND           ,Control transaction ends before the DataEnd bit has been set" "Not set,Set"
textline "                      "
bitfld.byte 0x00 3. " DATAEND                       ,Data End" "Not set,Set"
bitfld.byte 0x00 2. "               SENTSTALL            ,STALL handshake is transmitted" "Not set,Set"
bitfld.byte 0x00 1. "          TXPKTRDY               ,Data packet has been transmitted" "Not transmitted,Transmitted"
bitfld.byte 0x00 0. "    RXPKTRDY           ,Data packet has been received" "Not received,Received"
else
group.byte 0x12++0x00
line.byte 0x00 "CSR0L_REG,Select endpoint 0"
bitfld.byte 0x00 7. " NAK_TIMEOUT                   ,NAK Timeout" "Not set,Set"
bitfld.byte 0x00 6. "               STATUS_PKT           ,Status stage transaction" "Not set,Set"
bitfld.byte 0x00 5. "          REG_PKT                ,IN transaction requested" "Not requested,Requested"
bitfld.byte 0x00 4. "      ERROR              ,Error occurred" "Not occurred,Occurred"
textline "                      "
bitfld.byte 0x00 3. " SETUP_PKT                     ,Setup token has been send" "Not send,Send"
bitfld.byte 0x00 2. "              RX_STALL             ,STALL handshake has been received" "Not received,Received"
bitfld.byte 0x00 1. "     TXPKTRDY               ,Data packet has been transmitted" "Not transmitted,Transmitted"
bitfld.byte 0x00 0. "    RXPKTRDY           ,Data packet has been received" "Not received,Received"
endif
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)
group.byte 0x12++0x00
line.byte 0x00 "TX_CSRL_REG,Control and status register"
bitfld.byte 0x00 7. " INCOMP_TX                     ,High-bandwidth isochronous transfers status" "2,3"
bitfld.byte 0x00 6. "                     CLR_DATA_TOG         ,Endpoint Data toggle reset" "Not reset,Reset"
bitfld.byte 0x00 5. "        SENT_STALL             ,STALL handshake status" "Not transmitted,Transmitted"
bitfld.byte 0x00 4. "    SEND_STALL         ,STALL handshake to an IN token status" "Not issue,Issue"
textline "                      "
bitfld.byte 0x00 3. " FLUSH_FIFO                    ,The latest packet has been flushed" "Not flushed,Flushed"
bitfld.byte 0x00 2. "           UNDER_RUN            ,Under run" "Not under-run,Under-run"
bitfld.byte 0x00 1. "    FIFO_NOT_EMPTY         ,There is at least one packet in the transmit FIFO" "Empty,Not empty"
bitfld.byte 0x00 0. "          TX_PKT_RDY         ,Data packet into the FIFO has been loaded" "Not loaded,Loaded"
else
group.byte 0x12++0x00
line.byte 0x00 "TX_CSRL_REG,Control and status register"
bitfld.byte 0x00 7. " NAK_TIMEOUT/INCOMP_TX         ,Transmit endpoint has been halted/No response is received" "Not halted/No action,Halted/Not received"
bitfld.byte 0x00 6. "  CLR_DATA_TOG         ,Endpoint Data toggle reset" "Not reset,Reset"
bitfld.byte 0x00 5. "        RX_STALL               ,STALL handshake status" "Not received,Received"
bitfld.byte 0x00 4. "       SETUP_PKT          ,SETUP token instead OUT token" "OUT,SETUP"
textline "                      "
bitfld.byte 0x00 3. " FLUSH_FIFO                    ,The latest packet has been flushed" "Not flushed,Flushed"
bitfld.byte 0x00 2. "           ERROR                ,No handshake packet has been received" "Not occurred,Occurred"
bitfld.byte 0x00 1. "     FIFO_NOT_EMPTY         ,There is at least one packet in the transmit FIFO" "Empty,Not empty"
bitfld.byte 0x00 0. "          TX_PKT_RDY         ,Data packet into the FIFO has been loaded" "Not loaded,Loaded"
endif
group.byte 0x13++0x00
line.byte 0x00 "CSROH_REG,Bit Definitions"
bitfld.byte 0x00 0. " FLUSH_FIFO                    ,Flush the next packet to be transmitted/read from endpoint 0" "Disabled,Enabled"
group.byte 0x13++0x00
line.byte 0x00 "CSROH_REG,Bit Definitions"
bitfld.byte 0x00 3. " DIS_PING                      ,Not to issue PING tokens" "Issue,Not to issue"
bitfld.byte 0x00 2. "          DATA_TOGGLE_WRITE_EN ,The current state of the endpoint 0 enabled" "disabled,Enabled"
bitfld.byte 0x00 1. "         DATA_TOGGLE            ,Current state of the endpoint 0 data toggle" "0,1"
bitfld.byte 0x00 0. "                  FLUSH_FIFO         ,Flush the next packet to be transmitted/read from endpoint 0" "Disabled,Enabled"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)
group.byte 0x13++0x00
line.byte 0x00 "TX_CSRH_REG,Control and status bits for endpoint0"
bitfld.byte 0x00 7. " AUTO_SET                      ,Auto set" "Disabled,Enabled"
bitfld.byte 0x00 6. "              ISO                  ,Enable transmit endpoint for isochronous transfers" "Disabled,Enabled"
bitfld.byte 0x00 5. "         MODE                   ,Enable the endpoint direction as transmit" "Disabled,Enabled"
bitfld.byte 0x00 4. "           DMAReqEnab         ,Enable the DMA request for the transmit endpoint" "Disabled,Enabled"
textline "                      "
bitfld.byte 0x00 3. " FRCDATATOG                    ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
bitfld.byte 0x00 2. "            DMAREQMODE           ,DMA request mode" "Not selected,Selected"
else
group.byte 0x13++0x00
line.byte 0x00 "TX_CSRH_REG,Control and status bits for endpoint0"
bitfld.byte 0x00 7. " AUTO_SET                      ,Auto set" "Disabled,Enabled"
bitfld.byte 0x00 5. "              MODE                 ,Enable the endpoint direction as transmit" "Disabled,Enabled"
bitfld.byte 0x00 4. "         DMAReqEnab             ,Enable the DMA request for the transmit endpoint" "Disabled,Enabled"
textline "                      "
bitfld.byte 0x00 3. " FRCDATATOG                    ,Force the endpoint data toggle to switch and the data packet to be cleared from the FIFO" "Not forced,Forced"
bitfld.byte 0x00 2. "            DMAREQMODE           ,DMA request mode" "Not selected,Selected"
bitfld.byte 0x00 1. "     DATA_TOG_WRITE_EN      ,Data toggle wrtite enable" "Disabled,Enabled"
bitfld.byte 0x00 0. "           DATA_TOGGLE        ,Endpoint 0 status" "Ignored all value,Required setting"
endif
group.word 0x14++0x1
line.word 0x00 "RX_MAX_P_REG,Maximum amount of data in a single operation"
bitfld.word 0x00 11.--15. " M-1                           ,Multiplier M" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
hexmask.word 0x00 0.--10. 1. "                    TXMAXP               ,Maximum payload/transaction"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)
group.byte 0x16++0x00
line.byte 0x00 "RX_CSRL_REG,Control and status for currently selected receive endpoint"
bitfld.byte 0x00 7. " CLR_DATA_TOG                  ,Endpoint Data toggle reset" "Not reset,Reset"
bitfld.byte 0x00 6. "             SENT_STALL           ,STALL handshake status" "Not transmitted,Transmitted"
bitfld.byte 0x00 5. "  SEND_STALL             ,STALL handshake to an IN token status" "Not issue,Issue"
bitfld.byte 0x00 4. "          FLUSH_FIFO         ,The latest packet has been flushed" "Not flushed,Flushed"
textline "                      "
bitfld.byte 0x00 3. " IDATA_ERROR                   ,Data packet has a CRC or bit-stuff error" "No error,Error"
bitfld.byte 0x00 2. "              OVER_RUN             ,Over run" "Not over-run,Over-run"
bitfld.byte 0x00 1. "     FIFO_FULL              ,FIFO is full" "Not full,Full"
bitfld.byte 0x00 0. "           RX_PKT_RDY         ,Data packet has been received" "Not received,Received"
else
group.byte 0x16++0x00
line.byte 0x00 "RX_CSRL_REG,Control and status for currently selected receive endpoint"
bitfld.byte 0x00 7. " CLR_DATA_TOG                  ,Endpoint Data toggle reset" "Not reset,Reset"
bitfld.byte 0x00 6. "             RX_STALL             ,STALL handshake is received" "Not received,Received"
bitfld.byte 0x00 5. "     REQ_PKT                ,IN transaction requested" "Not requested,Requested"
bitfld.byte 0x00 4. "      FLUSH_FIFO         ,The latest packet has been flushed" "Not flushed,Flushed"
textline "                      "
bitfld.byte 0x00 3. " DATA_ERROR/NAK_TIMEOUT        ,Data error/NAK timeout" "Not occurred,Occurred"
bitfld.byte 0x00 2. "          ERROR                ,No data packet has been received" "Not occurred,Occurred"
bitfld.byte 0x00 1. "     FIFO_FULL              ,FIFO is full" "Not full,Full"
bitfld.byte 0x00 0. "           RX_PKT_RDY         ,Data packet has been received" "Not received,Received"
endif
if ((d.l(ad:0x40043000+0x60)&0x4)==0x0)
group.byte 0x17++0x00
line.byte 0x00 "RX_CSRH_REG,Control and status for transfer through the currently selected receive endpoint"
bitfld.byte 0x00 7. " AUTO_CLR                      ,Auto clear" "Disabled,Enabled"
bitfld.byte 0x00 6. "              ISO                  ,Enable transmit endpoint for isochronous transfers" "Disabled,Enabled"
bitfld.byte 0x00 4. "         DMAReqEnab             ,Enable the DMA request for the transmit endpoint" "Disabled,Enabled"
bitfld.byte 0x00 4. "           DIS_NYET/PID_ERROR ,Bulk/interrupt transactions/ISO transactions" "Not set,Set"
textline "                      "
bitfld.byte 0x00 3. " DMAREQMODE                    ,DMA request mode" "Not selected,Selected"
bitfld.byte 0x00 0. "          INCOMP_RX            ,Receive incomplete" "Complete,Incomplete"
else
group.byte 0x17++0x00
line.byte 0x00 "RX_CSRH_REG,Control and status for transfer through the currently selected receive endpoint"
bitfld.byte 0x00 7. " AUTO_CLR                      ,Auto clear" "Disabled,Enabled"
bitfld.byte 0x00 6. "              AUTO_REQ             ,Auto request" "Disabled,Enabled"
bitfld.byte 0x00 5. "         DMAREQENAB             ,Enable the DMA request for the transmit endpoint" "Disabled,Enabled"
bitfld.byte 0x00 4. "           PID_ERROR          ,PID error" "Not set,Set"
textline "                      "
bitfld.byte 0x00 3. " DMAREQMODE                    ,DMA request mode" "Not selected,Selected"
bitfld.byte 0x00 2. "          DATA_TOG_WRITE_EN    ,Data toggle wrtite enable" "Disabled,Enabled"
bitfld.byte 0x00 1. "         DATA_TOGGLE            ,Endpoint 0 status" "Ignored all value,Required setting"
bitfld.byte 0x00 0. "  INCOMP_RX          ,Receive incomplete" "Complete,Incomplete"
endif
rgroup.byte 0x18++0x00
line.byte 0x00 "COUNT0_REG,Number of received data bytes in the endpoint 0 FIFO"
hexmask.byte 0x00 0.--6. 1. " ENDPOINT0_RX_COUNT            ,Number of received data bytes in the endpoint 0"
rgroup.word 0x18++0x1
line.word 0x00 "RX_COUNT_REG,Number of data bytes in the packet currently in line to be read from the Rx FIFO"
hexmask.word 0x00 0.--13. 1. " ENDPOINT_RX_COUNT             ,Number of bytes in the packet currently in line to be read from FIFO"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x4)
group.byte 0x1A++0x00
line.byte 0x00 "TYPE_REG,Number of received bytes in endpoint0 FIFO"
bitfld.byte 0x00 6.--7. " SPEED                         ,Operating speed of the target device" "Unused,High,Full,Low"
endif
group.byte 0x1A++0x00
line.byte 0x00 "TX_TYPE_REG,Number of bytes to be read from the peripheral receive endpoint"
bitfld.byte 0x00 6.--7. " SPEED                         ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "                PROTOCOL             ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "      TARGET_ENDPOINT_NUMBER ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x4)
group.byte 0x1B++0x00
line.byte 0x00 "NAK_LIMIT0_REG,NAK response timeout on endpoint 0"
bitfld.byte 0x00 0.--4. " ENDP0_NAK_LIMIT               ,Number of frames after which endpoint 0 should timeout" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
group.byte 0x1B++0x00 "host"
line.byte 0x00 "TX_INTERVAL_REG,Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout"
hexmask.byte 0x00 0.--7. 1. " TX_POLLING_INTERVAL/NAK_LIMIT ,Polling interval/NAK limit"
group.byte 0x1D++0x00
line.byte 0x00 "RX_TYPE_REG,Polling interval for interrupt/ISOC transaction"
bitfld.byte 0x00 6.--7. " SPEED                         ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "                PROTOCOL             ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "      TARGET_ENDPOINT_NUMBER ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1E++0x00
line.byte 0x00 "RX_INTERVAL_REG,Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout"
hexmask.byte 0x00 0.--7. 1. " RX_POLLING_INTERVAL/NAK_LIMIT ,Polling interval/NAK limit"
endif
rgroup.byte 0x1F++0x00
line.byte 0x00 "CONFIG_DATAREG,Returns details of USB controller configuration"
bitfld.byte 0x00 7. " MPRXE                         ,Automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. "          MPTEXE               ,Automatic splitting of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 5. "     BIG_ENDIAN             ,Big endian" "Not selected,Selected"
bitfld.byte 0x00 4. "       HBRXE              ,High-bandwidth receive ISO endpoint support" "Not selected,Selected"
textline "                      "
bitfld.byte 0x00 3. " HBTXE                         ,High-bandwidth transmit ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. "          DYNFIFO_SIZING       ,Dynamic FIFO sizing" "Not selected,Selected"
bitfld.byte 0x00 1. "     SOFT_CON_E             ,Soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. "       UTMI_DATA_WIDTH    ,UTMI+ data width" "Not selected,Selected"
rgroup.byte 0x1F++0x00
line.byte 0x00 "FIFO_SIZE_REG,Returns the configured size of the selected receive and transmit FIFOs"
bitfld.byte 0x00 4.--7. " RX_FIFO_SIZE                  ,Size of FIFO's associated with the selected additional receive endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "                    TX_FIFO_SIZE         ,Size of FIFO's associated with the selected additional transmit endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "FIFO Registers"
group.long 0x20++0x13
line.long 0x0 "EP0_FIFO_REG,Loads,unloads data"
line.long 0x4 "EP1_FIFO_REG,Loads,unloads data"
line.long 0x8 "EP2_FIFO_REG,Loads,unloads data"
line.long 0xC "EP3_FIFO_REG,Loads,unloads data"
line.long 0x10 "EP4_FIFO_REG,Loads,unloads data"
tree.end
tree "Control and Status Registers"
rgroup.byte 0x60++0x01
line.byte 0x00 "DEV_CTRL_REG,Device control register"
bitfld.byte 0x00 7. " B-DEVICE ,USB controller status" "A device,B device"
bitfld.byte 0x00 6. "       FSDEV   ,Full-speed or high-speed device has been detected" "Not detected,Detected"
bitfld.byte 0x00 5. "  LSDEV ,Low-speed device has been detected" "Not detected,Detected"
bitfld.byte 0x00 2. "  HOST_MODE ,Host mode enable" "Disabled,Enabled"
textline "                      "
bitfld.byte 0x00 1. " HOST_REQ ,Host negotiation" "Completed,Initiated"
bitfld.byte 0x00 0. "      SESSION ,Start or end session" "End,Start"
line.byte 0x01 "MISC_REG,Contains the early DMA enable bits for receive and transmit"
bitfld.byte 0x01 1. " TX_EDMA  ,DMA_REQ signal status for all IN endpoints" "MAXP,MAXP-8"
bitfld.byte 0x01 0. "         RX_EDMA ,DMA_REQ signal status for all OUT endpoints" "MAXP,MAXP-8"
group.byte 0x62++0x01
line.byte 0x00 "TX_FIFO_SIZE_REG,Size of the selected transmit endpoint FIFO"
bitfld.byte 0x00 4. " DPB      ,Double-packet buffering" "Not supported,Supported"
bitfld.byte 0x00 0.--3. "  SZ      ,Maximum packet size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1.024 bytes,2.048 bytes,4.096 bytes,?..."
line.byte 0x01 "RX_FIFO_SIZE_REG,Size of the selected receive endpoint FIFO"
bitfld.byte 0x01 4. " DPB      ,Double-packet buffering" "Not supported,Supported"
bitfld.byte 0x01 0.--3. "  SZ      ,Maximum packet size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1.024 bytes,2.048 bytes,4.096 bytes,?..."
group.word 0x64++0x1
line.word 0x00 "TX_FIFO_ADD_REG,Addres register"
hexmask.word 0x00 0.--12. 1. " AD       ,Start address of the transmit endpoint FIFO"
group.word 0x66++0x1
line.word 0x00 "RX_FIFO_ADD_REG,Addres register"
hexmask.word 0x00 0.--12. 1. " AD       ,Start address of the receive endpoint FIFO"
wgroup.byte 0x68++0x00
line.byte 0x00 "VBUS_CSR_REG,VControl"
bitfld.byte 0x00 0.--3. " VCONTROL ,Vendor-specific control data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x68++0x00
line.byte 0x00 "VBUS_CSR_REG,VStatus"
hexmask.byte 0x00 0.--7. 1. " VSTATUS  ,Vendor-specific status data"
rgroup.word 0x6C++0x01
line.word 0x00 "HW_VERSION_REG,Version of the USB controller"
bitfld.word 0x00 10.--14. " XX       ,Major version num" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.word 0x00 0.--9. 1. "             YYY     ,Minor version number"
tree.end
width 20.
tree "ULPI and Configuration Registers"
rgroup.byte 0x70++0x06
line.byte 0x00 "ULPI_VBUS_CTRL_REG,ULPI VBus control register"
bitfld.byte 0x00 1. "     USEEXTVBUSIND   ,Use of an external VBus indicator" "Disabled,Enabled"
bitfld.byte 0x00 0. "      USEEXTVBUS   ,External charge pump" "Not used,Used"
line.byte 0x01 "ULPI_CARKIT_CTRL_REG,Interfacing to in-car CarKit systems control"
bitfld.byte 0x01 5. "         CARKITACTIVEEND ,CarKitActive cleared" "Not cleared,Cleared"
bitfld.byte 0x01 4. "   RXCMDEVENT   ,RxCmd has been latched" "Not latched,Lathced"
bitfld.byte 0x01 3. "    CANCELCARKIT ,abort CarKit mode and wake up the PHY" "nOT ABORTED,aBORTED"
bitfld.byte 0x01 2. "                         ALTINTEVENT ,alt_int event occurres" "Not occurred,Occurred"
textline "                         "
bitfld.byte 0x01 1. " CARKITACTIVE    ,CarKit mode is entered after DIR goes High" "Not entered,Entered"
bitfld.byte 0x01 0. "   DISABLEUTMI  ,Disable UTMI" "Disabled,Enabled"
line.byte 0x02 "ULPI_IRQ_MASK_REG,Enables the assertion of MC_NINT"
bitfld.byte 0x02 3. " RXCMDINT        ,Asserted if RxCmdEvent is set" "Not asserted,Asserted"
bitfld.byte 0x02 2. "  ACTIVEENDINT ,Asserted if CarKitActiveEnd is set" "Not asserted,Asserted"
bitfld.byte 0x02 1. "   ALTTNT       ,Asserted if AltIntEvent is set" "Not asserted,Asserted"
bitfld.byte 0x02 0. "                        REGINT      ,Asserted if ULPIRegCmplt is set" "Not asserted,Asserted"
line.byte 0x03 "ULPI_IRQ_SRC_REG,Unmasked value of the possible interrupt sources"
line.byte 0x04 "ULPI_DATA_REG,Contains the data associated with register reads/writes conducted through the ULPI interface"
line.byte 0x05 "ULPI_ADDR_REG,Contains the address of the register being read/written through the ULPI interface"
line.byte 0x06 "ULPI_REG_CTRL,Contains control and status bits relating to the register being read/written through the ULPI interface"
bitfld.byte 0x06 2. "     ULPIRDNWR       ,Read or write access" "Write,Read"
bitfld.byte 0x06 1. "         ULPIREGCMPLT ,Register access is complete" "Not completed,Completed"
bitfld.byte 0x06 0. "  ULPIREGREQ   ,Initiate register access" "Not initiated,Initiated"
if (((d.l(ad:0x40000000+0x30)&0x7)==0x7)||((d.l(ad:0x40010000+0x30)&0x7)==0x7))
rgroup.byte 0x77++0x00
line.byte 0x00 "ULPI_RAW_DATA_REG,Sample the ULPI bus(asynchronus)/Store the last received command(synchronous)"
bitfld.byte 0x00 7. "     ALL_INT         ,Non-USB interrupt" "Not occurred,Occurred"
bitfld.byte 0x00 4.--5. "  RX_EVENT     ,Encoded UTMI event signals" "0,1,2,3"
bitfld.byte 0x00 2.--3. "              VBUS_STATE   ,Encoded Vbus voltage state" "Vbus < VB_Sess_END,VB_Sess_END < = Vbus < VB_Sess_VLD,VB_Sess_VLD < = Vbus < VB_Vbus_VLD,VB_Sess_VLD < = Vbus"
bitfld.byte 0x00 0.--1. "  LINE_STATE  ,UTMI+ LineState signals" "0,1,2,3"
else
rgroup.byte 0x77++0x00
line.byte 0x00 "ULPI_RAW_DATA_REG,Sample the ULPI bus(asynchronus)/Store the last received command(synchronous)"
bitfld.byte 0x00 3. "     DATA3           ,Active high interrupt indication" "Not active,Active"
bitfld.byte 0x00 2. "    DATA2        ,Single-ended zero" "Not occurred,Occurred"
bitfld.byte 0x00 1. "   DATA1        ,Differential data" "Not occurred,Occurred"
bitfld.byte 0x00 0. "                        DATA0       ,Active high transmit enable" "Disabled,Enabled"
endif
rgroup.byte 0x78++0x01
line.byte 0x00 "EP_INFO_REG,Number of transmit and receive endpoints"
bitfld.byte 0x00 4.--7. "     RXENDPOINTS     ,The number of receive endpoints implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "            TXENDPOINTS  ,The number of transmit endpoints implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x01 "RAM_INFO_REG,Number of DMA channels and the width of the RAM"
bitfld.byte 0x01 4.--7. "     DMAChans        ,The number of DMA channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x01 0.--3. "            RamBits      ,The width of the RAM address bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x7A++0x05
line.byte 0x00 "LINK_INFO_REG,Configuration of linkspecific delays"
bitfld.byte 0x00 4.--7. "     WTCON           ,The wait for the connect/diconnect filter in units 533.3ns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "            WTID         ,The dalay to IDDIG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x01 "VP_LEN_REG,Duration of the Vbus pulsing charge"
line.byte 0x02 "HS_EOF1_REG,Minimum time gap for high-speed transactions"
line.byte 0x03 "FS_EOF1_REG,Minimum time gap for full-speed transactions"
line.byte 0x04 "LS_EOF1_REG,Minimum time gap for low-speed transactions"
line.byte 0x05 "SOFT_RESET_REG,Soft reset"
bitfld.byte 0x05 1. "     NRSTX           ,The output NRSTXO dalay" "Disabled,Enabled"
bitfld.byte 0x05 0. "      NRST         ,The output NRSTO dalay"  "Disabled,Enabled"
tree.end
tree "Non-Indexed End Point Control/Status Registers"
group.word 0x100++0x01 "Endpoint 0"
line.word 0x00 "EP0_TX_MAX_P_REG,Maximum packet size for host transmit endpoint0"
hexmask.word 0x00 0.--10. 1. " EP0_TxMAXP       ,Maximum payload/transaction"
rgroup.word (0x100+0x2)++0x01
line.word 0x00 "EP0_TX_CSR_REG,Transmit endpoint0 control and status"
group.word (0x100+0x4)++0x01
line.word 0x00 "EP0_RX_MAX_P_REG,Maximum amount of data can be transferred through the endpoint0"
hexmask.word 0x00 0.--10. 1. " EPX_RXMAXP        ,Maximum Payload/transaction"
rgroup.word (0x100+0x6)++0x03
line.word 0x00 "EP0_RX_CSR_REG,Receive endpoint0 control and status"
line.word 0x02 "EP0_RX_COUNT_REG,Number of data bytes to be read from the endpoint0 receive FIFO"
hexmask.word 0x00 0.--13. 1. " Endpoint_Rx_Count ,The number of data bytes to be read from the receive FIFO"
wgroup.byte (0x100+0xA)++0x00
line.byte 0x00 "EP0_TX_TYPE_REG,Number of bytes to be read from peripheral endpoint0 transmit FIFO"
bitfld.byte 0x00 6.--7. " EP0_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP0_PROTOCOL ,Protocol for the transmit endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP0_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor"  "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x100+0xB)++0x02
line.byte 0x00 "EP0_TX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
line.byte 0x01 "EP0_RX_TYPE_REG,The transaction protocol, speed and peripheral endpoint number setup"
bitfld.byte 0x00 6.--7. " EP0_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP0_PROTOCOL ,Protocol for the receive endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP0_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x02 "EP0_RX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
rgroup.byte (0x100+0xE)++0x00
line.byte 0x00 "EP0_FIFO_SIZE_REG,Size and endpoint0 receive and transmit FIFO"
bitfld.byte 0x00 4.--7. " EP0_Rx_FIFO_SIZE ,The sizes of the FIFOs receive endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "      Tx_FIFO_SIZE  ,The sizes of the FIFOs transmit endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x110++0x01 "Endpoint 1"
line.word 0x00 "EP1_TX_MAX_P_REG,Maximum packet size for host transmit endpoint0"
hexmask.word 0x00 0.--10. 1. " EP1_TxMAXP       ,Maximum payload/transaction"
rgroup.word (0x110+0x2)++0x01
line.word 0x00 "EP1_TX_CSR_REG,Transmit endpoint0 control and status"
group.word (0x110+0x4)++0x01
line.word 0x00 "EP1_RX_MAX_P_REG,Maximum amount of data can be transferred through the endpoint0"
hexmask.word 0x00 0.--10. 1. " EPX_RXMAXP        ,Maximum Payload/transaction"
rgroup.word (0x110+0x6)++0x03
line.word 0x00 "EP1_RX_CSR_REG,Receive endpoint0 control and status"
line.word 0x02 "EP1_RX_COUNT_REG,Number of data bytes to be read from the endpoint0 receive FIFO"
hexmask.word 0x00 0.--13. 1. " Endpoint_Rx_Count ,The number of data bytes to be read from the receive FIFO"
wgroup.byte (0x110+0xA)++0x00
line.byte 0x00 "EP1_TX_TYPE_REG,Number of bytes to be read from peripheral endpoint0 transmit FIFO"
bitfld.byte 0x00 6.--7. " EP1_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP1_PROTOCOL ,Protocol for the transmit endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP1_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor"  "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x110+0xB)++0x02
line.byte 0x00 "EP1_TX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
line.byte 0x01 "EP1_RX_TYPE_REG,The transaction protocol, speed and peripheral endpoint number setup"
bitfld.byte 0x00 6.--7. " EP1_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP1_PROTOCOL ,Protocol for the receive endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP1_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x02 "EP1_RX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
rgroup.byte (0x110+0xE)++0x00
line.byte 0x00 "EP1_FIFO_SIZE_REG,Size and endpoint0 receive and transmit FIFO"
bitfld.byte 0x00 4.--7. " EP1_Rx_FIFO_SIZE ,The sizes of the FIFOs receive endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "      Tx_FIFO_SIZE  ,The sizes of the FIFOs transmit endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x120++0x01 "Endpoint 2"
line.word 0x00 "EP2_TX_MAX_P_REG,Maximum packet size for host transmit endpoint0"
hexmask.word 0x00 0.--10. 1. " EP2_TxMAXP       ,Maximum payload/transaction"
rgroup.word (0x120+0x2)++0x01
line.word 0x00 "EP2_TX_CSR_REG,Transmit endpoint0 control and status"
group.word (0x120+0x4)++0x01
line.word 0x00 "EP2_RX_MAX_P_REG,Maximum amount of data can be transferred through the endpoint0"
hexmask.word 0x00 0.--10. 1. " EPX_RXMAXP        ,Maximum Payload/transaction"
rgroup.word (0x120+0x6)++0x03
line.word 0x00 "EP2_RX_CSR_REG,Receive endpoint0 control and status"
line.word 0x02 "EP2_RX_COUNT_REG,Number of data bytes to be read from the endpoint0 receive FIFO"
hexmask.word 0x00 0.--13. 1. " Endpoint_Rx_Count ,The number of data bytes to be read from the receive FIFO"
wgroup.byte (0x120+0xA)++0x00
line.byte 0x00 "EP2_TX_TYPE_REG,Number of bytes to be read from peripheral endpoint0 transmit FIFO"
bitfld.byte 0x00 6.--7. " EP2_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP2_PROTOCOL ,Protocol for the transmit endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP2_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor"  "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x120+0xB)++0x02
line.byte 0x00 "EP2_TX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
line.byte 0x01 "EP2_RX_TYPE_REG,The transaction protocol, speed and peripheral endpoint number setup"
bitfld.byte 0x00 6.--7. " EP2_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP2_PROTOCOL ,Protocol for the receive endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP2_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x02 "EP2_RX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
rgroup.byte (0x120+0xE)++0x00
line.byte 0x00 "EP2_FIFO_SIZE_REG,Size and endpoint0 receive and transmit FIFO"
bitfld.byte 0x00 4.--7. " EP2_Rx_FIFO_SIZE ,The sizes of the FIFOs receive endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "      Tx_FIFO_SIZE  ,The sizes of the FIFOs transmit endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x130++0x01 "Endpoint 3"
line.word 0x00 "EP3_TX_MAX_P_REG,Maximum packet size for host transmit endpoint0"
hexmask.word 0x00 0.--10. 1. " EP3_TxMAXP       ,Maximum payload/transaction"
rgroup.word (0x130+0x2)++0x01
line.word 0x00 "EP3_TX_CSR_REG,Transmit endpoint0 control and status"
group.word (0x130+0x4)++0x01
line.word 0x00 "EP3_RX_MAX_P_REG,Maximum amount of data can be transferred through the endpoint0"
hexmask.word 0x00 0.--10. 1. " EPX_RXMAXP        ,Maximum Payload/transaction"
rgroup.word (0x130+0x6)++0x03
line.word 0x00 "EP3_RX_CSR_REG,Receive endpoint0 control and status"
line.word 0x02 "EP3_RX_COUNT_REG,Number of data bytes to be read from the endpoint0 receive FIFO"
hexmask.word 0x00 0.--13. 1. " Endpoint_Rx_Count ,The number of data bytes to be read from the receive FIFO"
wgroup.byte (0x130+0xA)++0x00
line.byte 0x00 "EP3_TX_TYPE_REG,Number of bytes to be read from peripheral endpoint0 transmit FIFO"
bitfld.byte 0x00 6.--7. " EP3_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP3_PROTOCOL ,Protocol for the transmit endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP3_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor"  "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x130+0xB)++0x02
line.byte 0x00 "EP3_TX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
line.byte 0x01 "EP3_RX_TYPE_REG,The transaction protocol, speed and peripheral endpoint number setup"
bitfld.byte 0x00 6.--7. " EP3_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP3_PROTOCOL ,Protocol for the receive endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP3_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x02 "EP3_RX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
rgroup.byte (0x130+0xE)++0x00
line.byte 0x00 "EP3_FIFO_SIZE_REG,Size and endpoint0 receive and transmit FIFO"
bitfld.byte 0x00 4.--7. " EP3_Rx_FIFO_SIZE ,The sizes of the FIFOs receive endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "      Tx_FIFO_SIZE  ,The sizes of the FIFOs transmit endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x140++0x01 "Endpoint 4"
line.word 0x00 "EP4_TX_MAX_P_REG,Maximum packet size for host transmit endpoint0"
hexmask.word 0x00 0.--10. 1. " EP4_TxMAXP       ,Maximum payload/transaction"
rgroup.word (0x140+0x2)++0x01
line.word 0x00 "EP4_TX_CSR_REG,Transmit endpoint0 control and status"
group.word (0x140+0x4)++0x01
line.word 0x00 "EP4_RX_MAX_P_REG,Maximum amount of data can be transferred through the endpoint0"
hexmask.word 0x00 0.--10. 1. " EPX_RXMAXP        ,Maximum Payload/transaction"
rgroup.word (0x140+0x6)++0x03
line.word 0x00 "EP4_RX_CSR_REG,Receive endpoint0 control and status"
line.word 0x02 "EP4_RX_COUNT_REG,Number of data bytes to be read from the endpoint0 receive FIFO"
hexmask.word 0x00 0.--13. 1. " Endpoint_Rx_Count ,The number of data bytes to be read from the receive FIFO"
wgroup.byte (0x140+0xA)++0x00
line.byte 0x00 "EP4_TX_TYPE_REG,Number of bytes to be read from peripheral endpoint0 transmit FIFO"
bitfld.byte 0x00 6.--7. " EP4_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP4_PROTOCOL ,Protocol for the transmit endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP4_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor"  "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x140+0xB)++0x02
line.byte 0x00 "EP4_TX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
line.byte 0x01 "EP4_RX_TYPE_REG,The transaction protocol, speed and peripheral endpoint number setup"
bitfld.byte 0x00 6.--7. " EP4_SPEED        ,Operating speed of the target device" "Unused,High,Full,Low"
bitfld.byte 0x00 4.--5. "  EP4_PROTOCOL ,Protocol for the receive endpoint:" "Control,Isonchronous,Bulk,Interrupt"
bitfld.byte 0x00 0.--3. "  EP4_Target_Endp_Nr ,The endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x02 "EP4_RX_INTERVAL_REG,The polling interval for interrupt/SOC transactions"
rgroup.byte (0x140+0xE)++0x00
line.byte 0x00 "EP4_FIFO_SIZE_REG,Size and endpoint0 receive and transmit FIFO"
bitfld.byte 0x00 4.--7. " EP4_Rx_FIFO_SIZE ,The sizes of the FIFOs receive endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "      Tx_FIFO_SIZE  ,The sizes of the FIFOs transmit endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "Extended Registers"
group.word 0x300++0x01
line.word 0x00 "EP0_RQ_PKT_COUNT_REG,The number of packets that are to be transferred to receive endpoitn 0"
group.word 0x304++0x01
line.word 0x00 "EP1_RQ_PKT_COUNT_REG,The number of packets that are to be transferred to receive endpoitn 1"
group.word 0x308++0x01
line.word 0x00 "EP2_RQ_PKT_COUNT_REG,The number of packets that are to be transferred to receive endpoitn 2"
group.word 0x30C++0x01
line.word 0x00 "EP3_RQ_PKT_COUNT_REG,The number of packets that are to be transferred to receive endpoitn 3"
group.word 0x310++0x01
line.word 0x00 "EP4_RQ_PKT_COUNT_REG,The number of packets that are to be transferred to receive endpoitn 4"
group.word 0x340++0x9
line.word 0x00 "RX_DPKT_BUF_DIS_REG,The receive endpoints that have disabled the double pucket buffor"
bitfld.word 0x00 4. " EP4_RXDPKTBUFDIS ,Receive Double Packet Buffer Disable for endpoint 4" "No,Yes"
bitfld.word 0x00 3. "        EP3_RXDPKTBUFDIS ,Receive Double Packet Buffer Disable for endpoint 3" "No,Yes"
bitfld.word 0x00 2. "  EP2_RXDPKTBUFDIS ,Receive Double Packet Buffer Disable for endpoint 2" "No,Yes"
bitfld.word 0x00 1. "  EP1_RXDPKTBUFDIS ,Receive Double Packet Buffer Disable for endpoint 1" "No,Yes"
line.word 0x02 "TX_DPKT_BUF_DIS_REG,The transmit endpoints that have disabled the double pucket buffor"
bitfld.word 0x02 4. " EP4_TXDPKTBUFDIS ,Transmit Double Packet Buffer Disable for endpoint 4" "No,Yes"
bitfld.word 0x02 3. "        EP3_TXDPKTBUFDIS ,Transmit Double Packet Buffer Disable for endpoint 3" "No,Yes"
bitfld.word 0x02 2. "  EP2_TXDPKTBUFDIS ,Transmit Double Packet Buffer Disable for endpoint 2" "No,Yes"
bitfld.word 0x02 1. "  EP1_TXDPKTBUFDIS ,Transmit Double Packet Buffer Disable for endpoint 1" "No,Yes"
line.word 0x04 "C_T_UCH_REG,The chirp timeout"
line.word 0x06 "C_T_HHSRTN_REG,The delay to enable UTM normal operating mode"
line.word 0x08 "C_T_HSBT_REG,Value to be added to the minimum high speed timeout period of 736 bit times"
bitfld.word 0x08 0.--3. " HS_TIMEOUT_ADDER ,Delay adder" "1.534 us,1.667 us,1.801 us,1.934 us,2.067 us,2.201 us,2.334 us,2.467 us,2.601 us, 2.734 us,2.868 us,3.001 us,3.134 us,3.268 us,3.401 us,3.534 us"
tree.end
tree "DMA Registers"
rgroup.byte 0x200++0x00
line.byte 0x00 "DMA_INT_REG,Interrupt for DMA channels"
bitfld.byte 0x00 3. "     CH4_DMA_INTR ,Channel4 DMA interrupt" "Not occurred,Occurred"
bitfld.byte 0x00 2. "                              CH3_DMA_INTR ,Channel4 DMA interrupt" "Not occurred,Occurred"
bitfld.byte 0x00 1. "  CH2_DMA_INTR ,Channel4 DMA interrupt" "Not occurred,Occurred"
bitfld.byte 0x00 0. "  CH1_DMA_INTR ,Channel4 DMA interrupt" "Not occurred,Occurred"
group.word 0x204++0x01
line.word 0x00 "CH1_DMA_CTRL_REG,The DMA transfer control for channel 1"
bitfld.word 0x00 9.--10. "     DMA_BRSTM    ,Burst mode" "Bursts of unspecified length,INCR4 or unspecified length,INCR8;INCR4 or unspecified length,INCR16;INCR8;INCR4 or unspecified length"
bitfld.word 0x00 8. "  DMA_ERR      ,Bus error bit" "Not occurred,Occurred"
bitfld.word 0x00 4.--7. "  DMAEP        ,The endpoint number this channel is assigned to" "0,1,2,3,4,?..."
bitfld.word 0x00 3. "      DMAIE        ,DMA interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.word 0x00 2. " DMAMODE      ,DMA Transfer mode" "Mode 0,Mode 1"
bitfld.word 0x00 1. "                                    DMA_DIR      ,DMA transfer direction" "Write,Read"
bitfld.word 0x00 0. "         DMA_ENAB     ,DMA transfer enable"  "Disabled,Enabled"
group.long (0x204+0x4)++0x07
line.long 0x00 "CH1_DMA_ADDR_REG,The current memory address of the DMA channel 1"
line.long 0x04 "CH1_DMA_COUNT_REG,The current DMA count of the transfer for DMA channel 1"
group.word 0x214++0x01
line.word 0x00 "CH2_DMA_CTRL_REG,The DMA transfer control for channel 2"
bitfld.word 0x00 9.--10. "     DMA_BRSTM    ,Burst mode" "Bursts of unspecified length,INCR4 or unspecified length,INCR8;INCR4 or unspecified length,INCR16;INCR8;INCR4 or unspecified length"
bitfld.word 0x00 8. "  DMA_ERR      ,Bus error bit" "Not occurred,Occurred"
bitfld.word 0x00 4.--7. "  DMAEP        ,The endpoint number this channel is assigned to" "0,1,2,3,4,?..."
bitfld.word 0x00 3. "      DMAIE        ,DMA interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.word 0x00 2. " DMAMODE      ,DMA Transfer mode" "Mode 0,Mode 1"
bitfld.word 0x00 1. "                                    DMA_DIR      ,DMA transfer direction" "Write,Read"
bitfld.word 0x00 0. "         DMA_ENAB     ,DMA transfer enable"  "Disabled,Enabled"
group.long (0x214+0x4)++0x07
line.long 0x00 "CH2_DMA_ADDR_REG,The current memory address of the DMA channel 2"
line.long 0x04 "CH2_DMA_COUNT_REG,The current DMA count of the transfer for DMA channel 2"
group.word 0x224++0x01
line.word 0x00 "CH3_DMA_CTRL_REG,The DMA transfer control for channel 3"
bitfld.word 0x00 9.--10. "     DMA_BRSTM    ,Burst mode" "Bursts of unspecified length,INCR4 or unspecified length,INCR8;INCR4 or unspecified length,INCR16;INCR8;INCR4 or unspecified length"
bitfld.word 0x00 8. "  DMA_ERR      ,Bus error bit" "Not occurred,Occurred"
bitfld.word 0x00 4.--7. "  DMAEP        ,The endpoint number this channel is assigned to" "0,1,2,3,4,?..."
bitfld.word 0x00 3. "      DMAIE        ,DMA interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.word 0x00 2. " DMAMODE      ,DMA Transfer mode" "Mode 0,Mode 1"
bitfld.word 0x00 1. "                                    DMA_DIR      ,DMA transfer direction" "Write,Read"
bitfld.word 0x00 0. "         DMA_ENAB     ,DMA transfer enable"  "Disabled,Enabled"
group.long (0x224+0x4)++0x07
line.long 0x00 "CH3_DMA_ADDR_REG,The current memory address of the DMA channel 3"
line.long 0x04 "CH3_DMA_COUNT_REG,The current DMA count of the transfer for DMA channel 3"
tree.end
tree "Multipoint Control and Status Registers"
group.byte 0x80++0x5
line.byte 0x00 "EP0_TX_FUNC_ADDR_REG,The address of the target function (endpoint0 for transmit)"
hexmask.byte 0x00 0.--6. 1. " TXFUNCADDR        ,Address of target function for transmit endpoint0"
line.byte 0x01 "EP0_TX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x01 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x01 0.--6. 1. "  TX_HUB_ADDR ,Address of this USB 2.0 hub used for transmit"
line.byte 0x02 "EP0_TX_HUB_PORT_REG,Speed of transmit USB 2.0 device"
hexmask.byte 0x02 0.--6. 1. " TXHUBPORT         ,Hub port"
line.byte 0x03 "EP0_RX_FUNC_ADDR_REG,The address of the target function (endpoint0 for receive)"
hexmask.byte 0x01 0.--6. 1. " RXFUNCADDR        ,Address of target function for receive endpoint0"
line.byte 0x04 "EP0_RX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x04 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x04 0.--6. 1. "  RX_HUB_ADDR ,Address of this USB 2.0 hub used for receive"
line.byte 0x05 "EP0_RX_HUB_PORT_REG,Speed of receive USB 2.0 device"
hexmask.byte 0x05 0.--6. 1. " RXHUBPORT         ,Hub port"
group.byte 0x80++0x5
line.byte 0x00 "EP1_TX_FUNC_ADDR_REG,The address of the target function (endpoint0 for transmit)"
hexmask.byte 0x00 0.--6. 1. " TXFUNCADDR        ,Address of target function for transmit endpoint1"
line.byte 0x01 "EP1_TX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x01 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x01 0.--6. 1. "  TX_HUB_ADDR ,Address of this USB 2.0 hub used for transmit"
line.byte 0x02 "EP1_TX_HUB_PORT_REG,Speed of transmit USB 2.0 device"
hexmask.byte 0x02 0.--6. 1. " TXHUBPORT         ,Hub port"
line.byte 0x03 "EP1_RX_FUNC_ADDR_REG,The address of the target function (endpoint0 for receive)"
hexmask.byte 0x01 0.--6. 1. " RXFUNCADDR        ,Address of target function for receive endpoint1"
line.byte 0x04 "EP1_RX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x04 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x04 0.--6. 1. "  RX_HUB_ADDR ,Address of this USB 2.0 hub used for receive"
line.byte 0x05 "EP1_RX_HUB_PORT_REG,Speed of receive USB 2.0 device"
hexmask.byte 0x05 0.--6. 1. " RXHUBPORT         ,Hub port"
group.byte 0x80++0x5
line.byte 0x00 "EP2_TX_FUNC_ADDR_REG,The address of the target function (endpoint0 for transmit)"
hexmask.byte 0x00 0.--6. 1. " TXFUNCADDR        ,Address of target function for transmit endpoint2"
line.byte 0x01 "EP2_TX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x01 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x01 0.--6. 1. "  TX_HUB_ADDR ,Address of this USB 2.0 hub used for transmit"
line.byte 0x02 "EP2_TX_HUB_PORT_REG,Speed of transmit USB 2.0 device"
hexmask.byte 0x02 0.--6. 1. " TXHUBPORT         ,Hub port"
line.byte 0x03 "EP2_RX_FUNC_ADDR_REG,The address of the target function (endpoint0 for receive)"
hexmask.byte 0x01 0.--6. 1. " RXFUNCADDR        ,Address of target function for receive endpoint2"
line.byte 0x04 "EP2_RX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x04 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x04 0.--6. 1. "  RX_HUB_ADDR ,Address of this USB 2.0 hub used for receive"
line.byte 0x05 "EP2_RX_HUB_PORT_REG,Speed of receive USB 2.0 device"
hexmask.byte 0x05 0.--6. 1. " RXHUBPORT         ,Hub port"
group.byte 0x80++0x5
line.byte 0x00 "EP3_TX_FUNC_ADDR_REG,The address of the target function (endpoint0 for transmit)"
hexmask.byte 0x00 0.--6. 1. " TXFUNCADDR        ,Address of target function for transmit endpoint3"
line.byte 0x01 "EP3_TX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x01 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x01 0.--6. 1. "  TX_HUB_ADDR ,Address of this USB 2.0 hub used for transmit"
line.byte 0x02 "EP3_TX_HUB_PORT_REG,Speed of transmit USB 2.0 device"
hexmask.byte 0x02 0.--6. 1. " TXHUBPORT         ,Hub port"
line.byte 0x03 "EP3_RX_FUNC_ADDR_REG,The address of the target function (endpoint0 for receive)"
hexmask.byte 0x01 0.--6. 1. " RXFUNCADDR        ,Address of target function for receive endpoint3"
line.byte 0x04 "EP3_RX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x04 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x04 0.--6. 1. "  RX_HUB_ADDR ,Address of this USB 2.0 hub used for receive"
line.byte 0x05 "EP3_RX_HUB_PORT_REG,Speed of receive USB 2.0 device"
hexmask.byte 0x05 0.--6. 1. " RXHUBPORT         ,Hub port"
group.byte 0x80++0x5
line.byte 0x00 "EP4_TX_FUNC_ADDR_REG,The address of the target function (endpoint0 for transmit)"
hexmask.byte 0x00 0.--6. 1. " TXFUNCADDR        ,Address of target function for transmit endpoint4"
line.byte 0x01 "EP4_TX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x01 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x01 0.--6. 1. "  TX_HUB_ADDR ,Address of this USB 2.0 hub used for transmit"
line.byte 0x02 "EP4_TX_HUB_PORT_REG,Speed of transmit USB 2.0 device"
hexmask.byte 0x02 0.--6. 1. " TXHUBPORT         ,Hub port"
line.byte 0x03 "EP4_RX_FUNC_ADDR_REG,The address of the target function (endpoint0 for receive)"
hexmask.byte 0x01 0.--6. 1. " RXFUNCADDR        ,Address of target function for receive endpoint4"
line.byte 0x04 "EP4_RX_HUB_ADDR_REG,The address of USB 2.0 hub"
bitfld.byte 0x04 7. " MULTI_TRANSLATORS ,Multiple transaction translators" "Single,Multiple"
hexmask.byte 0x04 0.--6. 1. "  RX_HUB_ADDR ,Address of this USB 2.0 hub used for receive"
line.byte 0x05 "EP4_RX_HUB_PORT_REG,Speed of receive USB 2.0 device"
hexmask.byte 0x05 0.--6. 1. " RXHUBPORT         ,Hub port"
tree.end
tree "Link Power Management Registers"
rgroup.word 0x360++0x1
line.word 0x00 "LPM_ATTR_REG,The link power management transaction and sleep cycle"
bitfld.word 0x00 12.--15. " END_PNT  ,The endpoint that is in the token packet of the LPM transaction" "0,1,2,3,4,?..."
bitfld.word 0x00 8. "      RMTWAK   ,The remote wake-up enable bit" "Disabled,Enabled"
bitfld.word 0x00 4.--7. "             HIRD    ,The host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "            LINK_STATE ,The state after the receipt and acceptance of a LPM transaction" "Reserved,Sleep state,?..."
if ((d.l(ad:0x40043000+0x60)&0x4)==0x4)
rgroup.byte 0x362++0x00
line.byte 0x00 "LPM_CTRL_REG,LPM control"
bitfld.byte 0x00 4. " LPMNAK   ,The response to all transactions other than an LPM transaction will be a NAK" "Disabled,Enabled"
bitfld.byte 0x00 2.--3. "      LPMEN    ,Enable LPM in the USB" "Both not supported,Both not supported,Extended transactions supported,Both supported"
bitfld.byte 0x00 1. "  LPMRES  ,Remote wake-up" "No action,Wake-up"
bitfld.byte 0x00 0. "     LPMXMT     ,L1 state upon the next LPM transaction" "Disabled,Enabled"
else
rgroup.byte 0x362++0x00
line.byte 0x00 "LPM_CTRL_REG,LPM control"
bitfld.byte 0x00 1. " LPMRES   ,Remote wake-up from L1 state" "No action,Wake-up"
bitfld.byte 0x00 0. "     LPMXMT   ,Transmition of LPM transaction" "Disabled,Enabled"
endif
rgroup.byte 0x363++0x00
line.byte 0x00 "LPM_INTR_EN_REG,Enable interrupts in LPM_INTR_REG"
bitfld.byte 0x00 5. " LPMERREN ,The LPMERR interrupt enable" "Disabled,Enabled"
bitfld.byte 0x00 4. "      LPMRESEN ,The LPMRES interrupt enable" "Disabled,Enabled"
bitfld.byte 0x00 3. "             LPMNCEN ,The LPMNC interrupt enable" "Disabled,Enabled"
bitfld.byte 0x00 2. "      LPMACKEN   ,The LPMACK interrupt enable" "Disabled,Enabled"
textline "                      "
bitfld.byte 0x00 1. "    LPMNYEN  ,The LPMNY interrupt enable" "Disabled,Enabled"
bitfld.byte 0x00 0. "      LPMSTEN  ,The LPMST interrupt enable" "Disabled,Enabled"
if ((d.l(ad:0x40043000+0x60)&0x4)==0x4)
rgroup.byte 0x364++0x00
line.byte 0x00 "LPM_INTR_REG,LPM power state"
bitfld.byte 0x00 5. " LPMERR   ,LPM transaction is received that has a LinkState field that is not supported" "Not occurred,Occurred"
bitfld.byte 0x00 4. "  LPMRES   ,USB controller has benn resumed for any reason" "Not occurred,Occurred"
bitfld.byte 0x00 3. "         LPMNC   ,LPM transaction is received and the USB responds with a NYET due to data pending" "Not occurred,Occurred"
bitfld.byte 0x00 2. "  LPMACK     ,LPM transaction is received and the USB responds with an ACK" "Not occurred,Occurred"
textline "                      "
bitfld.byte 0x00 1. "    LPMNY    ,LPM transaction is received and the USB responds with a NYET" "Not occurred,Occurred"
bitfld.byte 0x00 0. "  LPMST    ,LPM transaction is received and the USB responds with a STALL" "Not occurred,Occurred"
else
rgroup.byte 0x364++0x00
line.byte 0x00 "LPM_INTR_REG,LPM power state"
bitfld.byte 0x00 5. " LPMERR   ,LPM transaction is received with a bit stuff error or PID error" "Not occurred,Occurred"
bitfld.byte 0x00 4. "  LPMRES   ,USB controller has benn resumed for any reason" "Not occurred,Occurred"
bitfld.byte 0x00 3. "         LPMNC   ,LPM transaction is transmitted and has failed to complete" "Not occurred,Occurred"
bitfld.byte 0x00 2. "  LPMACK     ,LPM transaction is transmitted and the device responds with an ACK" "Not occurred,Occurred"
textline "                      "
bitfld.byte 0x00 1. "    LPMNY    ,LPM transaction is transmitted and the device responds with a NYET" "Not occurred,Occurred"
bitfld.byte 0x00 0. "  LPMST    ,LPM transaction is transmitted and the device responds with a STALL" "Not occurred,Occurred"
endif
rgroup.byte 0x365++0x00
line.byte 0x00 "LPM_FADDR_REG,The function address for the LPM payload"
hexmask.byte 0x00 0.--6. 1. " LPMFADDR ,The LPM function address"
tree.end
width 19.
tree "USB System Registers"
group.long 0x8040++0x3
line.long 0x00 "MASTER_WEIGHT1_CR,The round robin weightage"
bitfld.long 0x00 5.--9. " SW_WEIGHT_USB         ,The round robin weightage for the USB master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8064++0x3
line.long 0x00 "USB_IO_INPUT_SEL_CR,USB data interfaces selection"
bitfld.long 0x00 0.--1. " USB_IO_INPUT_SEL      ,Used to select one of the four USB data interfaces from IOMUXCELLs and I/O pads" "USBA,USBB,USBC,USBD"
group.long 0x807c++0x3
line.long 0x0 "USB_CR,USB Configuration Register"
bitfld.long 0x0 1. " USB_DDR_SELECT        ,USB mode configuration" "SDR,DDR"
bitfld.long 0x0 0. "                                                                                                           USB_UTMI_SEL          ,USB interface configuration" "ULPI PHY,UTMI"
group.long 0x8104++0x3
line.long 0x00 "USB_EDAC_CNT,USB EDAC Count"
hexmask.long.word 0x00 16.--31. 1. " USB_EDAC_CNT_2E       ,16-bit counter that counts the number of 2-bit corrected errors for USB"
hexmask.long.word 0x00 0.--15. 1. "                                                                                                          USB_EDAC_CNT_1E       ,16-bit counter that counts the number of 1-bit corrected errors for USB"
group.long 0x8120++0x3
line.long 0x00 "USB_EDAC_ADR,USB EDAC Address Register"
hexmask.long.word 0x00 13.--25. 2. " USB_EDAC_2E_AD        ,This register stores the address from USB memory on which a 2-bit SECDED error has occurred"
hexmask.long.word 0x00 0.--12. 1. "                                                                                                          USB_EDAC_1E_AD        ,This register stores the address from USB memory on which a1-bit SECDED error has occurred"
group.long 0x8154++0x3
line.long 0x0 "USB_SR,USB Status Register"
bitfld.long 0x0 1. " LPI_CARKIT_EN         ,This bit is asserted when entry is made into CarKit mode and cleared on exit from CarKit mode" "Exit from CarKit,CarKit mode"
bitfld.long 0x0 0. "                                                                                              POWERDN               ,This bit is asserted when CLK may be stopped to save power" "Disabled,Enabled"
group.long 0x8190++0x03
line.long 0x00 "EDAC_SR,EDAC Status Register"
eventfld.long 0x00 13. " CAN_EDAC_2E           ,This status is updated by CAN when a 2-bit SECDED error has been detected for RAM memory" "Not detected,Detected"
eventfld.long 0x00 12. "                                                                                                  CAN_EDAC_1E           ,This status is updated by CAN when a 1-bit SECDED error has been detected and is corrected for RAM memory" "No action,Corrected"
eventfld.long 0x00 11. "                        USB_EDAC_2E           ,This status is updated by USB when a 2-bit SECDED error has been detected for RAM memory" "Not detected,Detected"
textline "                            "
eventfld.long 0x00 10. " USB_EDAC_1E           ,This status is updated by USB when a 1-bit SECDED error has been detected and is corrected for RAM memory" "No action,Corrected"
eventfld.long 0x00 9. "                                                                                                     MAC_EDAC_RX_2E        ,This status is updated by Ethernet when a 2-bit SECDED error has been detected for Rx RAM memory" "No action,Corrected"
eventfld.long 0x00 8. "                        MAC_EDAC_RX_1E        ,This status is updated by Ethernet when a 1-bit SECDED error has been detected and is corrected for Rx RAM memory" "No action,Corrected"
textline "                            "
eventfld.long 0x00 7. " MAC_EDAC_TX_2E        ,This status is updated by Ethernet when a 2-bit SECDED error has been detected for Tx RAM memory" "Not detected,Detected"
eventfld.long 0x00 6. "                                                                                                  MAC_EDAC_TX_E         ,This status is updated by Ethernet when a 1-bit SECDED error has been detected and is corrected for Tx RAM memory" "No action,Corrected"
eventfld.long 0x00 3. "                        ESRAM1_EDAC_2E        ,This status is updated by the eSRAM_1 controller when a 2-bit SECDED error has been detected for eSRAM1 memory" "Not detected,Detected"
textline "                            "
eventfld.long 0x00 2. " ESRAM1_EDAC_1E        ,This status is updated by the eSRAM_1 Controller when a 1-bit SECDED error has been detected and is corrected for eSRAM1" "No action,Corrected"
eventfld.long 0x00 1. "                                                                                                     ESRAM0_EDAC_2E        ,This status is updated by the eSRAM_0 controller when a 2-bit SECDED error has been detected for eSRAM0 memory" "Not detected,Detected"
eventfld.long 0x00 0. "                     ESRAM0_EDAC_1E        ,This status is updated by the eSRAM_0 controller when a 1-bit SECDED error has been detected and is corrected for eSRAM0" "No action,Corrected"
wgroup.long 0x91A4++0x3
line.long 0x00 "CLR_EDAC_COUNTERS,Clear EDAC Counters"
bitfld.long 0x00 13. " CAN_EDAC_CNTCLR_2E    ,This is a pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 2-bit errors" "No action,Clear"
bitfld.long 0x00 12. "                                                                                                     CAN_EDAC_CNTCLR_1E    ,This is a pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 1-bit errors" "No action,Clear"
bitfld.long 0x00 11. "                        USB_EDAC_CNTCLR_2E    ,This is a pulse generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 2-bit errors" "No action,Clear"
textline "                            "
bitfld.long 0x00 10. " USB_EDAC_CNTCLR_1E    ,This is a pulse generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 1-bit errors" "No action,Clear"
bitfld.long 0x00 9. "                                                                                                     MAC_EDAC_RX_CNTCLR_2E ,This is a pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM" "No action,Clear"
bitfld.long 0x00 8. "                        MAC_EDAC_RX_CNTCLR_1E ,This is a pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 1-bit errors" "No action,Clear"
textline "                            "
bitfld.long 0x00 7. " MAC_EDAC_TX_CNTCLR_2E ,This is a pulse generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 2-bit errors" "No action,Clear"
bitfld.long 0x00 6. "                                                                                                     MAC_EDAC_TX_CNTCLR_1E ,This is a pulse generated to clear the 16-bit counter value in Ethernet MAC Tx RAM" "No action,Clear"
bitfld.long 0x00 3. "                        ESRAM1_EDAC_CNTCLR_2E ,This is a pulse generated to clear the 16-bit counter value in ESRAM1 corresponding to the count value of EDAC 2-bit errors" "No action,Clear"
textline "                            "
bitfld.long 0x00 2. " ESRAM1_EDAC_CNTCLR_1E ,This is a pulse generated to clear the 16-bit counter value in eSRAM1 corresponding to count value of EDAC 1-bit errors" "No action,Clear"
bitfld.long 0x00 1. "                                                                                                     ESRAM0_EDAC_CNTCLR_2E ,This is a pulse generated to clear the 16-bit counter value in ESRAM0 corresponding to count value of EDAC 2bit Errors" "No action,Clear"
bitfld.long 0x00 0. "                        ESRAM0_EDAC_CNTCLR_1E ,This is a pulse generated to clear the 16-bit counter value in ESRAM0 corresponding to the count value of EDAC 1-bit errors" "No action,Clear"
tree.end
width 0xb
tree.end
tree "ETH (Ethernet MAC)"
base ad:0x40041000
width 15.
tree "Ethernet MAC M-AHB Registers"
group.long 0x180++0x1b
line.long 0x00 "DMA_TX_CTRL,Transmit control register"
bitfld.long 0x00 0. " TRANSMIT_CONTROL ,Enables DMA transmit packet transfers" "Disabled,Enabled"
line.long 0x04 "DMA_TX_DESC,Pointer to Transmit Descriptor"
hexmask.long 0x04 2.--31. 4. " ADDR_UPPER       ,Descriptor Address"
bitfld.long 0x04 0.--1. "      ADDR_LOWER       ,Ignored by DMA controller" "0,1,2,3"
line.long 0x08 "DMA_TX_STATUS,Transmit Status register"
hexmask.long.byte 0x08 16.--23. 1. " TXPKTCOUNT       ,The 8-bit transmit packet counter"
bitfld.long 0X08 3. "            BUSS_ERROR       ,Host slave split, retry or error response is received by the DMA controller" "No error,Error"
bitfld.long 0x08 1. "      TXUNDERRUN        ,Set whenever the DMA controller reads a '1' for the empty flag in the descriptor" "No action,Underrun"
bitfld.long 0x08 0. "     TXPKTSENT      ,One or more packets have been successfully transferred" "Not transfered,Transfered"
line.long 0x0c "DMA_RX_CTRL,Receive Control register"
bitfld.long 0x0c 0. " RX_ENABLE        ,Enabled DMA receive packet transfers" "Disabled,Enabled"
line.long 0x10 "DMA_RX_DESC,Pointer to Receive Descriptor"
hexmask.long 0x10 1.--31. 2. " ADDR_UPPER       ,Descriptor Address"
bitfld.long 0x10 0. "      ADDR_LOWER       ,Ignored by DMA controller" "0,1"
line.long 0x14 "DMA_RX_STATUS,Receive Status register"
hexmask.long.byte 0x14 16.--23. 1. " RXPKTCOUNT       ,The 8-bit receive packet counter"
bitfld.long 0X14 3. "            BUSS_ERROR       ,Host slave split, retry or error response is received by the DMA controller" "No error,Error"
bitfld.long 0x14 1. "      RXOVERFLOW        ,Receive Overflow" "No overflow,Overflow"
bitfld.long 0x14 0. "   RXPKTRECEIVED  ,One or more packets have been successfully transferred" "Not transfered,Transfered"
line.long 0x18 "DMA_IRQ_MASK,Interrupt Mask register"
bitfld.long 0x18 7. " BUS_ERROR_MASK   ,Enables the BusError bit in the DMARxStatus register as an interrupt source" "Masked,Not masked"
bitfld.long 0x18 6. "    RX_OVERFLOW_MASK ,Setting this bit to 1 enables the RxOverflow bit in the DMARxStatus register as an interrupt source" "Masked,Not masked"
bitfld.long 0x18 4. "    RXPKTRECEIVEDMASK ,Setting this bit to 1 enables the RxPktReceived bit in the DMARxStatus register as an interrupt source" "Masked,Not masked"
bitfld.long 0x18 3. "    BUS_ERROR_MASK ,Setting this bit to 1 enables the BusError bit in the DMATxStatus register as an interrupt source" "Masked,Not masked"
textline "                        "
bitfld.long 0x18 1. " TX_UNDERRUN_MASK ,Setting this bit to 1 enables the TxUnderrun bit in the DMATxStatus register as an interrupt source" "Masked,Not masked"
bitfld.long 0x18 0. "    TXPKTSENTMASK    ,Setting this bit to 1 enables the TxPktSent bit in the DMATxStatus register as an interrupt source" "Masked,Not masked"
rgroup.long 0x19c++0x3
line.long 0x00 "DMA_IRQ,Interrupts register"
bitfld.long 0x00 7. " BUS_ERROR        ,Receive Bus Error interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "  RX_OVERFLOW      ,Rx Overflow interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  RXPKTRECEIVED     ,RxPkt Received interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 3. "  BUS_ERROR      ,Transmit Bus Error interrupt" "No interrupt,Interrupt"
textline "                        "
bitfld.long 0x00 1. " TX_UNDERRUN      ,Tx Underrun interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 0. "  TXPKTSENT        ,Tx Pkt Sent interrupt" "No interrupt,Interrupt"
tree.end
width 18.
tree "Ethernet MAC PE-MCXMAC Registers"
group.long 0x00++0x13
line.long 0x00 "CFG1,MAC Configuration register"
bitfld.long 0x00 31. " SOFT_RESET                      ,Soft Reset" "No reset,Reset"
bitfld.long 0x00 30. "   SIMULATION_RESET             ,Simulation Reset" "No reset,Reset"
bitfld.long 0x00 19. "         RESET_RX_MAC_CONTROL    ,Setting this bit puts the PERMC Receive MAC control in reset" "Not reset,Reset"
bitfld.long 0x00 18. "  RESET_TX_MAC_CONTROL         ,Setting this bit puts the PETMC Transmit MAC control in reset" "Not reset,Reset"
textline "                           "
bitfld.long 0x00 17. " RESET_RX_FUNCTION               ,Setting this bit puts the PERFN receive function block in reset" "Not reset,Reset"
bitfld.long 0x00 16. "  RESET_TX_FUNCTION            ,Setting this bit puts the PETFN transmit function block in reset" "Not reset,Reset"
bitfld.long 0x00 8. "        LOOP_BACK               ,Setting this bit causes the PETFN MAC transmit outputs to be looped back to the MAC receive inputs" "Disabled,Enabled"
bitfld.long 0x00 5. "   RECEIVE_FLOW_CONTROL_ENABLE  ,Setting this bit causes the PERFN receive MAC Control to detect and act on PAUSE flow control frames" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 4. " TRANSMIT_FLOW_CONTROL_ENABLE    ,Setting this bit allows the PETMC transmit MAC Control to send PAUSE flow control frames when requested by the system" "Disabled,Enabled"
rbitfld.long 0x00 3. "   SYNCHRONIZED_RECEIVE_ENABLE  ,Receive Enable is synchronized to the receive stream" "Disabled,Enabled"
bitfld.long 0x00 2. "         RECEIVE_ENABLE          ,Setting this bit allows the MAC to receive frames from the PHY" "Disabled,Enabled"
rbitfld.long 0x00 1. "   SYNCHRONIZED_TRANSMIT_ENABLE ,Transmit Enable is synchronized to the transmit stream" "Disabled,Enabled"
textline "                           "
bitfld.long 0x00 0. " TRANSMIT_ENABLE                 ,Setting this bit allows the MAC to transmit frames from the system" "Disabled,Enabled"
line.long 0x04 "CFG2,MAC Configuration register"
bitfld.long 0x04 12.--15. " PREAMBLE_LENGTH                 ,This field determines the length of the preamble field of the packet in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--9. "         INTERFACE_MODE               ,This field determines the type of interface the MAC is connected to" "Reserved,Nibble mode,Byte mode,?..."
bitfld.long 0x04 5. "      HUGE_FRAME_ENABLE       ,Set this bit to allow frames longer than the MAXIMUM FRAME LENGTH to be transmitted and received" "Disabled,Enabled"
bitfld.long 0x04 4. "   LENGTH_FIELD_CHECKING        ,Set this bit to cause the MAC to check the frames length field to ensure it matches the actual data field length" "Disabled,Enabled"
textline "                           "
bitfld.long 0x04 2. " PAD/CRC_ENABLE                  ,Set this bit to have the MAC pads all the short frames and appends a CRC to every frame whether or not padding is required" "Disabled,Enabled"
bitfld.long 0x04 1. "   CRC_ENABLE                   ,Set this bit to have the MAC appends a CRC to all the frames" "Disabled,Enabled"
bitfld.long 0x04 0. "         FULL-DUPLEX             ,Full-duplex mode" "Disabled,Enabled"
line.long 0x08 "IFG,Inter Packet gap and Inter Frame gap register"
hexmask.long.byte 0x08 24.--30. 1. " NBACK_TOBACK_INTERPACKETGAP1    ,This programmable field represents the optional carrier Sense window"
hexmask.long.byte 0x08 16.--22. 1. "         NBACK_TOBACK_INTERPACKETGAP2 ,This programmable field represents the Non-Back-to-Back Inter-Packet-Gap in the bit times, which represent the minimum interpacket gap (IPG) of 96 bits"
hexmask.long.byte 0x08 8.--15. 1. "               MIN_IFG_ENF             ,This programmable field represents the minimum size of inter frame gap (IFG) to enforce between frames"
hexmask.long.byte 0x08 0.--6. 1. "         BACKTOBACK_INTERPACKET_GAP   ,This programmable field represents the IPG between Backto- Back packets"
line.long 0x0c "HALF_DUPLEX,Definition of half duplex register"
bitfld.long 0x0C 20.--23. " ALTERNATE_BIN_EXP_BACKOFF_TRUNC ,This field is used when ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 19. "         ALTERNATE_BIN_EXP_BACKOFF_EN ,Setting this bit configures the Tx MAC to use the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting instead of the 802.3 standard tenth collision" "Disabled,Enabled"
bitfld.long 0x0C 18. "         BACKPRESSURE_NO_BACKOFF ,Setting this bit configures the Tx MAC to immediately retransmit following a collision during backpressure operation" "Disabled,Enabled"
bitfld.long 0x0C 17. "   NO_BACKOFF                   ,Setting this bit configures the Tx MAC to immediately retransmit following a collision" "Disabled,Enabled"
textline "                           "
bitfld.long 0x0C 16. " EXCESSIVE_DEFER                 ,Setting this bit configures the Tx MAC to allow the transmission of a packet that has been excessively deferred" "Disabled,Enabled"
bitfld.long 0x0C 12.--15. "   RETRANSMISSION_MAXIMUM       ,This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--9. 1. "               COLLISION_WINDOW        ,This programmable field represents the slot time or collision window during which collisions might occur in a properly configured network"
line.long 0x10 "MAX_FRAME_LENGTH,Sets the maximum frame size in both transmit and receive directions"
hexmask.long.word 0x10 0.--15. 1. " MAX_FRAME_LENGTH                ,This programmable field sets the maximum frame size"
group.long 0x1c++0xf
line.long 0x00 "TEST,This test bit is used to predict back off times in Half-duplex mode"
bitfld.long 0x00 3. " MAX_FRAME_LENGTH                ,Setting this bit causes the MAC to backoff for the maximum possible length of time" "Disabled,Enabled"
bitfld.long 0x00 2. "   REG_TR_FLOW_EN               ,Registered transmit half-duplex flow enable" "Disabled,Enabled"
bitfld.long 0x00 1. "         TEST_PAUSE              ,Setting this bit allows the MAC to be paused via the host interface for the testing purposes" "Disabled,Enabled"
bitfld.long 0x00 0. "   SHORTC_SLOT_TIME             ,This bit allows the slot time counter to expire regardless of the current count" "Disabled,Enabled"
line.long 0x04 "MII_CONFIG,MII configuration"
bitfld.long 0x04 31. " RESET_MII_MGMT                  ,Setting this bit resets MII Mgmt" "No action,Reset"
bitfld.long 0x04 5. "  SCAN_AUTO_INCREMENT          ,Setting this bit causes MII Mgmt to continually read from a set of PHYs of contiguous address space" "No action,Scan"
bitfld.long 0x04 4. "        PREAMBLE_SUPPRESSION    ,Setting this bit causes MII Mgmt to suppress preamble generation and reduce the Mgmt cycle from 64 clocks to 32 clocks" "Disabled,Enabled"
bitfld.long 0x04 0.--2. "   MGMT_CLOCK_SELECT            ,This field determines the clock frequency of the Management Data clock" "/4,/4,/6,/8,/10,/14,/20,/28"
line.long 0x08 "MII_COMMAND,MONITERS link fails"
bitfld.long 0x08 1. " SCAN_CYCLE                      ,This bit causes MII Mgmt to perform Read cycles continuously" "Disabled,Enabled"
bitfld.long 0x08 0. "   READ_CYCLE                   ,This bit causes MII Mgmt to perform a single Read cycle" "Disabled,Enabled"
line.long 0x0c "MII_ADDRESS,This represents 5-bit PHY address field and 5 bit register address field"
bitfld.long 0x0c 8.--12. " PHY_ADDRESS                     ,This field represents the 5-bit PHY address field used in Mgmt cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0c 0.--4. "         REG_ADR                      ,This field represents the 5-bit register address field of Mgmt cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x2c++0x3
line.long 0x00 "MII_CTRL,Control register for MII Mgmt write cycle"
hexmask.long.word 0x00 0.--15. 1. " MII_MGMT_CONTROL                ,When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and register addresses"
rgroup.long 0x30++0x7
line.long 0x00 "MII_STATUS,Following an MII Mgmt read cycle, the 16-bit data"
hexmask.long.word 0x00 0.--15. 1. " MII_MGMT_STATUS                 ,Following an MII Mgmt read cycle, the 16-bit data can be read from this location"
line.long 0x04 "MII_INDICATORS,This indicates MII Mgmt block is currently performing an MII Mgmt read or write cycle"
bitfld.long 0x04 2. " NOT_VALID                       ,Read Data not validated" "Valid,Not valid"
bitfld.long 0x04 1. "  SCANNING                     ,Scan operation is in progress" "Not in progress,In progress"
bitfld.long 0x04 0. "  BUSY                    , MII Mgmt block busy" "Not busy,Busy"
group.long 0x38++0x3
line.long 0x00 "INTERFACE_CTRL,This configures PERMII for 10 Mbps or 100 Mbps speed"
bitfld.long 0x00 31. " RESET_INTERFACE_MODULE          ,Setting this bit resets the interface module" "Not reset,Reset"
bitfld.long 0x00 27. "  TBIMODE                      ,Setting this bit configures the A-RGMII module to expect TBI signals at the GMII interface" "No effect,TBI"
bitfld.long 0x00 26. "        GHDMODE                 ,Setting this bit configures the A-RGMII module to expect half-duplex GMII at the GMII interface" "No effect,GMII"
bitfld.long 0x00 25. "  LHDMODE                      ,Setting this bit configures the A-RGMII module to expect 10 or 100 half duplex MII at the GMII interface" "10,100"
textline "                           "
bitfld.long 0x00 24. " PHY_MODE                        ,Setting this bit configures the PESMII serial MII module to be in PHY mode" "MAC,PHY"
bitfld.long 0x00 23. "        RESET_PERMII                 ,Setting this bit resets the PERMII module. Clearing this bit allows for normal operation" "Not reset,Reset"
bitfld.long 0x00 16. "        SPEED                   ,This bit configures the PERMII Reduced MII module with the current operating speed" "10 Mbps,100 Mbps"
bitfld.long 0x00 15. "   RESET_PE100X                 ,This bit resets the 4B/5B symbol encipher/decipher logic" "Not reset,Reset"
textline "                           "
bitfld.long 0x00 10. " FORCE_QUIET                     ,When enabled, the transmit data is cleared which allows the contents of the cipher to be the output" "Disabled,Enabled"
bitfld.long 0x00 9. "   NO_CIPHER                    ,When enabled, the raw transmit 5B symbols are transmitted without ciphering" "Disabled,Enabled"
bitfld.long 0x00 8. "         DISABLE_LINK_FAIL       ,When enabled, the 330ms Link Fail timer is disabled allowing shorter simulations" "No,Yes"
bitfld.long 0x00 0. "        ENABLE_JABBER_PROTECTION     ,This bit enables the jabber protection logic" "Disabled,Enabled"
hgroup.long 0x3c++0x3
hide.long 0x00 "INTERFACE_STATUS,This indicates the serial MII PHY has detected a jabber condition on the link"
in
group.long 0x40++0x7
line.long 0x00 "STATION_ADDRESS1,The register fields hold the station address"
hexmask.long.byte 0x00 24.--31. 1. " STATION_ADDR1                   ,This field holds the fIRST octet of the station address"
hexmask.long.byte 0x00 16.--23. 1. "         STATION_ADDR2                ,This field holds the SECOND octet of the station address"
hexmask.long.byte 0x00 8.--15. 1. "               STATION_ADDR3           ,This field holds the third octet of the station address"
hexmask.long.byte 0x00 0.--7. 1. "         STATION_ADDR4                ,This field holds the fourth octet of the station address"
line.long 0x04 "STATION_ADDRESS2,The register fields hold the station address"
hexmask.long.byte 0x04 24.--31. 1. " STATION_ADDR5                   ,This field holds the fifth octet of the station address"
hexmask.long.byte 0x04 16.--23. 1. "         STATION_ADDR6                ,This field holds the sixth octet of the station address"
group.long 0x48++0x17
line.long 0x0 "FIFO_CFG0,Definition of A-MCXFIFO configuration register 0"
rbitfld.long 0x0 20. " FTFENRPLY  ,FIFO transmit interface enabled" "Disabled,Enabled"
rbitfld.long 0x0 19. "     STFENRPLY  ,FIFO PE-MCXMAC transmit interface module enabled" "Disabled,Enabled"
rbitfld.long 0x0 18. "      FRFENRPLY    ,FIFO receive interface module enabled" "Disabled,Enabled"
rbitfld.long 0x0 17. "     SRFENRPLY  ,FIFO PE-MCXMAC receive interface module enabled" "Disabled,Enabled"
textline "                           "
bitfld.long 0x0 16. " WTMENRPLY  ,FIFO PE-MCXMAC watermark module enabled" "Disabled,Enabled"
bitfld.long 0x0 12. "     FTFENREQ   ,FIFO fabric transmit interface module enabled" "Disabled,Enabled"
bitfld.long 0x0 11. "      STFENREQ     ,When asserted, this bit requests for enabling the FIFO PE-MCXMAC transmit interface module" "Disabled,Enabled"
bitfld.long 0x0 10. "     FRFENREQ   ,When asserted, this bit requests for enabling the FIFO fabric receive interface module" "Disabled,Enabled"
textline "                           "
bitfld.long 0x0 9. " SRFENREQ   ,FIFO PE-MCXMAC receive interface module enabled" "Disabled,Enabled"
bitfld.long 0x0 8. "     WTMENREQ   ,FIFO PE-MCXMAC Watermark module enabled" "Disabled,Enabled"
bitfld.long 0x0 4. "      HSTRSTFT     ,FIFO Fabric transmit interface module is in reset" "Not reset,Reset"
bitfld.long 0x0 3. "    HSTRSTST   ,FIFO PE-MCXMAC transmit interface module is in reset" "Not reset,Reset"
textline "                           "
bitfld.long 0x0 2. " HSTRSTFR   ,FIFO Fabric receive interface module is in reset" "Not reset,Reset"
bitfld.long 0x0 1. "    HSTRSTSR   ,FIFO PE-MCXMAC receive interface module is in reset" "Not reset,Reset"
bitfld.long 0x0 0. "     HSTRSTWT     ,FIFO PE-MCXMAC watermark module is in reset" "Not reset,Reset"
line.long 0x4 "FIFO_CFG1,Definition of A-MCXFIFO configuration register 1"
hexmask.long.word 0x4 16.--27. 1. " CFGSRTH    ,The minimum number of 4 byte locations simultaneously stored in the receive RAM"
hexmask.long.word 0x4 0.--15. 1. "         CFGXOFFRTX ,The number of pause quanta after an XOFF pause frame is acknowledged, until the A-MCXFIFO re-asserts pause"
line.long 0x8 "FIFO_CFG2,Definition of A-MCXFIFO configuration register 2"
hexmask.long.word 0x8 16.--28. 1.  " CFGLWM     ,TThe minimum number of 4 byte words that are simultaneously stored in the receive RAM before transmit flow control enabled"
line.long 0xC "FIFO_CFG3,Definition of A-MCXFIFO configuration register 3"
hexmask.long.word 0xC 16.--27. 1. " CFGHWMFT   ,The maximum number of 4 byte locations simultaneously stored in the transmit RAM before the fthwm is asserted"
hexmask.long.word 0xC 0.--11. 1. "         CFGFTTH    ,The minimum number of locations simultaneously stored in the transmit RAM, relative to the beginning of the frame being input"
line.long 0x10 "FIFO_CFG4,Definition of A-MCXFIFO configuration register 4"
bitfld.long 0x10 17. " RLE        ,Receive long event" "Not ignored,Ignored"
bitfld.long 0x10 16. "  VLAN       ,VLAN Tagged frame" "Not ignored,Ignored"
bitfld.long 0x10 15. "   CONTROLF     ,Frame was a Control frame other than PAUSE" "Not ignored,Ignored"
bitfld.long 0x10 14. "  PAUSEF     ,Frame was a PAUSE Control frame" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x10 13. " CONTROL    ,Frame was a Control frame" "Not ignored,Ignored"
bitfld.long 0x10 12. "  TRUNF      ,Frame was truncated" "Not ignored,Ignored"
bitfld.long 0x10 11. "   LONGEV       ,Long Event detected" "Not ignored,Ignored"
bitfld.long 0x10 10. "  DRINIB     ,Frame contained a dribble nibble" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x10 9. " BROADD     ,Broadcast Address Detected" "Not ignored,Ignored"
bitfld.long 0x10 8. "  MULTADD    ,Multicast Address Detected" "Not ignored,Ignored"
bitfld.long 0x10 7. "   REC          ,Reception OK" "Not ignored,Ignored"
bitfld.long 0x10 6. "  TYPE       ,Length/Type field was neither a Length nor Type" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x10 5. " LENGTH     ,Frames length field did not match actual data field length" "Not ignored,Ignored"
bitfld.long 0x10 4. "  CRC        ,Frame contained a valid CRC" "Not ignored,Ignored"
bitfld.long 0x10 3. "   RECERR       ,Frame contained a Receive Error" "Not ignored,Ignored"
bitfld.long 0x10 2. "  FALCARR    ,False Carrier previously seen" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x10 1. " RXDVEV     ,RX_DV Event previously seen" "Not ignored,Ignored"
bitfld.long 0x10 0. "  PRPACK     ,Whether or not a prior packet was dropped" "Not ignored,Ignored"
line.long 0x14 "FIFO_CFG5,Definition of A-MCXFIFO configuration register 5"
bitfld.long 0x14 22. " CFGHDPLX   ,The A-MCXFIFO to enable the half duplex as a flow control mechanism configuration" "Disabled,Enabled"
rbitfld.long 0x14 21. "     SRFULL     ,The maximum capacity of the receive FIFO storage is met or exceeded" "Not occurred,Occurred"
bitfld.long 0x14 20. "  HSTSRFULLCLR ,This bit should be written when it is desired to clear the srfull indicator bit" "No effect,Clear"
bitfld.long 0x14 19. "    CFGBYTMODE ,This bit should be asserted when the PE-MCXMAC is configured for GMII mode" "No effect,GMII mode"
textline "                           "
bitfld.long 0x14 18. " HSTDRPLT64 ,Setting this bit causes the frame to be dropped if a receive frame is less than 64 bytes in length" "No effect,Set"
bitfld.long 0x14 17. "    RLE        ,Receive long event" "Not ignored,Ignored"
bitfld.long 0x14 16. "   VLAN         ,VLAN Tagged frame" "Not ignored,Ignored"
bitfld.long 0x14 15. "  CONTROLF   ,Frame was a Control frame other than PAUSE" "Not ignored,Ignored"
bitfld.long 0x14 14. "  PAUSEF ,Frame was a PAUSE Control frame" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x14 13. " CONTROL    ,Frame was a Control frame" "Not ignored,Ignored"
bitfld.long 0x14 12. "  TRUNF      ,Frame was truncated" "Not ignored,Ignored"
bitfld.long 0x14 11. "   LONGEV       ,Long Event detected" "Not ignored,Ignored"
bitfld.long 0x14 10. "  DRINIB     ,Frame contained a dribble nibble" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x14 9. " BROADD     ,Broadcast Address Detected" "Not ignored,Ignored"
bitfld.long 0x14 8. "  MULTADD    ,Multicast Address Detected" "Not ignored,Ignored"
bitfld.long 0x14 7. "   REC          ,Reception OK" "Not ignored,Ignored"
bitfld.long 0x14 6. "  TYPE       ,Length/Type field was neither a Length nor Type" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x14 5. " LENGTH     ,Frames length field did not match actual data field length" "Not ignored,Ignored"
bitfld.long 0x14 4. "  CRC        ,Frame contained a valid CRC" "Not ignored,Ignored"
bitfld.long 0x14 3. "   RECERR       ,Frame contained a Receive Error" "Not ignored,Ignored"
bitfld.long 0x14 2. "  FALCARR    ,False Carrier previously seen" "Not ignored,Ignored"
textline "                           "
bitfld.long 0x14 1. " RXDVEV     ,RX_DV Event previously seen" "Not ignored,Ignored"
bitfld.long 0x14 0. "  PRPACK     ,Whether or not a prior packet was dropped" "Not ignored,Ignored"
group.long 0x60++0x1F
line.long 0x0 "FIFO_RAM_ACCESS0,The FIFO RAM access register 0 is intended for nonreal-time RAM testing and debug"
bitfld.long 0x0 31. " HSTTRAMWREQ ,Host transmit RAM write request" "0,1"
bitfld.long 0x0 30. "  HSTTRAMWACK ,Host transmit RAM write acknowledge" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "  HSTTRAMWDAT ,Host transmit RAM write data"
hexmask.long.word 0x0 0.--12. 1. "  HSTTRAMWADX ,Host transmit RAM write address"
line.long 0x4 "FIFO_RAM_ACCESS1,The FIFO RAM access register 1 is intended for nonreal-time RAM testing and debug"
line.long 0x8 "FIFO_RAM_ACCESS2,The FIFO RAM access register 2 is intended for nonreal-time RAM testing and debug"
bitfld.long 0x8 31. " HSTTRAMRREQ ,Host transmit RAM read request" "0,1"
bitfld.long 0x8 30. "  HSTTRAMRACK ,Host transmit RAM read acknowledge" "0,1"
hexmask.long.byte 0x8 16.--23. 1. "  HSTTRAMRDAT ,Host transmit RAM read data"
hexmask.long.word 0x8 0.--12. 1. "  HSTTRAMRADX ,Host transmit RAM read address"
line.long 0xC "FIFO_RAM_ACCESS3,The FIFO RAM access register 3 is intended for nonreal-time RAM testing and debug"
line.long 0x10 "FIFO_RAM_ACCESS4,The FIFO RAM access register 4 is intended for nonreal-time RAM testing and debug"
bitfld.long 0x10 31. " HSTRRAMWREQ ,Host receive RAM write request" "0,1"
bitfld.long 0x10 30. "  HSTRRAMWACK ,Host receive RAM write acknowledge" "0,1"
hexmask.long.byte 0x10 16.--23. 1. "  HSTRRAMWDAT ,Host receive RAM write data"
hexmask.long.word 0x10 0.--13. 1. "  HSTTRAMWADX ,Host receive RAM write address"
line.long 0x14 "FIFO_RAM_ACCESS5,The FIFO RAM access register 5 is intended for nonreal-time RAM testing and debug"
line.long 0x18 "FIFO_RAM_ACCESS6,The FIFO RAM access register 6 is intended for nonreal-time RAM testing and debug"
bitfld.long 0x18 31. " HSTRRAMRREQ ,Host receive RAM read request" "0,1"
bitfld.long 0x18 30. "  HSTRRAMRACK ,Host receive RAM read acknowledge" "0,1"
hexmask.long.byte 0x18 16.--23. 1. "  HSTRRAMRDAT ,Host receive RAM read data"
hexmask.long.word 0x18 0.--13. 1. "  HSTRRAMRADX ,Host receive RAM read address"
line.long 0x1C "FIFO_RAM_ACCESS7,The FIFO RAM access register 7 is intended for nonreal-time RAM testing and debug"
tree.end
width 7.
tree "Ethernet MAC PE-MSTAT Transmit and Receive counters Registers"
group.long 0x80++0x1b
line.long 0x00 "TR64,Transmit and Receive 64 byte frame counter"
hexmask.long.tbyte 0x00 0.--17. 1. " TR64  ,Transmit and Receive 64 byte frame counter"
line.long 0x04 "TR127,Transmit and Receive 65 to127 byte frame counter"
hexmask.long.tbyte 0x04 0.--17. 1. " TR127 ,Transmit and Receive 65 to 127 byte frame counter"
line.long 0x08 "TR255,Transmit and Receive 128 to 255 byte frame counter"
hexmask.long.tbyte 0x08 0.--17. 1. " TR225 ,Transmit and Receive 128 to 255 byte frame counter"
line.long 0x0c "TR511,Transmit and Receive 256 to 511 byte frame counter"
hexmask.long.tbyte 0x0c 0.--17. 1. " TR511 ,Transmit and Receive 256 to 511 byte frame counter"
line.long 0x10 "TR1K,Transmit and Receive 512 to 1023 byte frame counter"
hexmask.long.tbyte 0x10 0.--17. 1. " TR1K  ,Transmit and Receive 512 to 1023 byte frame counter"
line.long 0x14 "TRMAX,Transmit and Receive 1024 to 1518 byte frame counter"
hexmask.long.tbyte 0x14 0.--17. 1. " TRMAX ,Transmit and Receive 1024 to 1518 Byte Frame Counter"
line.long 0x18 "TRMGV,Transmit and Receive 1519 to 1522 byte good VLAN frame counter"
hexmask.long.tbyte 0x18 0.--17. 1. " TRMGV ,Transmit and Receive 1519 to 1522 Byte VLAN Frame Counter"
tree.end
width 6.
tree "Ethernet MAC PE-MSTAT Receive counters Register Map"
group.long 0x9c++0x93
line.long 0x00 "RBYT,The statistic counter register is incremented by the byte count of all frames received"
hexmask.long.tbyte 0x00 0.--23. 1. " RBYT  ,Receive Byte Counter"
line.long 0x04 "RPKT,Incremented for each frame received packet"
hexmask.long.tbyte 0x04 0.--17. 1. " RPKT  ,Receive packet counter"
line.long 0x08 "RFCS,This is incremented for each frame received that has an integral 64 to 1518 length and contains a frame check sequence error"
hexmask.long.word 0x08 0.--11. 1. " RFCS  ,Receive FCS error counter"
line.long 0x0c "RMCA,This is incremented for each multicast good frame of lengths smaller than 1518 (non VLAN) or 1522 (VLAN) excluding broadcast frames"
hexmask.long.tbyte 0x0c 0.--17. 1. " RMAC  ,Receive multicast packet counter"
line.long 0x10 "RBCA,This is incremented for each broadcast good frame of lengths smaller than 1518 (non VLAN) or 1522 (VLAN) excluding broadcast frames"
hexmask.long.tbyte 0x10 0.--21. 1. " RBCA  ,Receive broadcast packet counter"
line.long 0x14 "RXCF,This is incremented for each MAC control frame received"
hexmask.long.tbyte 0x14 0.--17. 1. " RXCF  ,Receive control frame packet counter"
line.long 0x18 "RXPF,This is incremented each time a valid PAUSE MAC control frame is received"
hexmask.long.word 0x18 0.--11. 1. " RXPF  ,Receive PAUSE frame packet counter"
line.long 0x1c "RXUO,This is incremented each time a MAC control frame is received which contains an op code other than a PAUSE"
hexmask.long.word 0x1C 0.--11. 1. " RXUO  ,Receive unknown OP code counter"
line.long 0x20 "RALN,This is incremented for each received frame from 64 to 1518"
hexmask.long.word 0x20 0.--11. 1. " RALN  ,Receive alignment error counter"
line.long 0x24 "RFLR,This is incremented for each frame received in which the 802.3 length field does not match the number of data bytes actually received"
hexmask.long.word 0x24 0.--15. 1. " RFLR  ,Receive frame length error counter"
line.long 0x28 "RCDE,This is incremented each time a valid carrier is present and at least one invalid data symbol is detected"
hexmask.long.word 0x28 0.--11. 1. " RCDE  ,Receive code error counter"
line.long 0x2c "RCSE,This is incremented each time a false carrier is detected"
hexmask.long.word 0x2C 0.--11. 1. " RCSE  ,Receive false carrier counter"
line.long 0x30 "RUND,This is incremented each time a frame is received, which is less than 64 bytes in length and contains a valid frame check sequence (FCS)"
hexmask.long.word 0x30 0.--11. 1. " RUND  ,Receive undersize packet counter"
line.long 0x34 "ROVR,This is incremented each time a frame is received which exceeds1518 (non VLAN) or 1522 (VLAN) bytes and contains a valid FCS"
hexmask.long.word 0x34 0.--11. 1. " ROVR  ,Receive oversize packet counter"
line.long 0x38 "RFRG,This is incremented for each frame received which is less than 64 bytes in length and contains an invalid FCS"
hexmask.long.word 0x38 0.--11. 1. " RFRG  ,Receive fragments counter"
line.long 0x3c "RJBR,This is incremented for frames received which exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contains an invalid FCS"
hexmask.long.word 0x3C 0.--11. 1. " RJBR  ,Receive jabber counter"
line.long 0x40 "RDRP,This is incremented for frames received which are streamed to system but are later dropped due to lack of system resources"
hexmask.long.word 0x40 0.--11. 1. " RDRP  ,Receive dropped packets counter"
line.long 0x44 "TBYT,This is incremented for each transmitted byte including fragments of frames which are involved in collisions"
hexmask.long.tbyte 0x44 0.--23. 1. " TBYT  ,Transmit byte counter"
line.long 0x48 "TPKT,This is incremented for each transmitted packet"
hexmask.long.tbyte 0x48 0.--23. 1. " TPKT  ,Transmit packet counter"
line.long 0x4c "TMCA,This is incremented for each transmitted Multicast valid frame"
hexmask.long.tbyte 0x4C 0.--17. 1. " TPKT  ,Transmit packet counter"
line.long 0x50 "TBCA,This is incremented for each transmitted Broadcast frame"
hexmask.long.tbyte 0x50 0.--17. 1. " TBCA  ,Transmit broadcast packet counter"
line.long 0x54 "TXPF,This is incremented each time a valid PAUSE MAC control frame is transmitted"
hexmask.long.word 0x54 0.--11. 1. " TXPF  ,Transmit PAUSE frame packet counter"
line.long 0x58 "TDFR,This incremented for each frame, which is deferred on its first transmission attempt"
hexmask.long.word 0x58 0.--11. 1. " TDFR  ,Transmit deferral packet counter"
line.long 0x5c "TEDF,This is incremented for aborted frames, which are deferred for an excessive period of time"
hexmask.long.word 0x5C 0.--11. 1. " TEDF  ,Transmit excessive deferral packet counter"
line.long 0x60 "TSCL,This is incremented for each transmitted frame that experiences exactly one collision during the transmission"
hexmask.long.word 0x60 0.--11. 1. " TSCL  ,Transmit single collision packet counter"
line.long 0x64 "TMCL,This is incremented for each transmitted frame that experiences 2 to 15 collisions during the transmission"
hexmask.long.word 0x64 0.--11. 1. " TMCL  ,Transmit multiple collision packet counter"
line.long 0x68 "TLCL,This is incremented for each transmitted frame which experiences a late collision during a transmission attempt"
hexmask.long.word 0x68 0.--11. 1. " TLCL  ,Transmit late collision packet counter"
line.long 0x6c "TXCL,This is incremented for each frame that experiences 16 collisions during the transmission and is aborted"
hexmask.long.word 0x6C 0.--11. 1. " TXCL  ,Transmit excessive collision packet counter"
line.long 0x70 "TNCL,This is incremented by the number of collisions experienced during the transmission of a frame"
hexmask.long.word 0x70 0.--12. 1. " TNCL  ,Transmit total collision counter"
line.long 0x74 "TPFH,This is incremented each time a valid PAUSE MAC Control frame is transmitted and honored"
hexmask.long.word 0x74 0.--11. 1. " TPFH  ,Transmit PAUSE frames honored counter"
line.long 0x78 "TDRP,This is incremented each time PAUSE frame is honored"
hexmask.long.word 0x78 0.--11. 1. " TDRP  ,Transmit Drop Frame Counter"
line.long 0x7c "TJBR,This is incremented for each oversized transmitted frame with an incorrect FCS value"
hexmask.long.word 0x7C 0.--11. 1. " TJBR  ,Transmit jabber frame counter"
line.long 0x80 "TFCS,This is incremented for each valid sized packet with an incorrect FCS value"
hexmask.long.word 0x80 0.--11. 1. " TFCS  ,Transmit FCS Error Counter"
line.long 0x84 "TXCF,This is incremented for each valid size frame with a Type Field signifying a Control frame"
hexmask.long.word 0x84 0.--11. 1. " TXCS  ,Transmit control frame counter"
line.long 0x88 "TOVR,This is incremented for each oversized transmitted frame with a correct FCS value"
hexmask.long.word 0x88 0.--11. 1. " TOVR  ,Transmit oversize frame counter"
line.long 0x8c "TUND,This is incremented for each frame which is less than 64 bytes with a correct FCS value"
hexmask.long.word 0x8C 0.--11. 1. " TUND  ,Transmit undersize frame counter"
line.long 0x90 "TFRG,This is incremented for each frame which is less than 64 bytes, with an incorrect FCS value"
hexmask.long.word 0x90 0.--11. 1. " TFRG  ,Transmit fragment counter"
rgroup.long 0x94++0x7
line.long 0x00 "CAR1,Carry register 1"
bitfld.long 0x00 31. " C164  , TR64 counter carry bit" "0,1"
bitfld.long 0x00 30. "           C1127 , TR127 counter carry bit" "0,1"
bitfld.long 0x00 29. "           C1255 , TR255 counter carry bit" "0,1"
bitfld.long 0x00 28. "           C1511 , TR511 counter carry bit" "0,1"
bitfld.long 0x00 27. "  C11K , TR1K counter carry bit" "0,1"
textline "               "
bitfld.long 0x00 26. " C1MAX , TRMAX counter carry bit" "0,1"
bitfld.long 0x00 25. "           C1MGV , TRMGV counter carry bit" "0,1"
bitfld.long 0x00 16. "           C1RBY , RBYT counter carry bit" "0,1"
bitfld.long 0x00 15. "           C1RPK , RPKT counter carry bit" "0,1"
bitfld.long 0x00 14. "  C1RFC , RFCS counter carry bit" "0,1"
textline "               "
bitfld.long 0x00 13. " C1RMC , RMCA counter carry bit" "0,1"
bitfld.long 0x00 12. "           C1RBC , RBCA counter carry bit" "0,1"
bitfld.long 0x00 11. "           C1RXC , RXCF counter carry bit" "0,1"
bitfld.long 0x00 10. "           C1RXP , RXPF counter carry bit" "0,1"
bitfld.long 0x00 9. "  C1RXU , RXUO counter carry bit" "0,1"
textline "               "
bitfld.long 0x00 8. " C1RAL , RALN counter carry bit" "0,1"
bitfld.long 0x00 7. "           C1RFL , RFLR counter carry bit" "0,1"
bitfld.long 0x00 6. "           C1RCD , RCDE counter carry bit" "0,1"
bitfld.long 0x00 5. "           C1RCS , RCSE counter carry bit" "0,1"
bitfld.long 0x00 4. "  C1RUN , RUND counter carry bit" "0,1"
textline "               "
bitfld.long 0x00 3. " C1ROV , ROVR counter carry bit" "0,1"
bitfld.long 0x00 2. "           C1RFR , RFRG counter carry bit" "0,1"
bitfld.long 0x00 1. "           C1RJB , RJBR counter carry bit" "0,1"
bitfld.long 0x00 0. "           C1RDR , RDRP counter carry bit" "0,1"
line.long 0x04 "CAR2,Carry register 2"
bitfld.long 0x04 19. " C2TJB , TJBR counter carry bit" "0,1"
bitfld.long 0x04 18. "           C2TFC , TXFC counter carry bit" "0,1"
bitfld.long 0x04 17. "           C2TCF , TXCF counter carry bit" "0,1"
bitfld.long 0x04 16. "           C2TOV , TOVR counter carry bit" "0,1"
bitfld.long 0x04 15. "  C2TUN , TUND counter carry bit" "0,1"
textline "               "
bitfld.long 0x04 14. " C2TFG , TFRG counter carry bit" "0,1"
bitfld.long 0x04 13. "           C2TBY , TBYT counter carry bit" "0,1"
bitfld.long 0x04 12. "           C2TPK , TPKT counter carry bit" "0,1"
bitfld.long 0x04 11. "           C2TMC , TMCA counter carry bit" "0,1"
bitfld.long 0x04 10. "  C2TBC , TBCA counter carry bit" "0,1"
textline "               "
bitfld.long 0x04 9. " C2TPF , TXPF counter carry bit" "0,1"
bitfld.long 0x04 8. "           C2TDF , TDFR counter carry bit" "0,1"
bitfld.long 0x04 7. "           C2TED , TEDF counter carry bit" "0,1"
bitfld.long 0x04 6. "           C2TSC , TSCL counter carry bit" "0,1"
bitfld.long 0x04 5. "  C2TMA , TMCL counter carry bit" "0,1"
textline "               "
bitfld.long 0x04 4. " C2TLC , TLCL counter carry bit" "0,1"
bitfld.long 0x04 3. "           C2TXC , TXCL counter carry bit" "0,1"
bitfld.long 0x04 2. "           C2TNC , TNCL counter carry bit" "0,1"
bitfld.long 0x04 1. "           C2TPH , TPFH counter carry bit" "0,1"
bitfld.long 0x04 0. "  C2TDP , TDRP counter carry bit" "0,1"
group.long 0x9c++0x7
line.long 0x0 "CAM1,Counter Carry Mask Register 1"
bitfld.long 0x0 31. " M164  ,Mask register 1 TR64 counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 30. "    M1127 ,Mask register 1 TR127 counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 29. "    M1255 ,Mask register 1 TR255 counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 28. "    M1511 ,Mask register 1 TR511 counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 27. "  M11K ,Mask register 1 TR1K counter carry bit" "Unmaskek,Masked"
textline "               "
bitfld.long 0x0 26. " M1MAX ,Mask register 1 TRMAX counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 25. "    M1MGV ,Mask register 1 TRMGV counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 16. "    M1RBY ,Mask register 1 RBYT counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 15. "    M1RPK ,Mask register 1 RPKT counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 14. "  M1RFC ,Mask register 1 RFCS counter carry bit" "Unmaskek,Masked"
textline "               "
bitfld.long 0x0 13. " M1RMC ,Mask register 1 RMCA counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 12. "    M1RBC ,Mask register 1 RBCA counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 11. "    M1RXC ,Mask register 1 RXCF counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 10. "    M1RXP ,Mask register 1 RXPF counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 9. "  M1RXU ,Mask register 1 RXUO counter carry bit" "Unmaskek,Masked"
textline "               "
bitfld.long 0x0 8. " M1RAL ,Mask register 1 RALN counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 7. "    M1RFL ,Mask register 1 RFLR counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 6. "    M1RCD ,Mask register 1 RCDE counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 5. "    M1RCS ,Mask register 1 RCSE counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 4. "  M1RUN ,Mask register 1 RUND counter carry bit" "Unmaskek,Masked"
textline "               "
bitfld.long 0x0 3. " M1ROV ,Mask register 1 ROVR counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 2. "    M1RFR ,Mask register 1 RFRG counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 1. "    M1RJB ,Mask register 1 RJBR counter carry bit" "Unmaskek,Masked"
bitfld.long 0x0 0. "    M1RDR ,Mask register 1 RDRP counter carry bit" "Unmaskek,Masked"
line.long 0x04 "CAM2,Counter Carry Mask Register 2"
bitfld.long 0x04 19. " M2TJB ,Mask register 2 TJBR counter carry bit" "Not masked,Masked"
bitfld.long 0x04 18. "  M2TFC ,Mask register 2 TXFC counter carry bit" "Not masked,Masked"
bitfld.long 0x04 17. "  M2TCF ,Mask register 2 TXCF counter carry bit" "Not masked,Masked"
bitfld.long 0x04 16. "  M2TOV ,Mask register 2 TOVR counter carry bit" "Not masked,Masked"
bitfld.long 0x04 15. "  M2TUN ,Mask register 2 TUND counter carry bit" "Not masked,Masked"
textline "               "
bitfld.long 0x04 14. " M2TFG ,Mask register 2 TFRG counter carry bit" "Not masked,Masked"
bitfld.long 0x04 13. "  M2TBY ,Mask register 2 TBYT counter carry bit" "Not masked,Masked"
bitfld.long 0x04 12. "  M2TPK ,Mask register 2 TPKT counter carry bit" "Not masked,Masked"
bitfld.long 0x04 11. "  M2TMC ,Mask register 2 TMCA counter carry bit" "Not masked,Masked"
bitfld.long 0x04 10. "  M2TBC ,Mask register 2 TBCA counter carry bit" "Not masked,Masked"
textline "               "
bitfld.long 0x04 9. " M2TPF ,Mask register 2 TXPF counter carry bit" "Not masked,Masked"
bitfld.long 0x04 8. "  M2TDF ,Mask register 2 TDFR counter carry bit" "Not masked,Masked"
bitfld.long 0x04 7. "  M2TED ,Mask register 2 TEDF counter carry bit" "Not masked,Masked"
bitfld.long 0x04 6. "  M2TSC ,Mask register 2 TSCL counter carry bit" "Not masked,Masked"
bitfld.long 0x04 5. "  M2TMA ,Mask register 2 TMCL counter carry bit" "Not masked,Masked"
textline "               "
bitfld.long 0x04 4. " M2TLC ,Mask register 2 TLCL counter carry bit" "Not masked,Masked"
bitfld.long 0x04 3. "  M2TXC ,Mask register 2 TXCL counter carry bit" "Not masked,Masked"
bitfld.long 0x04 2. "  M2TNC ,Mask register 2 TNCL counter carry bit" "Not masked,Masked"
bitfld.long 0x04 1. "  M2TPH ,Mask register 2 TPFH counter carry bit" "Not masked,Masked"
bitfld.long 0x04 0. "  M2TDP ,Mask register 2 TDRP counter carry bit" "Not masked,Masked"
tree.end
width 0xb
tree.end
tree "CAN (Control Area Network)"
base ad:0x40015000
width 20.
group.long 0x18++0x3
line.long 0x00 "CAN_CONFIG,CAN Configuration Register"
hexmask.long.word 0x00 16.--30. 1. " CFG_BITRATE    ,Configuration bitrate"
bitfld.long 0x00 14. "            ECR_MODE       ,Error-capture mode" "Free running,Capture mode"
bitfld.long 0x00 13. "  SWAP_ENDIAN   ,Endian setting" "Big endian,Little endian"
textline "                             "
bitfld.long 0x00 12. " CFG_ARBITER    ,Transmit buffer arbiter" "Round robin,Fixed priority"
bitfld.long 0x00 8.--11. "  CFG_TSEG1      ,Time segment 1" "Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x00 5.--7. "      CFG_TSEG2     ,Time segment 2" "Reserved,2(direct-sam),3,4,5,6,7,8"
textline "                             "
bitfld.long 0x00 4. " AUTO_RESTART   ,Auto Restart" "Disabled,Enabled"
bitfld.long 0x00 2.--3. "        CFG_SJW        ,Synchronization Jump Width 1" "0,1,2,3"
bitfld.long 0x00 1. "             SAMPLING_MODE ,CAN bus bit sampling" "One sampling,3 sampling"
textline "                             "
bitfld.long 0x00 0. " EDGE_MODE      ,CAN bus synchronization logic" "From R to D,Both edges"
group.long 0x14++0x3
line.long 0x00 "CAN_COMMAND,Command Register"
bitfld.long 0x00 28.--31. " REV_CONTR3     ,Major version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "              REV_CONTR2     ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--23. "            REV_CONTR1    ,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
bitfld.long 0x00 3. "             CAN_COMMAND[3] ,SRAM Test mode" "Disabled,Enabled"
bitfld.long 0x00 2. "  CAN_COMMAND[2] ,Loopback-test mode" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " CAN_COMMAND[1] ,Listen-only mode" "Disabled,Enabled"
bitfld.long 0x00 0. "        CAN_COMMAND[0] ,Run/Stop mode" "Stop mode,Run mode"
group.long 0x20++0xF "Transmit Message 0 buffer registers"
line.long 0x00 "TX_MSG0_CTRL_CMD,Transmit Message 0 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG0_ID,Transmit Message 0 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG0_DATA_HIGH,Transmit Message 0 buffer data high register"
line.long 0x0C "TX_MSG0_DATA_LOW,Transmit Message 0 buffer data low register"
group.long 0x30++0xF "Transmit Message 1 buffer registers"
line.long 0x00 "TX_MSG1_CTRL_CMD,Transmit Message 1 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG1_ID,Transmit Message 1 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG1_DATA_HIGH,Transmit Message 1 buffer data high register"
line.long 0x0C "TX_MSG1_DATA_LOW,Transmit Message 1 buffer data low register"
group.long 0x40++0xF "Transmit Message 2 buffer registers"
line.long 0x00 "TX_MSG2_CTRL_CMD,Transmit Message 2 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG2_ID,Transmit Message 2 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG2_DATA_HIGH,Transmit Message 2 buffer data high register"
line.long 0x0C "TX_MSG2_DATA_LOW,Transmit Message 2 buffer data low register"
group.long 0x50++0xF "Transmit Message 3 buffer registers"
line.long 0x00 "TX_MSG3_CTRL_CMD,Transmit Message 3 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG3_ID,Transmit Message 3 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG3_DATA_HIGH,Transmit Message 3 buffer data high register"
line.long 0x0C "TX_MSG3_DATA_LOW,Transmit Message 3 buffer data low register"
group.long 0x60++0xF "Transmit Message 4 buffer registers"
line.long 0x00 "TX_MSG4_CTRL_CMD,Transmit Message 4 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG4_ID,Transmit Message 4 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG4_DATA_HIGH,Transmit Message 4 buffer data high register"
line.long 0x0C "TX_MSG4_DATA_LOW,Transmit Message 4 buffer data low register"
group.long 0x70++0xF "Transmit Message 5 buffer registers"
line.long 0x00 "TX_MSG5_CTRL_CMD,Transmit Message 5 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG5_ID,Transmit Message 5 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG5_DATA_HIGH,Transmit Message 5 buffer data high register"
line.long 0x0C "TX_MSG5_DATA_LOW,Transmit Message 5 buffer data low register"
group.long 0x80++0xF "Transmit Message 6 buffer registers"
line.long 0x00 "TX_MSG6_CTRL_CMD,Transmit Message 6 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG6_ID,Transmit Message 6 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG6_DATA_HIGH,Transmit Message 6 buffer data high register"
line.long 0x0C "TX_MSG6_DATA_LOW,Transmit Message 6 buffer data low register"
group.long 0x90++0xF "Transmit Message 7 buffer registers"
line.long 0x00 "TX_MSG7_CTRL_CMD,Transmit Message 7 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG7_ID,Transmit Message 7 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG7_DATA_HIGH,Transmit Message 7 buffer data high register"
line.long 0x0C "TX_MSG7_DATA_LOW,Transmit Message 7 buffer data low register"
group.long 0xA0++0xF "Transmit Message 8 buffer registers"
line.long 0x00 "TX_MSG8_CTRL_CMD,Transmit Message 8 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG8_ID,Transmit Message 8 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG8_DATA_HIGH,Transmit Message 8 buffer data high register"
line.long 0x0C "TX_MSG8_DATA_LOW,Transmit Message 8 buffer data low register"
group.long 0xB0++0xF "Transmit Message 9 buffer registers"
line.long 0x00 "TX_MSG9_CTRL_CMD,Transmit Message 9 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG9_ID,Transmit Message 9 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG9_DATA_HIGH,Transmit Message 9 buffer data high register"
line.long 0x0C "TX_MSG9_DATA_LOW,Transmit Message 9 buffer data low register"
group.long 0xC0++0xF "Transmit Message 10 buffer registers"
line.long 0x00 "TX_MSG10_CTRL_CMD,Transmit Message 10 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG10_ID,Transmit Message 10 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG10_DATA_HIGH,Transmit Message 10 buffer data high register"
line.long 0x0C "TX_MSG10_DATA_LOW,Transmit Message 10 buffer data low register"
group.long 0xD0++0xF "Transmit Message 11 buffer registers"
line.long 0x00 "TX_MSG11_CTRL_CMD,Transmit Message 11 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG11_ID,Transmit Message 11 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG11_DATA_HIGH,Transmit Message 11 buffer data high register"
line.long 0x0C "TX_MSG11_DATA_LOW,Transmit Message 11 buffer data low register"
group.long 0xE0++0xF "Transmit Message 12 buffer registers"
line.long 0x00 "TX_MSG12_CTRL_CMD,Transmit Message 12 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG12_ID,Transmit Message 12 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG12_DATA_HIGH,Transmit Message 12 buffer data high register"
line.long 0x0C "TX_MSG12_DATA_LOW,Transmit Message 12 buffer data low register"
group.long 0xF0++0xF "Transmit Message 13 buffer registers"
line.long 0x00 "TX_MSG13_CTRL_CMD,Transmit Message 13 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG13_ID,Transmit Message 13 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG13_DATA_HIGH,Transmit Message 13 buffer data high register"
line.long 0x0C "TX_MSG13_DATA_LOW,Transmit Message 13 buffer data low register"
group.long 0x100++0xF "Transmit Message 14 buffer registers"
line.long 0x00 "TX_MSG14_CTRL_CMD,Transmit Message 14 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG14_ID,Transmit Message 14 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG14_DATA_HIGH,Transmit Message 14 buffer data high register"
line.long 0x0C "TX_MSG14_DATA_LOW,Transmit Message 14 buffer data low register"
group.long 0x110++0xF "Transmit Message 15 buffer registers"
line.long 0x00 "TX_MSG15_CTRL_CMD,Transmit Message 15 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG15_ID,Transmit Message 15 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG15_DATA_HIGH,Transmit Message 15 buffer data high register"
line.long 0x0C "TX_MSG15_DATA_LOW,Transmit Message 15 buffer data low register"
group.long 0x120++0xF "Transmit Message 16 buffer registers"
line.long 0x00 "TX_MSG16_CTRL_CMD,Transmit Message 16 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG16_ID,Transmit Message 16 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG16_DATA_HIGH,Transmit Message 16 buffer data high register"
line.long 0x0C "TX_MSG16_DATA_LOW,Transmit Message 16 buffer data low register"
group.long 0x130++0xF "Transmit Message 17 buffer registers"
line.long 0x00 "TX_MSG17_CTRL_CMD,Transmit Message 17 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG17_ID,Transmit Message 17 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG17_DATA_HIGH,Transmit Message 17 buffer data high register"
line.long 0x0C "TX_MSG17_DATA_LOW,Transmit Message 17 buffer data low register"
group.long 0x140++0xF "Transmit Message 18 buffer registers"
line.long 0x00 "TX_MSG18_CTRL_CMD,Transmit Message 18 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG18_ID,Transmit Message 18 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG18_DATA_HIGH,Transmit Message 18 buffer data high register"
line.long 0x0C "TX_MSG18_DATA_LOW,Transmit Message 18 buffer data low register"
group.long 0x150++0xF "Transmit Message 19 buffer registers"
line.long 0x00 "TX_MSG19_CTRL_CMD,Transmit Message 19 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG19_ID,Transmit Message 19 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG19_DATA_HIGH,Transmit Message 19 buffer data high register"
line.long 0x0C "TX_MSG19_DATA_LOW,Transmit Message 19 buffer data low register"
group.long 0x160++0xF "Transmit Message 20 buffer registers"
line.long 0x00 "TX_MSG20_CTRL_CMD,Transmit Message 20 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG20_ID,Transmit Message 20 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG20_DATA_HIGH,Transmit Message 20 buffer data high register"
line.long 0x0C "TX_MSG20_DATA_LOW,Transmit Message 20 buffer data low register"
group.long 0x170++0xF "Transmit Message 21 buffer registers"
line.long 0x00 "TX_MSG21_CTRL_CMD,Transmit Message 21 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG21_ID,Transmit Message 21 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG21_DATA_HIGH,Transmit Message 21 buffer data high register"
line.long 0x0C "TX_MSG21_DATA_LOW,Transmit Message 21 buffer data low register"
group.long 0x180++0xF "Transmit Message 22 buffer registers"
line.long 0x00 "TX_MSG22_CTRL_CMD,Transmit Message 22 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG22_ID,Transmit Message 22 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG22_DATA_HIGH,Transmit Message 22 buffer data high register"
line.long 0x0C "TX_MSG22_DATA_LOW,Transmit Message 22 buffer data low register"
group.long 0x190++0xF "Transmit Message 23 buffer registers"
line.long 0x00 "TX_MSG23_CTRL_CMD,Transmit Message 23 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG23_ID,Transmit Message 23 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG23_DATA_HIGH,Transmit Message 23 buffer data high register"
line.long 0x0C "TX_MSG23_DATA_LOW,Transmit Message 23 buffer data low register"
group.long 0x1A0++0xF "Transmit Message 24 buffer registers"
line.long 0x00 "TX_MSG24_CTRL_CMD,Transmit Message 24 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG24_ID,Transmit Message 24 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG24_DATA_HIGH,Transmit Message 24 buffer data high register"
line.long 0x0C "TX_MSG24_DATA_LOW,Transmit Message 24 buffer data low register"
group.long 0x1B0++0xF "Transmit Message 25 buffer registers"
line.long 0x00 "TX_MSG25_CTRL_CMD,Transmit Message 25 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG25_ID,Transmit Message 25 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG25_DATA_HIGH,Transmit Message 25 buffer data high register"
line.long 0x0C "TX_MSG25_DATA_LOW,Transmit Message 25 buffer data low register"
group.long 0x1C0++0xF "Transmit Message 26 buffer registers"
line.long 0x00 "TX_MSG26_CTRL_CMD,Transmit Message 26 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG26_ID,Transmit Message 26 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG26_DATA_HIGH,Transmit Message 26 buffer data high register"
line.long 0x0C "TX_MSG26_DATA_LOW,Transmit Message 26 buffer data low register"
group.long 0x1D0++0xF "Transmit Message 27 buffer registers"
line.long 0x00 "TX_MSG27_CTRL_CMD,Transmit Message 27 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG27_ID,Transmit Message 27 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG27_DATA_HIGH,Transmit Message 27 buffer data high register"
line.long 0x0C "TX_MSG27_DATA_LOW,Transmit Message 27 buffer data low register"
group.long 0x1E0++0xF "Transmit Message 28 buffer registers"
line.long 0x00 "TX_MSG28_CTRL_CMD,Transmit Message 28 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG28_ID,Transmit Message 28 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG28_DATA_HIGH,Transmit Message 28 buffer data high register"
line.long 0x0C "TX_MSG28_DATA_LOW,Transmit Message 28 buffer data low register"
group.long 0x1F0++0xF "Transmit Message 29 buffer registers"
line.long 0x00 "TX_MSG29_CTRL_CMD,Transmit Message 29 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG29_ID,Transmit Message 29 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG29_DATA_HIGH,Transmit Message 29 buffer data high register"
line.long 0x0C "TX_MSG29_DATA_LOW,Transmit Message 29 buffer data low register"
group.long 0x200++0xF "Transmit Message 30 buffer registers"
line.long 0x00 "TX_MSG30_CTRL_CMD,Transmit Message 30 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG30_ID,Transmit Message 30 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG30_DATA_HIGH,Transmit Message 30 buffer data high register"
line.long 0x0C "TX_MSG30_DATA_LOW,Transmit Message 30 buffer data low register"
group.long 0x210++0xF "Transmit Message 31 buffer registers"
line.long 0x00 "TX_MSG31_CTRL_CMD,Transmit Message 31 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not Bit[21:16]" "Disabled,Enabled"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "         WPN   ,Write protect not Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 2. "           TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Removal"
bitfld.long 0x00 0. "   TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG31_ID,Transmit Message 31 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID      ,Transmit Message0 buffer identifier"
line.long 0x08 "TX_MSG31_DATA_HIGH,Transmit Message 31 buffer data high register"
line.long 0x0C "TX_MSG31_DATA_LOW,Transmit Message 31 buffer data low register"
group.long 0x0c++0x3
line.long 0x00 "TX_BUF_STATUS,Transmit (TX) Message buffer status"
bitfld.long 0x00 31. " TxMESSAGE31 ,Message available in TxMESSAGE buffer31" "Not available,Available"
bitfld.long 0x00 30. "  TxMESSAGE30 ,Message available in TxMESSAGE buffer30" "Not available,Available"
bitfld.long 0x00 29. "  TxMESSAGE29 ,Message available in TxMESSAGE buffer29" "Not available,Available"
textline "                             "
bitfld.long 0x00 28. " TxMESSAGE28 ,Message available in TxMESSAGE buffer28" "Not available,Available"
bitfld.long 0x00 27. "  TxMESSAGE27 ,Message available in TxMESSAGE buffer27" "Not available,Available"
bitfld.long 0x00 26. "  TxMESSAGE26 ,Message available in TxMESSAGE buffer26" "Not available,Available"
textline "                             "
bitfld.long 0x00 25. " TxMESSAGE25 ,Message available in TxMESSAGE buffer25" "Not available,Available"
bitfld.long 0x00 24. "  TxMESSAGE24 ,Message available in TxMESSAGE buffer24" "Not available,Available"
bitfld.long 0x00 23. "  TxMESSAGE23 ,Message available in TxMESSAGE buffer23" "Not available,Available"
textline "                             "
bitfld.long 0x00 22. " TxMESSAGE22 ,Message available in TxMESSAGE buffer22" "Not available,Available"
bitfld.long 0x00 21. "  TxMESSAGE21 ,Message available in TxMESSAGE buffer21" "Not available,Available"
bitfld.long 0x00 20. "  TxMESSAGE20 ,Message available in TxMESSAGE buffer20" "Not available,Available"
textline "                             "
bitfld.long 0x00 19. " TxMESSAGE19 ,Message available in TxMESSAGE buffer19" "Not available,Available"
bitfld.long 0x00 18. "  TxMESSAGE18 ,Message available in TxMESSAGE buffer18" "Not available,Available"
bitfld.long 0x00 17. "  TxMESSAGE17 ,Message available in TxMESSAGE buffer17" "Not available,Available"
textline "                             "
bitfld.long 0x00 16. " TxMESSAGE16 ,Message available in TxMESSAGE buffer16" "Not available,Available"
bitfld.long 0x00 15. "  TxMESSAGE15 ,Message available in TxMESSAGE buffer15" "Not available,Available"
bitfld.long 0x00 14. "  TxMESSAGE14 ,Message available in TxMESSAGE buffer14" "Not available,Available"
textline "                             "
bitfld.long 0x00 13. " TxMESSAGE13 ,Message available in TxMESSAGE buffer13" "Not available,Available"
bitfld.long 0x00 12. "  TxMESSAGE12 ,Message available in TxMESSAGE buffer12" "Not available,Available"
bitfld.long 0x00 11. "  TxMESSAGE11 ,Message available in TxMESSAGE buffer11" "Not available,Available"
textline "                             "
bitfld.long 0x00 10. " TxMESSAGE10 ,Message available in TxMESSAGE buffer10" "Not available,Available"
bitfld.long 0x00 9. "  TxMESSAGE9  ,Message available in TxMESSAGE buffer9" "Not available,Available"
bitfld.long 0x00 8. "  TxMESSAGE8  ,Message available in TxMESSAGE buffer8" "Not available,Available"
textline "                             "
bitfld.long 0x00 7. " TxMESSAGE7  ,Message available in TxMESSAGE buffer7" "Not available,Available"
bitfld.long 0x00 6. "  TxMESSAGE6  ,Message available in TxMESSAGE buffer6" "Not available,Available"
bitfld.long 0x00 5. "  TxMESSAGE5  ,Message available in TxMESSAGE buffer5" "Not available,Available"
textline "                             "
bitfld.long 0x00 4. " TxMESSAGE4  ,Message available in TxMESSAGE buffer4" "Not available,Available"
bitfld.long 0x00 3. "  TxMESSAGE3  ,Message available in TxMESSAGE buffer3" "Not available,Available"
bitfld.long 0x00 2. "  TxMESSAGE2  ,Message available in TxMESSAGE buffer2" "Not available,Available"
textline "                             "
bitfld.long 0x00 1. " TxMESSAGE1  ,Message available in TxMESSAGE buffer1" "Not available,Available"
bitfld.long 0x00 0. "  TxMESSAGE0  ,Message available in TxMessage buffer0" "Not available,Available"
tree "Receive Message Buffers"
group.long 0x220++0x1F  "Receive Message 0 buffer registers"
line.long 0x00 "RX_MSG0_CTRL_CMD,Receive Message 0 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG0_ID,Receive Message 0 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG0_DATA_HIGH,Receive Message 0 buffer data high register"
line.long 0x0C "RX_MSG0_DATA_LOW,Receive Message 0 buffer data low register"
line.long 0x10 "RX_MSG0_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG0_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG0_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG0_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x240++0x1F  "Receive Message 1 buffer registers"
line.long 0x00 "RX_MSG1_CTRL_CMD,Receive Message 1 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG1_ID,Receive Message 1 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG1_DATA_HIGH,Receive Message 1 buffer data high register"
line.long 0x0C "RX_MSG1_DATA_LOW,Receive Message 1 buffer data low register"
line.long 0x10 "RX_MSG1_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG1_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG1_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG1_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x260++0x1F  "Receive Message 2 buffer registers"
line.long 0x00 "RX_MSG2_CTRL_CMD,Receive Message 2 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG2_ID,Receive Message 2 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG2_DATA_HIGH,Receive Message 2 buffer data high register"
line.long 0x0C "RX_MSG2_DATA_LOW,Receive Message 2 buffer data low register"
line.long 0x10 "RX_MSG2_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG2_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG2_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG2_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x280++0x1F  "Receive Message 3 buffer registers"
line.long 0x00 "RX_MSG3_CTRL_CMD,Receive Message 3 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG3_ID,Receive Message 3 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG3_DATA_HIGH,Receive Message 3 buffer data high register"
line.long 0x0C "RX_MSG3_DATA_LOW,Receive Message 3 buffer data low register"
line.long 0x10 "RX_MSG3_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG3_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG3_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG3_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x2A0++0x1F  "Receive Message 4 buffer registers"
line.long 0x00 "RX_MSG4_CTRL_CMD,Receive Message 4 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG4_ID,Receive Message 4 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG4_DATA_HIGH,Receive Message 4 buffer data high register"
line.long 0x0C "RX_MSG4_DATA_LOW,Receive Message 4 buffer data low register"
line.long 0x10 "RX_MSG4_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG4_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG4_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG4_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x2C0++0x1F  "Receive Message 5 buffer registers"
line.long 0x00 "RX_MSG5_CTRL_CMD,Receive Message 5 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG5_ID,Receive Message 5 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG5_DATA_HIGH,Receive Message 5 buffer data high register"
line.long 0x0C "RX_MSG5_DATA_LOW,Receive Message 5 buffer data low register"
line.long 0x10 "RX_MSG5_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG5_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG5_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG5_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x2E0++0x1F  "Receive Message 6 buffer registers"
line.long 0x00 "RX_MSG6_CTRL_CMD,Receive Message 6 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG6_ID,Receive Message 6 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG6_DATA_HIGH,Receive Message 6 buffer data high register"
line.long 0x0C "RX_MSG6_DATA_LOW,Receive Message 6 buffer data low register"
line.long 0x10 "RX_MSG6_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG6_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG6_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG6_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x300++0x1F  "Receive Message 7 buffer registers"
line.long 0x00 "RX_MSG7_CTRL_CMD,Receive Message 7 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG7_ID,Receive Message 7 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG7_DATA_HIGH,Receive Message 7 buffer data high register"
line.long 0x0C "RX_MSG7_DATA_LOW,Receive Message 7 buffer data low register"
line.long 0x10 "RX_MSG7_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG7_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG7_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG7_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x320++0x1F  "Receive Message 8 buffer registers"
line.long 0x00 "RX_MSG8_CTRL_CMD,Receive Message 8 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG8_ID,Receive Message 8 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG8_DATA_HIGH,Receive Message 8 buffer data high register"
line.long 0x0C "RX_MSG8_DATA_LOW,Receive Message 8 buffer data low register"
line.long 0x10 "RX_MSG8_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG8_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG8_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG8_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x340++0x1F  "Receive Message 9 buffer registers"
line.long 0x00 "RX_MSG9_CTRL_CMD,Receive Message 9 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG9_ID,Receive Message 9 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG9_DATA_HIGH,Receive Message 9 buffer data high register"
line.long 0x0C "RX_MSG9_DATA_LOW,Receive Message 9 buffer data low register"
line.long 0x10 "RX_MSG9_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG9_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG9_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG9_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x360++0x1F  "Receive Message 10 buffer registers"
line.long 0x00 "RX_MSG10_CTRL_CMD,Receive Message 10 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG10_ID,Receive Message 10 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG10_DATA_HIGH,Receive Message 10 buffer data high register"
line.long 0x0C "RX_MSG10_DATA_LOW,Receive Message 10 buffer data low register"
line.long 0x10 "RX_MSG10_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG10_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG10_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG10_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x380++0x1F  "Receive Message 11 buffer registers"
line.long 0x00 "RX_MSG11_CTRL_CMD,Receive Message 11 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG11_ID,Receive Message 11 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG11_DATA_HIGH,Receive Message 11 buffer data high register"
line.long 0x0C "RX_MSG11_DATA_LOW,Receive Message 11 buffer data low register"
line.long 0x10 "RX_MSG11_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG11_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG11_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG11_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x3A0++0x1F  "Receive Message 12 buffer registers"
line.long 0x00 "RX_MSG12_CTRL_CMD,Receive Message 12 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG12_ID,Receive Message 12 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG12_DATA_HIGH,Receive Message 12 buffer data high register"
line.long 0x0C "RX_MSG12_DATA_LOW,Receive Message 12 buffer data low register"
line.long 0x10 "RX_MSG12_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG12_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG12_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG12_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x3C0++0x1F  "Receive Message 13 buffer registers"
line.long 0x00 "RX_MSG13_CTRL_CMD,Receive Message 13 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG13_ID,Receive Message 13 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG13_DATA_HIGH,Receive Message 13 buffer data high register"
line.long 0x0C "RX_MSG13_DATA_LOW,Receive Message 13 buffer data low register"
line.long 0x10 "RX_MSG13_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG13_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG13_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG13_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x3E0++0x1F  "Receive Message 14 buffer registers"
line.long 0x00 "RX_MSG14_CTRL_CMD,Receive Message 14 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG14_ID,Receive Message 14 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG14_DATA_HIGH,Receive Message 14 buffer data high register"
line.long 0x0C "RX_MSG14_DATA_LOW,Receive Message 14 buffer data low register"
line.long 0x10 "RX_MSG14_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG14_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG14_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG14_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x400++0x1F  "Receive Message 15 buffer registers"
line.long 0x00 "RX_MSG15_CTRL_CMD,Receive Message 15 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG15_ID,Receive Message 15 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG15_DATA_HIGH,Receive Message 15 buffer data high register"
line.long 0x0C "RX_MSG15_DATA_LOW,Receive Message 15 buffer data low register"
line.long 0x10 "RX_MSG15_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG15_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG15_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG15_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x420++0x1F  "Receive Message 16 buffer registers"
line.long 0x00 "RX_MSG16_CTRL_CMD,Receive Message 16 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG16_ID,Receive Message 16 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG16_DATA_HIGH,Receive Message 16 buffer data high register"
line.long 0x0C "RX_MSG16_DATA_LOW,Receive Message 16 buffer data low register"
line.long 0x10 "RX_MSG16_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG16_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG16_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG16_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x440++0x1F  "Receive Message 17 buffer registers"
line.long 0x00 "RX_MSG17_CTRL_CMD,Receive Message 17 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG17_ID,Receive Message 17 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG17_DATA_HIGH,Receive Message 17 buffer data high register"
line.long 0x0C "RX_MSG17_DATA_LOW,Receive Message 17 buffer data low register"
line.long 0x10 "RX_MSG17_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG17_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG17_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG17_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x460++0x1F  "Receive Message 18 buffer registers"
line.long 0x00 "RX_MSG18_CTRL_CMD,Receive Message 18 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG18_ID,Receive Message 18 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG18_DATA_HIGH,Receive Message 18 buffer data high register"
line.long 0x0C "RX_MSG18_DATA_LOW,Receive Message 18 buffer data low register"
line.long 0x10 "RX_MSG18_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG18_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG18_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG18_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x480++0x1F  "Receive Message 19 buffer registers"
line.long 0x00 "RX_MSG19_CTRL_CMD,Receive Message 19 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG19_ID,Receive Message 19 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG19_DATA_HIGH,Receive Message 19 buffer data high register"
line.long 0x0C "RX_MSG19_DATA_LOW,Receive Message 19 buffer data low register"
line.long 0x10 "RX_MSG19_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG19_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG19_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG19_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x4A0++0x1F  "Receive Message 20 buffer registers"
line.long 0x00 "RX_MSG20_CTRL_CMD,Receive Message 20 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG20_ID,Receive Message 20 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG20_DATA_HIGH,Receive Message 20 buffer data high register"
line.long 0x0C "RX_MSG20_DATA_LOW,Receive Message 20 buffer data low register"
line.long 0x10 "RX_MSG20_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG20_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG20_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG20_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x4C0++0x1F  "Receive Message 21 buffer registers"
line.long 0x00 "RX_MSG21_CTRL_CMD,Receive Message 21 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG21_ID,Receive Message 21 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG21_DATA_HIGH,Receive Message 21 buffer data high register"
line.long 0x0C "RX_MSG21_DATA_LOW,Receive Message 21 buffer data low register"
line.long 0x10 "RX_MSG21_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG21_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG21_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG21_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x4E0++0x1F  "Receive Message 22 buffer registers"
line.long 0x00 "RX_MSG22_CTRL_CMD,Receive Message 22 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG22_ID,Receive Message 22 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG22_DATA_HIGH,Receive Message 22 buffer data high register"
line.long 0x0C "RX_MSG22_DATA_LOW,Receive Message 22 buffer data low register"
line.long 0x10 "RX_MSG22_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG22_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG22_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG22_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x500++0x1F  "Receive Message 23 buffer registers"
line.long 0x00 "RX_MSG23_CTRL_CMD,Receive Message 23 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG23_ID,Receive Message 23 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG23_DATA_HIGH,Receive Message 23 buffer data high register"
line.long 0x0C "RX_MSG23_DATA_LOW,Receive Message 23 buffer data low register"
line.long 0x10 "RX_MSG23_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG23_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG23_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG23_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x520++0x1F  "Receive Message 24 buffer registers"
line.long 0x00 "RX_MSG24_CTRL_CMD,Receive Message 24 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG24_ID,Receive Message 24 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG24_DATA_HIGH,Receive Message 24 buffer data high register"
line.long 0x0C "RX_MSG24_DATA_LOW,Receive Message 24 buffer data low register"
line.long 0x10 "RX_MSG24_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG24_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG24_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG24_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x540++0x1F  "Receive Message 25 buffer registers"
line.long 0x00 "RX_MSG25_CTRL_CMD,Receive Message 25 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG25_ID,Receive Message 25 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG25_DATA_HIGH,Receive Message 25 buffer data high register"
line.long 0x0C "RX_MSG25_DATA_LOW,Receive Message 25 buffer data low register"
line.long 0x10 "RX_MSG25_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG25_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG25_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG25_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x560++0x1F  "Receive Message 26 buffer registers"
line.long 0x00 "RX_MSG26_CTRL_CMD,Receive Message 26 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG26_ID,Receive Message 26 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG26_DATA_HIGH,Receive Message 26 buffer data high register"
line.long 0x0C "RX_MSG26_DATA_LOW,Receive Message 26 buffer data low register"
line.long 0x10 "RX_MSG26_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG26_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG26_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG26_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x580++0x1F  "Receive Message 27 buffer registers"
line.long 0x00 "RX_MSG27_CTRL_CMD,Receive Message 27 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG27_ID,Receive Message 27 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG27_DATA_HIGH,Receive Message 27 buffer data high register"
line.long 0x0C "RX_MSG27_DATA_LOW,Receive Message 27 buffer data low register"
line.long 0x10 "RX_MSG27_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG27_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG27_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG27_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x5A0++0x1F  "Receive Message 28 buffer registers"
line.long 0x00 "RX_MSG28_CTRL_CMD,Receive Message 28 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG28_ID,Receive Message 28 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG28_DATA_HIGH,Receive Message 28 buffer data high register"
line.long 0x0C "RX_MSG28_DATA_LOW,Receive Message 28 buffer data low register"
line.long 0x10 "RX_MSG28_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG28_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG28_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG28_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x5C0++0x1F  "Receive Message 29 buffer registers"
line.long 0x00 "RX_MSG29_CTRL_CMD,Receive Message 29 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG29_ID,Receive Message 29 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG29_DATA_HIGH,Receive Message 29 buffer data high register"
line.long 0x0C "RX_MSG29_DATA_LOW,Receive Message 29 buffer data low register"
line.long 0x10 "RX_MSG29_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG29_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG29_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG29_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x5E0++0x1F  "Receive Message 30 buffer registers"
line.long 0x00 "RX_MSG30_CTRL_CMD,Receive Message 30 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG30_ID,Receive Message 30 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG30_DATA_HIGH,Receive Message 30 buffer data high register"
line.long 0x0C "RX_MSG30_DATA_LOW,Receive Message 30 buffer data low register"
line.long 0x10 "RX_MSG30_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG30_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG30_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG30_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
group.long 0x600++0x1F  "Receive Message 31 buffer registers"
line.long 0x00 "RX_MSG31_CTRL_CMD,Receive Message 31 buffer control and command register"
bitfld.long 0x00 23. " WPNH     ,Write protect not high" "Disabled,Enabled"
bitfld.long 0x00 21. "   RTR      ,Remote Transmission Request; Control flag bit" "Standard,RTR"
bitfld.long 0x00 20. "     IDE         ,Extended identifier bit; Control flag bit" "Standard,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC      ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 7. "          WPNL     ,Write protect not low" "Disabled,Enabled"
bitfld.long 0x00 6. "     LF          ,Link flag" "Not linked,Linked"
textline "                             "
bitfld.long 0x00 5. " RXINTEBL ,Receive interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "   RTRREPLY ,Automatic message reply upon receipt of an RTR message" "Disabled,Enabled"
bitfld.long 0x00 3. "     TXBUFFEREBL ,Transaction buffer enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 2. " RTRABORT ,RTR abort request" "Idle,Requested"
bitfld.long 0x00 1. "  RTRP     ,RTReply pending" "Not pending,Pending"
bitfld.long 0x00 0. "  MSGAV/RTRS  ,Message available/RTR sent(R/W)" "Idle/Idle,New message available/Acknowledges receipt"
line.long 0x04 "RX_MSG31_ID,Receive Message 31 buffer identifier register"
hexmask.long 0x04 3.--31. 1. " ID       ,Receive Message0 buffer identifier"
line.long 0x08 "RX_MSG31_DATA_HIGH,Receive Message 31 buffer data high register"
line.long 0x0C "RX_MSG31_DATA_LOW,Receive Message 31 buffer data low register"
line.long 0x10 "RX_MSG31_AMR,Acceptance mask register"
hexmask.long 0x10 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x10 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x10 1. "            RTR         ,RTR" "0,1"
line.long 0x14 "RX_MSG31_ACR,Acceptance mask register"
hexmask.long 0x14 3.--30. 1. " IDENT    ,Identifier"
bitfld.long 0x14 2. "   IDE      ,IDE" "0,1"
bitfld.long 0x14 1. "            RTR         ,RTR" "0,1"
line.long 0x18 "RX_MSG31_AMR_DATA,Receive Message0 buffer AMR Data register"
hexmask.long.byte 0x18 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x18 0.--7. 1. "         CANB2    ,CAN data byte 2"
line.long 0x1c "RX_MSG31_ACR_DATA,ACR Data"
hexmask.long.byte 0x1c 8.--15. 1. " CANB1    ,CAN data byte 1"
hexmask.long.byte 0x1c 0.--7. 1. "         CANB2    ,CAN data byte 2"
tree.end
rgroup.long 0x08++0x3
line.long 0x00 "RX_BUF_STATUS,Receive (RX) Message buffer status"
bitfld.long 0x00 31. " RxMESSAGE31      ,Message available in RxMESSAGE buffer31" "Not available,Available"
bitfld.long 0x00 30. "       RxMESSAGE30     ,Message available in RxMESSAGE buffer30" "Not available,Available"
bitfld.long 0x00 29. "       RxMESSAGE29      ,Message available in RxMESSAGE buffer29" "Not available,Available"
textline "                             "
bitfld.long 0x00 28. " RxMESSAGE28      ,Message available in RxMESSAGE buffer28" "Not available,Available"
bitfld.long 0x00 27. "       RxMESSAGE27     ,Message available in RxMESSAGE buffer27" "Not available,Available"
bitfld.long 0x00 26. "       RxMESSAGE26      ,Message available in RxMESSAGE buffer26" "Not available,Available"
textline "                             "
bitfld.long 0x00 25. " RxMESSAGE25      ,Message available in RxMESSAGE buffer25" "Not available,Available"
bitfld.long 0x00 24. "       RxMESSAGE24     ,Message available in RxMESSAGE buffer24" "Not available,Available"
bitfld.long 0x00 23. "       RxMESSAGE23      ,Message available in RxMESSAGE buffer23" "Not available,Available"
textline "                             "
bitfld.long 0x00 22. " RxMESSAGE22      ,Message available in RxMESSAGE buffer22" "Not available,Available"
bitfld.long 0x00 21. "       RxMESSAGE21     ,Message available in RxMESSAGE buffer21" "Not available,Available"
bitfld.long 0x00 20. "       RxMESSAGE20      ,Message available in RxMESSAGE buffer20" "Not available,Available"
textline "                             "
bitfld.long 0x00 19. " RxMESSAGE19      ,Message available in RxMESSAGE buffer19" "Not available,Available"
bitfld.long 0x00 18. "       RxMESSAGE18     ,Message available in RxMESSAGE buffer18" "Not available,Available"
bitfld.long 0x00 17. "       RxMESSAGE17      ,Message available in RxMESSAGE buffer17" "Not available,Available"
textline "                             "
bitfld.long 0x00 16. " RxMESSAGE16      ,Message available in RxMESSAGE buffer16" "Not available,Available"
bitfld.long 0x00 15. "       RxMESSAGE15     ,Message available in RxMESSAGE buffer15" "Not available,Available"
bitfld.long 0x00 14. "       RxMESSAGE14      ,Message available in RxMESSAGE buffer14" "Not available,Available"
textline "                             "
bitfld.long 0x00 13. " RxMESSAGE13      ,Message available in RxMESSAGE buffer13" "Not available,Available"
bitfld.long 0x00 12. "       RxMESSAGE12     ,Message available in RxMESSAGE buffer12" "Not available,Available"
bitfld.long 0x00 11. "       RxMESSAGE11      ,Message available in RxMESSAGE buffer11" "Not available,Available"
textline "                             "
bitfld.long 0x00 10. " RxMESSAGE10      ,Message available in RxMESSAGE buffer10" "Not available,Available"
bitfld.long 0x00 9. "       RxMESSAGE9      ,Message available in RxMESSAGE buffer9" "Not available,Available"
bitfld.long 0x00 8. "       RxMESSAGE8       ,Message available in RxMESSAGE buffer8" "Not available,Available"
textline "                             "
bitfld.long 0x00 7. " RxMESSAGE7       ,Message available in RxMESSAGE buffer7" "Not available,Available"
bitfld.long 0x00 6. "       RxMESSAGE6      ,Message available in RxMESSAGE buffer6" "Not available,Available"
bitfld.long 0x00 5. "       RxMESSAGE5       ,Message available in RxMESSAGE buffer5" "Not available,Available"
textline "                             "
bitfld.long 0x00 4. " RxMESSAGE4       ,Message available in RxMESSAGE buffer4" "Not available,Available"
bitfld.long 0x00 3. "       RxMESSAGE3      ,Message available in RxMESSAGE buffer3" "Not available,Available"
bitfld.long 0x00 2. "       RxMESSAGE2       ,Message available in RxMESSAGE buffer2" "Not available,Available"
textline "                             "
bitfld.long 0x00 1. " RxMESSAGE1       ,Message available in RxMESSAGE buffer1" "Not available,Available"
bitfld.long 0x00 0. "       RxMESSAGE0      ,Message available in RXMessage buffer0" "Not available,Available"
group.long 0x1c++0x3
line.long 0x00 "ECR,Error Capture Register"
bitfld.long 0x00 12.--16. " FIELD            ,Receiver Mode" "Stopped,Synchronize,Interframe,Bus idle,Start of frame,Arbitration,Control,Data,CRC,ACK,End of frame,Error flag,Error echo,Error delimiter,Overload flag,Overload echo,Overload delimiter,?..."
hexmask.long.byte 0x00 6.--11. 1. "  BIT_NUMBER      ,Bit number inside of field"
bitfld.long 0x00 5. "                  RX_MODE          ,Receiver mode" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 4. " TX_MODE          ,Transmitter Mode" "Disabled,Enabled"
bitfld.long 0x00 1.--3. "            ERROR_TYPE      ,Specifies different error types" "Arbitration loss,Bit error,Bit stuffing error,Acknowledge error,Form error,CRC error,?..."
bitfld.long 0x00 0. "  STATUS           ,Status of the ECR register" "Busy,Idle"
rgroup.long 0x10++0x3
line.long 0x00 "ERROR_STATUS,CAN error status indicator register"
bitfld.long 0x00 19. " RXGTE96          ,The receive error counter is greater or equal 96 dec" "Not occurred,Occurred"
bitfld.long 0x00 18. "        TXGTE96         ,The transmit error counter is greater or equal 96 dec" "Not occurred,Occurred"
bitfld.long 0x00 16.--17. "        ERROR_STATE      ,The error state of the CAN mode" "Active,Passive,Bus off,Bus off"
textline "                             "
hexmask.long.byte 0x00 8.--15. 1. " RX_ERR_CNT       ,The receive error counter as defined in CAN 2.0 specification"
hexmask.long.byte 0x00 0.--7. 1. "                  TX_ERR_CNT      ,The transmit error counter as defined in CAN 2.0 specification"
group.long 0x4++0x3
line.long 0x00 "INT_ENABLE,Interrupt enable register"
bitfld.long 0x00 15. " SST_FAILURE_ENBL ,Single shot transmission failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 14. "            STUCK_AT_0_ENBL ,Stuck at dominant error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 13. "            RTR_MSG_ENBL     ,RTR auto-reply message sent interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 12. " RX_MSG_ENBL      ,Receive message available interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 11. "            TX_MSG_ENBL     ,Message transmitted interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 10. "            RX_MSG_LOSS_ENBL ,Received message lost interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 9. " BUS_OFF_ENBL     ,Bus off interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. "            CRC_ERR_ENBL    ,CRC error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 7. "            FORM_ERR_ENBL    ,Format error interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 6. " ACK_ERR_ENBL     ,Acknowledge error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. "            STUFF_ERR_ENBL  ,Bit stuffing error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "            BIT_ERR_ENBL     ,Bit error interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 3. " OVR_LOAD_ENBL    ,Overload message detected interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "            ARB_LOSS_ENBL   ,Arbitration loss interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "            INT_ENBL         ,Global interrupt enable flag" "Disabled,Enabled"
group.long 0x0++0x3
line.long 0x00 "INT_STATUS,Interrupt status register"
bitfld.long 0x00 15. " SST_FAILURE      ,Single shot transmission failure" "Not occurred,Occurred"
bitfld.long 0x00 14. "        STUCK_AT_0      ,Stuck at dominant error" "Not occurred,Occurred"
bitfld.long 0x00 13. "        RTR_MSG          ,RTR auto-reply message sent" "Not occurred,Occurred"
textline "                             "
bitfld.long 0x00 12. " RX_MSG           ,Receive message available" "Not occurred,Occurred"
bitfld.long 0x00 11. "        TX_MSG          ,Message transmitted" "Not occurred,Occurred"
bitfld.long 0x00 10. "        RX_MSG_LOSS      ,Received message lost" "Not occurred,Occurred"
textline "                             "
bitfld.long 0x00 9. " BUS_OFF          ,Bus off" "Not occurred,Occurred"
bitfld.long 0x00 8. "        CRC_ERR         ,CRC error" "Not occurred,Occurred"
bitfld.long 0x00 7. "        FORM_ERR         ,Format error" "Not occurred,Occurred"
textline "                             "
bitfld.long 0x00 6. " ACK_ERR          ,Acknowledge error" "Not occurred,Occurred"
bitfld.long 0x00 5. "        STUFF_ERR       ,Bit stuffing error" "Not occurred,Occurred"
bitfld.long 0x00 4. "        BIT_ERR          ,Bit error" "Not occurred,Occurred"
textline "                             "
bitfld.long 0x00 3. " OVR_LOAD         ,Overload message detected" "Not occurred,Occurred"
bitfld.long 0x00 2. "        ARB_LOSS        ,Arbitration loss" "Not occurred,Occurred"
tree "Transmit Message Buffers"
group.long 0x30++0xF
line.long 0x00 "TX_MSG0_CTRL_CMD,Transmit Message 0 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG0_ID,Transmit Message 0 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 0 buffer identifier"
line.long 0x08 "TX_MSG0_DATA_HIGH,Transmit Message 0 buffer data high register"
line.long 0x0c "TX_MSG0_DATA_LOW,Transmit Message 0 buffer data low register"
group.long 0x40++0xF
line.long 0x00 "TX_MSG1_CTRL_CMD,Transmit Message 1 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG1_ID,Transmit Message 1 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 1 buffer identifier"
line.long 0x08 "TX_MSG1_DATA_HIGH,Transmit Message 1 buffer data high register"
line.long 0x0c "TX_MSG1_DATA_LOW,Transmit Message 1 buffer data low register"
group.long 0x50++0xF
line.long 0x00 "TX_MSG2_CTRL_CMD,Transmit Message 2 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG2_ID,Transmit Message 2 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 2 buffer identifier"
line.long 0x08 "TX_MSG2_DATA_HIGH,Transmit Message 2 buffer data high register"
line.long 0x0c "TX_MSG2_DATA_LOW,Transmit Message 2 buffer data low register"
group.long 0x60++0xF
line.long 0x00 "TX_MSG3_CTRL_CMD,Transmit Message 3 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG3_ID,Transmit Message 3 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 3 buffer identifier"
line.long 0x08 "TX_MSG3_DATA_HIGH,Transmit Message 3 buffer data high register"
line.long 0x0c "TX_MSG3_DATA_LOW,Transmit Message 3 buffer data low register"
group.long 0x70++0xF
line.long 0x00 "TX_MSG4_CTRL_CMD,Transmit Message 4 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG4_ID,Transmit Message 4 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 4 buffer identifier"
line.long 0x08 "TX_MSG4_DATA_HIGH,Transmit Message 4 buffer data high register"
line.long 0x0c "TX_MSG4_DATA_LOW,Transmit Message 4 buffer data low register"
group.long 0x80++0xF
line.long 0x00 "TX_MSG5_CTRL_CMD,Transmit Message 5 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG5_ID,Transmit Message 5 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 5 buffer identifier"
line.long 0x08 "TX_MSG5_DATA_HIGH,Transmit Message 5 buffer data high register"
line.long 0x0c "TX_MSG5_DATA_LOW,Transmit Message 5 buffer data low register"
group.long 0x90++0xF
line.long 0x00 "TX_MSG6_CTRL_CMD,Transmit Message 6 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG6_ID,Transmit Message 6 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 6 buffer identifier"
line.long 0x08 "TX_MSG6_DATA_HIGH,Transmit Message 6 buffer data high register"
line.long 0x0c "TX_MSG6_DATA_LOW,Transmit Message 6 buffer data low register"
group.long 0xA0++0xF
line.long 0x00 "TX_MSG7_CTRL_CMD,Transmit Message 7 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG7_ID,Transmit Message 7 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 7 buffer identifier"
line.long 0x08 "TX_MSG7_DATA_HIGH,Transmit Message 7 buffer data high register"
line.long 0x0c "TX_MSG7_DATA_LOW,Transmit Message 7 buffer data low register"
group.long 0xB0++0xF
line.long 0x00 "TX_MSG8_CTRL_CMD,Transmit Message 8 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG8_ID,Transmit Message 8 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 8 buffer identifier"
line.long 0x08 "TX_MSG8_DATA_HIGH,Transmit Message 8 buffer data high register"
line.long 0x0c "TX_MSG8_DATA_LOW,Transmit Message 8 buffer data low register"
group.long 0xC0++0xF
line.long 0x00 "TX_MSG9_CTRL_CMD,Transmit Message 9 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG9_ID,Transmit Message 9 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 9 buffer identifier"
line.long 0x08 "TX_MSG9_DATA_HIGH,Transmit Message 9 buffer data high register"
line.long 0x0c "TX_MSG9_DATA_LOW,Transmit Message 9 buffer data low register"
group.long 0xD0++0xF
line.long 0x00 "TX_MSG10_CTRL_CMD,Transmit Message 10 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG10_ID,Transmit Message 10 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 10 buffer identifier"
line.long 0x08 "TX_MSG10_DATA_HIGH,Transmit Message 10 buffer data high register"
line.long 0x0c "TX_MSG10_DATA_LOW,Transmit Message 10 buffer data low register"
group.long 0xE0++0xF
line.long 0x00 "TX_MSG11_CTRL_CMD,Transmit Message 11 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG11_ID,Transmit Message 11 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 11 buffer identifier"
line.long 0x08 "TX_MSG11_DATA_HIGH,Transmit Message 11 buffer data high register"
line.long 0x0c "TX_MSG11_DATA_LOW,Transmit Message 11 buffer data low register"
group.long 0xF0++0xF
line.long 0x00 "TX_MSG12_CTRL_CMD,Transmit Message 12 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG12_ID,Transmit Message 12 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 12 buffer identifier"
line.long 0x08 "TX_MSG12_DATA_HIGH,Transmit Message 12 buffer data high register"
line.long 0x0c "TX_MSG12_DATA_LOW,Transmit Message 12 buffer data low register"
group.long 0x100++0xF
line.long 0x00 "TX_MSG13_CTRL_CMD,Transmit Message 13 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG13_ID,Transmit Message 13 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 13 buffer identifier"
line.long 0x08 "TX_MSG13_DATA_HIGH,Transmit Message 13 buffer data high register"
line.long 0x0c "TX_MSG13_DATA_LOW,Transmit Message 13 buffer data low register"
group.long 0x110++0xF
line.long 0x00 "TX_MSG14_CTRL_CMD,Transmit Message 14 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG14_ID,Transmit Message 14 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 14 buffer identifier"
line.long 0x08 "TX_MSG14_DATA_HIGH,Transmit Message 14 buffer data high register"
line.long 0x0c "TX_MSG14_DATA_LOW,Transmit Message 14 buffer data low register"
group.long 0x120++0xF
line.long 0x00 "TX_MSG15_CTRL_CMD,Transmit Message 15 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG15_ID,Transmit Message 15 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 15 buffer identifier"
line.long 0x08 "TX_MSG15_DATA_HIGH,Transmit Message 15 buffer data high register"
line.long 0x0c "TX_MSG15_DATA_LOW,Transmit Message 15 buffer data low register"
group.long 0x130++0xF
line.long 0x00 "TX_MSG16_CTRL_CMD,Transmit Message 16 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG16_ID,Transmit Message 16 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 16 buffer identifier"
line.long 0x08 "TX_MSG16_DATA_HIGH,Transmit Message 16 buffer data high register"
line.long 0x0c "TX_MSG16_DATA_LOW,Transmit Message 16 buffer data low register"
group.long 0x140++0xF
line.long 0x00 "TX_MSG17_CTRL_CMD,Transmit Message 17 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG17_ID,Transmit Message 17 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 17 buffer identifier"
line.long 0x08 "TX_MSG17_DATA_HIGH,Transmit Message 17 buffer data high register"
line.long 0x0c "TX_MSG17_DATA_LOW,Transmit Message 17 buffer data low register"
group.long 0x150++0xF
line.long 0x00 "TX_MSG18_CTRL_CMD,Transmit Message 18 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG18_ID,Transmit Message 18 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 18 buffer identifier"
line.long 0x08 "TX_MSG18_DATA_HIGH,Transmit Message 18 buffer data high register"
line.long 0x0c "TX_MSG18_DATA_LOW,Transmit Message 18 buffer data low register"
group.long 0x160++0xF
line.long 0x00 "TX_MSG19_CTRL_CMD,Transmit Message 19 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG19_ID,Transmit Message 19 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 19 buffer identifier"
line.long 0x08 "TX_MSG19_DATA_HIGH,Transmit Message 19 buffer data high register"
line.long 0x0c "TX_MSG19_DATA_LOW,Transmit Message 19 buffer data low register"
group.long 0x170++0xF
line.long 0x00 "TX_MSG20_CTRL_CMD,Transmit Message 20 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG20_ID,Transmit Message 20 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 20 buffer identifier"
line.long 0x08 "TX_MSG20_DATA_HIGH,Transmit Message 20 buffer data high register"
line.long 0x0c "TX_MSG20_DATA_LOW,Transmit Message 20 buffer data low register"
group.long 0x180++0xF
line.long 0x00 "TX_MSG21_CTRL_CMD,Transmit Message 21 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG21_ID,Transmit Message 21 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 21 buffer identifier"
line.long 0x08 "TX_MSG21_DATA_HIGH,Transmit Message 21 buffer data high register"
line.long 0x0c "TX_MSG21_DATA_LOW,Transmit Message 21 buffer data low register"
group.long 0x190++0xF
line.long 0x00 "TX_MSG22_CTRL_CMD,Transmit Message 22 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG22_ID,Transmit Message 22 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 22 buffer identifier"
line.long 0x08 "TX_MSG22_DATA_HIGH,Transmit Message 22 buffer data high register"
line.long 0x0c "TX_MSG22_DATA_LOW,Transmit Message 22 buffer data low register"
group.long 0x1A0++0xF
line.long 0x00 "TX_MSG23_CTRL_CMD,Transmit Message 23 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG23_ID,Transmit Message 23 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 23 buffer identifier"
line.long 0x08 "TX_MSG23_DATA_HIGH,Transmit Message 23 buffer data high register"
line.long 0x0c "TX_MSG23_DATA_LOW,Transmit Message 23 buffer data low register"
group.long 0x1B0++0xF
line.long 0x00 "TX_MSG24_CTRL_CMD,Transmit Message 24 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG24_ID,Transmit Message 24 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 24 buffer identifier"
line.long 0x08 "TX_MSG24_DATA_HIGH,Transmit Message 24 buffer data high register"
line.long 0x0c "TX_MSG24_DATA_LOW,Transmit Message 24 buffer data low register"
group.long 0x1C0++0xF
line.long 0x00 "TX_MSG25_CTRL_CMD,Transmit Message 25 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG25_ID,Transmit Message 25 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 25 buffer identifier"
line.long 0x08 "TX_MSG25_DATA_HIGH,Transmit Message 25 buffer data high register"
line.long 0x0c "TX_MSG25_DATA_LOW,Transmit Message 25 buffer data low register"
group.long 0x1D0++0xF
line.long 0x00 "TX_MSG26_CTRL_CMD,Transmit Message 26 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG26_ID,Transmit Message 26 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 26 buffer identifier"
line.long 0x08 "TX_MSG26_DATA_HIGH,Transmit Message 26 buffer data high register"
line.long 0x0c "TX_MSG26_DATA_LOW,Transmit Message 26 buffer data low register"
group.long 0x1E0++0xF
line.long 0x00 "TX_MSG27_CTRL_CMD,Transmit Message 27 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG27_ID,Transmit Message 27 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 27 buffer identifier"
line.long 0x08 "TX_MSG27_DATA_HIGH,Transmit Message 27 buffer data high register"
line.long 0x0c "TX_MSG27_DATA_LOW,Transmit Message 27 buffer data low register"
group.long 0x1F0++0xF
line.long 0x00 "TX_MSG28_CTRL_CMD,Transmit Message 28 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG28_ID,Transmit Message 28 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 28 buffer identifier"
line.long 0x08 "TX_MSG28_DATA_HIGH,Transmit Message 28 buffer data high register"
line.long 0x0c "TX_MSG28_DATA_LOW,Transmit Message 28 buffer data low register"
group.long 0x200++0xF
line.long 0x00 "TX_MSG29_CTRL_CMD,Transmit Message 29 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG29_ID,Transmit Message 29 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 29 buffer identifier"
line.long 0x08 "TX_MSG29_DATA_HIGH,Transmit Message 29 buffer data high register"
line.long 0x0c "TX_MSG29_DATA_LOW,Transmit Message 29 buffer data low register"
group.long 0x210++0xF
line.long 0x00 "TX_MSG30_CTRL_CMD,Transmit Message 30 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG30_ID,Transmit Message 30 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 30 buffer identifier"
line.long 0x08 "TX_MSG30_DATA_HIGH,Transmit Message 30 buffer data high register"
line.long 0x0c "TX_MSG30_DATA_LOW,Transmit Message 30 buffer data low register"
group.long 0x220++0xF
line.long 0x00 "TX_MSG31_CTRL_CMD,Transmit Message 31 buffer control and command register"
bitfld.long 0x00 23. " WPN     ,Write protect not [Bit 21:16]" "Write protect,No write protect"
bitfld.long 0x00 21. "  RTR   ,Remote Transmission Request" "Standard,RTR"
bitfld.long 0x00 20. "           IDE      ,Extended identifier bit" "Standrad,Extended"
textline "                             "
bitfld.long 0x00 16.--19. " DLC     ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
bitfld.long 0x00 3. "                 WPN   ,Write protect not[Bit 2]" "Write protect,No write protect"
bitfld.long 0x00 2. "   TXINTEBL ,Tx interrupt enable" "Disabled,Enabled"
textline "                             "
bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested"
bitfld.long 0x00 0. "         TXREQ ,Transmit request(W/R)" "Idle/Completed,Requested/Pending"
line.long 0x04 "TX_MSG31_ID,Transmit Message 31 buffer identifier register"
hexmask.long.word 0x04 3.--31. 1. " ID      ,Transmit Message 31 buffer identifier"
line.long 0x08 "TX_MSG31_DATA_HIGH,Transmit Message 31 buffer data high register"
line.long 0x0c "TX_MSG31_DATA_LOW,Transmit Message 31 buffer data low register"
tree.end
width 0xb
tree.end
tree "MMUART (Multi-mode universal asynchronous/synchronous receiver/transmitter)"
tree "MMUART_0"
base ad:0x40000000
width 5.
if ((d.l(ad:0x40000000+0xc)&0x80)==0x80)
group.long 0x00++0x7
line.long 0x00 "DLR,Divisor latch"
hexmask.long.byte 0x00 0.--7. 1. " DLR               ,This divisor latch LSB register (DLR) holds the LSB of the integer divisor value used to calculate the buad rate"
line.long 0x04 "DMR,Divisor latch"
hexmask.long.byte 0x04 0.--7. 1. " DMR               ,This divisor latch MSB register (DMR) holds the MSB of the integer divisor value used to calculate the buad rate"
else
rgroup.long 0x00++0x3
line.long 0x00 "RBR,Receiver buffer register"
bitfld.long 0x00 12. " RBR               ,This register holds the receive data bits for MMUART_0" "0,1"
wgroup.long 0x00++0x3
line.long 0x00 "THR,Transmit holding register"
hexmask.long.byte 0x00 0.--7. 1. " THR               ,This register holds the data bits to be transmitted"
group.long 0x4++0x3
line.long 0x00 "IER,Interrupt enable register"
bitfld.long 0x00 3. " EDSSI             ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "                            ELSI               ,Receiver line status interrupt enable" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 1. " ETBEI             ,Transmitter holding register empty interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "                            ERBFI              ,Enables received data available interrupt" "Disabled,Enabled"
endif
group.long 0x3c++0x3
line.long 0x00 "DFR,Fractional divisor register"
bitfld.long 0x00 0.--5.  " DFR               ,The fractional divisor register (DFR) is used to store the fractional divisor used to calculate the fractional baud rate value in 1/64th using EQ 5" "0/64,1/64,2/64,3/64,4/64,5/64,6/64,7/64,8/64,9/64,10/64,11/64,12/64,13/64,14/64,15/64,16/64,17/64,18/64,19/64,20/64,21/64,22/64,23/64,24/64,25/64,26/64,27/64,28/64,29/64,30/64,31/64,32/64,33/64,34/64,35/64,36/64,37/64,38/64,39/64,40/64,41/64,42/64,43/64,44/64,45/64,46/64,47/64,48/64,49/64,50/64,51/64,52/64,53/64,54/64,55/64,56/64,57/64,58/64,59/64,60/64,61/64,62/64,63/64"
group.long 0x24++0x3
line.long 0x00 "IEM,Multi-mode interrupt enable register"
bitfld.long 0x00 4. " ELINSI            ,Enables the LIN sync detection interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. "                            ELINBI             ,Enables LIN break interrupt" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 2. " EPID_PEI          ,Enables PID parity error interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. "                            ENACKI             ,Enables NACK interrupt" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 0. " ERTOI             ,Enables receiver timeout interrupt" "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "IIR,Interrupt identification register"
bitfld.long 0x00 6.--7. " MODE              ,Enables FIFO mode" "Disabled,Disabled,Disabled,Enabled"
textline "              "
bitfld.long 0x00 0.--3. " IIR               ,Interrupt identification bits" "Modem status,Reserved,Transmitter holding register empty,Multi mode interrupt,Received data available,Reserved,Receiver line status,Reserved,Reserved,Reserved,Reserved,Reserved,Character timeout indication,?..."
hgroup.long 0x28++0x3
hide.long 0x00 "IIM,Multi-mode interrupt identification register"
in
wgroup.long 0x8++0x3
line.long 0x00 "FCR,FIFO control register"
bitfld.long 0x00 6.--7. " RX_TRIG           ,These bits are used to set the trigger level for the Rx FIFO interrupt" "1,4,8,14"
bitfld.long 0x00 3. "                                  ENABLE_TXRDY_RXRDY ,Software must always set this bit to 1 for efficient data transfer from transmit FIFO to PDMA" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 2. " CLEAR_TX_FIFO     ,Clears all bytes in the Tx FIFO and resets its counter logic" "Disabled,Enabled"
bitfld.long 0x00 1. "                            CLEAR_RX_FIFO      ,Clears all bytes in Rx FIFO and resets counter logic" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 0. " ENABLE_TX_RX_FIFO ,It enables both the Tx and Rx FIFOs and is hardwired to 1" "Disabled,Enabled"
group.long 0xc++0x7
line.long 0x00 "LCR,Line control register"
bitfld.long 0x00 7. " DLAB              ,Divisor latch access bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                            SB                 ,Set break" "Disabled,Set break"
textline "              "
bitfld.long 0x00 5. " SP                ,Stick parity" "Disabled,Enabled"
bitfld.long 0x00 4. "                            EPS                ,Even parity select" "Odd,Even"
textline "              "
bitfld.long 0x00 3. " PEN               ,Parity enable" "Disabled,Enabled"
bitfld.long 0x00 2. "                            STB                ,Number of stop bits" "1,11/2"
textline "              "
bitfld.long 0x00 0.--1. " WLS               ,Word length select" "5 bits,6 bits,7 bits,8 bits"
line.long 0x04 "MCR,Modem control register"
bitfld.long 0x04 5.--6. " RLOOP             ,Remote loopback enable bits" "Disabled,Remote loopback enabled,Automatic echo enabled,?..."
bitfld.long 0x04 4. "             LOOP               ,Local loopback enabled" "Disabled,Enabled"
textline "              "
bitfld.long 0x04 3. " OUT2              ,Controls the output2 (OUT2) signal" "Less than equal to 1,Less than equal to 0"
bitfld.long 0x04 2.  "                OUT1               ,Controls the output1 (OUT1) signal" "Less than equal to 1,Less than equal to 0"
textline "              "
bitfld.long 0x04 1. " RTS               ,Controls the request to send (MMUART_x_RTS) signal" "Less than equal to 1,Less than equal to 0"
bitfld.long 0x04 0. "                DTR                ,Data terminal ready (MMUART_x_DTR) output" "Less than equal to 1,Less than equal to 0"
hgroup.long 0x14++0x3
hide.long 0x00 "LSR,Line status register"
in
hgroup.long 0x18++0x3
hide.long 0x00 "MSR,Modem status register"
in
group.long 0x1c++0x3
line.long 0x00 "SR,Scratch register"
hexmask.long.byte 0x00 0.--7. 1. " SCR               ,Scratch register"
group.long 0x30++0xb
line.long 0x00 "MM0,Multi-mode control register0"
bitfld.long 0x00 7. " EFBR              ,Enable fractional baud rate (FBR) mode" "Disabled,Enabled"
bitfld.long 0x00 6. "                            ERTO               ,Enable receiver timeout" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 5. " ETTG              ,Enable transmitter time guard" "Disabled,Enabled"
bitfld.long 0x00 3. "                            ELIN               ,Enable LIN header detection and automatic baud rate calculation" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 0.--2. " ESYN              ,Enable synchronous operation" "Disabled,Positive-edge clock(slave),Negative-edge clock(slave),Positive-edge clock(master),Negative-edge clock(master),?..."
line.long 0x04 "MM1,Multi-mode control register1"
bitfld.long 0x04 5. " EITP              ,Output pulse width for RZI mod can be modified using this bit" "3/16th Tbit pulse width,1/4th Tbit pulse width"
bitfld.long 0x04 4. "                        EITX               ,You can configure output polarity for RZI modulation" "Active low and signify a low NRZ value,Active high and signify a high NRZ value"
textline "              "
bitfld.long 0x04 3. " EIRX              ,You can configure input polarity for RZI demodulation" "Active low;signifying a low NRZ value,Active high;signifying a high NRZ value"
bitfld.long 0x04 2. "        EIRD               ,Enables RZI modulation/demodulation" "Disabled,Enabled"
textline "              "
bitfld.long 0x04 1. " E_MSB_TX ,THR's bit received order" "LSB,MSB"
bitfld.long 0x04 0. "                      E_MSB_RX,RX ,RX        ,THR's bit received order" "LSB,MSB"
line.long 0x08 "MM2,Multi-mode control register2"
bitfld.long 0x08 3. " ESWM     ,Enable single-wire, half-duplex mode" "Disabled,Enabled"
bitfld.long 0x08 2. "                 EAFC        ,Enable a flag clear" "Disabled,Enabled"
textline "              "
bitfld.long 0x08 1. " EAFM     ,Enable automatic 9-bit address flag mode" "Disabled,Enabled"
bitfld.long 0x08 0. "                 EERR        ,Receiver forces an error signal transmit out, if an incoming parity error is detected" "Disabled,Enabled"
group.long 0x44++0xf
line.long 0x00 "GFR,Glitch filter register"
bitfld.long 0x00 0.--2. " GLR      ,Glitch filter resynchronizes. Filter lengths in the PCLK cycles that can be written into the GLR register" "2(no spike suppression),3(no spike suppression),3(1 PCLK),3(2 PCLK),3(3 PCLK),3(4 PCLK),3(5 PCLK),3(6 PCLK)"
line.long 0x04 "TTG,Transmitter time guard register"
hexmask.long.byte 0x04 0.--7. 1. " TTG      ,Transmitter time guard"
line.long 0x08 "RTO,Receiver time-out register"
hexmask.long.byte 0x08 0.--7. 1. " RTO      ,Transmitter time guard"
line.long 0x0c "ADR,Address register"
hexmask.long.byte 0x0c 0.--7. 1. " ADR      ,Address register"
width 0xb
tree.end
tree "MMUART_1"
base ad:0x40010000
width 5.
if ((d.l(ad:0x40010000+0xc)&0x80)==0x80)
group.long 0x00++0x7
line.long 0x00 "DLR,Divisor latch"
hexmask.long.byte 0x00 0.--7. 1. " DLR               ,This divisor latch LSB register (DLR) holds the LSB of the integer divisor value used to calculate the buad rate"
line.long 0x04 "DMR,Divisor latch"
hexmask.long.byte 0x04 0.--7. 1. " DMR               ,This divisor latch MSB register (DMR) holds the MSB of the integer divisor value used to calculate the buad rate"
else
rgroup.long 0x00++0x3
line.long 0x00 "RBR,Receiver buffer register"
bitfld.long 0x00 12. " RBR               ,This register holds the receive data bits for MMUART_1" "0,1"
wgroup.long 0x00++0x3
line.long 0x00 "THR,Transmit holding register"
hexmask.long.byte 0x00 0.--7. 1. " THR               ,This register holds the data bits to be transmitted"
group.long 0x4++0x3
line.long 0x00 "IER,Interrupt enable register"
bitfld.long 0x00 3. " EDSSI             ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "                            ELSI               ,Receiver line status interrupt enable" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 1. " ETBEI             ,Transmitter holding register empty interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "                            ERBFI              ,Enables received data available interrupt" "Disabled,Enabled"
endif
group.long 0x3c++0x3
line.long 0x00 "DFR,Fractional divisor register"
bitfld.long 0x00 0.--5.  " DFR               ,The fractional divisor register (DFR) is used to store the fractional divisor used to calculate the fractional baud rate value in 1/64th using EQ 5" "0/64,1/64,2/64,3/64,4/64,5/64,6/64,7/64,8/64,9/64,10/64,11/64,12/64,13/64,14/64,15/64,16/64,17/64,18/64,19/64,20/64,21/64,22/64,23/64,24/64,25/64,26/64,27/64,28/64,29/64,30/64,31/64,32/64,33/64,34/64,35/64,36/64,37/64,38/64,39/64,40/64,41/64,42/64,43/64,44/64,45/64,46/64,47/64,48/64,49/64,50/64,51/64,52/64,53/64,54/64,55/64,56/64,57/64,58/64,59/64,60/64,61/64,62/64,63/64"
group.long 0x24++0x3
line.long 0x00 "IEM,Multi-mode interrupt enable register"
bitfld.long 0x00 4. " ELINSI            ,Enables the LIN sync detection interrupt" "Disabled,Enabled"
bitfld.long 0x00 3. "                            ELINBI             ,Enables LIN break interrupt" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 2. " EPID_PEI          ,Enables PID parity error interrupt" "Disabled,Enabled"
bitfld.long 0x00 1. "                            ENACKI             ,Enables NACK interrupt" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 0. " ERTOI             ,Enables receiver timeout interrupt" "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "IIR,Interrupt identification register"
bitfld.long 0x00 6.--7. " MODE              ,Enables FIFO mode" "Disabled,Disabled,Disabled,Enabled"
textline "              "
bitfld.long 0x00 0.--3. " IIR               ,Interrupt identification bits" "Modem status,Reserved,Transmitter holding register empty,Multi mode interrupt,Received data available,Reserved,Receiver line status,Reserved,Reserved,Reserved,Reserved,Reserved,Character timeout indication,?..."
hgroup.long 0x28++0x3
hide.long 0x00 "IIM,Multi-mode interrupt identification register"
in
wgroup.long 0x8++0x3
line.long 0x00 "FCR,FIFO control register"
bitfld.long 0x00 6.--7. " RX_TRIG           ,These bits are used to set the trigger level for the Rx FIFO interrupt" "1,4,8,14"
bitfld.long 0x00 3. "                                  ENABLE_TXRDY_RXRDY ,Software must always set this bit to 1 for efficient data transfer from transmit FIFO to PDMA" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 2. " CLEAR_TX_FIFO     ,Clears all bytes in the Tx FIFO and resets its counter logic" "Disabled,Enabled"
bitfld.long 0x00 1. "                            CLEAR_RX_FIFO      ,Clears all bytes in Rx FIFO and resets counter logic" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 0. " ENABLE_TX_RX_FIFO ,It enables both the Tx and Rx FIFOs and is hardwired to 1" "Disabled,Enabled"
group.long 0xc++0x7
line.long 0x00 "LCR,Line control register"
bitfld.long 0x00 7. " DLAB              ,Divisor latch access bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                            SB                 ,Set break" "Disabled,Set break"
textline "              "
bitfld.long 0x00 5. " SP                ,Stick parity" "Disabled,Enabled"
bitfld.long 0x00 4. "                            EPS                ,Even parity select" "Odd,Even"
textline "              "
bitfld.long 0x00 3. " PEN               ,Parity enable" "Disabled,Enabled"
bitfld.long 0x00 2. "                            STB                ,Number of stop bits" "1,11/2"
textline "              "
bitfld.long 0x00 0.--1. " WLS               ,Word length select" "5 bits,6 bits,7 bits,8 bits"
line.long 0x04 "MCR,Modem control register"
bitfld.long 0x04 5.--6. " RLOOP             ,Remote loopback enable bits" "Disabled,Remote loopback enabled,Automatic echo enabled,?..."
bitfld.long 0x04 4. "             LOOP               ,Local loopback enabled" "Disabled,Enabled"
textline "              "
bitfld.long 0x04 3. " OUT2              ,Controls the output2 (OUT2) signal" "Less than equal to 1,Less than equal to 0"
bitfld.long 0x04 2.  "                OUT1               ,Controls the output1 (OUT1) signal" "Less than equal to 1,Less than equal to 0"
textline "              "
bitfld.long 0x04 1. " RTS               ,Controls the request to send (MMUART_x_RTS) signal" "Less than equal to 1,Less than equal to 0"
bitfld.long 0x04 0. "                DTR                ,Data terminal ready (MMUART_x_DTR) output" "Less than equal to 1,Less than equal to 0"
hgroup.long 0x14++0x3
hide.long 0x00 "LSR,Line status register"
in
hgroup.long 0x18++0x3
hide.long 0x00 "MSR,Modem status register"
in
group.long 0x1c++0x3
line.long 0x00 "SR,Scratch register"
hexmask.long.byte 0x00 0.--7. 1. " SCR               ,Scratch register"
group.long 0x30++0xb
line.long 0x00 "MM0,Multi-mode control register0"
bitfld.long 0x00 7. " EFBR              ,Enable fractional baud rate (FBR) mode" "Disabled,Enabled"
bitfld.long 0x00 6. "                            ERTO               ,Enable receiver timeout" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 5. " ETTG              ,Enable transmitter time guard" "Disabled,Enabled"
bitfld.long 0x00 3. "                            ELIN               ,Enable LIN header detection and automatic baud rate calculation" "Disabled,Enabled"
textline "              "
bitfld.long 0x00 0.--2. " ESYN              ,Enable synchronous operation" "Disabled,Positive-edge clock(slave),Negative-edge clock(slave),Positive-edge clock(master),Negative-edge clock(master),?..."
line.long 0x04 "MM1,Multi-mode control register1"
bitfld.long 0x04 5. " EITP              ,Output pulse width for RZI mod can be modified using this bit" "3/16th Tbit pulse width,1/4th Tbit pulse width"
bitfld.long 0x04 4. "                        EITX               ,You can configure output polarity for RZI modulation" "Active low and signify a low NRZ value,Active high and signify a high NRZ value"
textline "              "
bitfld.long 0x04 3. " EIRX              ,You can configure input polarity for RZI demodulation" "Active low;signifying a low NRZ value,Active high;signifying a high NRZ value"
bitfld.long 0x04 2. "        EIRD               ,Enables RZI modulation/demodulation" "Disabled,Enabled"
textline "              "
bitfld.long 0x04 1. " E_MSB_TX ,THR's bit received order" "LSB,MSB"
bitfld.long 0x04 0. "                      E_MSB_RX,RX ,RX        ,THR's bit received order" "LSB,MSB"
line.long 0x08 "MM2,Multi-mode control register2"
bitfld.long 0x08 3. " ESWM     ,Enable single-wire, half-duplex mode" "Disabled,Enabled"
bitfld.long 0x08 2. "                 EAFC        ,Enable a flag clear" "Disabled,Enabled"
textline "              "
bitfld.long 0x08 1. " EAFM     ,Enable automatic 9-bit address flag mode" "Disabled,Enabled"
bitfld.long 0x08 0. "                 EERR        ,Receiver forces an error signal transmit out, if an incoming parity error is detected" "Disabled,Enabled"
group.long 0x44++0xf
line.long 0x00 "GFR,Glitch filter register"
bitfld.long 0x00 0.--2. " GLR      ,Glitch filter resynchronizes. Filter lengths in the PCLK cycles that can be written into the GLR register" "2(no spike suppression),3(no spike suppression),3(1 PCLK),3(2 PCLK),3(3 PCLK),3(4 PCLK),3(5 PCLK),3(6 PCLK)"
line.long 0x04 "TTG,Transmitter time guard register"
hexmask.long.byte 0x04 0.--7. 1. " TTG      ,Transmitter time guard"
line.long 0x08 "RTO,Receiver time-out register"
hexmask.long.byte 0x08 0.--7. 1. " RTO      ,Transmitter time guard"
line.long 0x0c "ADR,Address register"
hexmask.long.byte 0x0c 0.--7. 1. " ADR      ,Address register"
width 0xb
tree.end
tree.end
tree "SPI (Serial Peripheral Interface)"
tree "SPI_0"
base ad:0x40001000
width 14.
group.long 0x00++0x7
line.long 0x00 "CONTROL,Control register"
bitfld.long 0x00 31. " RESET      ,SPI reset" "No reset,Reset"
bitfld.long 0x00 30. "           OENOFF      ,SPI output enable active" "Asserted,Not asserted"
bitfld.long 0x00 29. "                      BIGFIFO     ,Alters FIFO depth when frame size is 4-8 bits" "4 frames,32/16/8"
textline "                       "
bitfld.long 0x00 28. " CLKMODE    ,Specifies the methodology used to calculate the SPICLK divider" "1/(2 CLK_GEN+1),1/(2x(CLK_GEN+1))"
bitfld.long 0x00 27. "  FRAMEURUN   ,Under-run condition" "Generated,Ignored"
bitfld.long 0x00 26. "                         SPS         ,Define slave select behavior" "Low,High"
textline "                       "
bitfld.long 0x00 25. " SPH        ,Clock phase" "Low,High"
bitfld.long 0x00 24. "               SPO         ,Clock polarity" "Low,High"
hexmask.long.word 0x00 8.--23. 1. "                              TXRXDFCOUNT ,Number of data frames to be sent or received"
textline "                       "
bitfld.long 0x00 7. " INTTXTURUN ,Interrupt on transmit the under-run" "Disabled,Enabled"
bitfld.long 0x00 6. "           INTRXOVRFLO ,Interrupt on receive overflow" "Disabled,Enabled"
bitfld.long 0x00 5. "                          INTTXDATA   ,Interrupt on transmit data" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 4. " INTRXDATA  ,Interrupt on receive data" "Reserved,?..."
bitfld.long 0x00 2.--3. "           TRANSFPRTL  ,Transfer protocol" "Motorola SPI,TI synchronous serial,National Semiconductor MICROWIRE,?..."
bitfld.long 0x00 1. "  MODE        ,SPI implementation" "Slave,Master"
textline "                       "
bitfld.long 0x00 0. " ENABLE     ,Core enable" "Disabled,Enabled"
line.long 0x04 "TXRXDF_SIZE,Transmit and receive data frame size"
bitfld.long 0x04 0.--5. " TXRXDFS    ,Transmit and receive data size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
rgroup.long 0x8++0x3
line.long 0x00 "STATUS,Status register"
bitfld.long 0x00 14. " ACTIVE         ,SPI is still transmitting or receiving data" "Not transmitting,Still transmitting"
bitfld.long 0x00 13. "  SSEL         ,Current state of SPI_X_SS[0]" "0,1"
bitfld.long 0x00 12. "                                 FRAMESTART     ,SPI output enable" "Active as required,Not asserted"
textline "                       "
bitfld.long 0x00 11. " TXFIFOEMPNXT   ,Transmit FIFO empty on next read" "Not empty,Empty on next read"
bitfld.long 0x00 10. "  TXFIFOEMP    ,Transmit FIFO is empty" "Not empty,Empty"
bitfld.long 0x00 9. "                         TXFIFOFULNXT   ,Transmit FIFO full on next write" "Not full,Full on next write"
textline "                       "
bitfld.long 0x00 8. " TXFIFOFUL      ,Transmit FIFO is full" "Not full,Full"
bitfld.long 0x00 7. "            RXFIFOEMPNXT ,Receive FIFO empty on next read" "Not empty,Empty on next read"
bitfld.long 0x00 6. "                RXFIFOEMP      ,Receive FIFO empty" "Not empty,Empty"
textline "                       "
bitfld.long 0x00 5. " RXFIFOFULNXT   ,Receive FIFO full on next write" "Not full,Full on next write"
bitfld.long 0x00 4. "  RXFIFOFUL    ,Receive FIFO is full" "Not full,Full"
bitfld.long 0x00 3. "                          TXUNDERRUN     ,No data available for transmission" "No action,FIFO is empty"
textline "                       "
bitfld.long 0x00 2. " RXOVERFLOW     ,Channel is unable to write to receive FIFO as it is full." "No action,Overflow"
bitfld.long 0x00 1. "           RXDATRCED    ,When set it indicates that, the number of frames specified by TxRXDFCOUNT have been received and can be read" "No action,Received"
bitfld.long 0x00 0. "                         TXDATSENT      ,When set it indicates that, the numbers of frames specified by TxRXDFCOUNT have been sent" "No action,Sent"
wgroup.long 0xc++0x3
line.long 0x00 "INT_CLEAR,Interrupt clear register"
bitfld.long 0x00 5. " SSEND          ,Write one to clear the interrupt" "No effect,Clear"
bitfld.long 0x00 4. "           CMDINT       ,Write one to clear the interrupt" "No effect,Clear"
bitfld.long 0x00 3. "                         TXCHUNDRUN     ,No data available for transmission" "No effect,Clear"
textline "                       "
bitfld.long 0x00 2. " RXCHOVRFLW     ,Receive channel over flow" "No effect,Clear"
bitfld.long 0x00 1. "           RXRDYCLR     ,Clears receive ready" "No effect,Clear"
bitfld.long 0x00 0. "                         TXDONECLR      ,Clears transmit done" "No effect,Clear"
hgroup.long 0x10++0x3
hide.long 0x00 "RX_DATA,Receive data register"
in
wgroup.long 0x14++0x03
line.long 0x00 "TX_DATA,Transmit data register"
group.long 0x18++0x7
line.long 0x00 "CLK_GEN,Output clock generator"
hexmask.long.byte 0x00 0.--7. 1. " CLK_GEN        ,Specifies the methodology used to calculate the SPICLK divider"
line.long 0x04 "SLAVE_SELECT,Specifies slave selected"
bitfld.long 0x04 7. " SLAVE_SEL7     ,Slave select" "Not selected,Selected"
bitfld.long 0x04 6. "        SLAVE_SEL6   ,Slave select" "Not selected,Selected"
bitfld.long 0x04 5. "                      SLAVE_SEL5     ,Slave select" "Not selected,Selected"
textline "                       "
bitfld.long 0x04 4. " SLAVE_SEL4     ,Slave select" "Not selected,Selected"
bitfld.long 0x04 3. "        SLAVE_SEL3   ,Slave select" "Not selected,Selected"
bitfld.long 0x04 2. "                      SLAVE_SEL2     ,Slave select" "Not selected,Selected"
textline "                       "
bitfld.long 0x04 1. " SLAVE_SEL1     ,Slave select" "Not selected,Selected"
bitfld.long 0x04 0. "        SLAVE_SEL0   ,Slave select" "Not selected,Selected"
rgroup.long 0x20++0x7
line.long 0x00 "MIS,Masked interrupt status"
bitfld.long 0x00 5. " SSEND          ,Equals RIS[5] and CONTROL2[5]" "Masked,Not masked"
bitfld.long 0x00 4. "          CMDINT       ,Equals RIS[4] and CONTROL2[4]" "Masked,Not masked"
bitfld.long 0x00 3. "                        TXCHUNDDMSKINT ,Masked interrupt status" "Masked,Not masked"
textline "                       "
bitfld.long 0x00 2. " RXCHOVRFMSKINT ,Masked status of receive channel overflow" "Masked,Not masked"
bitfld.long 0x00 1. "          RXRDYMSKINT  ,Masked status of receive data ready" "Masked,Not masked"
bitfld.long 0x00 0. "                        TXDONEMSKINT   ,Masked status of transmit done" "Masked,Not masked"
line.long 0x04 "RIS,Raw interrupt status"
bitfld.long 0x04 5. " SSEND          ,Indicates that SPI_X_SS[x] has gone inactive" "Not occurred,Occurred"
bitfld.long 0x04 4. "        CMDINT       ,Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames" "Not occurred,Occurred"
bitfld.long 0x04 3. "                      TXCHUNDR       ,RAW interrupt status" "Not occurred,Occurred"
textline "                       "
bitfld.long 0x04 2. " RXCHOVRF       ,Raw status of receive channel overflow" "Not occurred,Occurred"
bitfld.long 0x04 1. "        RXRDY        ,Receive data ready" "Not occurred,Occurred"
bitfld.long 0x04 0. "                      TXDONE         ,Raw status of transmit done" "Not occurred,Occurred"
group.long 0x28++0x13
line.long 0x00 "CONTROL2,Control bits for enhanced modes"
bitfld.long 0x00 5. " INTEN_SSEND    ,Indicates that SPI_X_SS[x] has gone inactive" "Active,Not active"
bitfld.long 0x00 4. "          INTEN_CMD    ,Indicates that the number of frames set by the CMDSIZE register have been received as a single packet of frames" "No action,Received"
textline "                       "
bitfld.long 0x00 2. " DISFRMCNT      ,The internal frame counter status" "Active,Not active"
bitfld.long 0x00 1. "          AUTOPOLL     ,POLL function" "No effect,Enabled"
bitfld.long 0x00 0. "                         AUTOSTATUS     ,The first transmitted frame (Slave mode) contains the hardware status" "No effect,Enabled"
line.long 0x04 "COMMAND,Command register"
bitfld.long 0x04 6. " TXNOW          ,Writing one clears the TxBUSY bit in Slave mode" "No effect,Clear"
bitfld.long 0x04 5. "           AUTOSTALL    ,Writing one will cause the master to delay transmission until the transmit FIFO contains the number of frames specified by the PKTSIZE register" "No effect,Delay"
bitfld.long 0x04 4. "                         CLRFRAMECNT    ,Writing one clears the internal frame counter" "No effect,Clear"
textline "                       "
bitfld.long 0x04 3. " TXFIFORST      ,Writing one resets the Tx FIFO" "No effect,Reset"
bitfld.long 0x04 2. "           RXFIFORST    ,Writing one resets the Rx FIFO" "No action,Reset"
bitfld.long 0x04 1. "                         AUTOEMPTY      ,Automatic discard received data" "Not effect,Enabled"
textline "                       "
bitfld.long 0x04 0. " AUTOFILL       ,Writing one causes the SPI core to automatically fill the transmit FIFO with zeros to match the number of frames requested in the FRAMECNT register" "No action,Fill"
line.long 0x08 "PKTSIZE,Packet size"
hexmask.long.byte 0x08 0.--7. 1. " PKTSIZE        ,Sets the size of the SPI CMD/data frame"
line.long 0x0c "CMD_SIZE,Command size"
hexmask.long.byte 0x0c 0.--7. 1. " CMDSIZE        ,Number of frames after SPI_SS[0] going active that the CMD interrupt should be generated"
line.long 0x10 "HWSTATUS,Slave hardware status"
bitfld.long 0x10 2.--3. " USER           ,These bits are set by the CPU" "0,1,2,3"
bitfld.long 0x10 1. "                   TXBUSY       ,Transmit Buffer Busy" "Not busy,Busy"
bitfld.long 0x10 0. "                          RXBUSY         ,Receive Buffer Busy" "Not busy,Busy"
rgroup.long 0x3c++0x3
line.long 0x00 "STAT8,Status register"
bitfld.long 0x00 7. " ACTIVE         ,SPI is still transmitting the data" "Not active,Active"
bitfld.long 0x00 6. "          SSEL         ,Current state of SPI_X_SS[0]" "0,1"
bitfld.long 0x00 5. "                                 TXUNDERRUN     ,Transmit FIFO underflowed" "Not underflowed,Underflowed"
textline "                       "
bitfld.long 0x00 4. " RXOVERFLOW     ,Receive FIFO overflowed" "Not overflowed,Overflowed"
bitfld.long 0x00 3. "      TXFIFOFUL    ,Transmit FIFO is full" "Not full,Full"
bitfld.long 0x00 2. "                          RXFIFOEMP      ,Receive FIFO is empty" "Not empty,Empty"
textline "                       "
bitfld.long 0x00 1. " DONE           ,The number of request frames have been transmitted and received" "Not done,Done"
bitfld.long 0x00 0. "            FRAMESTART   ,Next frame in receive FIFO was received after SPI_X_SS[x] went active" "Not started,Started"
group.long 0x40++0xf
line.long 0x00 "CTRL0,Aliased CONTROL register bits 7:0"
line.long 0x04 "CTRL1,Aliased CONTROL register bits 15:8"
line.long 0x08 "CTRL2,Aliased CONTROL register bits 23:16"
line.long 0x0c "CTRL3,Aliased CONTROL register bits 25:24"
tree.end
tree "SPI_1"
base ad:0x40011000
width 14.
group.long 0x00++0x7
line.long 0x00 "CONTROL,Control register"
bitfld.long 0x00 31. " RESET      ,SPI reset" "No reset,Reset"
bitfld.long 0x00 30. "           OENOFF      ,SPI output enable active" "Asserted,Not asserted"
bitfld.long 0x00 29. "                      BIGFIFO     ,Alters FIFO depth when frame size is 4-8 bits" "4 frames,32/16/8"
textline "                       "
bitfld.long 0x00 28. " CLKMODE    ,Specifies the methodology used to calculate the SPICLK divider" "1/(2 CLK_GEN+1),1/(2x(CLK_GEN+1))"
bitfld.long 0x00 27. "  FRAMEURUN   ,Under-run condition" "Generated,Ignored"
bitfld.long 0x00 26. "                         SPS         ,Define slave select behavior" "Low,High"
textline "                       "
bitfld.long 0x00 25. " SPH        ,Clock phase" "Low,High"
bitfld.long 0x00 24. "               SPO         ,Clock polarity" "Low,High"
hexmask.long.word 0x00 8.--23. 1. "                              TXRXDFCOUNT ,Number of data frames to be sent or received"
textline "                       "
bitfld.long 0x00 7. " INTTXTURUN ,Interrupt on transmit the under-run" "Disabled,Enabled"
bitfld.long 0x00 6. "           INTRXOVRFLO ,Interrupt on receive overflow" "Disabled,Enabled"
bitfld.long 0x00 5. "                          INTTXDATA   ,Interrupt on transmit data" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 4. " INTRXDATA  ,Interrupt on receive data" "Reserved,?..."
bitfld.long 0x00 2.--3. "           TRANSFPRTL  ,Transfer protocol" "Motorola SPI,TI synchronous serial,National Semiconductor MICROWIRE,?..."
bitfld.long 0x00 1. "  MODE        ,SPI implementation" "Slave,Master"
textline "                       "
bitfld.long 0x00 0. " ENABLE     ,Core enable" "Disabled,Enabled"
line.long 0x04 "TXRXDF_SIZE,Transmit and receive data frame size"
bitfld.long 0x04 0.--5. " TXRXDFS    ,Transmit and receive data size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
rgroup.long 0x8++0x3
line.long 0x00 "STATUS,Status register"
bitfld.long 0x00 14. " ACTIVE         ,SPI is still transmitting or receiving data" "Not transmitting,Still transmitting"
bitfld.long 0x00 13. "  SSEL         ,Current state of SPI_X_SS[0]" "0,1"
bitfld.long 0x00 12. "                                 FRAMESTART     ,SPI output enable" "Active as required,Not asserted"
textline "                       "
bitfld.long 0x00 11. " TXFIFOEMPNXT   ,Transmit FIFO empty on next read" "Not empty,Empty on next read"
bitfld.long 0x00 10. "  TXFIFOEMP    ,Transmit FIFO is empty" "Not empty,Empty"
bitfld.long 0x00 9. "                         TXFIFOFULNXT   ,Transmit FIFO full on next write" "Not full,Full on next write"
textline "                       "
bitfld.long 0x00 8. " TXFIFOFUL      ,Transmit FIFO is full" "Not full,Full"
bitfld.long 0x00 7. "            RXFIFOEMPNXT ,Receive FIFO empty on next read" "Not empty,Empty on next read"
bitfld.long 0x00 6. "                RXFIFOEMP      ,Receive FIFO empty" "Not empty,Empty"
textline "                       "
bitfld.long 0x00 5. " RXFIFOFULNXT   ,Receive FIFO full on next write" "Not full,Full on next write"
bitfld.long 0x00 4. "  RXFIFOFUL    ,Receive FIFO is full" "Not full,Full"
bitfld.long 0x00 3. "                          TXUNDERRUN     ,No data available for transmission" "No action,FIFO is empty"
textline "                       "
bitfld.long 0x00 2. " RXOVERFLOW     ,Channel is unable to write to receive FIFO as it is full." "No action,Overflow"
bitfld.long 0x00 1. "           RXDATRCED    ,When set it indicates that, the number of frames specified by TxRXDFCOUNT have been received and can be read" "No action,Received"
bitfld.long 0x00 0. "                         TXDATSENT      ,When set it indicates that, the numbers of frames specified by TxRXDFCOUNT have been sent" "No action,Sent"
wgroup.long 0xc++0x3
line.long 0x00 "INT_CLEAR,Interrupt clear register"
bitfld.long 0x00 5. " SSEND          ,Write one to clear the interrupt" "No effect,Clear"
bitfld.long 0x00 4. "           CMDINT       ,Write one to clear the interrupt" "No effect,Clear"
bitfld.long 0x00 3. "                         TXCHUNDRUN     ,No data available for transmission" "No effect,Clear"
textline "                       "
bitfld.long 0x00 2. " RXCHOVRFLW     ,Receive channel over flow" "No effect,Clear"
bitfld.long 0x00 1. "           RXRDYCLR     ,Clears receive ready" "No effect,Clear"
bitfld.long 0x00 0. "                         TXDONECLR      ,Clears transmit done" "No effect,Clear"
hgroup.long 0x10++0x3
hide.long 0x00 "RX_DATA,Receive data register"
in
wgroup.long 0x14++0x03
line.long 0x00 "TX_DATA,Transmit data register"
group.long 0x18++0x7
line.long 0x00 "CLK_GEN,Output clock generator"
hexmask.long.byte 0x00 0.--7. 1. " CLK_GEN        ,Specifies the methodology used to calculate the SPICLK divider"
line.long 0x04 "SLAVE_SELECT,Specifies slave selected"
bitfld.long 0x04 7. " SLAVE_SEL7     ,Slave select" "Not selected,Selected"
bitfld.long 0x04 6. "        SLAVE_SEL6   ,Slave select" "Not selected,Selected"
bitfld.long 0x04 5. "                      SLAVE_SEL5     ,Slave select" "Not selected,Selected"
textline "                       "
bitfld.long 0x04 4. " SLAVE_SEL4     ,Slave select" "Not selected,Selected"
bitfld.long 0x04 3. "        SLAVE_SEL3   ,Slave select" "Not selected,Selected"
bitfld.long 0x04 2. "                      SLAVE_SEL2     ,Slave select" "Not selected,Selected"
textline "                       "
bitfld.long 0x04 1. " SLAVE_SEL1     ,Slave select" "Not selected,Selected"
bitfld.long 0x04 0. "        SLAVE_SEL0   ,Slave select" "Not selected,Selected"
rgroup.long 0x20++0x7
line.long 0x00 "MIS,Masked interrupt status"
bitfld.long 0x00 5. " SSEND          ,Equals RIS[5] and CONTROL2[5]" "Masked,Not masked"
bitfld.long 0x00 4. "          CMDINT       ,Equals RIS[4] and CONTROL2[4]" "Masked,Not masked"
bitfld.long 0x00 3. "                        TXCHUNDDMSKINT ,Masked interrupt status" "Masked,Not masked"
textline "                       "
bitfld.long 0x00 2. " RXCHOVRFMSKINT ,Masked status of receive channel overflow" "Masked,Not masked"
bitfld.long 0x00 1. "          RXRDYMSKINT  ,Masked status of receive data ready" "Masked,Not masked"
bitfld.long 0x00 0. "                        TXDONEMSKINT   ,Masked status of transmit done" "Masked,Not masked"
line.long 0x04 "RIS,Raw interrupt status"
bitfld.long 0x04 5. " SSEND          ,Indicates that SPI_X_SS[x] has gone inactive" "Not occurred,Occurred"
bitfld.long 0x04 4. "        CMDINT       ,Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames" "Not occurred,Occurred"
bitfld.long 0x04 3. "                      TXCHUNDR       ,RAW interrupt status" "Not occurred,Occurred"
textline "                       "
bitfld.long 0x04 2. " RXCHOVRF       ,Raw status of receive channel overflow" "Not occurred,Occurred"
bitfld.long 0x04 1. "        RXRDY        ,Receive data ready" "Not occurred,Occurred"
bitfld.long 0x04 0. "                      TXDONE         ,Raw status of transmit done" "Not occurred,Occurred"
group.long 0x28++0x13
line.long 0x00 "CONTROL2,Control bits for enhanced modes"
bitfld.long 0x00 5. " INTEN_SSEND    ,Indicates that SPI_X_SS[x] has gone inactive" "Active,Not active"
bitfld.long 0x00 4. "          INTEN_CMD    ,Indicates that the number of frames set by the CMDSIZE register have been received as a single packet of frames" "No action,Received"
textline "                       "
bitfld.long 0x00 2. " DISFRMCNT      ,The internal frame counter status" "Active,Not active"
bitfld.long 0x00 1. "          AUTOPOLL     ,POLL function" "No effect,Enabled"
bitfld.long 0x00 0. "                         AUTOSTATUS     ,The first transmitted frame (Slave mode) contains the hardware status" "No effect,Enabled"
line.long 0x04 "COMMAND,Command register"
bitfld.long 0x04 6. " TXNOW          ,Writing one clears the TxBUSY bit in Slave mode" "No effect,Clear"
bitfld.long 0x04 5. "           AUTOSTALL    ,Writing one will cause the master to delay transmission until the transmit FIFO contains the number of frames specified by the PKTSIZE register" "No effect,Delay"
bitfld.long 0x04 4. "                         CLRFRAMECNT    ,Writing one clears the internal frame counter" "No effect,Clear"
textline "                       "
bitfld.long 0x04 3. " TXFIFORST      ,Writing one resets the Tx FIFO" "No effect,Reset"
bitfld.long 0x04 2. "           RXFIFORST    ,Writing one resets the Rx FIFO" "No action,Reset"
bitfld.long 0x04 1. "                         AUTOEMPTY      ,Automatic discard received data" "Not effect,Enabled"
textline "                       "
bitfld.long 0x04 0. " AUTOFILL       ,Writing one causes the SPI core to automatically fill the transmit FIFO with zeros to match the number of frames requested in the FRAMECNT register" "No action,Fill"
line.long 0x08 "PKTSIZE,Packet size"
hexmask.long.byte 0x08 0.--7. 1. " PKTSIZE        ,Sets the size of the SPI CMD/data frame"
line.long 0x0c "CMD_SIZE,Command size"
hexmask.long.byte 0x0c 0.--7. 1. " CMDSIZE        ,Number of frames after SPI_SS[0] going active that the CMD interrupt should be generated"
line.long 0x10 "HWSTATUS,Slave hardware status"
bitfld.long 0x10 2.--3. " USER           ,These bits are set by the CPU" "0,1,2,3"
bitfld.long 0x10 1. "                   TXBUSY       ,Transmit Buffer Busy" "Not busy,Busy"
bitfld.long 0x10 0. "                          RXBUSY         ,Receive Buffer Busy" "Not busy,Busy"
rgroup.long 0x3c++0x3
line.long 0x00 "STAT8,Status register"
bitfld.long 0x00 7. " ACTIVE         ,SPI is still transmitting the data" "Not active,Active"
bitfld.long 0x00 6. "          SSEL         ,Current state of SPI_X_SS[0]" "0,1"
bitfld.long 0x00 5. "                                 TXUNDERRUN     ,Transmit FIFO underflowed" "Not underflowed,Underflowed"
textline "                       "
bitfld.long 0x00 4. " RXOVERFLOW     ,Receive FIFO overflowed" "Not overflowed,Overflowed"
bitfld.long 0x00 3. "      TXFIFOFUL    ,Transmit FIFO is full" "Not full,Full"
bitfld.long 0x00 2. "                          RXFIFOEMP      ,Receive FIFO is empty" "Not empty,Empty"
textline "                       "
bitfld.long 0x00 1. " DONE           ,The number of request frames have been transmitted and received" "Not done,Done"
bitfld.long 0x00 0. "            FRAMESTART   ,Next frame in receive FIFO was received after SPI_X_SS[x] went active" "Not started,Started"
group.long 0x40++0xf
line.long 0x00 "CTRL0,Aliased CONTROL register bits 7:0"
line.long 0x04 "CTRL1,Aliased CONTROL register bits 15:8"
line.long 0x08 "CTRL2,Aliased CONTROL register bits 23:16"
line.long 0x0c "CTRL3,Aliased CONTROL register bits 25:24"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
tree "I2C_0"
base ad:0x40002000
width 11.
group.long 0x00++0x3
line.long 0x00 "CTRL,Control Register"
bitfld.long 0x00 6. " ENS1     ,Enable bit" "Disabled,I2C Enabled"
bitfld.long 0x00 5. "   STA     ,The Start flag" "Not occurred,Occurred"
bitfld.long 0x00 4. "  STO     ,The Stop flag" "Not occurred,Occurred"
bitfld.long 0x00 3. "  SI     ,The SI flag" "Not occurred,Occurred"
textline "                    "
bitfld.long 0x00 2. " AA     ,The assert acknowledge flag" "Not occurred,Occurred"
bitfld.long 0x00 0.--1. 7. "  CR     ,Serial clock" "/256,/224,/192,/160,/960,/120,/60,/8"
rgroup.long 0x04++0x3
line.long 0x00 "STATUS,Status Register"
hexmask.long.byte 0x00 0.--7. 1. " SR                ,Status Register"
group.long 0x08++0x17
line.long 0x00 "DATA,Data Register"
bitfld.long 0x00 7. " SD7               ,Serial data bit 7 / address bit 6" "0,1"
bitfld.long 0x00 6. "             SD6              ,Serial data bit 6 / address bit 5" "0,1"
bitfld.long 0x00 5. "          SD5             ,Serial data bit 5 / address bit 4" "0,1"
bitfld.long 0x00 4. "          SD4                ,Serial data bit 4 / address bit 3" "0,1"
textline "                    "
bitfld.long 0x00 3. " SD3               ,Serial data bit 3 / address bit 2" "0,1"
bitfld.long 0x00 2. "             SD2              ,Serial data bit 2 / address bit 1" "0,1"
bitfld.long 0x00 1. "          SD1             ,Serial data bit 1 / address bit 0" "0,1"
bitfld.long 0x00 0. "          SD0                ,Serial data bit 0 / address direction bit" "0,1"
line.long 0x04 "SLAVE0ADR,Slave 0 Address Register"
bitfld.long 0x04 7. " ADR6              ,Own Slave0 address bit 7" "0,1"
bitfld.long 0x04 6. "             ADR5             ,Own Slave0 address bit 6" "0,1"
bitfld.long 0x04 5. "          ADR4            ,Own Slave0 address bit 5" "0,1"
bitfld.long 0x04 4. "          ADR3               ,Own Slave0 address bit 4" "0,1"
textline "                    "
bitfld.long 0x04 3. " ADR2              ,Own Slave0 address bit 3" "0,1"
bitfld.long 0x04 2. "             ADR1             ,Own Slave0 address bit 2" "0,1"
bitfld.long 0x04 1. "          ADR0            ,Own Slave0 address bit 1" "0,1"
bitfld.long 0x04 0. "          GC                 ,General call (GC) address acknowledge" "Ignored,Recognized"
line.long 0x08 "SMBUS,SMBus register"
bitfld.long 0x08 7. " SMBUSRESET        ,SMBus Reset" "Not reset,Reset"
bitfld.long 0x08 6. "     SMBSUS_NOCONTROL ,SMBus No control" "Disabled,Enabled"
bitfld.long 0x08 5. "   SMBSUS_NISTATUS ,Status of SMBSUS_NI signal" "Stopped,Resume"
bitfld.long 0x08 4. "    SMBALERT_NOCONTROL ,SMBALERT_NO control" "Disabled,Enabled"
textline "                    "
bitfld.long 0x08 3. " SMBALERT_NISTATUS ,Status of SMBALERT_NI signal" "0,1"
bitfld.long 0x08 2. "             SMBUS_ENABLE     ,SMBus timeouts and status logic enabled" "Disabled,Enabled"
bitfld.long 0x08 1.    "   SMBSUS_INT_EN   ,SMBSUS interrupt signal (SMBS) enabled" "Disabled,Enabled"
bitfld.long 0x08 0. "   SMBALERT_INT_EN    ,SMBALERT interrupt signal (SMBA) enabled" "Disabled,Enabled"
line.long 0x0c "FREQ,Frequency Register"
hexmask.long.byte 0x0c 0.--7. 1. " FREQ              ,PCLKx frequency in MHz from 1 to 255"
line.long 0x10 "GLITCHREG,Glitch Register"
hexmask.long.byte 0x10 0.--7. 1. " GLITCHREG_NUM     ,This read/write register is used to adjust the input glitch filter length"
line.long 0x14 "SLAVE1ADR,Slave1 Address Register"
bitfld.long 0x14 7. " ADR6              ,Own Slave1 address bit 7" "0,1"
bitfld.long 0x14 6. "             ADR5             ,Own Slave1 address bit 6" "0,1"
bitfld.long 0x14 5. "          ADR4            ,Own Slave1 address bit 5" "0,1"
bitfld.long 0x14 4. "          ADR3               ,Own Slave1 address bit 4" "0,1"
textline "                    "
bitfld.long 0x14 3. " ADR2              ,Own Slave1 address bit 3" "0,1"
bitfld.long 0x14 2. "             ADR1             ,Own Slave1 address bit 2" "0,1"
bitfld.long 0x14 1. "          ADR0            ,Own Slave1 address bit 1" "0,1"
bitfld.long 0x14 0. "        ENADR,Slave1 Address Comparisons Enable" "Disabled,Enabled"
width 0xb
tree.end
tree "I2C_1"
base ad:0x40012000
width 11.
group.long 0x00++0x3
line.long 0x00 "CTRL,Control Register"
bitfld.long 0x00 6. " ENS1     ,Enable bit" "Disabled,I2C Enabled"
bitfld.long 0x00 5. "   STA     ,The Start flag" "Not occurred,Occurred"
bitfld.long 0x00 4. "  STO     ,The Stop flag" "Not occurred,Occurred"
bitfld.long 0x00 3. "  SI     ,The SI flag" "Not occurred,Occurred"
textline "                    "
bitfld.long 0x00 2. " AA     ,The assert acknowledge flag" "Not occurred,Occurred"
bitfld.long 0x00 0.--1. 7. "  CR     ,Serial clock" "/256,/224,/192,/160,/960,/120,/60,/8"
rgroup.long 0x04++0x3
line.long 0x00 "STATUS,Status Register"
hexmask.long.byte 0x00 0.--7. 1. " SR                ,Status Register"
group.long 0x08++0x17
line.long 0x00 "DATA,Data Register"
bitfld.long 0x00 7. " SD7               ,Serial data bit 7 / address bit 6" "0,1"
bitfld.long 0x00 6. "             SD6              ,Serial data bit 6 / address bit 5" "0,1"
bitfld.long 0x00 5. "          SD5             ,Serial data bit 5 / address bit 4" "0,1"
bitfld.long 0x00 4. "          SD4                ,Serial data bit 4 / address bit 3" "0,1"
textline "                    "
bitfld.long 0x00 3. " SD3               ,Serial data bit 3 / address bit 2" "0,1"
bitfld.long 0x00 2. "             SD2              ,Serial data bit 2 / address bit 1" "0,1"
bitfld.long 0x00 1. "          SD1             ,Serial data bit 1 / address bit 0" "0,1"
bitfld.long 0x00 0. "          SD0                ,Serial data bit 0 / address direction bit" "0,1"
line.long 0x04 "SLAVE0ADR,Slave 0 Address Register"
bitfld.long 0x04 7. " ADR6              ,Own Slave0 address bit 7" "0,1"
bitfld.long 0x04 6. "             ADR5             ,Own Slave0 address bit 6" "0,1"
bitfld.long 0x04 5. "          ADR4            ,Own Slave0 address bit 5" "0,1"
bitfld.long 0x04 4. "          ADR3               ,Own Slave0 address bit 4" "0,1"
textline "                    "
bitfld.long 0x04 3. " ADR2              ,Own Slave0 address bit 3" "0,1"
bitfld.long 0x04 2. "             ADR1             ,Own Slave0 address bit 2" "0,1"
bitfld.long 0x04 1. "          ADR0            ,Own Slave0 address bit 1" "0,1"
bitfld.long 0x04 0. "          GC                 ,General call (GC) address acknowledge" "Ignored,Recognized"
line.long 0x08 "SMBUS,SMBus register"
bitfld.long 0x08 7. " SMBUSRESET        ,SMBus Reset" "Not reset,Reset"
bitfld.long 0x08 6. "     SMBSUS_NOCONTROL ,SMBus No control" "Disabled,Enabled"
bitfld.long 0x08 5. "   SMBSUS_NISTATUS ,Status of SMBSUS_NI signal" "Stopped,Resume"
bitfld.long 0x08 4. "    SMBALERT_NOCONTROL ,SMBALERT_NO control" "Disabled,Enabled"
textline "                    "
bitfld.long 0x08 3. " SMBALERT_NISTATUS ,Status of SMBALERT_NI signal" "0,1"
bitfld.long 0x08 2. "             SMBUS_ENABLE     ,SMBus timeouts and status logic enabled" "Disabled,Enabled"
bitfld.long 0x08 1.    "   SMBSUS_INT_EN   ,SMBSUS interrupt signal (SMBS) enabled" "Disabled,Enabled"
bitfld.long 0x08 0. "   SMBALERT_INT_EN    ,SMBALERT interrupt signal (SMBA) enabled" "Disabled,Enabled"
line.long 0x0c "FREQ,Frequency Register"
hexmask.long.byte 0x0c 0.--7. 1. " FREQ              ,PCLKx frequency in MHz from 1 to 255"
line.long 0x10 "GLITCHREG,Glitch Register"
hexmask.long.byte 0x10 0.--7. 1. " GLITCHREG_NUM     ,This read/write register is used to adjust the input glitch filter length"
line.long 0x14 "SLAVE1ADR,Slave1 Address Register"
bitfld.long 0x14 7. " ADR6              ,Own Slave1 address bit 7" "0,1"
bitfld.long 0x14 6. "             ADR5             ,Own Slave1 address bit 6" "0,1"
bitfld.long 0x14 5. "          ADR4            ,Own Slave1 address bit 5" "0,1"
bitfld.long 0x14 4. "          ADR3               ,Own Slave1 address bit 4" "0,1"
textline "                    "
bitfld.long 0x14 3. " ADR2              ,Own Slave1 address bit 3" "0,1"
bitfld.long 0x14 2. "             ADR1             ,Own Slave1 address bit 2" "0,1"
bitfld.long 0x14 1. "          ADR0            ,Own Slave1 address bit 1" "0,1"
bitfld.long 0x14 0. "        ENADR,Slave1 Address Comparisons Enable" "Disabled,Enabled"
width 0xb
tree.end
tree.end
tree "GPIO (General Purpose Input/Output)"
base ad:0x40013000
width 12.
group.long 0x00++0x83
line.long 0x0 "GPIO_0_CFG,GPIO Configuration register for bit 0"
bitfld.long 0x0 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x0 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x0 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x0 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x0 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x4 "GPIO_1_CFG,GPIO Configuration register for bit 1"
bitfld.long 0x4 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x4 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x4 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x4 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x4 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x8 "GPIO_2_CFG,GPIO Configuration register for bit 2"
bitfld.long 0x8 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x8 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x8 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x8 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x8 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0xC "GPIO_3_CFG,GPIO Configuration register for bit 3"
bitfld.long 0xC 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0xC 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0xC 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0xC 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0xC 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x10 "GPIO_4_CFG,GPIO Configuration register for bit 4"
bitfld.long 0x10 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x10 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x10 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x14 "GPIO_5_CFG,GPIO Configuration register for bit 5"
bitfld.long 0x14 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x14 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x14 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x14 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x18 "GPIO_6_CFG,GPIO Configuration register for bit 6"
bitfld.long 0x18 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x18 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x18 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x18 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x18 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x1C "GPIO_7_CFG,GPIO Configuration register for bit 7"
bitfld.long 0x1C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x1C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x1C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x1C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x1C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x20 "GPIO_8_CFG,GPIO Configuration register for bit 8"
bitfld.long 0x20 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x20 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x20 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x20 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x24 "GPIO_9_CFG,GPIO Configuration register for bit 9"
bitfld.long 0x24 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x24 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x24 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x24 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x24 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x28 "GPIO_10_CFG,GPIO Configuration register for bit 10"
bitfld.long 0x28 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x28 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x28 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x28 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x28 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x2C "GPIO_11_CFG,GPIO Configuration register for bit 11"
bitfld.long 0x2C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x2C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x2C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x2C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x2C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x30 "GPIO_12_CFG,GPIO Configuration register for bit 12"
bitfld.long 0x30 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x30 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x30 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x30 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x30 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x34 "GPIO_13_CFG,GPIO Configuration register for bit 13"
bitfld.long 0x34 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x34 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x34 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x34 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x34 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x38 "GPIO_14_CFG,GPIO Configuration register for bit 14"
bitfld.long 0x38 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x38 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x38 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x38 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x38 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x3C "GPIO_15_CFG,GPIO Configuration register for bit 15"
bitfld.long 0x3C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x3C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x3C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x3C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x3C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x40 "GPIO_16_CFG,GPIO Configuration register for bit 16"
bitfld.long 0x40 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x40 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x40 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x40 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x40 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x44 "GPIO_17_CFG,GPIO Configuration register for bit 17"
bitfld.long 0x44 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x44 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x44 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x44 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x44 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x48 "GPIO_18_CFG,GPIO Configuration register for bit 18"
bitfld.long 0x48 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x48 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x48 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x48 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x48 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x4C "GPIO_19_CFG,GPIO Configuration register for bit 19"
bitfld.long 0x4C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x4C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x4C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x4C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x4C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x50 "GPIO_20_CFG,GPIO Configuration register for bit 20"
bitfld.long 0x50 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x50 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x50 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x50 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x50 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x54 "GPIO_21_CFG,GPIO Configuration register for bit 21"
bitfld.long 0x54 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x54 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x54 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x54 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x54 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x58 "GPIO_22_CFG,GPIO Configuration register for bit 22"
bitfld.long 0x58 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x58 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x58 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x58 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x58 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x5C "GPIO_23_CFG,GPIO Configuration register for bit 23"
bitfld.long 0x5C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x5C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x5C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x5C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x5C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x60 "GPIO_24_CFG,GPIO Configuration register for bit 24"
bitfld.long 0x60 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x60 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x60 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x60 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x60 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x64 "GPIO_25_CFG,GPIO Configuration register for bit 25"
bitfld.long 0x64 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x64 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x64 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x64 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x64 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x68 "GPIO_26_CFG,GPIO Configuration register for bit 26"
bitfld.long 0x68 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x68 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x68 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x68 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x68 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x6C "GPIO_27_CFG,GPIO Configuration register for bit 27"
bitfld.long 0x6C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x6C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x6C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x6C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x6C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x70 "GPIO_28_CFG,GPIO Configuration register for bit 28"
bitfld.long 0x70 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x70 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x70 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x70 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x70 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x74 "GPIO_29_CFG,GPIO Configuration register for bit 29"
bitfld.long 0x74 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x74 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x74 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x74 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x74 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x78 "GPIO_30_CFG,GPIO Configuration register for bit 30"
bitfld.long 0x78 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x78 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x78 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x78 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x78 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x7C "GPIO_31_CFG,GPIO Configuration register for bit 31"
bitfld.long 0x7C 5.--7. " GPIOINT_TYPE ,Input Interrupt Type Configuration" "Level High,Level Low,Positive edge,Negative edge,Both edges,?..."
bitfld.long 0x7C 3. "  GPINTEN ,GPI interrupt enable" "Disabled,Enabled"
bitfld.long 0x7C 2. "  GPO_OUTBUFEN ,GPO output buffer enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x7C 1. " GPINEN       ,GPI register enable" "Disabled,Enabled"
bitfld.long 0x7C 0. "       GPOUTEN ,GPU register enable" "Disabled,Enabled"
line.long 0x80 "GPIO_IRQ,Interrupt Status register"
rgroup.long 0x84++0x03
line.long 0x00 "GPIO_IN,Read only bits for ports configured as inputs"
group.long 0x88++0x03
line.long 0x00 "GPIO_OUT,Read/write bits for ports configured as outputs"
width 0xB
tree.end
tree "COMM_BLK (Communication Block)"
base ad:0x40016000
width 15.
group.long 0x00++0xb
line.long 0x00 "CONTROL,Control register"
bitfld.long 0x00 5. " LOOPBACK     ,All the COM interface received data is sent back via the transmit channel" "Disabled,Enabled"
bitfld.long 0x00 4. "      ENABLE   ,Enable transfers on the COMM_BLK interface" "Disabled,Enabled"
bitfld.long 0x00 3. "      SIZERX    ,Sets the number of bytes that each APB transfer reads from the RX FIFO" "1 Byte,4 Bytes"
bitfld.long 0x00 2. "       SIZETX  ,Sets the number of bytes that each APB transfer writes into the TX FIFO" "1 Byte,4 Bytes"
textline "                        "
bitfld.long 0x00 1. " FLUSHIN      ,Indicates FIFO flush status. '1' indicates flush process is in progress" "Completed,In progress"
bitfld.long 0x00 0. "   FLUSHOUT ,Flush all FIFOs" "Completed,Started"
line.long 0x04 "STATUS,Status register"
eventfld.long 0x04 7. " COMMAND      ,First byte queued in receive FIFO has the command marker set" "Not occurred,Occurred"
eventfld.long 0x04 6. "  SIIERROR ,The start of frame marker is set on one or more of the bytes" "Not occurred,Occurred"
eventfld.long 0x04 5. "  FLUSHRCVD ,Indicates that a FLUSH has been received" "Not occurred,Occurred"
eventfld.long 0x04 4. "  SIIDONE ,Indicated that the transfer to SII Bus is complete" "Not occurred,Occurred"
textline "                        "
eventfld.long 0x04 3. " UNDERFLOW    ,The receive FIFO was read when empty" "Not occurred,Occurred"
eventfld.long 0x04 2. "  OVERFLOW ,Transmit Overflow. Indicates that the Transmit FIFO was written when full" "Not occurred,Occurred"
rbitfld.long 0x04 1. "  RCVOKAY   ,RCV FIFO non empty" "Not occurred,Occurred"
rbitfld.long 0x04 0. "  TXTOKAY ,TXT FIFO non full" "Not occurred,Occurred"
line.long 0x08 "INT_ENABLE,Interrupt enable"
bitfld.long 0x08 7. " ENCOMMAND    ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 6. "      ENSIIERR ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 5. "      ENFLUSH   ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 4. "      ENASIID ,Enabled interrupt" "Disabled,Enabled"
textline "                        "
bitfld.long 0x08 3. " ENUNDERF     ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 2. "      ENOVERF  ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 1. "      ENRCV     ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 0. "      ENTXTOK ,Enabled interrupt" "Disabled,Enabled"
group.long 0x10++0xf
line.long 0x00 "DATA8,Byte Data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA8        ,This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO"
line.long 0x04 "DATA32,Word Data register"
line.long 0x08 "FRAME_START8,Frame/Command Byte register"
hexmask.long.byte 0x08 0.--7. 1. " FRAME_START8 ,This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO"
line.long 0x0c "FRAME_START32,Frame/Command Word register"
width 0xb
tree.end
tree "RTC (Real-Time Counter)"
base ad:0x40017000
width 15.
group.long 0x00++0xb
line.long 0x00 "CONTROL,Control register"
bitfld.long 0x00 5. " LOOPBACK     ,All the COM interface received data is sent back via the transmit channel" "Disabled,Enabled"
bitfld.long 0x00 4. "      ENABLE   ,Enable transfers on the COMM_BLK interface" "Disabled,Enabled"
bitfld.long 0x00 3. "      SIZERX    ,Sets the number of bytes that each APB transfer reads from the RX FIFO" "1 Byte,4 Bytes"
bitfld.long 0x00 2. "       SIZETX  ,Sets the number of bytes that each APB transfer writes into the TX FIFO" "1 Byte,4 Bytes"
textline "                        "
bitfld.long 0x00 1. " FLUSHIN      ,Indicates FIFO flush status. '1' indicates flush process is in progress" "Completed,In progress"
bitfld.long 0x00 0. "   FLUSHOUT ,Flush all FIFOs" "Completed,Started"
line.long 0x04 "STATUS,Status register"
eventfld.long 0x04 7. " COMMAND      ,First byte queued in receive FIFO has the command marker set" "Not occurred,Occurred"
eventfld.long 0x04 6. "  SIIERROR ,The start of frame marker is set on one or more of the bytes" "Not occurred,Occurred"
eventfld.long 0x04 5. "  FLUSHRCVD ,Indicates that a FLUSH has been received" "Not occurred,Occurred"
eventfld.long 0x04 4. "  SIIDONE ,Indicated that the transfer to SII Bus is complete" "Not occurred,Occurred"
textline "                        "
eventfld.long 0x04 3. " UNDERFLOW    ,The receive FIFO was read when empty" "Not occurred,Occurred"
eventfld.long 0x04 2. "  OVERFLOW ,Transmit Overflow. Indicates that the Transmit FIFO was written when full" "Not occurred,Occurred"
rbitfld.long 0x04 1. "  RCVOKAY   ,RCV FIFO non empty" "Not occurred,Occurred"
rbitfld.long 0x04 0. "  TXTOKAY ,TXT FIFO non full" "Not occurred,Occurred"
line.long 0x08 "INT_ENABLE,Interrupt enable"
bitfld.long 0x08 7. " ENCOMMAND    ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 6. "      ENSIIERR ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 5. "      ENFLUSH   ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 4. "      ENASIID ,Enabled interrupt" "Disabled,Enabled"
textline "                        "
bitfld.long 0x08 3. " ENUNDERF     ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 2. "      ENOVERF  ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 1. "      ENRCV     ,Enabled interrupt" "Disabled,Enabled"
bitfld.long 0x08 0. "      ENTXTOK ,Enabled interrupt" "Disabled,Enabled"
group.long 0x10++0xf
line.long 0x00 "DATA8,Byte Data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA8        ,This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO"
line.long 0x04 "DATA32,Word Data register"
line.long 0x08 "FRAME_START8,Frame/Command Byte register"
hexmask.long.byte 0x08 0.--7. 1. " FRAME_START8 ,This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO"
line.long 0x0c "FRAME_START32,Frame/Command Word register"
width 0xb
tree.end
tree "ST (System timer)"
base ad:0x40004000
width 19.
rgroup.long 0x0++0x03
line.long 0x00 "TIM1_VAL,Current value of Timer 1"
group.long (0x0+0x04)++0xf
line.long 0x00 "TIM1_LOADVAL,Load value for Timer 1"
line.long 0x04 "TIM1_BGLOADVAL,Background load value for Timer 1"
line.long 0x8 "TIM1_CTRL,Control register for Timer 1"
bitfld.long 0x08 2. " TIM1INTEN ,Timer 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x08 1. "         TIM1MODE ,Timer 1 mode" "Periodic mode,One-shot mode"
bitfld.long 0x08 0. "  TIM1ENABLE ,Timer 1 enable" "Disabled,Enabled"
line.long 0xc "TIM1_RIS,Timer 1 raw interrupt status"
bitfld.long 0xc 0. " TIM1_RIS  ,Timer 1 raw interrupt status" "Not reached 0,Reached 0"
rgroup.long (0x0+0x14)++0x3
line.long 0x00 "TIM1_MIS,Timer 1 masked interrupt status"
bitfld.long 0x00 0. " TIM1_MIS  ,Timer 1 masked interrupt status" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "TIM2_VAL,Current value of Timer 2"
group.long (0x18+0x04)++0xf
line.long 0x00 "TIM2_LOADVAL,Load value for Timer 2"
line.long 0x04 "TIM2_BGLOADVAL,Background load value for Timer 2"
line.long 0x8 "TIM2_CTRL,Control register for Timer 2"
bitfld.long 0x08 2. " TIM2INTEN ,Timer 2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x08 1. "         TIM2MODE ,Timer 2 mode" "Periodic mode,One-shot mode"
bitfld.long 0x08 0. "  TIM2ENABLE ,Timer 2 enable" "Disabled,Enabled"
line.long 0xc "TIM2_RIS,Timer 2 raw interrupt status"
bitfld.long 0xc 0. " TIM2_RIS  ,Timer 2 raw interrupt status" "Not reached 0,Reached 0"
rgroup.long (0x18+0x14)++0x3
line.long 0x00 "TIM2_MIS,Timer 2 masked interrupt status"
bitfld.long 0x00 0. " TIM2_MIS  ,Timer 2 masked interrupt status" "0,1"
rgroup.long 0x30++0x7
line.long 0x00 "TIM64_VAL_U,Upper 32-bit word for 64-bit mode"
line.long 0x04 "TIM64_VAL_L,Lower 32-bit word for 64-bit mode"
group.long 0x38++0x17
line.long 0x00 "TIM64_LOADVAL_U,Upper 32-bit word for 64-bit mode immediate load"
line.long 0x04 "TIM64_LOADVAL_L,Lower 32-bit word for 64-bit mode immediate load"
line.long 0x08 "TIM64_BGLOADVAL_U,Upper 32-bit word for background value for 64-bit mode"
line.long 0x0c "TIM64_BGLOADVAL_L,Lower 32-bit word for background value for 64-bit mode"
line.long 0x10 "TIM64_CTRL,Control register for 64-bit mode"
bitfld.long 0x10 2. " TIM64INTEN ,Timer 64 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 1. "         TIM64MODE ,Timer 64 mode" "Periodic mode,One-shot mode"
bitfld.long 0x10 0. "  TIM64ENABLE ,Timer 64 enable" "Disabled,Enabled"
line.long 0x14 "TIM64_RIS,Raw interrupt status for 64-bit mode"
bitfld.long 0x14 0. " TIM64_RIS  ,Timer 64 raw interrupt status" "Not reached 0,Reached 0"
rgroup.long 0x50++0x3
line.long 0x00 "TIM64_MIS,Masked interrupt status for 64-bit mode"
bitfld.long 0x00 0. " TIM64_MIS  ,Timer 64 masked interrupt status" "0,1"
group.long 0x54++0x3
line.long 0x00 "TIM64_MODE,System timer dual 32-bit or 64-bit"
bitfld.long 0x00 0. " TIM64_MODE ,Timer 64 mode" "Disabled,Enabled"
width 0xb
tree.end
tree "WD (Watchdog Timer)"
base ad:0x40005000
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "WDOGVALUE,Current value of counter"
group.long 0x04++0x07
line.long 0x00 "WDOGLOAD,Load value for counter"
line.long 0x04 "WDOGMVRP,Maximum value for which refreshing is permitted"
wgroup.long 0x0C++0x03
line.long 0x00 "WDOGREFRESH,Causes the counter to be refreshed with the value in the WDOGLOAD register"
group.long 0x10++0x07
line.long 0x00 "WDOGENABLE,Watchdog enable register"
hexmask.long 0x00 1.--31. 1. " DISABLE_KEY   ,Value 0x4C6E55FA clear ENABLE bit"
bitfld.long 0x00 0. "              ENABLE      ,Watchdog enable" "Disabled,Enabled"
line.long 0x04 "WDOGCONTROL,Control register"
bitfld.long 0x04 2. " MODE          ,Watchdog mode of operation" "Reset generated,Interrupt generated"
textline "                       "
bitfld.long 0x04 1. " TIMEOUTINTEN  ,Time out interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 0. "              WAKEUPINTEN ,Wake up interrupt enable" "Disabled,Enabled"
rgroup.long 0x18++0x03
line.long 0x00 "WDOGSTATUS,Watchdog status register"
bitfld.long 0x00 0. " REFRESHSTATUS ,Watchdog freshing status" "Interrupt/Reset,No interrupt/No reset"
group.long 0x1C++0x03
line.long 0x00 "WDOGRIS,Raw interrupt status"
eventfld.long 0x00 1. " WAKEUPRS      ,Raw Status of the WDOGWAKEUPINT interrupt" "0,1"
eventfld.long 0x00 0. "                     TIMEOUTRS   ,Raw Status of the WDOGTIMEOUTINT interrupt" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "WDOGMIS,Masked interrupt status"
bitfld.long 0x00 1. " WAKEUPMS      ,Status of the WDOGWAKEUPINT interrupt" "Not masked,Masked"
bitfld.long 0x00 0. "            TIMEOUTMS   ,Status of the WDOGTIMEOUTINT interrupt" "Not masked,Masked"
width 0xB
tree.end
tree "SYSREG (System Register Block)"
base ad:0x40038000
width 25.
group.long 0x00++0x73
line.long 0x00 "ESRAM_CR,Controls address mapping of the eSRAMs"
bitfld.long 0x00 1. " COM_ESRAM1FWREMAP           ,Remap of embedded SRAMs" "Not remapped,Remapped"
bitfld.long 0x00 0. "                 COM_ESRAMFWREMAP            ,Remap of embedded SRAMs" "Not remapped,Remapped"
line.long 0x04 "ESRAM_MAX_LAT,Defines the maximum number of processor cycles"
bitfld.long 0x04 3.--5. " SW_MAX_LAT_ESRAM1           ,Maximum number of cycles the processor bus will wait for eSRAM1" "8,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. "                            SW_MAX_LAT_ESRAM0           ,Maximum number of cycles the processor bus will wait for eSRAM0" "8,1,2,3,4,5,6,7"
line.long 0x08 "DDR_CR,DDR Configuration Register"
bitfld.long 0x08 0. " SW_CC_DDRFWREMAP            ,DDR_Space0 and DDR_Space1 are remapped to the lCODE/DCODE space" "Not remapped,Remapped"
line.long 0x0C "ENVM_CR,eNVM configuration register"
bitfld.long 0x0C 16. " ENVM_SENSE_ON               ,Turn on or off the sense amps for both NVM0 and NVM1" "Turn off,Turn on"
bitfld.long 0x0C 15. "                     ENVM_PERSIST                ,Reset control for NVM0 and NVM1" "SYSRESET_N and PORESET_N,PORESET_N"
textline "                                  "
bitfld.long 0x0C 14. " NV_DPD1                     ,Deep power-down control for the NVM1" "Normal operation,Deep power-down"
bitfld.long 0x0C 13. "             NV_DPD0                     ,Deep power-down control for the NVM0" "Normal operation,Deep power-down"
textline "                                  "
bitfld.long 0x0C 5.--7. " NV_FREQRNG                  ,Behavior of ENVM BUSY_B with respect to the interface clock" "Page Read=1/Other modules=1,Page Read=2/Other modules=1,Page Read=3/Other modules=2,Page Read=4/Other modules=2,Page Read=5/Other modules=2,Page Read=6/Other modules=3,Page Read=7/Other modules=3,Page Read=8/Other modules=4"
bitfld.long 0x0C 0.--4. "  SW_ENVMREMAPSIZE            ,Size of the segment in eNVM which is to be remapped to location 0x00000000" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,?..."
line.long 0x10 "ENVM_REMAP_BASE_CR,Configuration register"
hexmask.long.tbyte 0x10 1.--18. 2. " SW_ENVMREMAPBASE            ,Offset address of eNVM for remapping"
bitfld.long 0x10 0. "                       SW_ENVMREMAPENABLE          ,Enables remap for eNVM" "Disabled,Enabled"
line.long 0x14 "ENVM_REMAP_FAB_CR,Fabric protect size"
hexmask.long.tbyte 0x14 1.--18. 2. " SW_ENVMREMAPBASE            ,Offset address of eNVM for remapping"
bitfld.long 0x14 0. "                       SW_ENVMREMAPENABLE          ,Enables remap for eNVM" "Disabled,Enabled"
line.long 0x18 "CC_CR,Cache configure"
bitfld.long 0x18 2. " CC_CACHE_LOCK               ,This signal allows the cache lock to be enabled" "Disabled,Enabled"
bitfld.long 0x18 1. "                     CC_SBUS_WR_MODE             ,This signal allows debug mode SBUS writes to cache memory to be enabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x18 0. " CC_CACHE_ENB                ,This signal allows the cache to be disabled" "Disabled,Enabled"
line.long 0x1c "CC_REGION_CR,Cache Region Control Register"
bitfld.long 0x1c 0.--3. " CC_CACHE_REGION             ,These bits define the cache region size" "0-128 MB,128-256 MB,256-384 MB,384-512 MB,?..."
line.long 0x20 "CC_LOCK_BASE_ADDR_CR,Cache Lock Base Address Control Register"
hexmask.long.tbyte 0x20 0.--18. 1. " CC_LOCK_BASEADD             ,Base address can be used to initiate the transaction to re-read the erroneous data"
line.long 0x24 "CC_FLUSH_INDX_CR,Cache Flush Index Control Register"
hexmask.long.byte 0x24 0.--5. 1. " CC_FLUSH_INDEX              ,Cache memory index to be flushed or invalidated"
line.long 0x28 "DDRB_BUF_TIMER_CR,MSS DDR Bridge Buffer Timer Control Register"
hexmask.long.word 0x28 0.--9. 1. " DDRB_TIMER                  ,Configure the timeout register in the write buffer module"
line.long 0x2c "DDRB_NB_ADDR_CR,MSS DDR Bridge Non-Bufferable Address Control Register"
hexmask.long.word 0x2c 0.--15. 1. " DDRB_NB_ADDR                ,Base address of a non-bufferable address region"
line.long 0x30 "DDRB_NB_SIZE_CR,MSS DDR Bridge Non-Bufferable Size Control Register"
bitfld.long 0x30 0.--3. " DDRB_NB_SZ                  ,Size of non-bufferable address region" "No region,64 KB,128 KB,256 KB,512 KB,1 MB,2 Mb,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB"
line.long 0x34 "DDRB_CR,MSS DDR Bridge Configuration Register"
bitfld.long 0x34 20.--23. " DDR_IDC_MAP                 ,This signal sets the DSG interface to DDR address space mapping mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 16.--19. "                           DDR_SW_MAP                  ,This signal sets the AHB bus master to DDR address space mapping mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x34 12.--15. " DDR_HPD_MAP                 ,This signal sets the HPDA Master to DDR address space mapping mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 8.--11. "                           DDR_DS_MAP                  ,This signal sets the DSG Master to DDR address space mapping mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x34 7. " DDRB_BUF_SZ                 ,This is used to configure the write buffer and read buffer size as per DDR burst size" "16 bytes,32 bytes"
bitfld.long 0x34 6. "                     DDRB_IDC_EN                 ,The bit allows read buffer for IDC interface in MSS DDR bridge to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x34 5. " DDRB_SW_REN                 ,This bit allows the read buffer for AHB BUS master in MSS DDR bridge to be disabled" "Disabled,Enabled"
bitfld.long 0x34 4. "                     DDRB_SW_WEN                 ,The bit allows the write combining buffer for AHB bus Master in MSS DDR bridge to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x34 3. " DDRB_HPD_REN                ,This bit allows the read buffer for high performance DMA master in MSS DDR bridge to be disabled" "Disabled,Enabled"
bitfld.long 0x34 2. "                     DDRB_HPD_WEN                ,This bit allows the write combining buffer for high performance DMA master in MSS DDR bridge to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x34 1. " DDRB_DS_REN                 ,This bit allows the read buffer for DSG master in MSS DDR bridge to be disabled" "Disabled,Enabled"
bitfld.long 0x34 0. "                     DDRB_DS_WEN                 ,This bit allows write combining buffer for DSG Master in MSS DDR bridge to be disabled" "Disabled,Enabled"
line.long 0x38 "EDAC_CR,EDAC Configuration Register"
bitfld.long 0x38 6. " CAN_EDAC_EN                 ,This signal allows the EDAC for CAN to be disabled" "Disabled,Enabled"
bitfld.long 0x38 5. "                     USB_EDAC_EN                 ,This signal allows the EDAC for USB to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x38 4. " MAC_EDAC_RX_EN              ,This signal allows the EDAC for Ethernet Rx RAM to be disabled" "Disabled,Enabled"
bitfld.long 0x38 3. "                     MAC_EDAC_TX_EN              ,This signal allows the EDAC for Ethernet Tx RAM to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x38 2. " CC_EDAC_EN                  ,This signal allows the EDAC for cache to be disabled" "Disabled,Enabled"
bitfld.long 0x38 1. "                     ESRAM1_EDAC_EN              ,This signal allows the EDAC for eSRAM1 to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x38 0. " ESRAM0_EDAC_EN              ,This bit allows the EDAC for eSRAM0 to be disabled" "Disabled,Enabled"
line.long 0x3c "MASTER_WEIGHT0_CR,Master Weight Configuration Register 0"
bitfld.long 0x3c 25.--29. " SW_WEIGHT_PDMA              ,Configures the round robin weight for peripheral DMA master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3c 20.--24. "                           SW_WEIGHT_FAB_1             ,Configures the round robin weight for fabric (FIC_1) master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x3c 15.--19. " SW_WEIGHT_FAB_0             ,Configures the round robin weight for fabric (FIC_0) master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3c 10.--14. "                           SW_WEIGHT_GIGE              ,Configures the round robin weight for Ethernet master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x3c 5.--9. " SW_WEIGHT_S                 ,Configures the round robin weight for S master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3c 0.--4. "                           SW_WEIGHT_IC                ,Configures the round robin weight for IC master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "MASTER_WEIGHT1_CR,Master Weight Configuration Register 1"
bitfld.long 0x40 10.--14. " SW_WEIGHT_G                 ,Configures the round robin weight for G master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 5.--9. "                           SW_WEIGHT_USB               ,Configures the round robin weight for USB master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x40 0.--4. " SW_WEIGHT_HPDMA             ,Configures the round robin weight for HPDMA master" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "SOFT_IRQ_CR,Software Interrupt Register"
bitfld.long 0x44 0. " SOFTINTERRUPT               ,Software Interrupt asserted" "Cleared,Asserted"
line.long 0x48 "SOFT_RESET_CR,Software Reset Control Register"
bitfld.long 0x48 26. " MDDR_FIC64_SOFTRESET        ,Software DDR_FIC Reset" "No reset,Reset"
bitfld.long 0x48 25. "                     MDDR_CTLR_SOFTRESET         ,Software MDDR Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 24. " MSS_GPOUT_31_24_SOFTRESET   ,Software GPIO_OUT[31:24] Reset" "No reset,Reset"
bitfld.long 0x48 23. "                     MSS_GPOUT_23_16_SOFTRESET   ,Software GPIO_OUT[23:16] Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 22. " MSS_GPOUT_15_8_SOFTRESET    ,Software GPIO_OUT[15:8] Reset" "No reset,Reset"
bitfld.long 0x48 21. "                     MSS_GPOUT_7_0_SOFTRESET     ,Software GPIO_OUT[7:0] Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 20. " MSS_GPIO_SOFTRESET          ,Software GPIO Reset" "No reset,Reset"
bitfld.long 0x48 19. "                     FIC32_1_SOFTRESET           ,Software FIC _1 Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 18. " FIC32_0_SOFTRESET           ,Software FIC _0 Reset" "No reset,Reset"
bitfld.long 0x48 17. "                     HPDMA_SOFTRESET             ,Software HPDMA Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 16. " FPGA_SOFTRESET              ,Software FPGA Reset" "No reset,Reset"
bitfld.long 0x48 15. "                     COMBLK_SOFTRESET            ,Software COMM_BLK Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 14. " USB_SOFTRESET               ,Software USB Reset" "No reset,Reset"
bitfld.long 0x48 13. "                     CAN_SOFTRESET               ,Software CAN Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 12. " I2C1_SOFTRESET              ,Software I2C_1 Reset" "No reset,Reset"
bitfld.long 0x48 11. "                     I2C0_SOFTRESET              ,Software I2C_0 Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 10. " SPI1_SOFTRESET              ,Software SPI1 Reset" "No reset,Reset"
bitfld.long 0x48 9. "                     SPI0_SOFTRESET              ,Software SPI0 Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 8. " MMUART1_SOFTRESET           ,Software MMUART_1 Reset" "No reset,Reset"
bitfld.long 0x48 7. "                     MMUART0_SOFTRESET           ,Software MMUART_0 Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 6. " TIMER_SOFTRESET             ,Software system timer Reset" "No reset,Reset"
bitfld.long 0x48 5. "                     PDMA_SOFTRESET              ,Software PDMA Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 4. " MAC_SOFTRESET               ,Software Ethernet MAC Reset" "No reset,Reset"
bitfld.long 0x48 3. "                     ESRAM1_SOFTRESET            ,Software ESRAM_1 Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 2. " ESRAM0_SOFTRESET            ,Software ESRAM_0 Reset" "No reset,Reset"
bitfld.long 0x48 1. "                     ENVM1_SOFTRESET             ,Software ENVM_1 Reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x48 0. " ENVM0_SOFTRESET             ,Software ENVM_0 Reset" "No reset,Reset"
line.long 0x4C "M3_CR,M3 Configuration Register"
bitfld.long 0x4c 28. " M3_MPU_DISABLE              ,Disables the memory protection unit" "No,Yes"
bitfld.long 0x4c 26.--27. "                          STCLK_DIVISOR               ,Control the frequency of STCLK" "M3_CLK/4,M3_CLK/8,M3_CLK/16,M3_CLK/32"
textline "                                  "
bitfld.long 0x4c 25. " STCALIB[25]                 ,NOREF bit of SysTick Calibration Value Register" "Provided,Not provided"
bitfld.long 0x4c 24. "                 STCALIB[24]                 ,SKEW bit of SysTick Calibration Value Register" "10 ms,Other value"
textline "                                  "
hexmask.long.tbyte 0x4c 0.--23. 1. " STCALIB[23:0]               ,TENMS field of SysTick Calibration Value Register"
line.long 0x50 "FAB_IF_CR,Fabric Interface Control (FIC) Register"
bitfld.long 0x50 9. " SW_FIC_REG_SEL5             ,Indicates whether a specific fabric region is accessible by FIC_0 or IC_1" "FIC_0,FIC_1"
bitfld.long 0x50 8. "                        SW_FIC_REG_SEL4             ,Indicates whether a specific fabric region is accessible by FIC_0 or IC_1" "FIC_0,FIC_1"
textline "                                  "
bitfld.long 0x50 7. " SW_FIC_REG_SEL3             ,Indicates whether a specific fabric region is accessible by FIC_0 or IC_1" "FIC_0,FIC_1"
bitfld.long 0x50 6. "                        SW_FIC_REG_SEL2             ,Indicates whether a specific fabric region is accessible by FIC_0 or IC_1" "FIC_0,FIC_1"
textline "                                  "
bitfld.long 0x50 5. " SW_FIC_REG_SEL1             ,Indicates whether a specific fabric region is accessible by FIC_0 or IC_1" "FIC_0,FIC_1"
bitfld.long 0x50 4. "                        SW_FIC_REG_SEL0             ,Indicates whether a specific fabric region is accessible by FIC_0 or IC_1" "FIC_0,FIC_1"
textline "                                  "
bitfld.long 0x50 3. " FAB1_AHB_MODE               ,This signal is used to control whether the FIC_1 fabric interface supports AHB mode or APB Mode" "APB,AHB"
bitfld.long 0x50 2. "                          FAB0_AHB_MODE               ,This bit is used to control whether FIC_0 fabric interface supports AHB mode or APB mode" "APB,AHB"
textline "                                  "
bitfld.long 0x50 1. " FAB1_AHB_BYPASS             ,FIC_1 configuration" "Not bypassed,Bypassed"
bitfld.long 0x50 0. "                 FAB0_AHB_BYPASS             ,FIC_0 configuration" "Not bypassed,Bypassed"
line.long 0x54 "LOOPBACK_CR,Loopback Control Register"
bitfld.long 0x54 3. " MSS_GPIOLOOPBACK            ,controls whether internal loopback on the MSS GPIO is enabled" "Disabled,Enabled"
bitfld.long 0x54 2. "                     MSS_I2CLOOPBACK             ,This bit controls whether internal loopback between I2C_0 and I2C_1 is enabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x54 1. " MSS_SPILOOPBACK             ,This bit controls whether internal loopback between SPI_0 and SPI_1 is enabled" "Disabled,Enabled"
bitfld.long 0x54 0. "                     MSS_MMUARTLOOPBACK          ,Loopback between MMUART_0 and MMUART_1" "No,Yes"
line.long 0x58 "GPIO_SYSRESET_SEL_CR,GPIO System Reset Control Register"
bitfld.long 0x58 3. " MSS_GPIO_31_24_SYSRESET_SEL ,MSS GPIO Loopback" "No loopback,Loopback"
bitfld.long 0x58 2. "                  MSS_GPIO_23_16_SYSRESET_SEL ,I2C_0 and I2C_1 Loopback " "No loopback,Loopback"
textline "                                  "
bitfld.long 0x58 1. " MSS_GPIO_15_8_SYSRESET_SEL  ,SPI_0 and SPI_1 Loopback" "No loopback,Loopback"
bitfld.long 0x58 0. "                  MSS_GPIO_7_0_SYSRESET_SEL   ,MMUART_0 and MMUART_1 Loopback" "No loopback,Loopback"
line.long 0x5c "GPIN_SRC_SEL_CR,GPIO Input Source Select Control Register"
line.long 0x60 "MDDR_CR,MDDR Configuration Register"
bitfld.long 0x60 3. " PHY_SELF_REF_EN             ,This signal indicates that the DRAM has been put into self-refresh" "Disabled,Enabled"
bitfld.long 0x60 2. "                     F_AXI_AHB_MODE              ,This signal is used by the SMC_FIC, DDR_FIC, and DDR CTL to select the AXI/AHB interface in the fabric" "AHB,AXI"
textline "                                  "
bitfld.long 0x60 1. " SDR_MODE                    ,This signal is used to select whether the MSS AXI interface accesses DDR memory or SDR memory inside the fabric" "DDR,SDR"
bitfld.long 0x60 0. "                          MDDR_CONFIG_LOCAL           ,AHBTOAPB2 bridge can access MDDR APB slave" "Disabled,Enabled"
line.long 0x64 "USB_IO_INPUT_SEL_CR,USB I/O Input Select Control Register"
bitfld.long 0x64 0.--1. " USB_IO_INPUT_SEL            ,Used to select one of the four USB data interfaces from IOMUXCELLs and I/O pads" "USBA,USBB,USBC,USBD"
line.long 0x68 "PERIPH_CLK_MUX_SEL_CR,Peripheral Clock MUX Select Control Register"
bitfld.long 0x68 2. " TRACECLK_DIV2_SEL           ,TRACECLKIN_I source selection" "M3_CLK,M3_CLK/2"
bitfld.long 0x68 1. "                     SPI1_SCK_FAB_SEL            ,This clock selection bit is used to select the SPI1_SCK from the fabric or I/O pads" "I/O,Fabric"
textline "                                  "
bitfld.long 0x68 0. " SPI0_SCK_FAB_SEL            ,This clock selection bit is used to select the SPI0_SCK from the fabric or I/O pads" "I/O,Fabric"
line.long 0x6c "WDOG_CR,Watchdog Configuration Register"
bitfld.long 0x6c 1. " WDOGMODE                    ,This bit is the reset/interrupt mode selection bit from the system register" "0,1"
bitfld.long 0x6c 0. "                            WDOGENABLE                  ,This is the enable bit for the Watchdog module" "Disabled,Enabled"
line.long 0x70 "MDDR_IO_CALIB_CR,MDDR I/O Calibration Control Register"
bitfld.long 0x70 14. " CALIB_LOCK                  ,This signal is used in the DDRIO calibration block as an override to lock the codes during intermediate runs" "Not locked,Locked"
bitfld.long 0x70 13. "                   CALIB_START                 ,Rerun of the calibration state machine is required" "Not required,Required"
textline "                                  "
bitfld.long 0x70 12. " CALIB_TRIM                  ,Override of the calibration value from the PC code/programmed code values" "0,1"
hexmask.long.byte 0x70 6.--11. 1. "                            NCODE                       ,DPC override NCODE from flash"
textline "                                  "
hexmask.long.byte 0x70 0.--5. 1. " PCODE                       ,PC override PODE from flash"
group.long 0x78++0x3b
line.long 0x00 "EDAC_IRQ_ENABLE_CR,EDAC Interrupt Enable Control Register"
bitfld.long 0x00 14. " MDDR_ECC_INT_EN             ,Allows the error EDAC for MDDR status update to be disabled" "Disabled,Enabled"
bitfld.long 0x00 13. "                     CAN_EDAC_2E_EN              ,Allows the 2-bit error EDAC for CAN status update to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 12. " CAN_EDAC_1E_EN              ,Allows the 1-bit error EDAC for CAN status update to be disabled" "Disabled,Enabled"
bitfld.long 0x00 11. "                     USB_EDAC_2E_EN              ,Allows the 2-bit error EDAC for USB status update to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 10. " USB_EDAC_1E_EN              ,Allows the 1-bit error EDAC for USB status update to be disabled" "Disabled,Enabled"
bitfld.long 0x00 9. "                     MAC_EDAC_RX_2E_EN           ,Allows the 2-bit error EDAC for Ethernet Rx RAM status update to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 8. " MAC_EDAC_RX_1E_EN           ,Allows the 1-bit error EDAC for Ethernet Rx RAM status update to be disabled" "Disabled,Enabled"
bitfld.long 0x00 7. "                     MAC_EDAC_TX_2E_EN           ,Allows the 2-bit error EDAC for Ethernet Tx RAM status update to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 6. " MAC_EDAC_TX_1E_EN           ,Allows the 1-bit error EDAC for Ethernet Tx RAM status update to be disabled" "Disabled,Enabled"
bitfld.long 0x00 3. "                     ESRAM1_EDAC_2E_EN           ,Allows the 2-bit error EDAC for eSRAM1 status update to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 2. " ESRAM1_EDAC_1E_EN           ,Allows the 1-bit error EDAC for eSRAM1 status update to be disabled" "Disabled,Enabled"
bitfld.long 0x00 1. "                     ESRAM0_EDAC_2E_EN           ,Allows the 2-bit error EDAC for eSRAM0 status update to be disabled" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 0. " ESRAM0_EDAC_1E_EN           ,Allows the 1-bit error EDAC for eSRAM0 status update to be disabled" "Disabled,Enabled"
line.long 0x04 "USB_CR,USB Configuration Register"
bitfld.long 0x04 1. " USB_DDR_SELECT              ,USB mode configuration" "SDR,DDR"
bitfld.long 0x04 0. "                          USB_UTMI_SEL                ,USB interface configuration" "ULPI PHY,UTMI"
line.long 0x08 "ESRAM_PIPELINE_CR,eSRAM PIPELINE Configuration Register"
bitfld.long 0x08 0. " ESRAM_PIPELINE_ENABLE       ,Pipeline control" "Disabled,Enabled"
line.long 0x0c "MSS_IRQ_ENABLE_CR,MSS Interrupt Enable Control Register"
hexmask.long.word 0xc 10.--19. 1. " DDRB_INTERRUPT_EN           ,This signal is used to mask the MSS DDR bridge interrupt to the Cortex-M3 processor"
bitfld.long 0x0c 7.--9. "                         CC_INTERRUPT_EN             ,This signal is used to mask the cache interrupt to the Cortex-M3 processor" "0,1,2,3,4,5,6,7"
textline "                                  "
hexmask.long.byte 0x0c 0.--6. 1. " SW_INTERRUPT_EN             ,This signal is used to mask the AHB bus interrupt to the Cortex-M3 processor"
line.long 0x10 "RTC_WAKEUP_CR,RTC Wake Up Configuration Register"
bitfld.long 0x10 2. " RTC_WAKEUP_G4C_EN           ,This is a masking signal to enable RTC_WAKEUP interrupt to the system controller" "Disabled,Enabled"
bitfld.long 0x10 1. "                     RTC_WAKEUP_FAB_EN           ,This is a masking signal to enable the RTC_WAKEUP interrupt to the fabric" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x10 0. " RTC_WAKEUP_M3_EN            ,This is a masking signal to enable the RTC_WAKEUP interrupt to the Cortex-M3 processor" "Disabled,Enabled"
line.long 0x14 "MAC_CR,MAC Configuration Register"
bitfld.long 0x14 5.--8. " RGMII_TXC_DELAY_SEL         ,Specifies how many delay taps the RGMII transmit clock passes through 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 2.--4. "                           ETH_PHY_MODE                ,These bits indicate the Ethernet PHY mode" "RMII,Reserved,TBI,MII,GMII,?..."
textline "                                  "
bitfld.long 0x14 0.--1. " ETH_LINE_SPEED              ,These bits indicate the Ethernet line speed" "10 Mbps,100 Mbps,1.000 Mbps,?..."
line.long 0x18 "MSSDDR_PLL_STATUS_LOW_CR,MSS DDR PLL Status Low Configuration Register"
bitfld.long 0x18 26.--29. " FACC_PLL_LOCKCNT            ,LOCK counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 23.--25. "                           FACC_PLL_LOCKWIN            ,The register configures the phase error window for LOCK assertion as a fraction of the divided reference period" "500 ppm,1000 ppm,2000 ppm,4000 ppm,8000 ppm,16000 ppm,32000 ppm,64000 ppm"
textline "                                  "
bitfld.long 0x18 19.--22. " FACC_PLL_RANGE              ,This register configures the PLL filter range[MHz]" "Bypass,1-1.6,1.6-2.6,2.6-4.2,4.2-6.8,6.8-11,11-18,18-29,29-46,46-75,75-120,120-200,?..."
bitfld.long 0x18 16.--19. "                     FACC_PLL_DIVQ               ,These bits are used to configure the amount of division to be performed on the internal (multiplied) PLL clock" "/1,/2,/4,/8,/16,/32,?..."
textline "                                  "
hexmask.long.word 0x18 6.--15. 1. " FACC_PLL_DIVF               ,This register configures the feedback divider value"
hexmask.long.byte 0x18 0.--5. 1. "                         FACC_PLL_DIVR               ,This register is used to configure the Reference divider value"
line.long 0x1c "MSSDDR_PLL_STATUS_HIGH_CR,MSS DDR PLL Status High Configuration Register"
bitfld.long 0x1c 8.--12. " FACC_PLL_SSMF               ,This field drives the spread spectrum modulation frequency (SSMF) input of the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1c 6.--7. "                           FACC_PLL_SSMD               ,This field drives the spread spectrum modulation depth (SSMD) input of the PLL" "0,1,2,3"
textline "                                  "
bitfld.long 0x1c 5. " FACC_PLL_SSE                ,This field drives the SSE input of the PLL" "0,1"
bitfld.long 0x1c 4. "                            FACC_PLL_PD                 ,A PD signal is provided for lowest quiescent current" "0,1"
textline "                                  "
bitfld.long 0x1c 3. " FACC_PLL_FSE                ,This register configures internal and external input paths" "FB pin input,Internal feedback"
bitfld.long 0x1c 2. "            FACC_PLL_MODE_3V3           ,This register configures analog voltage" "3.3 V,2.5 V"
textline "                                  "
bitfld.long 0x1c 1. " FACC_PLL_MODE_1V2           ,This register configures Core Voltage" "1.0 V,1.2 V"
bitfld.long 0x1c 0. "                        FACC_PLL_BYPASS             ,This signal comes from MSS system registers and may be selected to control the corresponding configuration input of the MPLL" "0,1"
line.long 0x20 "MSSDDR_FACC1_CR,MSS DDR Fabric Alignment Clock Controller (FACC) 1 Configuration Register"
bitfld.long 0x20 27. " FACC_FAB_REF_SEL            ,This selects the source of the reference clock to be supplied to the MPLL" "25/50 MHz RC oscillator,Fabric clock"
bitfld.long 0x20 26. "      CONTROLLER_PLL_INIT         ,This signal is used to indicate whether the FACC is to be configured for PLL init mode" "From the normal run-time conf.,Hardwired PLL"
textline "                                  "
bitfld.long 0x20 25. " PERSIST_CC                  ,This feeds into the MSS reset controller" "0,1"
bitfld.long 0x20 22.--24. "                            BASE_DIVISOR                ,This signaal is used to indicate the ratio between CLK_MSS and the re-generated version of CLK_BASE" "1:1,2:1,4:1,Reserved,8:1,16:1,32:1,?..."
textline "                                  "
bitfld.long 0x20 19.--21. " FIC64_DIVISOR               ,This signal is used to indicate the ratio between CLK_MSS and CLK_FIC64" "1:1,2:1,4:1,Reserved,8:1,16:1,32:1,?..."
bitfld.long 0x20 16.--18. "                     FIC32_1_DIVISOR             ,This signal is used to indicate the ratio between CLK_MSS and the clock being used in the fabric" "1:1,2:1,4:1,Reserved,8:1,16:1,32:1,?..."
textline "                                  "
bitfld.long 0x20 13.--15. " FIC32_0_DIVISOR             ,indicate the ratio between CLK_MSS and the clock being used in the fabric, to clock the soft IP block which is interfacing to FIC_0 of the MSS" "1:1,2:1,4:1,Reserved,8:1,16:1,32:1,?..."
bitfld.long 0x20 12. "                     FACC_GLMUX_SEL              ,This signal contains the select line for the four glitchless multiplexers within the FACC, which are related to the aligned clocks" "CLK_STANDBY,Stage 2 divider"
textline "                                  "
bitfld.long 0x20 9.--11. " M3_CLK_DIVISOR              ,This signal is used to indicate the ratio between CLK_MSS and M3_CLK" "1,2,3,4,5,6,7,8"
bitfld.long 0x20 8. "                            DDR_CLK_EN                  ,This signal is used to determine whether or not the clock to the MDDR_SUBSYS block is to be gated off" "Gated off,Not gated off"
textline "                                  "
bitfld.long 0x20 5.--7. " APB1_DIVISOR                ,This signal is used to indicate the ratio between CLK_MSS and PCLK1" "1:1,2:1,4:1,Reserved,8:1,16:1,32:1,?..."
bitfld.long 0x20 2.--4. "                     APB0_DIVISOR                ,This signal is used to indicate the ratio between CLK_MSS and PCLK0" "1:1,2:1,4:1,Reserved,8:1,16:1,32:1,?..."
textline "                                  "
bitfld.long 0x20 0.--1. " DIVISOR_A                   ,This signal is used to indicate the ratio between CLK_SRC and CLK_MSS" "1:1,2:1,3:1,?..."
line.long 0x24 "MSSDDR_FACC2_CR,MSS DDR Fabric Alignment Clock Controller 2 Configuration Register"
bitfld.long 0x24 13. " MSS_XTAL_RTC_EN             ,Enable signal for RTC crystal oscillator" "Disabled,Enabled"
bitfld.long 0x24 12. "                     MSS_XTAL_EN                 ,This bit enables the signal for the crystal oscillator" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x24 11. " MSS_CLK_ENVM_EN             ,This bit enables signal for eNVM RC oscillator"  "Disabled,Enabled"
bitfld.long 0x24 10. "                     MSS_1MHZ_EN                 ,This bit enables the signal for the 1 MHz RC oscillator" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x24 9. " MSS_25_50MHZ_EN             ,This bit enables the signal for the 25/50MHz RC oscillator" "Disabled,Enabled"
bitfld.long 0x24 8. "                     FACC_STANDBY_SEL[8]         ,This signal contains the select lines for the three 2 to 1 glitchless multiplexers" "MUX 0,MUX 1"
textline "                                  "
bitfld.long 0x24 7. " FACC_STANDBY_SEL[7]         ,This signal contains the select lines for the three 2 to 1 glitchless multiplexers" "CLK_1MHZ,CCC2ASIC"
bitfld.long 0x24 6. "                     FACC_STANDBY_SEL[6]         ,This signal contains the select lines for the three 2 to 1 glitchless multiplexers" "CLK_25_50MHZ,CLK_XTAL"
textline "                                  "
bitfld.long 0x24 5. " FACC_PRE_SRC_SEL            ,This signal indicates whether CLK_1MHZ or CCC2ASIC is to be fed into the source glitchless clock multiplexer in the FACC" "CLK_1MHZ,CCC2ASIC"
bitfld.long 0x24 4. "                     FACC_SRC_SEL[4]             ,This signal contains the select lines for the three 2 to 1 glitchless multiplexers" "MUX 0,MUX 1"
textline "                                  "
bitfld.long 0x24 3. " FACC_SRC_SEL[3]             ,This signal contains the select lines for the three 2 to 1 glitchless multiplexers" "CLK_1MHZ,MSSDDR_PLL_OUT_CLK"
bitfld.long 0x24 2. "           FACC_SRC_SEL[2]             ,This signal contains the select lines for the three 2 to 1 glitchless multiplexers" "CLK_25_50MHZ,CLK_XTAL"
textline "                                  "
bitfld.long 0x24 0.--1. " RTC_CLK_SEL                 ,This signal indicates which of three possible clocks are to be configured as the source of the RTC clock" "CLK_XTAL,CLK_1MHZ,CLK_25_50MHZ,CLK_XTAL_RTC"
line.long 0x28 "PLL_LOCK_EN_CR,PLL LOCK Enable Control Register"
bitfld.long 0x28 3. " FAB_PLL_LOCK_LOST_EN        ,Used as a masking signal to enable FAB PLL LOCK LOST interrupt to Cortex-M3 processor" "Disabled,Enabled"
bitfld.long 0x28 2. "                     FAB_PLL_LOCK_EN             ,Used as a masking signal to enable FAB PLL LOCK" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x28 1. " MPLL_LOCK_LOST_EN           ,MPLL_LOCK_LOST_EN 0 Used for masking signal to enable MPLL LOCK LOST" "Disabled,Enabled"
bitfld.long 0x28 0. "                     MPLL_LOCK_EN                ,Used as a masking signal to enable MPLL LOCK" "Disabled,Enabled"
line.long 0x2c "MSSDDR_CLK_CALIB_CR,MSS DDR Clock Calibration Control Register"
bitfld.long 0x2c 0. " FAB_CALIB_START             ,Writing to this bit causes a one clock tick pulse to be generated on FABCALIBSTART" "No effect,Start"
line.long 0x30 "PLL_DELAY_LINE_SEL_CR,PLL Delay Line Select Control Register"
bitfld.long 0x30 2.--3. " PLL_REF_DEL_SEL             ,It must be programmed to a specific value by Libero SoC and never modified after that" "0,1,2,3"
bitfld.long 0x30 0.--1. "                            PLL_REF_DEL_SEL             ,It must be programmed to a specific value by Libero SoC and never modified after that" "0,1,2,3"
line.long 0x34 "MAC_STAT_CLRONRD_CR,MAC Status Clear on Read Control Register"
bitfld.long 0x34 0. " MAC_STAT_CLRONRD            ,MAC statistics counters that have been set are cleared after they are read" "0,1"
line.long 0x38 "RESET_SOURCE_CR,Reset Source Control Register"
bitfld.long 0x38 7. " USER_M3_RESET_DETECT        ,Indicates that an M3 user reset has occurred" "Not occurred,Occurred"
bitfld.long 0x38 6. "                 USER_RESET_DETECT           ,Indicates that a MSS user reset has occurred" "Not occurred,Occurred"
textline "                                  "
bitfld.long 0x38 5. " WDOG_RESET_DETECT           ,Indicates that a Watchdog reset has occurred" "Not occurred,Occurred"
bitfld.long 0x38 4. "                 LOCKUP_RESET_DETECT         ,Indicates that a Cortex-M3 processor lockup reset has occurred" "Not occurred,Occurred"
textline "                                  "
bitfld.long 0x38 3. " SOFT_RESET_DETECT           ,Indicates that a soft reset has occurred" "Not occurred,Occurred"
bitfld.long 0x38 2. "                 CONTROLLER_M3_RESET_DETECT  ,Indicates that a controller M3 reset has occurred" "Not occurred,Occurred"
textline "                                  "
bitfld.long 0x38 1. " CONTROLLER_RESET_DETECT     ,Indicates that an MSS controller reset has occurred" "Not occurred,Occurred"
bitfld.long 0x38 0. "                 PO_RESET_DETECT             ,Indicates that a power-up reset has occurred" "Not occurred,Occurred"
rgroup.long 0xc4++0x67
line.long 0x00 "CC_DC_ERR_ADDR_SR,Dcode Bus Error Address Status Register"
line.long 0x04 "CC_IC_ERR_ADDR_SR,Icode Bus Error Address Status Register"
line.long 0x08 "CC_SB_ERR_ADDR_SR,System Bus Error Address Status Register"
line.long 0x0c "CC_IC_MISS_CNTR_SR,ICode Miss Control Status Register"
line.long 0x10 "CC_IC_HIT_CNTR_SR,ICode Hit Control Status Register"
line.long 0x14 "CC_DC_MISS_CNTR_SR,DCode Miss Control Status Register"
line.long 0x18 "CC_DC_HIT_CNTR_CR,DCode Hit Control Status Register"
line.long 0x1c "CC_IC_TRANS_CNTR_SR,ICode Transaction count Control Status Register"
line.long 0x20 "CC_DC_TRANS_CNTR_SR,DCode Transaction Count Control Status Register"
line.long 0x24 "DDRB_DS_ERR_ADR_SR,MS DDR Bridge DS master Error Address Status Register"
line.long 0x28 "DDRB_HPD_ERR_ADR_SR,MSS DDR Bridge High Performance DMA Master Error Address Status Register"
line.long 0x2c "DDRB_SW_ERR_ADR_SR,MSS DDR Bridge AHB Bus Error Address Status Register"
line.long 0x30 "DDRB_BUF_EMPTY_SR,MSS DDR Bridge Buffer Empty Status Register"
bitfld.long 0x30 6. " DDRB_IDC_RBEMPTY            ,IDC master read buffer status" "Not empty,Empty"
bitfld.long 0x30 5. "                    DDRB_HPD_RBEMPTY            ,HPDMA master read buffer status" "Not empty,Empty"
textline "                                  "
bitfld.long 0x30 4. " DDRB_HPD_WBEMPTY            ,HPDMA master write buffer status" "Not empty,Empty"
bitfld.long 0x30 3. "                    DDRB_SW_RBEMPTY             ,AHB master read buffer status" "Not empty,Empty"
textline "                                  "
bitfld.long 0x30 2. " DDRB_SW_WBEMPTY             ,AHB master write buffer status" "Not empty,Empty"
bitfld.long 0x30 1. "                    DDRB_DS_RBEMPTY             ,DSG master read buffer status" "Not empty,Empty"
textline "                                  "
bitfld.long 0x30 0. " DDRB_DS_WBEMPTY             ,DSG master write buffer status" "Not empty,Empty"
line.long 0x34 "DDRB_DSBL_DN_SR,MSS DDR Bridge Disable Buffer Status Register"
bitfld.long 0x34 6. " DDRB_IDC_DSBL_DN            ,AHB bus matrix read buffer disabled" "No,Yes"
bitfld.long 0x34 5. "                          DDRB_HPD_DSBL_DN            ,IDC DMA read buffer disabled" "No,Yes"
textline "                                  "
bitfld.long 0x34 4. " DDRB_HPD_WDSBL_DN           ,HPDMA read buffer disabled" "No,Yes"
bitfld.long 0x34 3. "                          DDRB_SW_RDSBL_DN            ,HPDMA write buffer disabled" "No,Yes"
textline "                                  "
bitfld.long 0x34 2. " DDRB_SW_WDSBL_DN            ,AHB read buffer disabled" "No,Yes"
bitfld.long 0x34 1. "                          DDRB_DS_RDSBL_DN            ,DS read buffer disabled" "No,Yes"
textline "                                  "
bitfld.long 0x34 0. " DDRB_DS_WDSBL_DN            ,DS write buffer disabled" "No,Yes"
line.long 0x38 "ESRAM0_EDAC_CNT,eSRAM0 EDAC Count"
hexmask.long.word 0x38 16.--31. 1. " ESRAM0_EDAC_CNT_2E          ,16-bit counter that counts the number of 2-bit uncorrected errors for eSRAM0"
hexmask.long.word 0x38 0.--15. 1. "                         ESRAM0_EDAC_CNT_1E          ,16-bit counter that counts the number of 1-bit corrected errors for eSRAM0"
line.long 0x3c "ESRAM1_EDAC_CNT,eSRAM1 EDAC Count"
hexmask.long.word 0x3c 16.--31. 1. " ESRAM1_EDAC_CNT_2E          ,16-bit counter that counts the number of 2-bit uncorrected errors for eSRAM1"
hexmask.long.word 0x3c 0.--15. 1. "                         ESRAM1_EDAC_CNT_1E          ,16-bit counter that counts the number of 1-bit corrected errors for eSRAM1"
line.long 0x40 "CC_EDAC_CNT,Cache Control EDAC Count"
hexmask.long.word 0x40 16.--31. 1. " CC_EDAC_CNT_2E              ,16-bit counter that counts the number of 2-bit uncorrected errors for the cache controller"
hexmask.long.word 0x40 0.--15. 1. "                         CC_EDAC_CNT_1E              ,16-bit counter that counts the number of 1-bit corrected errors for the cache controller"
line.long 0x44 "MAC_EDAC_TX_CNT,MAC EDAC Transmitter Count"
hexmask.long.word 0x44 16.--31. 1. " MAC_EDAC_TX_CNT_2E          ,16-bit counter that counts the number of 2-bit corrected errors for Ethernet"
hexmask.long.word 0x44 0.--15. 1. "                         MAC_EDAC_TX_CNT_1E          ,16-bit counter that counts the number of 1-bit corrected errors for Ethernet"
line.long 0x48 "MAC_EDAC_RX_CNT,MAC EDAC Transmitter Count"
hexmask.long.word 0x48 16.--31. 1. " MAC_EDAC_RX_CNT_2E          ,16-bit counter that counts the number of 2-bit corrected errors for Ethernet"
hexmask.long.word 0x48 0.--15. 1. "                         MAC_EDAC_RX_CNT_1E          ,16-bit counter that counts the number of 1-bit corrected errors for Ethernet"
line.long 0x4c "USB_EDAC_CNT,USB EDAC Count"
hexmask.long.word 0x4c 16.--31. 1. " USB_EDAC_CNT_2E             ,16-bit counter that counts the number of 2-bit corrected errors for USB"
hexmask.long.word 0x4c 0.--15. 1. "                         USB_EDAC_CNT_1E             ,16-bit counter that counts the number of 1-bit corrected errors for USB"
line.long 0x50 "CAN_EDAC_CNT,CAN EDAC Count"
hexmask.long.word 0x50 16.--31. 1. " CAN_EDAC_CNT_2E             ,16-bit counter that counts the number of 2-bit corrected errors for CAN"
hexmask.long.word 0x50 0.--15. 1. "                         CAN_EDAC_CNT_1E             ,16-bit counter that counts the number of 1-bit corrected errors for CAN"
line.long 0x54 "ESRAM0_EDAC_ADR,eSRAM0 EDAC Address Register"
hexmask.long.tbyte 0x54 13.--25. 0x20 " ESRAM0_EDAC_2E_AD           ,This register stores the address from eSRAM0 on which a 2-bit SECDED error has occurred"
hexmask.long.word 0x54 0.--12. 1. "                       ESRAM0_EDAC_1E_AD           ,This register stores the address from eSRAM0 on which a 1-bit SECDED error has occurred"
line.long 0x58 "ESRAM1_EDAC_ADR,eSRAM1 EDAC Address Register"
hexmask.long.tbyte 0x58 13.--25. 0x20 " ESRAM1_EDAC_2E_AD           ,This register stores the address from eSRAM1 on which a 2-bit SECDED error has occurred"
hexmask.long.word 0x58 0.--12. 1. "                       ESRAM1_EDAC_1E_AD           ,This register stores the address from eSRAM1 on which a 1-bit SECDED error has occurred"
line.long 0x5c "MAC_EDAC_RX_ADR,MAC EDAC Receiver Address Register"
hexmask.long.tbyte 0x5c 13.--25. 0x20 " MAC_EDAC_TX_2E_AD           ,This register stores the address from Ethernet TX memory on which a 2-bit SECDED error has occurred"
hexmask.long.word 0x5c 0.--12. 1. "                       MAC_EDAC_TX_1E_AD           ,This register stores the address from Ethernet TX memory on which a 1-bit SECDED error has occurred"
line.long 0x60 "CAN_EDAC_ADR,CAN EDAC Address Register"
hexmask.long.tbyte 0x60 13.--25. 0x20 " CAN_EDAC_2E_AD              ,This register stores the address from CAN memory on which a 2-bit SECDED error has occurred"
hexmask.long.word 0x60 0.--12. 1. "                       CAN_EDAC_1E_AD              ,This register stores the address from CAN memory on which a 1-bit SECDED error has occurred"
line.long 0x64 "USB_EDAC_ADR,USB EDAC Address Register"
hexmask.long.tbyte 0x64 13.--25. 0x20 " USB_EDAC_2E_AD              ,This register stores the address from USB memory on which a 2-bit SECDED error has occurred"
hexmask.long.word 0x64 0.--12. 1. "                       USB_EDAC_1E_AD              ,This register stores the address from USB memory on which a1-bit SECDED error has occurred"
rgroup.long 0x124++0x37
line.long 0x00 "MM0_1_2_SECURITY,Security Configuration Register for Masters 0, 1, and 2"
bitfld.long 0x00 9. " MM0_1_2_MS6_ALLOWED_W     ,Masters 0/1/2 write access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x00 8. "                     MM0_1_2_MS6_ALLOWED_R     ,Masters 0/1/2 read access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x00 7. "          MM0_1_2_MS3_ALLOWED_W     ,Masters 0/1/2 write access to Slave 3 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 6. " MM0_1_2_MS3_ALLOWED_R     ,Masters 0/1/2 read access to Slave 3 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x00 5. "                     MM0_1_2_MS2_ALLOWED_W     ,Masters 0/1/2 write access to Slave 2 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x00 4. "          MM0_1_2_MS2_ALLOWED_R     ,Masters 0/1/2 read access to Slave 2 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 3. " MM0_1_2_MS1_ALLOWED_W     ,Masters 0/1/2 write access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x00 2. "                     MM0_1_2_MS1_ALLOWED_R     ,Masters 0/1/2 read access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x00 1. "          MM0_1_2_MS0_ALLOWED_W     ,Masters 0/1/2 write access to Slave 0 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x00 0. " MM0_1_2_MS0_ALLOWED_R     ,Masters 0/1/2 read access to Slave 0 (MSS DDR bridge)" "Disabled,Enabled"
line.long 0x04 "MM4_5_FIC64_SECURITY,SSecurity Configuration Register for Masters 4, 5, and DDR_FIC"
bitfld.long 0x04 9. " MM4_5_FIC64_MS6_ALLOWED_W ,Masters 4/5/6 write access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x04 8. "                     MM4_5_FIC64_MS6_ALLOWED_R ,Masters 4/5/6 read access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x04 7. "          MM4_5_FIC64_MS3_ALLOWED_W ,Masters 4/5/6 write access to Slave 3 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x04 6. " MM4_5_FIC64_MS3_ALLOWED_R ,Masters 4/5/6 read access to Slave 3 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x04 5. "                     MM4_5_FIC64_MS2_ALLOWED_W ,Masters 4/5/6 write access to Slave 2 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x04 4. "          MM4_5_FIC64_MS2_ALLOWED_R ,Masters 4/5/6 read access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x04 3. " MM4_5_FIC64_MS1_ALLOWED_W ,Masters 4/5/6 write access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x04 2. "                     MM4_5_FIC64_MS1_ALLOWED_R ,Masters 4/5/6 read access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x04 1. "          MM4_5_FIC64_MS0_ALLOWED_W ,Masters 4/5/6 write access to Slave 0 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x04 0. " MM4_5_FIC64_MS0_ALLOWED_R ,Masters 4/5/6 read access to Slave 0 (MSS DDR bridge)" "Disabled,Enabled"
line.long 0x08 "MM3_6_7_8_SECURITY,Security Configuration Register for Masters 3, 6, 7, and 8"
bitfld.long 0x8 9. " MM3_6_7_8_MS6_ALLOWED_W   ,Masters 3/6/7/8 write access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x8 8. "                     MM3_6_7_8_MS6_ALLOWED_R   ,Masters 3/6/7/8 read access to Slave 6 (MSS DDR bridge) " "Disabled,Enabled"
bitfld.long 0x8 7. "          MM3_6_7_8_MS3_ALLOWED_W   ,Masters 3/6/7/8 write access to Slave 3 (MSS DDR bridge) " "Disabled,Enabled"
textline "                                  "
bitfld.long 0x8 6. " MM3_6_7_8_MS3_ALLOWED_R   ,Masters 3/6/7/8 read access to Slave 3 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x8 5. "                     MM3_6_7_8_MS2_ALLOWED_W   ,Masters 3/6/7/8 write access to Slave 2 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x8 4. "          MM3_6_7_8_MS2_ALLOWED_R   ,Masters 3/6/7/8 read access to Slave 2 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x8 3. " MM3_6_7_8_MS1_ALLOWED_W   ,Masters 3/6/7/8 write access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x8 2. "                     MM3_6_7_8_MS1_ALLOWED_R   ,Masters 3/6/7/8 read access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x8 1. "          MM3_6_7_8_MS0_ALLOWED_W   ,Masters 3/6/7/8 write access to Slave 0 (MSS DDR bridge) " "Disabled,Enabled"
textline "                                  "
bitfld.long 0x8 0. " MM3_6_7_8_MS0_ALLOWED_R   ,Masters 3/6/7/8 read access to Slave 0 (MSS DDR bridge)" "Disabled,Enabled"
line.long 0x0c "MM9_SECURITY,Security Configuration Register for Master 9"
bitfld.long 0x0c 9. " MM9_MS6_ALLOWED_W         ,Master 9 write access to Slave 6 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x0c 8. "                     MM9_MS6_ALLOWED_R         ,Master 9 read access to Slave 6 (MSS DDR bridge) " "Disabled,Enabled"
bitfld.long 0x0c 7. "          MM9_MS3_ALLOWED_W         ,Master 9 write access to Slave 3 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x0c 6. " MM9_MS3_ALLOWED_R         ,Master 9 read access to Slave 3 (MSS DDR bridge) " "Disabled,Enabled"
bitfld.long 0x0c 5. "                     MM9_MS2_ALLOWED_W         ,Master 9 write access to Slave 2 (MSS DDR bridge) " "Disabled,Enabled"
bitfld.long 0x0c 4. "          MM9_MS2_ALLOWED_R         ,Master 9 read access to Slave 2 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x0c 3. " MM9_MS1_ALLOWED_W         ,Master 9 write access to Slave 1 (MSS DDR bridge)" "Disabled,Enabled"
bitfld.long 0x0c 2. "                     MM9_MS1_ALLOWED_R         ,Master 9 read access to Slave 1 (MSS DDR bridge) " "Disabled,Enabled"
bitfld.long 0x0c 1. "          MM9_MS0_ALLOWED_W         ,Master 9 write access to Slave 0 (MSS DDR bridge)" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x0c 0. " MM9_MS0_ALLOWED_R         ,Master 9 read access to Slave 0 (MSS DDR bridge) " "Disabled,Enabled"
line.long 0x10 "M3_SR,M3 Status Register"
hexmask.long.byte 0x10 0.--7. 1. " CURRPRI                   ,Indicates which priority interrupt, or base boost, is being used now"
line.long 0x14 "ETM_COUNT_LOW,ETM Count Low Register"
line.long 0x18 "ETM_COUNT_HIGH,ETM Count High Register"
bitfld.long 0x18 25.--27. " ETMINTSTAT                ,Indicates the interrupt status" "No status,Interrupt entry,Interrupt exit,Interrupt return,Vector fetch and stack push,?..."
hexmask.long.word 0x18 16.--24. 1. "  ETMINTNUM                 ,Marks the interrupt number of the current execution context"
hexmask.long.word 0x18 0.--15. 1. "              ETMCOUNT_47_32            ,Indicates the 47 to 32 of timestamp value"
line.long 0x1c "DEVICE_SR,Device Status Register"
bitfld.long 0x1c 6. " M3_DEBUG_ENABLE           ,Writing 1 to this bit enables the debug access port (DAP) logic within the Cortex-M3 processor" "Disabled,Enabled"
bitfld.long 0x1c 5. "                     M3_DISABLE                ,This RO-U bit is used to disable/enable the Cortex-M3 processor" "Not reset,Reset"
bitfld.long 0x1c 4. "         FLASH_VALID_SYNC          ,This bit is asserted when FPGA fabric is valid" "Not valid,Valid"
textline "                                  "
bitfld.long 0x1c 3. " WATCHDOG_FREEZE_SYNC      ,This bit, when asserted, freezes the watchdog counter" "Not freeze,Freeze"
bitfld.long 0x1c 2. "                   FF_IN_PROGRESS_SYNC       ,This bit indicates the FF_IN_PROGRESS STATE" "0,1"
bitfld.long 0x1c 1. "                 VIRGIN_PART               ,This bit indicates the device as virgin or non-virgin type" "Non virgin,Virgin"
textline "                                  "
bitfld.long 0x1c 0. " CORE_UP_SYNC              ,This bit indicates the status of the synchronized CORE_UP input from the system controller" "0,1"
line.long 0x20 "ENVM_PROTECT_USER,eNVM Protect User Register"
bitfld.long 0x20 15. " NVM1_UPPER_WRITE_ALLOWED  , Write access to the upper protection region of eNVM1" "Disabled,Enabled"
bitfld.long 0x20 14. "                     NVM1_UPPER_OTHERS_ACCESS  ,Other to access the upper protection region of eNVM1" "Disabled,Enabled"
bitfld.long 0x20 13. "          NVM1_UPPER_FABRIC_ACCESS  ,The fabric access to the upper protection region of eNVM1" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x20 12. " NVM1_UPPER_M3ACCESS       ,The Cortex-M3 processor access to the upper protection region of eNVM1" "Disabled,Enabled"
bitfld.long 0x20 11. "                     NVM1_LOWER_WRITE_ALLOWED  ,The masters who have read access can have write access to the lower region of eNVM1" "Disabled,Enabled"
bitfld.long 0x20 10. "          NVM1_LOWER_OTHERS_ACCESS  ,The other masters access to the lower protection region of eNVM1" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x20 9. " NVM1_LOWER_FABRIC_ACCESS  ,The fabric access to the lower protection region of eNVM1" "Disabled,Enabled"
bitfld.long 0x20 8. "                     NVM1_LOWER_M3ACCESS       ,The M3 access to the lower protection region of eNVM1" "Disabled,Enabled"
bitfld.long 0x20 7. "          NVM0_UPPER_WRITE_ALLOWED  ,The masters who have read access can have write access to the upper region of eNVM0" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x20 6. " NVM0_UPPER_OTHERS_ACCESS  ,The other masters access to the upper protection region of eNVM0" "Disabled,Enabled"
bitfld.long 0x20 5. "                     NVM0_UPPER_FABRIC_ACCESS  ,The fabric access to the upper protection region of eNVM0" "Disabled,Enabled"
bitfld.long 0x20 4. "          NVM0_UPPER_M3ACCESS       ,The M3 access to the upper protection region of eNVM0" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x20 3. " NVM0_LOWER_WRITE_ALLOWED  ,The masters who have read access can have write access to the lower protection region of eNVM0" "Disabled,Enabled"
bitfld.long 0x20 2. "                     NVM0_LOWER_OTHERS_ACCESS  ,The other masters access to the lower protection region of eNVM0" "Disabled,Enabled"
bitfld.long 0x20 1. "          NVM0_LOWER_FABRIC_ACCESS  ,The fabric access to the lower protection region of eNVM0" "Disabled,Enabled"
textline "                                  "
bitfld.long 0x20 0. " NVM0_LOWER_M3ACCESS       ,The M3 access to the lower protection region of eNVM0" "Disabled,Enabled"
line.long 0x24 "ENVM_STATUS,Smart Fusion2 eNVM Status Register"
bitfld.long 0x24 0. " CODE_SHADOW_EN            ,This register is read by the system controller during device start-up" "Disabled,Enabled"
line.long 0x28 "DEVICE_VERSION,Device Version Register"
bitfld.long 0x28 16.--19. " IDV                       ,Internal device version (4 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x28 0.--15. 1. "                           IDP                       ,Internal device product (16 bits)"
line.long 0x2c "MSSDDR_PLL_STATUS,MSS DDR PLL Status Register"
bitfld.long 0x2c 3. " RCOSC_DIV2                ,RC oscillator is running at 25 MHz or 50 MHz" "25 MHz,50 MHz"
bitfld.long 0x2c 2. "                       MPLL_LOCK                 ,Input lock signal from MPLL" "Not locked,Locked"
bitfld.long 0x2c 1. "        FAB_PLL_LOCK              ,If CLK_BASE is generated from a PLL in the fabric, this signal must be connected from the LOCK output of that PLL" "Not locked,Locked"
textline "                                  "
bitfld.long 0x2c 0. " FACC_PLL_LOCK             ,This signal is used to indicate to the user logic in the fabric when it is safe to begin communicating with the MSS" "Not aligned,Aligned"
line.long 0x30 "USB_SR,USB Status Register"
bitfld.long 0x30 1. " LPI_CARKIT_EN             ,CarKit mode status" "Disabled,Enabled"
bitfld.long 0x30 0. "                     POWERDN                   , CLK power down" "Not powered down,Powered down"
line.long 0x34 "ENVM_SR,eNVM Status Register"
bitfld.long 0x34 1. " ENVM_BUSY1                ,Active low signals indicate a busy state per eNVM" "Not busy,Busy"
bitfld.long 0x34 0. "                     ENVM_BUSY0                ,Active low signals indicate a busy state per eNVM" "Not busy,Busy"
rgroup.long 0x160++0x2f
line.long 0x00 "DDRB_STATUS,DDRB Status Register"
bitfld.long 0x00 30.--31. " SYR_DDRB_DP               ,DSG write buffer mode status" "0,1,2,3"
bitfld.long 0x00 28.--29. "                            SYR_DDRB_DP               ,AHB bus write buffer mode status" "0,1,2,3"
bitfld.long 0x00 26.--27. "                 SYR_DDRB_DP               ,HPDMA write buffer mode status" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 23.--25. " SYR_DDRB_DP               ,IDC read buffer mode status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "                            SYR_DDRB_DP               ,DSG read buffer mode status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 17.--19. "                 SYR_DDRB_DP               ,AHB bus read buffer mode status" "0,1,2,3,4,5,6,7"
textline "                                  "
bitfld.long 0x00 14.--16. " SYR_DDRB_DP               ,HPDMA read buffer mode status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--27. "                            SYR_DDRB_DP               ,DSG write request to arbiter" "0,1,2,3"
bitfld.long 0x00 13. "                 SYR_DDRB_DP               ,HPDMA write buffer mode status" "0,1"
textline "                                  "
bitfld.long 0x00 12. " SYR_DDRB_DP               ,AHB bus write request to arbiter" "0,1"
bitfld.long 0x00 11. "                            SYR_DDRB_DP               ,HPDMA write request to arbiter" "0,1"
bitfld.long 0x00 10. "                 SYR_DDRB_DP               ,IDC read req to arbiter" "0,1"
textline "                                  "
bitfld.long 0x00 9. " SYR_DDRB_DP               ,DSG read req to arbiter" "0,1"
bitfld.long 0x00 8. "                            SYR_DDRB_DP               ,AHB bus read req to arbiter" "0,1"
bitfld.long 0x00 7. "                 SYR_DDRB_DP               ,HPDMA read request to arbiter" "0,1"
textline "                                  "
bitfld.long 0x00 6. " SYR_DDRB_DP               ,AXI write address channel acknowledge to DSG write request" "0,1"
bitfld.long 0x00 5. "                            SYR_DDRB_DP               ,AXI write address channel acknowledge to AHB bus write request" "0,1"
bitfld.long 0x00 4. "                 SYR_DDRB_DP               ,AXI write address channel acknowledge to HPDMA write request" "0,1"
textline "                                  "
bitfld.long 0x00 3. " SYR_DDRB_DP               ,AXI write data channel acknowledge to DSG write request" "0,1"
bitfld.long 0x00 2. "                            SYR_DDRB_DP               ,AXI write data channel acknowledge to AHB bus write request" "0,1"
bitfld.long 0x00 1. "                 SYR_DDRB_DP               ,AXI write data channel acknowledge to HPDMA write request" "0,1"
textline "                                  "
bitfld.long 0x00 0. " SYR_DDRB_DP               ,Lock input to arbiter from AHB bus WCB" "0,1"
line.long 0x04 "MDDR_IO_CALIB_STATUS,MDDR IO Calibration Status Register"
bitfld.long 0x04 14. " CALIB_PCOMP               ,The state of the P analog comparator" "0,1"
bitfld.long 0x04 13. "                            CALIB_NCOMP               ,The state of the N analog comparator" "0,1"
hexmask.long.byte 0x04 6.--12. 1. "                 CALIB_PCODE               ,The current PCODE value set on the MDDR DDR I/O bank"
textline "                                  "
bitfld.long 0x04 1.--5. " CALIB_NCODE               ,The current NCODE value set on the MDDR DDR I/O bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "                           CALIB_STATUS              ,This is 1 when the codes are actually locked" "0,1"
line.long 0x08 "MSSDDR_CLK_CALIB_STATUS,MSS DDR Clock Calibration Status"
bitfld.long 0x08 0. " FAB_CALIB_FAIL            ,This bit indicates the status of a fabric clock calibration test" "Correct,Fail"
line.long 0x0c "WDOGLOAD,Watch Dog Load Register"
hexmask.long 0x0c 0.--25. 1. " G4_TESTWDOGLOAD           ,This flash bit contains upper 26 bits of the WDOGLOAD value register"
line.long 0x10 "G4_TESTWDOGMVRP,This user flash bit contains the WDOGMVRP value"
line.long 0x14 "USERCONFIG0,User Configuration Register 0"
line.long 0x18 "USERCONFIG1,User Configuration Register 1"
line.long 0x1c "USERCONFIG2,User Configuration Register 2"
line.long 0x20 "USERCONFIG3,User Configuration Register 3"
line.long 0x24 "FAB_PROT_SIZE,Fabric Protected Size Register"
hexmask.long.byte 0x24 0.--5. 1. " SW_PROTREGIONSIZE         ,Size of the memory region inaccessible to the FPGA fabric master"
line.long 0x28 "FAB_PROT_BASE,Fabric Protected Base Address Register"
line.long 0x2c "MSS_GPIO_DEF,MSS GPIO Definitions"
bitfld.long 0x2c 3. " MSS_GPIO_31_24_DEF        ,This bit is used to initialize GPIO Bank [31:24] to 0 or 1" "0,1"
bitfld.long 0x2c 2. "                            MSS_GPIO_23_16_DEF        ,This bit is used to initialize GPIO Bank [23:16] to 0 or 1" "0,1"
bitfld.long 0x2c 1. "                 MSS_GPIO_15_8_DEF         ,This bit is used to initialize GPIO Bank [15:8] to 0 or 1" "0,1"
textline "                                  "
bitfld.long 0x2c 0. " MSS_GPIO_7_0_DEF          ,This bit is used to initialize GPIO Bank [7:0] to 0 or 1" "0,1"
group.long 0x190++0xf
line.long 0x00 "EDAC_SR,EDAC Status Register"
eventfld.long 0x00 13. " CAN_EDAC_2E               ,This status is updated by CAN when a 2-bit SECDED error has been detected for RAM memory" "Not occurred,Occurred"
eventfld.long 0x00 12. "                 CAN_EDAC_1E               ,This status is updated by CAN when a 1-bit SECDED error has been detected and is corrected for RAM memory" "No action,Corrected"
eventfld.long 0x00 11. "         USB_EDAC_2E               ,This status is updated by USB when a 2-bit SECDED error has been detected for RAM memory" "Not occurred,Occurred"
textline "                                  "
eventfld.long 0x00 10. " USB_EDAC_1E               ,This status is updated by USB when a 1-bit SECDED error has been detected and is corrected for RAM memory" "No action,Corrected"
eventfld.long 0x00 9. "                    MAC_EDAC_RX_2E            ,This status is updated by Ethernet when a 2-bit SECDED error has been detected for Rx RAM memory" "No action,Corrected"
eventfld.long 0x00 8. "         MAC_EDAC_RX_1E            ,This status is updated by Ethernet when a 1-bit SECDED error has been detected and is corrected for Rx RAM memory" "No action,Corrected"
textline "                                  "
eventfld.long 0x00 7. " MAC_EDAC_TX_2E            ,This status is updated by Ethernet when a 2-bit SECDED error has been detected for Tx RAM memory" "Not occurred,Occurred"
eventfld.long 0x00 6. "                 MAC_EDAC_TX_E             ,This status is updated by Ethernet when a 1-bit SECDED error has been detected and is corrected for Tx RAM memory" "No action,Corrected"
eventfld.long 0x00 3. "         ESRAM1_EDAC_2E            ,This status is updated by the eSRAM_1 controller when a 2-bit SECDED error has been detected for eSRAM1 memory" "Not occurred,Occurred"
textline "                                  "
eventfld.long 0x00 2. " ESRAM1_EDAC_1E            ,This status is updated by the eSRAM_1 Controller when a 1-bit SECDED error has been detected and is corrected for eSRAM1" "No action,Corrected"
eventfld.long 0x00 1. "                    ESRAM0_EDAC_2E            ,This status is updated by the eSRAM_0 controller when a 2-bit SECDED error has been detected for eSRAM0 memory" "Not occurred,Occurred"
eventfld.long 0x00 0. "      ESRAM0_EDAC_1E            ,This status is updated by the eSRAM_0 controller when a 1-bit SECDED error has been detected and is corrected for eSRAM0" "No action,Corrected"
line.long 0x04 "MSS_INTERNAL_SR,MSS Internal Status Register"
eventfld.long 0x04 6. " FIC64_INT                 ,This bit indicates an interrupt from DDR_FIC" "No interrupt,Interrupt"
eventfld.long 0x04 5. "                 MDDR_ECC_INT              ,This bit indicates when an SECDED interrupt from the MDDR subsystem is asserted" "0,1"
eventfld.long 0x04 4. "                 MDDR_IO_CALIB_INT         ,The interrupt is generated when the calibration is finished" "Not gemnerated,Generated"
textline "                                  "
eventfld.long 0x04 3. " FAB_PLL_LOCKLOST_INT      ,This bit indicates that a falling edge event occurred on the FAB_PLL_LOCK signal" "Not occurred,Occurred"
eventfld.long 0x04 2. "                 FAB_PLL_LOCK_INT          ,This bit indicates that a rising edge event occurred on the FAB_PLL_LOCK signal" "Not occurred,Occurred"
eventfld.long 0x04 1. "      MPLL_LOCKLOST_INT         ,This bit indicates that a falling edge event occurred on the MPLL_LOCK signal" "Not occurred,Occurred"
textline "                                  "
eventfld.long 0x04 0. " MPLL_LOCK_INT             ,This bit indicates that a rising edge event occurred on the MPLL_LOCK signal" "Not occurred,Occurred"
line.long 0x08 "MSS_EXTERNAL_SR,MSS External Status Register"
eventfld.long 0x08 18. " CC_HRESP_ERR              ,HRESP assertion issue" "Slave to the CACHE,To the master"
eventfld.long 0x08 17. "           DDRB_LOCK_MID             ,Lock timeout condition responsible" "AHB bus master,HPDMA"
eventfld.long 0x08 16. "    DDRB_LCKOUT               ,Asserted when lock timeout counter reaches its maximum value" "Not reached,Reached"
textline "                                  "
eventfld.long 0x08 15. " DDRB_HPD_WR_ERR           ,Asserted when the MSS DDR bridge gets an error response from the DDR slave for an HPDMA write request" "No error,Error"
eventfld.long 0x08 14. "                     DDRB_SW_WR_ERR            ,Asserted when the MSS DDR bridge gets an error response from the DDR slave for an AHB bus master write request" "No error,Error"
eventfld.long 0x08 13. "          DDRB_DS_WR_ERR            ,Asserted when the MSS DDR bridge gets an error response from the DDR slave for a DS master write request" "No error,Error"
textline "                                  "
bitfld.long 0x08 12. " DDRB_RDWR_ERR_REG5        ,IDC and DS are trying to access same address" "No error,Error"
bitfld.long 0x08 11. "                     DDRB_RDWR_ERR_REG4        ,IDC and AHB Bus are trying to access same address" "No error,Error"
bitfld.long 0x08 10. "          DDRB_RDWR_ERR_REG3        ,IDC and HPDMA are trying to access same address" "No error,Error"
textline "                                  "
bitfld.long 0x08 9. " DDRB_RDWR_ERR_REG2        ,HPDMA and DS are trying to access same address" "No error,Error"
bitfld.long 0x08 8. "                     DDRB_RDWR_ERR_REG1        ,AHB bus and DS are trying to access same address" "No error,Error"
bitfld.long 0x08 7. "          DDRB_RDWR_ERR_REG0        ,AHB bus and HPDMA are trying to access same address" "No error,Error"
textline "                                  "
bitfld.long 0x08 6. " SW_ERRORSTATUS6           ,Corresponds to an HRESP assertion being issued to the HPDMA interface" "No error,Error"
bitfld.long 0x08 5. "                     SW_ERRORSTATUS5           ,Corresponds to an HRESP assertion being issued to FIC_0 interface" "No error,Error"
bitfld.long 0x08 4. "          SW_ERRORSTATUS4           ,Corresponds to an HRESP assertion being issued to FIC_1 System interface S interface" "No error,Error"
textline "                                  "
bitfld.long 0x08 3. " SW_ERRORSTATUS3           ,Corresponds to an HRESP assertion being issued to the Ethernet MAC" "No error,Error"
bitfld.long 0x08 2. "                     SW_ERRORSTATUS2           ,Corresponds to an HRESP assertion being issued to the peripheral DMA engine" "No error,Error"
bitfld.long 0x08 1. "          SW_ERRORSTATUS1           ,Corresponds to an HRESP assertion being issued to the USB" "No error,Error"
textline "                                  "
bitfld.long 0x08 0. " SW_ERRORSTATUS0           ,Corresponds to an HRESP assertion being issued to the system controller" "No error,Error"
line.long 0x0c "WDOGTIMEOUTEVENT,Watchdog Timeout Event"
eventfld.long 0x0c 0. " WDOGTIMEOUTEVENT          ,This allows firmware to determine if a system reset occurred due to a watchdog timeout event" "Not occurred,Occurred"
wgroup.long 0x1A0++0xf
line.long 0x00 "CLR_MSS_COUNTERS,Clear MSS Counters"
bitfld.long 0x00 5. " CC_DC_TRANS_CNTCLR        ,CC_DC_TRANS_CNT counter reset" "No reset,Reset"
bitfld.long 0x00 4. "                     CC_IC_TRANS_CNTCLR        ,CC_IC_TRANS_CNT counter reset"  "No reset,Reset"
bitfld.long 0x00 3. "          CC_DC_HIT_CNTCLR          ,CC_DC_HIT_CNT counter reset" "No reset,Reset"
textline "                                  "
bitfld.long 0x00 2. " CC_DC_MISS_CNTCLR         ,CC_DC_MISS_CNT counter reset" "No reset,Reset"
bitfld.long 0x00 1. "                     CC_IC_HIT_CNTCLR          ,CC_IC_HIT_CNT counter reset" "No reset,Reset"
bitfld.long 0x00 0. "          CC_IC_MISS_CNTCLR         ,CC_IC_MISS_CNT counter reset" "No reset,Reset"
line.long 0x04 "CLR_EDAC_COUNTERS,Clear EDAC Counters"
bitfld.long 0x04 13. " CAN_EDAC_CNTCLR_2E        ,CAN_EDAC_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 12. "                    CAN_EDAC_CNTCLR_1E        ,CAN_EDAC_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 11. "         USB_EDAC_CNTCLR_2E        ,USB_EDAC_CNT counter reset" "No effect,Clear"
textline "                                  "
bitfld.long 0x04 10. " USB_EDAC_CNTCLR_1E        ,USB_EDAC_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 9. "                    MAC_EDAC_RX_CNTCLR_2E     ,MAC_EDAC_RX_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 8. "         MAC_EDAC_RX_CNTCLR_1E     ,MAC_EDAC_RX_CNT upper 16 bits clear" "No effect,Clear"
textline "                                  "
bitfld.long 0x04 7. " MAC_EDAC_TX_CNTCLR_2E     ,MAC_EDAC_TX_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 6. "                    MAC_EDAC_TX_CNTCLR_1E     ,MAC_EDAC_TX_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 3. "         ESRAM1_EDAC_CNTCLR_2E     ,ESRAM1_EDAC_CNT upper 16 bits clear" "No effect,Clear"
textline "                                  "
bitfld.long 0x04 2. " ESRAM1_EDAC_CNTCLR_1E     ,ESRAM1_EDAC_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 1. "                    ESRAM0_EDAC_CNTCLR_2E     ,ESRAM0_EDAC_CNT upper 16 bits clear" "No effect,Clear"
bitfld.long 0x04 0. "         ESRAM0_EDAC_CNTCLR_1E     ,ESRAM0_EDAC_CNT upper 16 bits clear" "No effect,Clear"
line.long 0x08 "FLUSH_CR,Flush Configuration Register"
bitfld.long 0x08 8. " DDRB_INVALID_IDC          ,Invalidate IDC read buffer" "No effect,Invalidate"
bitfld.long 0x08 7. "                   DDRB_INVALID_HPD          ,Invalidate HPD read buffer" "No effect,Invalidate"
bitfld.long 0x08 6. "        DDRB_INVALID_SW           ,Invalidate SW read buffer" "No effect,Invalidate"
textline "                                  "
bitfld.long 0x08 5. " DDRB_INVALID_DS           ,Invalidate DS read buffer" "No effect,Invalidate"
bitfld.long 0x08 4. "                   DDRB_FLSHSW               ,Invalidate AHB read buffer" "No effect,Flush"
bitfld.long 0x08 3. "         DDRB_FLSHHPD              ,Flush HPD write access" "No effect,Flush"
textline "                                  "
bitfld.long 0x08 2. " DDRB_FLSHDS               ,Flush DSG write access" "No effect,Flush"
bitfld.long 0x08 1. "                    CC_FLUSH_CHLINE           ,Flush only one index" "No effect,Flush"
bitfld.long 0x08 0. "         CC_FLUSH_CACHE            ,Flush cache memory" "No effect,Flush"
line.long 0x0c "MAC_STAT_CLR_CR,MAC Status Clear Control Register"
bitfld.long 0x0c 0. " MAC_STAT_CLR              ,Writing a '1' to this bit will clear the MAC statistics registers" "No effect,Clear"
tree "IOMUXCELL Configuration Registers"
group.long 0x1b0++0xe7
line.long 0x0 "IOMUXCELL_CONFIG[0],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x0 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x0 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x0 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x0 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x0 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x0 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x4 "IOMUXCELL_CONFIG[1],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x4 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x4 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x4 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x4 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x4 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x4 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x8 "IOMUXCELL_CONFIG[2],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x8 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x8 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x8 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x8 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x8 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x8 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xC "IOMUXCELL_CONFIG[3],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xC 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xC 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xC 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xC 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x10 "IOMUXCELL_CONFIG[4],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x10 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x10 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x10 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x10 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x10 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x10 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x14 "IOMUXCELL_CONFIG[5],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x14 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x14 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x14 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x14 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x14 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x14 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x18 "IOMUXCELL_CONFIG[6],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x18 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x18 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x18 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x18 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x18 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x18 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x1C "IOMUXCELL_CONFIG[7],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x1C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x1C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x1C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x1C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x1C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x1C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x20 "IOMUXCELL_CONFIG[8],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x20 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x20 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x20 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x20 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x20 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x20 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x24 "IOMUXCELL_CONFIG[9],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x24 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x24 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x24 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x24 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x24 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x24 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x28 "IOMUXCELL_CONFIG[10],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x28 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x28 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x28 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x28 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x28 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x28 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x2C "IOMUXCELL_CONFIG[11],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x2C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x2C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x2C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x2C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x2C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x2C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x30 "IOMUXCELL_CONFIG[12],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x30 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x30 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x30 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x30 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x30 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x30 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x34 "IOMUXCELL_CONFIG[13],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x34 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x34 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x34 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x34 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x34 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x34 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x38 "IOMUXCELL_CONFIG[14],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x38 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x38 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x38 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x38 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x38 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x38 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x3C "IOMUXCELL_CONFIG[15],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x3C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x3C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x3C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x3C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x3C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x3C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x40 "IOMUXCELL_CONFIG[16],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x40 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x40 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x40 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x40 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x40 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x40 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x44 "IOMUXCELL_CONFIG[17],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x44 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x44 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x44 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x44 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x44 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x44 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x48 "IOMUXCELL_CONFIG[18],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x48 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x48 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x48 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x48 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x48 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x48 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x4C "IOMUXCELL_CONFIG[19],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x4C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x4C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x4C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x4C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x4C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x4C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x50 "IOMUXCELL_CONFIG[20],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x50 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x50 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x50 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x50 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x50 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x50 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x54 "IOMUXCELL_CONFIG[21],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x54 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x54 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x54 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x54 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x54 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x54 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x58 "IOMUXCELL_CONFIG[22],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x58 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x58 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x58 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x58 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x58 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x58 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x5C "IOMUXCELL_CONFIG[23],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x5C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x5C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x5C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x5C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x5C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x5C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x60 "IOMUXCELL_CONFIG[24],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x60 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x60 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x60 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x60 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x60 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x60 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x64 "IOMUXCELL_CONFIG[25],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x64 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x64 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x64 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x64 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x64 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x64 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x68 "IOMUXCELL_CONFIG[26],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x68 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x68 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x68 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x68 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x68 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x68 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x6C "IOMUXCELL_CONFIG[27],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x6C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x6C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x6C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x6C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x6C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x6C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x70 "IOMUXCELL_CONFIG[28],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x70 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x70 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x70 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x70 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x70 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x70 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x74 "IOMUXCELL_CONFIG[29],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x74 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x74 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x74 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x74 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x74 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x74 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x78 "IOMUXCELL_CONFIG[30],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x78 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x78 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x78 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x78 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x78 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x78 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x7C "IOMUXCELL_CONFIG[31],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x7C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x7C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x7C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x7C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x7C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x7C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x80 "IOMUXCELL_CONFIG[32],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x80 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x80 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x80 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x80 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x80 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x80 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x84 "IOMUXCELL_CONFIG[33],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x84 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x84 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x84 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x84 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x84 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x84 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x88 "IOMUXCELL_CONFIG[34],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x88 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x88 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x88 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x88 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x88 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x88 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x8C "IOMUXCELL_CONFIG[35],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x8C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x8C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x8C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x8C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x8C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x8C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x90 "IOMUXCELL_CONFIG[36],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x90 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x90 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x90 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x90 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x90 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x90 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x94 "IOMUXCELL_CONFIG[37],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x94 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x94 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x94 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x94 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x94 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x94 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x98 "IOMUXCELL_CONFIG[38],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x98 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x98 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x98 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x98 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x98 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x98 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0x9C "IOMUXCELL_CONFIG[39],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0x9C 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0x9C 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0x9C 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x9C 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0x9C 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0x9C 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xA0 "IOMUXCELL_CONFIG[40],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xA0 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xA0 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xA0 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xA0 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xA0 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xA0 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xA4 "IOMUXCELL_CONFIG[41],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xA4 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xA4 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xA4 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xA4 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xA4 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xA4 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xA8 "IOMUXCELL_CONFIG[42],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xA8 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xA8 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xA8 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xA8 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xA8 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xA8 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xAC "IOMUXCELL_CONFIG[43],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xAC 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xAC 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xAC 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xAC 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xAC 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xAC 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xB0 "IOMUXCELL_CONFIG[44],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xB0 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xB0 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xB0 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xB0 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xB0 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xB0 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xB4 "IOMUXCELL_CONFIG[45],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xB4 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xB4 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xB4 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xB4 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xB4 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xB4 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xB8 "IOMUXCELL_CONFIG[46],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xB8 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xB8 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xB8 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xB8 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xB8 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xB8 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xBC "IOMUXCELL_CONFIG[47],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xBC 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xBC 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xBC 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xBC 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xBC 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xBC 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xC0 "IOMUXCELL_CONFIG[48],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xC0 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xC0 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xC0 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC0 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xC0 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC0 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xC4 "IOMUXCELL_CONFIG[49],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xC4 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xC4 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xC4 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC4 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xC4 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC4 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xC8 "IOMUXCELL_CONFIG[50],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xC8 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xC8 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xC8 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC8 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xC8 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xC8 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xCC "IOMUXCELL_CONFIG[51],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xCC 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xCC 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xCC 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xCC 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xCC 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xCC 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xD0 "IOMUXCELL_CONFIG[52],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xD0 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xD0 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xD0 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xD0 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xD0 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xD0 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xD4 "IOMUXCELL_CONFIG[53],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xD4 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xD4 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xD4 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xD4 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xD4 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xD4 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xD8 "IOMUXCELL_CONFIG[54],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xD8 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xD8 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xD8 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xD8 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xD8 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xD8 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xDC "IOMUXCELL_CONFIG[55],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xDC 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xDC 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xDC 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xDC 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xDC 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xDC 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
line.long 0xE0 "IOMUXCELL_CONFIG[56],IOMUXCELL_CONFIG Configuration Register"
bitfld.long 0xE0 7.--9. " MSS_IOMUXSEL5UPPER ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
bitfld.long 0xE0 4.--6. "  MSS_IOMUXSEL4UPPER ,This field is used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL" "1,0,From OE of interface MSS GPIO,From OE of interface serial comms,From OE of interface USB controller,?..."
textline "                                  "
bitfld.long 0xE0 3. " MSS_IOMUXSEL3      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xE0 2. "               MSS_IOMUXSEL2      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
textline "                                  "
bitfld.long 0xE0 1. " MSS_IOMUXSEL1      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
bitfld.long 0xE0 0. "               MSS_IOMUXSEL0      ,Source of the OE port of the I/O cell corresponding to this IOMUXCELL" "Interface MSS GPIO,Interface serial comms"
tree.end
width 0xb
tree.end
tree "FIIC (Fabric Interface Interrupt Controller)"
base ad:0x40006000
width 19.
group.long 0x00++0x7
line.long 0x00 "INTERRUPT_ENABLE0,Enables MSS to fabric interrupts"
bitfld.long 0x00 30. " USB_DMA_INT_ENBL       ,Enables the USB_DMA_INT interrupt from USBs DMA controller to fabric" "Disabled,Enabled"
bitfld.long 0x00 29. "  COMBLK_INTR_ENBL            ,Enables the COMBLK_INTR interrupt from the COMM_BLK block to fabric" "Disabled,Enabled"
bitfld.long 0x00 28. "  SOFTINTERRUPT_ENBL       ,Enables the SOFTINTERRUPT interrupt from the SYSREG block to fabric" "Disabled,Enabled"
bitfld.long 0x00 27. "  CACHE_ERRINTR_ENBL             ,Enables the CACHE_ERRINTR interrupt from the cache controller block to fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 26. " ECCINTR_ENBL           ,Enables the ECCINTR interrupt from ESRAM0, ESRAM1, the cache controller, CAN, MDDR, and USB to fabric" "Disabled,Enabled"
bitfld.long 0x00 25. "  DDRB_INTR_ENBL              ,Enables the MSS DDR bridge DDRB_INTR to fabric" "Disabled,Enabled"
bitfld.long 0x00 24. "  SW_ERRORINTERRUPT_ENBL   ,Enables the SW_ERRORINTERRUPT interrupt from the SYSREG block to fabric" "Disabled,Enabled"
bitfld.long 0x00 23. "  MSSDDR_PLL_LOCK_INT_ENBL       ,Enables the MSSDDR_PLL_LOCK_INT interrupt from the MPLL block to fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 22. " HPD_XFR_ERR_INT_ENBL   ,Enables the HPD_XFR_ERR_INT interrupt from the MSS HPDMA block to fabric" "Disabled,Enabled"
bitfld.long 0x00 21. "  I2C_SMBSUS1_ENBL            ,Enables the I2C_SMBSUS1 interrupt from the MSS I2C_1 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 20. "  I2C_SMBALERT1_ENBL       ,Enables the I2C_SMBALERT1 interrupt from the MSS I2C_1 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 19. "  I2C_SMBSUS0_ENBL               ,Enables the I2C_SMBSUS0 interrupt from the MSS I2C_0 block to fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 18. " I2C_SMBALERT0_ENBL     ,Enables the I2C_SMBALERT0 interrupt from MSS I2C_0 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 17. "  ENVM_INT1_ENBL              ,Enables the ENVM_INT1 interrupt from MSS ENVM1 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 16. "  ENVM_INT0_ENBL           ,Enables the ENVM_INT0 interrupt from the MSS ENVM0 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 15. "  MSSDDR_PLL_LOCKLOST_INT         ,Enables the MSSDDR_PLL_LOCKLOST_INT interrupt from MPLL to the fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 14. " WDOGWAKEUPINT_ENBL     ,Enables the WDOGWAKEUPINT interrupt from the MSS Watchdog block to fabric" "Disabled,Enabled"
bitfld.long 0x00 13. "  RTC_WAKEUP_INTR_ENBL        ,Enables the RTC_WAKEUP_INTR interrupt from the MSS RTC block to fabric" "Disabled,Enabled"
bitfld.long 0x00 12. "  CAN_INTR_ENBL            ,Enables the CAN_INTR interrupt from the MSS CAN controller block to fabric" "Disabled,Enabled"
bitfld.long 0x00 11. "  TIMER2_INTR_ENBL               ,Enables the TIMER2_INTR interrupt from the MSS TIMER2 block to fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 10. " TIMER1_INTR_ENBL       ,Enables the TIMER1_INTR interrupt from the MSS TIMER1 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 9. "  HPD_XFR_CMP_INT_ENBL        ,Enables the HPD_XFR_CMP_INT interrupt from the MSS HPDMA block to fabric" "Disabled,Enabled"
bitfld.long 0x00 8. "  PDMAINTERRUPT_ENBL       ,Enables the PDMAINTERRUPT interrupt from the MSS peripheral DMA block to fabric" "Disabled,Enabled"
bitfld.long 0x00 7. "  USB_MC_INT_ENBL                ,Enables the USB_MC_INT interrupt from the MSS USB block to fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 6. " MAC_INT_ENBL           ,Enables the MAC_INT interrupt from the MSS Ethernet MAC block to fabric" "Disabled,Enabled"
bitfld.long 0x00 5. "  MMUART1_INTR_ENBL           ,Enables the MMUART1_INTR interrupt from the MSS MMUART_1 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 4. "  MMUART0_INTR_ENBL        ,Enables the MMUART0_INTR interrupt from the MSS MMUART_0 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 3. "  I2C_INT1_ENBL                  ,Enables the I2C_INT1 interrupt from the MSS I2C_1 block to fabric" "Disabled,Enabled"
textline "                            "
bitfld.long 0x00 2. " I2C_INT0_ENBL          ,Enables the I2C_INT0 interrupt from the MSS I2C_0 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 1. "  SPIINT1_ENBL                ,Enables the SPIINT1 interrupt from the MSS SPI_1 block to fabric" "Disabled,Enabled"
bitfld.long 0x00 0. "  SPIINT0_ENBL             ,Enables the SPIINT0 interrupt from the MSS SPI_0 block to fabric" "Disabled,Enabled"
line.long 0x04 "INTERRUPT_ENABLE1,Enables MSS to fabric interrupts"
bitfld.long 0x04 7. " FIC64_INT_ENBL         ,Enables the FIC64_INT interrupt from the DDR_FIC block" "Disabled,Enabled"
bitfld.long 0x04 6. "  FAB_PLL_LOCKLOST_INT_ENBL   ,Enables the FAB_PLL_LOCKLOST_INT interrupt from FAB_PLL" "Disabled,Enabled"
bitfld.long 0x04 5. "  FAB_PLL_LOCK_INT_ENBL    ,Enables the FAB_PLL_LOCK_INT interrupt from FAB_PLL" "Disabled,Enabled"
bitfld.long 0x04 3. "  MDDR_IO_CALIB_INT_ENBL         ,Enables the MDDR_IO_CALIB_INT interrupt from the MDDR block to fabric" "Disabled,Enabled"
rgroup.long 0x8++0x7
line.long 0x00 "INTERRUPT_REASON0,Indicates which interrupts are active"
bitfld.long 0x00 30. " USB_DMA_INT_STATUS     ,USB_DMA_INT Status" "Not activated,Activated"
bitfld.long 0x00 29. "   COMBLK_INT Status          , COMBLK_INTR_STATUS" "Not activated,Activated"
bitfld.long 0x00 28. "   SOFTINTERRUPT_STATUS     ,SOFTINTERRUPT Status" "Not activated,Activated"
bitfld.long 0x00 27. "   CACHE_ERRINTR_STATUS           ,CACHE_ERRINTR Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 26. " ECCINTR_STATUS         , ECCINTR Status" "Not activated,Activated"
bitfld.long 0x00 25. "   DDRB_INTR_STATUS            ,DDRB_INTR Status" "Not activated,Activated"
bitfld.long 0x00 24. "   SW_ERRORINTERRUPT_STATUS ,SW_ERRORINTERRUPT Status" "Not activated,Activated"
bitfld.long 0x00 23. "   MSSDDR_PLL_LOCK_INT_STATUS     ,MSSDDR_PLL_LOCK_INT Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 22. " HPD_XFR_ERR_INT_STATUS ,HPD_XFR_ERR_INT Status" "Not activated,Activated"
bitfld.long 0x00 21. "   I2C_SMBSUS1_STATUS          , I2C_SMBSUS1 Status" "Not activated,Activated"
bitfld.long 0x00 20. "   I2C_SMBALERT1_STATUS     ,I2C_SMBALERT1 Status " "Not activated,Activated"
bitfld.long 0x00 19. "   I2C_SMBSUS0_STATUS             ,I2C_SMBSUS0 Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 18. " I2C_SMBALERT0_STATUS   ,I2C_SMBALERT0 Status" "Not activated,Activated"
bitfld.long 0x00 17. "   ENVM_INT1_STATUS            ,ENVM_INT1 Status" "Not activated,Activated"
bitfld.long 0x00 16. "   ENVM_INT0_STATUS         ,ENVM_INT0 Status" "Not activated,Activated"
bitfld.long 0x00 15. "   MSSDDR_PLL_LOCKLOST_INT_STATUS ,MSSDDR_PLL_LOCKLOST_INT Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 14. " WDOGWAKEUPINT_STATUS   ,WDOGWAKEUPINT Status" "Not activated,Activated"
bitfld.long 0x00 13. "   RTC_WAKEUP_INTR_STATUS      ,RTC_WAKEUP_INTR Status" "Not activated,Activated"
bitfld.long 0x00 12. "   CAN_INTR_STATUS          ,CAN_INTR Status" "Not activated,Activated"
bitfld.long 0x00 11. "   TIMER2_INTR_STATUS             ,TIMER2_INTR Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 10. " TIMER1_INTR_STATUS     ,TIMER1_INTR Status" "Not activated,Activated"
bitfld.long 0x00 9. "   HPD_XFR_CMP_INT_STATUS      ,HPD_XFR_CMP_INT Status" "Not activated,Activated"
bitfld.long 0x00 8. "   PDMAINTERRUPT_STATUS     ,PDMAINTERRUPT Status" "Not activated,Activated"
bitfld.long 0x00 7. "   USB_MC_INT_STATUS              ,USB_MC_INT Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 6. " MAC_INT_STATUS         ,MAC_INT Status" "Not activated,Activated"
bitfld.long 0x00 5. "   MMUART1_INTR_STATUS         , MMUART1_INTR Status" "Not activated,Activated"
bitfld.long 0x00 4. "   MMUART0_INTR_STATUS      ,MMUART0_INTR Status" "Not activated,Activated"
bitfld.long 0x00 3. "   I2C_INT1_STATUS                ,I2C_INT1 Status" "Not activated,Activated"
textline "                            "
bitfld.long 0x00 2. " I2C_INT0_STATUS        ,I2C_INT0 Status" "Not activated,Activated"
bitfld.long 0x00 1. "   SPIINT1_STATUS              ,SPIINT1 Status" "Not activated,Activated"
bitfld.long 0x00 0. "   SPIINT0_STATUS           ,SPIINT0 Status" "Not activated,Activated"
line.long 0x04 "INTERRUPT_REASON1,Indicates which interrupts are active"
bitfld.long 0x04 7. " FIC64_INT_STATUS       ,FIC64_INT Status" "Not activated,Activated"
bitfld.long 0x04 6. "   FAB_PLL_LOCKLOST_INT_STATUS ,FAB_PLL_LOCKLOST_INT Status" "Not activated,Activated"
bitfld.long 0x04 5. "   FAB_PLL_LOCK_INT_STATUS  ,FAB_PLL_LOCK_INT Status" "Not activated,Activated"
bitfld.long 0x04 3. "   MDDR_IO_CALIB_INT_STATUS       , MDDR_IO_CALIB_INT Status" "Not activated,Activated"
group.long 0x10++0x3
line.long 0x00 "INTERRUPT_MODE,Indicates select group 0 or select group 1."
bitfld.long 0x00 0. " SELECT_MODE            ,Select mode" "Group 0,Group 1"
width 0xb
tree.end
tree "DDR"
base ad:0x40020000
width 33.
tree "DDR Controller Configuration Registers"
group.long 0x00++0x3
line.long 0x00 "DDRC_DYN_SOFT_RESET_CR,DDRC Reset register"
bitfld.long 0x00 2. " AXIRESET                                  ,AXI reset signal" "Not asserted,Asserted"
bitfld.long 0x00 1. "              RESET_APB_REG                             ,Full soft reset" "No reset,Reset"
bitfld.long 0x00 0. "     REG_DDRC_SOFT_RSTB           ,Soft reset" "No reset,Reset"
group.long 0x08++0x53
line.long 0x0 "DDRC_DYN_REFRESH_1_CR,DDRC Refresh Control"
hexmask.long.byte 0x00 7.--14. 1. " REG_DDRC_T_RFC_MIN                        ,Minimum time from refresh to refresh or activate"
bitfld.long 0x00 6. "                        REG_DDRC_REFRESH_UPDATE_LEVEL             ,The refresh register(s) have been updated" "Not updated,Updated"
bitfld.long 0x00 5. "  REG_DDRC_SELFREF_EN          ,DRAM in self refresh" "Disabled,Enabled"
textline "                                          "
bitfld.long 0x00 0.--4. " REG_DDRC_REFRESH_TO_X32 ,Speculative refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRC_DYN_REFRESH_2_CR,DDRC Refresh Control"
hexmask.long.word 0x04 3.--14. 1. " REG_DDRC_T_RFC_NOM_X32                    ,Average time between refreshes"
bitfld.long 0x04 0.--2. "                      REG_DDRC_REFRESH_BURST                    ,The number of refresh timeouts" "1,2,3,4,5,6,7,8"
line.long 0x08 "DDRC_DYN_POWERDOWN_CR,DDRC Power-Down Control"
bitfld.long 0x08 1. " REG_DDRC_POWERDOWN_EN                     ,The controller goes into power-down" "Disabled,Enabled"
bitfld.long 0x08 0. "                  REG_DDRC_DEEPPOWERDOWN_EN                 ,DRAM into deep power-down" "Disabled,Enabled"
line.long 0x0c "DDRC_DYN_DEBUG_CR,DDRC Debug register"
bitfld.long 0x0c 0. " REG_DDRC_DIS_DQ                           ,DDRC will not de-queue any transactions from the CAM" "Disabled,Enabled"
line.long 0x10 "DDRC_MODE_CR,DDRC Mode register"
bitfld.long 0x10 8. " REG_DDRC_DDR3                             ,DDR3 operating mode" "DDR2,DDR3"
bitfld.long 0x10 7. "                      REG_DDRC_MOBILE                           ,Mobile/LPDDR1 DRAM device in use" "Disabled,Enabled"
bitfld.long 0x10 6. "     REG_DDRC_SDRAM               ,SDRAM mode" "Disabled,Enabled"
textline "                                          "
bitfld.long 0x10 5. " REG_DDRC_TEST_MODE                        ,Controller is in test mode" "Disabled,Enabled"
bitfld.long 0x10 2.--4. "                  REG_DDRC_MODE                             ,DRAM SECDED mode" "No SECDED,Reserved,Reserved,Reserved,Reserved,SECDED,?..."
bitfld.long 0x10 0.--1. "    REG_DDRC_DATA_BUS_WIDTH      ,Bus width selection" "Full DQ,Half DQ,Quarter DQ,?..."
line.long 0x14 "DDRC_ADDR_MAP_BANK_CR,DDRC Bank Address Map"
bitfld.long 0x14 8.--11. " REG_DDRC_ADDRMAP_BANK_B0                  ,Selects the address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
bitfld.long 0x14 4.--7. "                  REG_DDRC_ADDRMAP_BANK_B1                  ,Selects the address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
bitfld.long 0x14 0.--3. "     REG_DDRC_ADDRMAP_BANK_B2     ,Selects the address bits used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
line.long 0x18 "DDRC_ECC_DATA_MASK_CR,DDRC SECDED Test Data"
hexmask.long.byte 0x18 1.--8. 1. " CO_WU_RXDATA_INT_ECC                      ,Internal SECDED"
bitfld.long 0x18 0. "                        CO_WU_RXDATA_MASK_INT_ECC                 ,Mask to be used during production test" "Not masked,Masked"
line.long 0x1c "DDRC_ADDR_MAP_COL_1_CR,DDRC Column Address Map"
bitfld.long 0x1c 12.--15. " REG_DDRC_ADDRMAP_COL_B2                   ,Address map column B2" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x1c 8.--11. "                  REG_DDRC_ADDRMAP_COL_B3                   ,Address map column B3" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x1c 4.--7. "     REG_DDRC_ADDRMAP_COL_B4      ,Address map column B3" "0,1,2,3,4,5,6,7,?..."
textline "                                          "
bitfld.long 0x1c 0.--3. " REG_DDRC_ADDRMAP_COL_B7 ,Address map column B3" "0,1,2,3,4,5,6,7,?..."
line.long 0x20 "DDRC_ADDR_MAP_COL_2_CR,DDRC Column Address Map"
bitfld.long 0x20 12.--15. " REG_DDRC_ADDRMAP_COL_B8                   ,Address map column B8" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x20 8.--11. "                  REG_DDRC_ADDRMAP_COL_B9                   ,Address map column B9" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x20 4.--7. "     REG_DDRC_ADDRMAP_COL_B10     ,Address map column B10" "0,1,2,3,4,5,6,7,?..."
textline "                                          "
bitfld.long 0x20 0.--3. " REG_DDRC_ADDRMAP_COL_B11                  ,Address map column B11" "0,1,2,3,4,5,6,7,?..."
line.long 0x24 "DDRC_ADDR_MAP_ROW_1_CR,DDRC Row Address Map"
bitfld.long 0x24 12.--15. " REG_DDRC_ADDRMAP_ROW_B0                   ,Row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x24 8.--11. "                  REG_DDRC_ADDRMAP_ROW_B1                   ,Row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
bitfld.long 0x24 4.--7. "     REG_DDRC_ADDRMAP_ROW_b2_B11  ,Row address bits form 2 to 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
textline "                                          "
bitfld.long 0x24 0.--3. " REG_DDRC_ADDRMAP_ROW_B12                  ,Row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
line.long 0x28 "DDRC_ADDR_MAP_ROW_2_CR,DDRC Row Address Map"
bitfld.long 0x28 8.--11. " REG_DDRC_ADDRMAP_ROW_B13                  ,Row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,Reserved,Reserved,Reserved,15"
bitfld.long 0x28 4.--7. "                  REG_DDRC_ADDRMAP_ROW_b2_B14               ,Row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,Reserved,Reserved,Reserved,15"
bitfld.long 0x28 0.--3. "     REG_DDRC_ADDRMAP_ROW_B15     ,Row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,Reserved,Reserved,Reserved,15"
line.long 0x2c "DDRC_INIT_1_CR,DDRC Initialization Control"
bitfld.long 0x2c 8.--11. " REG_DDRC_PRE_OCD_X32                      ,Wait period before driving the OCD Complete command to DRAM" "Disabled,Enabled,?..."
hexmask.long.byte 0x2c 1.--7. 1. "                  REG_DDRC_FINAL_WAIT_X32                   ,Cycles to wait after completing the DRAM initialization sequence"
bitfld.long 0x2c 0. "           REG_DDRC_SKIP_OCD            ,Skip the OCD adjustment step during DDR2 initialization" "Not supported,Supported"
line.long 0x30 "DDRC_CKE_RSTN_CYCLES_1_CR,DDRC Initialization Control"
hexmask.long.byte 0x30 8.--15. 1. " REG_DDRC_PRE_CKE_X1024                    ,Cycles to wait after reset before driving CKE High to start the DRAM"
hexmask.long.byte 0x30 0.--7. 1. "                        REG_DDRC_DRAM_RSTN_X1024                  ,Number of cycles to assert DRAM reset signal during initialization sequence"
line.long 0x34 "DDRC_ CKE_RSTN_CYCLES_2_CR,DDRC Initialization Control"
hexmask.long.word 0x34 3.--11. 1. " REG_DDRC_POST_CKE_X1024                   ,Cycles to wait after driving CKE High to start the DRAM initialization sequence"
bitfld.long 0x34 0.--1. "                      REG_DDRC_PRE_CKE_X1024                    ,Cycles to wait after reset before driving CKE High to start the DRAM" "0,1,2,3"
line.long 0x38 "DDRC_INIT_MR_CR,DDRC MR Initialization"
hexmask.long.word 0x38 0.--15. 1. " REG_DDRC_MR                               ,Value to be loaded into the DRAM Mode register"
line.long 0x3c "DDRC_INIT_EMR_CR,DDRC EMR Initialization"
hexmask.long.word 0x3c 0.--15. 1. " REG_DDRC_EMR                              ,Value to be loaded into DRAM EMR registers"
line.long 0x40 "DDRC_INIT_EMR2_CR,DDRC EMR2 Initialization"
hexmask.long.word 0x40 0.--15. 1. " REG_DDRC_EMR2                             ,Value to be loaded into DRAM EMR2 registers"
line.long 0x44 "DDRC_INIT_EMR3_CR,DDRC EMR3 Initialization"
hexmask.long.word 0x44 0.--15. 1. " REG_DDRC_EMR3                             ,Value to be loaded into DRAM EMR3 registers"
line.long 0x48 "DDRC_DRAM_BANK_TIMING_PARAM_CR,DDRC DRAM Bank Timing Parametr"
bitfld.long 0x48 6.--11. " REG_DDRC_T_RC                             ,Minimum time between activates to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x48 0.--5. "                        REG_DDRC_T_FAW                            ,Valid only in burst-of-8 mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4c "DDRC_DRAM_RD_WR_LATENCY_CR,DDRC DRAM Write Latency"
bitfld.long 0x4c 5.--9. " REG_DDRC_WRITE_LATENCY                    ,Number of clocks between the write command to write data enable PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4c 0.--4. "                        RREG_DDRC_READ_LATENCY                    ,Time from read command to read data on DRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x50 "DDRC_DRAM_RD_WR_PRE_CR,DDRC DRAM Read-Write Precharge Timing"
bitfld.long 0x50 5.--9. " REG_DDRC_WR2PRE                           ,Minimum time between write and precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 0.--4. "                        REG_DDRC_RD2PRE                           ,Minimum time from read to precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5c++0x8b
line.long 0x00 "DDRC_DRAM_MR_TIMING_PARAM_CR,DDRC DRAM Mode Register Timing Parameter"
hexmask.long.word 0x00 3.--12. 1. " REG_DDRC_T_MOD                            ,Mode register"
bitfld.long 0x00 0.--2. "                      REG_DDRC_T_MRD                            ,Cycles between load mode commands" "0,1,2,3,4,5,6,7"
line.long 0x04 "DDRC_DRAM_RAS_TIMING_CR,DDRC DRAM RAS Timing Parameter"
bitfld.long 0x04 5.--10. " REG_DDRC_T_RAS_MAX                        ,Maximum time between activate and precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--4. "                        REG_DDRC_T_RAS_MIN                        ,Minimum time between activate and precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DDRC_DRAM_RD_WR_TRNARND_TIME_CR,DDRC DRAM Read Write Turn-around Timing"
bitfld.long 0x08 5.--9. " REG_DDRC_RD2WR                            ,Minimum time from READ command to WRITE command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "                        REG_DDRC_WR2RD                            ,Minimum time from WRITE command to READ command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0c "DDRC_DRAM_T_PD_CR,DDRC DRAM Power-Down Parameter"
bitfld.long 0x0c 4.--8. " REG_DDRC_T_XP                             ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0c 0.--3. "                        RREG_DDRC_T_CKE                           ,Minimum number of cycles of CKE High/Low during power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "DDRC_DRAM_BANK_ACT_TIMING_CR,DDRC DRAM Bank Activate Timing Parameter"
bitfld.long 0x10 10.--13. " REG_DDRC_T_RCD                            ,Minimum time from activate to READ or WRITE command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 7.--9. "                        REG_DDRC_T_CCD                            ,Minimum time between two reads or two writes" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "            REG_DDRC_T_RRD               ,Minimum time between activates from bank A to bank B" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x10 0.--3. " REG_DDRC_T_RP                             ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "DDRC_ODT_PARAM_1_CR,DDRC ODT Delay Control"
bitfld.long 0x14 8.--11. " REG_DDRC_RD_ODT_DELAY                     ,The delay from issuing a READ command to setting ODT values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 4.--7. "                        REG_DDRC_WR_ODT_DELAY                     ,The delay from issuing a WRITE command to setting ODT values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 2.--3. "           REG_DDRC_RANK0_WR_ODT        ,Remote ODTs selection during write to bank 0" "0,1,2,3"
textline "                                          "
bitfld.long 0x14 0.--1. " REG_DDRC_RANK0_RD_ODT                     ,Remote ODTs selection during write to bank 0" "0,1,2,3"
line.long 0x18 "DDRC_ODT_PARAM_2_CR,DDRC ODT Hold/Block cycles"
bitfld.long 0x18 6.--9. " REG_DDRC_RD_ODT_HOLD                      ,Cycles to hold ODT for a READ command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2.--5. "                        REG_DDRC_WR_ODT_HOLD                      ,Cycles to hold ODT for a WRITE command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--1. "           REG_DDRC_WR_ODT_BLOCK        ,Cycles block for write ODT settings changing" "1,2,3,?..."
line.long 0x1c "DDRC_ADDR_MAP_COL_3_CR,Upper byte is DDRC Column Address Map register and lower byte controls debug features"
bitfld.long 0x1c 12.--15. " REG_DDRC_ADDRMAP_COL_B5                   ,Adrress map for column bit 5" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x1c 8.--11. "                  REG_DDRC_ADDRMAP_COL_B6                   ,Adrress map for column bit 6" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x1c 5. "     REG_DDRC_DIS_WC              ,Write combine disabled" "No,Yes"
textline "                                          "
bitfld.long 0x1c 4. " REG_DDRC_DIS_ACT_BYPASS                   ,Bypass path for high priority read activates disabled" "No,Yes"
bitfld.long 0x1c 3. "                       REG_DDRC_DIS_RD_BYPASS                    ,Bypass path for high priority read page hits disabled" "No,Yes"
bitfld.long 0x1c 2. "          REG_DDRC_DIS_PRE_BYPASS      ,Bypass path for high priority precharges disabled" "No,Yes"
textline "                                          "
bitfld.long 0x1c 1. " REG_DDRC_DIS_COLLISION_PAGE_OPT           ,Auto-precharge disabled" "No,Yes"
bitfld.long 0x1c 0. "                       REG_DDRC_DIS_SCRUB                        ,SECDED scrubs disabled" "No,Yes"
line.long 0x20 "DDRC_MODE_REG_RD_WR_CR,DDRC Mode Register Read/Write Command"
bitfld.long 0x20 3. " REG_DDRC_MR_WR                            ,Mode register started" "Not started,Started"
bitfld.long 0x20 1.--2. "               REG_DDRC_MR_ADDR                          ,Address of the Mode register that is to be written to" "MR0,MR1,MR2,MR3"
bitfld.long 0x20 0. "          REG_DDRC_MR_TYPE             ,Indicates whether the Mode register operation is read or write" "Write,Read"
line.long 0x24 "DDRC_MODE_REG_DATA_CR,DDRC Mode Register Write Data"
hexmask.long.word 0x24 0.--15. 1. " REG_DDRC_MR_DATA                          ,Mode register write data"
line.long 0x28 "DDRC_PWR_SAVE_1_CR,DDRC Power Save register"
hexmask.long.byte 0x28 6.--12. 1. " REG_DDRC_POST_SELFREF_GAP_X32             ,Minimum time to wait after coming out of self refresh"
bitfld.long 0x28 1.--5. "                        REG_DDRC_POWERDOWN_TO_X32                 ,Power down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0. "           REG_DDRC_CLOCK_STOP_EN       ,Stops the clock" "Not stopped,Stopped"
line.long 0x2c "DDRC_PWR_SAVE_2_CR,DDRC Power Save register"
bitfld.long 0x2c 11. " REG_DDRC_DIS_PAD_PD                       ,Disable the pad power-down feature" "No,Yes"
hexmask.long.byte 0x2c 3.--10. 1. "                       REG_DDRC_DEEPPOWERDOWN_TO_X1024           ,Minimum deep power-down time applicable only for LPDDR2"
bitfld.long 0x2c 0.--2. "           REG_DDRC_PAD_PD              ,The time to enter or exit power-down" "0,1,2,3,4,5,6,7"
line.long 0x30 "DDRC_ZQ_LONG _TIME_CR,DDRC ZQ Long Time Calibration"
hexmask.long.word 0x30 0.--9. 1. " REG_DDRC_T_ZQ_LONG_NOP                    ,Number of cycles of NOP required after a ZQCL"
line.long 0x34 "DDRC_ZQ_SHORT_TIME_CR,DDRC ZQ Short Time Calibration"
hexmask.long.word 0x34 0.--9. 1. " REG_DDRC_T_ZQ_SHORT_NOP                   ,Number of cycles of NOP required after a ZQCS"
line.long 0x38 "DDRC_ZQ_SHORT_INT_REFR_M_1_CR,DDRC ZQ Short Time Calibration"
hexmask.long.word 0x38 4.--15. 1. " REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024        ,Average interval to wait between automatically issuing ZQCS"
bitfld.long 0x38 0.--3. "                      REG_DDRC_REFRESH_MARGIN                   ,Value of refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3c "DDRC_ZQ_SHORT_INT_REFR_M_2_CR,DDRC ZQ Short Time Calibration"
hexmask.long.byte 0x3c 0.--7. 1. " REG_DDRC_T_ZQ_SHORT_INTERVAL_X1024        ,Average interval to wait between automatically issuing ZQCS"
line.long 0x40 "DDRC_PERF_PARAM_1_CR,DDRC Performance Parameter"
bitfld.long 0x40 13.--15. " REG_DDRC_BURST_RDWR                       ,The burst size used to access the DRAM" "Reserved,4,8,Reserved,16,?..."
hexmask.long.byte 0x40 5.--11. 1. "                  REG_DDRC_RDWR_IDLE_GAP                    ,The alternate transaction store"
bitfld.long 0x40 4. "           REG_DDRC_PAGECLOSE           ,Bank is closed and kept closed if no transactions are available for it" "Open,Closed"
textline "                                          "
bitfld.long 0x40 0.--2. " REG_DDRC_LPR_NUM_ENTRIES                  ,Number of entries in the low priority transaction store" "1,2,3,4,5,6,7,8"
line.long 0x44 "DDRC_HPR_QUEUE_PARAM_1_CR,DDRC Performance Parameter"
bitfld.long 0x44 15. " REG_DDRC_HPR_MAX_STARVE_X32               ,Lower 1 bit of REG_DDRC_HPR_MAX_STARVE_X32" "0,1"
hexmask.long.word 0x44 4.--14. 1. "                         REG_DDRC_HPR_MIN_NON_CRITICAL             ,Number of clocks that the HPR queue is guaranteed to be non-critical"
bitfld.long 0x44 0.--3. "         REG_DDRC_HPR_XACT_RUN_LENGTH ,Number of transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "DDRC_HPR_QUEUE_PARAM_2_CR,DDRC Performance Parameter"
hexmask.long.word 0x48 0.--10. 1. " REG_DDRC_HPR_MAX_STARVE_X32               ,Number of clocks that the HPR queue can be starved before it goes critical"
line.long 0x4c "DDRC_LPR_QUEUE_PARAM_1_CR,DDRC Performance Parameter"
bitfld.long 0x4c 15. " REG_DDRC_LPR_MAX_STARVE_X32               ,Lower 1 bit of REG_DDRC_LPR_MAX_STARVE_X32" "0,1"
hexmask.long.word 0x4c 4.--14. 1. "                         REG_DDRC_LPR_MIN_NON_CRITICAL             ,Number of clocks that the LPR queue is guaranteed to be non-critical"
bitfld.long 0x4c 0.--3. "         REG_DDRC_LPR_XACT_RUN_LENGTH ,Number of transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "DDRC_LPR_QUEUE_PARAM_2_CR,DDRC Performance Parameter"
hexmask.long.word 0x50 0.--10. 1. " REG_DDRC_LPR_MAX_STARVE_X32               ,Number of clocks that the LPR queue can be starved before it goes critical"
line.long 0x54 "DDRC_WR_QUEUE_PARAM_CR,DDRC Performance Parameter"
hexmask.long.word 0x54 4.--14. 1. " REG_DDRC_W_MIN_NON_CRITICAL               ,Number of clocks that the write queue is guaranteed to be non-critical"
bitfld.long 0x54 0.--3. "                      REG_DDRC_W_XACT_RUN_LENGTH                ,WR queue run length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "DDRC_PERF_PARAM_2_CR,DDRC Performance Parameter"
bitfld.long 0x58 10. " REG_DDRC_BURST_MODE                       ,Burst mode" "Sequential,Interleaved"
hexmask.long.byte 0x58 2.--9. 1. "               REG_DDRC_GO2CRITICAL_HYSTERESIS           ,The number of cycles before the critical state"
bitfld.long 0x58 1. "           REG_DDRC_PREFER_WRITE        ,The bank selector preferences" "Read,Write"
textline "                                          "
bitfld.long 0x58 0. " REG_DDRC_FORCE_LOW_PRI_N                  ,Active Low signal" "Disabled,Enabled"
line.long 0x5c "DDRC_PERF_PARAM_3_CR,DDRC Performance Parameter"
bitfld.long 0x5c 0. " REG_DDRC_EN_2T_TIMING_MODE                ,Timing mode" "1T,2T"
line.long 0x60 "DDRC_DFI_RDDATA_EN_CR,DDRC DFI Read Command Timing"
bitfld.long 0x60 0.--4. " REG_DDRC_DFI_T_RDDATA_EN                  ,Time from the assertion of a READ command to the DDRC_DFI_RDDATA_EN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "DDRC_DFI_MIN_CTRLUPD_TIMING_CR,DDRC DFI Controller Update Min Time"
hexmask.long.word 0x64 0.--9. 1. " REG_DDRC_DFI_T_CTRLUP_MIN                 ,The minimum number of clock cycles for the DDRC_DFI_CTRLUPD_REQ signal"
LINE.LONG 0X68 "DDRC_DFI_MAX_CTRLUPD_TIMING_CR,DDRC DFI Controller Update Max Time register"
hexmask.long.word 0x68 0.--9. 1. " REG_DDRC_DFI_T_CTRLUP_MAX                 ,The maximum number of clock cycles for the DDRC_DFI_CTRLUPD_REQ signal"
line.long 0x6c "DDRC_DFI_WR_LVL_CONTROL_1_CR,DDRC DFI Write Levelling Control register"
hexmask.long.byte 0x6c 8.--15. 1. " REG_DDRC_DFI_WRLVL_MAX_X1024              ,Write leveling maximum time[0:7]"
hexmask.long.byte 0x6c 0.--7. 1. "                        REG_DDRC_WRLVL_WW                         ,Write leveling write-to-write delay"
line.long 0x70 "DDRC_DFI_WR_LVL_CONTROL_2_CR,DDRC DFI Write Levelling Control register"
hexmask.long.word 0x70 5.--14. 1. " REG_DDRC_DFI_T_WLMRD                      ,First DQS/DQS# rising edge after write leveling mode is programmed"
bitfld.long 0x70 4. "                      REG_DDRC_DFI_WR_LEVEL_EN                  ,Write leveling mode has been enabled as part of the initialization sequence" "Disabled,Enabled"
bitfld.long 0x70 0.--3. "     REG_DDRC_DFI_WRLVL_MAX_X1024 ,Write leveling maximum time[8:11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "DDRC_DFI_RD_LVL_CONTROL_1_CR,DDRC DFI Read Levelling Control register"
hexmask.long.byte 0x74 8.--15. 1. " REG_DDRC_DFI_RDLVL_MAX_X1024              ,Read leveling maximum time[0:7]"
hexmask.long.byte 0x74 0.--7. 1. "                        REG_DDRC_RDLVL_RR                         ,Read leveling read-to-read delay"
line.long 0x78 "DDRC_DFI_RD_LVL_CONTROL_2_CR,DDRC DFI Read Levelling Control register"
bitfld.long 0x78 5. " REG_DDRC_DFI_RD_DATA_EYE_TRAIN            ,RD Eye training mode has been enabled as part of the initialization sequence" "Disabled,Enabled"
bitfld.long 0x78 4. "                  REG_DDRC_DFI_RD_DQS_GATE_LEVEL            ,Read DQS Gate Leveling mode has been enabled as part of the initialization sequence" "Disabled,Enabled"
bitfld.long 0x78 0.--3. "     REG_DDRC_DFI_RDLVL_MAX_X1024 ,Read leveling maximum time[8:12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7c "DDRC_DFI_CTRLUPD_TIME_INTER_CR,DDRC DFI Controller Update Time Interval register"
hexmask.long.byte 0x7c 8.--15. 1. " REG_DDRC_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between controller initiated DFI update requests"
hexmask.long.byte 0x7c 0.--7. 1. "                        REG_DDRC_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between controller initiated DFI update requests"
line.long 0x80 "DDRC_DYN_SOFT_RESET_2_CR,DDRC reset register"
bitfld.long 0x80 2. " AXIRESET                                  ,Main AXI reset signal is asserted" "Not asserted,Asserted"
bitfld.long 0x80 1. "              RESET_APB_REG                             ,Full soft reset" "Not reset,Reset"
bitfld.long 0x80 0. "    REG_DDRC_SOFT_RSTB           ,This is a soft reset" "Not reset,Reset"
line.long 0x84 "DDRC_AXI_FABRIC_PRI_ID_CR,DDRC AXI Interface Fabric Priority ID Register"
bitfld.long 0x84 4.--5. " PRIORITY_ENABLE_BIT                       ,The priority of the fabric master ID" "0,1,2,3"
bitfld.long 0x84 0.--3. "                         PRIORITY_ID                               ,Priority ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "DDRC _SR,DDRC Status register"
bitfld.long 0x88 3.--5. " DDRC_CORE_REG_OPERATING_MODE              ,Operating mode(Non-mobile/Mobile)" "Init,Normal,Power-down,Self-refresh,Reserved/Deep power-down,Reserved/Deep power-down,Reserved/Deep power-down,Reserved/Deep power-down"
bitfld.long 0x88 2. "  DDRC_REG_TRDLVL_MAX_ERROR                 ,RDRLVL_MAX timer has timed out" "No error,Error"
bitfld.long 0x88 1. "     DDRC_REG_TWRLVL_MAX_ERROR    ,WRLVL_MAX timer has timed out" "No error,Error"
textline "                                          "
bitfld.long 0x88 0. " DDRC_REG_MR_WR_BUSY                       ,A mode register write operation is in progress" "Not busy,Busy"
rgroup.long 0xe8++0x57
line.long 0x00 "DDRC_SINGLE_ERR_CNT_STATUS_SR,DDRC single error count Status register"
line.long 0x04 "DDRC_DOUBLE_ERR_CNT_STATUS_SR,DDRC double error count status register"
line.long 0x08 "DDRC_LUE_SYNDROME_1_SR,DDRC last uncorrected error syndrome register"
hexmask.long.word 0x08 0.--15. 1. " DDRC_REG_ECC_SYNDROMES0                   ,Data 0"
line.long 0x0c "DDRC_LUE_SYNDROME_2_SR,DDRC last uncorrected error syndrome register"
hexmask.long.word 0x0c 0.--15. 1. " DDRC_REG_ECC_SYNDROMES1                   ,Data 1"
line.long 0x10 "DDRC_LUE_SYNDROME_3_SR,DDRC last uncorrected error syndrome register"
hexmask.long.word 0x10 0.--15. 1. " DDRC_REG_ECC_SYNDROMES2                   ,Data 2"
line.long 0x14 "DDRC_LUE_SYNDROME_4_SR,DDRC last uncorrected error syndrome register"
hexmask.long.word 0x14 0.--15. 1. " DDRC_REG_ECC_SYNDROMES3                   ,Data 3"
line.long 0x18 "DDRC_LUE_SYNDROME_5_SR,DDRC last uncorrectederror syndrome register"
hexmask.long.byte 0x18 0.--7. 1. " DDRC_REG_ECC_SYNDROMES4                   ,SECDED error"
line.long 0x1c "DDRC_LUE_ADDRESS_1_SR,DDRC last uncorrected error address register"
hexmask.long.word 0x1c 0.--15. 1. " DDRC_REG_ECC_ROW                          ,Row where the SECDED error occurred"
line.long 0x20 "DDRC_LUE_ADDRESS_2_SR,DDRC last uncorrected error address register"
bitfld.long 0x20 12.--14. " DDRC_REG_ECC_BANK                         ,Bank where the SECDED error occurred" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x20 0.--11. 1. "                         DDRC_REG_ECC_COL                          ,Column where the SECDED error occurred"
line.long 0x24 "DDRC_LCE_SYNDROME_1_SR,DDRC last corrected error syndrome register"
hexmask.long.word 0x24 0.--15. 1. " DDRC_REG_ECC_SYNDROMES0                   ,Data 0"
line.long 0x28 "DDRC_LCE_SYNDROME_2_SR,DDRC last corrected error syndrome register"
hexmask.long.word 0x28 0.--15. 1. " DDRC_REG_ECC_SYNDROMES1                   ,Data 1"
line.long 0x2c "DDRC_LCE_SYNDROME_3_SR,DDRC last corrected error syndrome register"
hexmask.long.word 0x2c 0.--15. 1. " DDRC_REG_ECC_SYNDROMES2                   ,Data 2"
line.long 0x30 "DDRC_LCE_SYNDROME_4_SR,DDRC last corrected error syndrome register"
hexmask.long.byte 0x30 0.--7. 1. " DDRC_REG_ECC_SYNDROMES3                   ,SECDED error"
line.long 0x34 "DDRC_LCE_SYNDROME_5_SR,DDRC last corrected error syndrome register"
hexmask.long.word 0x34 0.--15. 1. " DDRC_REG_ECC_ROW                          ,Row where the SECDED error occurred"
line.long 0x38 "DDRC_LCE_ADDRESS_1_SR,DDRC last corrected error address register"
bitfld.long 0x38 12.--14. " DDRC_REG_ECC_BANK                         ,Bank where the SECDED error occurred" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x38 0.--11. 1. "                         DDRC_REG_ECC_COL                          ,Column where the SECDED error occurred"
line.long 0x3c "DDRC_LCE_ADDRESS_2_SR,DDRC last corrected error address register"
hexmask.long.byte 0x3c 0.--6. 1. " DDRC_LCB_BIT_NUM                          ,The location of the bit that caused a single-bit error in SECDED case"
line.long 0x40 "DDRC_LCB_NUMBER_SR,DDRC last corrected bit number register"
hexmask.long.word 0x40 0.--15. 1. " DDRC_LCB_MASK0                            ,Indicates the mask of the corrected data"
line.long 0x44 "DDRC_LCB_MASK_1_SR,DDRC last corrected bit mask status register"
hexmask.long.word 0x44 0.--15. 1. " DDRC_LCB_MASK1                            ,Indicates the mask of the corrected data"
line.long 0x48 "DDRC_LCB_MASK_2_SR,DDRC last corrected bit mask status register"
hexmask.long.word 0x48 0.--15. 1. " DDRC_LCB_MASK2                            ,Indicates the mask of the corrected data"
line.long 0x4c "DDRC_LCB_MASK_3_SR,DDRC last corrected bit mask status register"
hexmask.long.word 0x4c 0.--15. 1. " DDRC_LCB_MASK3                            ,Indicates the mask of the corrected data"
line.long 0x50 "DDRC_LCB_MASK_4_SR,DDRC last corrected bit mask status register"
hexmask.long.word 0x50 0.--15. 1. " DDRC_LCB_MASK4                            ,Indicates the mask of the corrected data"
line.long 0x54 "DDRC_ECC_INT_SR,DDRC SECDED interrupt status register"
bitfld.long 0x54 0.--2. " DDRC_ECC_STATUS_SR                        ,The SECDED interrupt status" "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "DDRC_ECC_INT_CLR_REG,DDRC SECDED interrupt clear register"
bitfld.long 0x00 0. " DDRC_ECC_INT_CLR_REG                      ,Clears all the SECDED status information" "No action,Cleared"
tree.end
width 37.
tree "PHY Configuration Register Summary"
group.long 0x200++0x6f
line.long 0x00 "PHY_DYN_BIST_TEST_CR,PHY BIST test configuration register"
bitfld.long 0x00 4. " REG_PHY_AT_SPD_ATPG                        ,Test with full clock speed but lower coverage" "Disabled,Enabled"
textline "                                              "
bitfld.long 0x00 3. " REG_PHY_BIST_ENABLE                        ,Enable the internal BIST generation and checker logic when this port is set High" "Disabled,Enabled"
textline "                                              "
bitfld.long 0x00 1.--2. " REG_PHY_BIST_MODE                          ,The mode bits select the pattern type generated by the BIST generator" "Constant pattern,Low frequency,PRBS pattern,?..."
textline "                                              "
bitfld.long 0x00 0. " REG_PHY_BIST_FORCE_ERR                     ,The false pass checker" "No error,Error"
line.long 0x04 "PHY_DYN_BIST_TEST_ERRCLR_1_CR,PHY BIST test error clear register"
hexmask.long.word 0x04 0.--15. 1. " REG_PHY_BIST_ERR_CLR1                      ,Clear the mismatch error flag from the BIST checker[0:15]"
line.long 0x08 "PHY_DYN_BIST_TEST_ERRCLR_2_CR,PHY BIST test error clear register"
hexmask.long.word 0x08 0.--15. 1. " REG_PHY_BIST_ERR_CLR2                      ,Clear the mismatch error flag from the BIST checker[16:31]"
line.long 0x0c "PHY_DYN_BIST_TEST_ERRCLR_3_CR,PHY BIST test error clear register"
hexmask.long.word 0x0c 0.--11. 1. " REG_PHY_BIST_ERR_CLR3                      ,Clear the mismatch error flag from the BIST checker[32:43]"
line.long 0x10 "PHY_BIST_TEST_SHIFT_PATTERN_1_CR,PHY BIST test shift pattern register"
hexmask.long.word 0x10 0.--15. 1. " REG_PHY_BIST_SHIFT_DQ1                     ,Determines whether early shifting is required for a particular DQ[0:15]"
line.long 0x14 "PHY_BIST_TEST_SHIFT_PATTERN_2_CR,PHY BIST test shift pattern register"
hexmask.long.word 0x14 0.--15. 1. " REG_PHY_BIST_SHIFT_DQ2                     ,Determines whether early shifting is required for a particular DQ[16:31]"
line.long 0x18 "PHY_BIST_TEST_SHIFT_PATTERN_3_CR,PHY BIST test shift pattern register"
hexmask.long.word 0x18 0.--11. 1. " REG_PHY_BIST_SHIFT_DQ3                     ,Determines whether early shifting is required for a particular DQ[32:43]"
line.long 0x1c "PHY_DYN_LOOPBACK_CR,PHY loopback test configuration register"
bitfld.long 0x1c 0. " REG_PHY_LOOPBACK                           ,Loopback testing" "Disabled,Enabled"
line.long 0x20 "PHY_BOARD_LOOPBACK_CR,PHY Board loopback test configuration register"
bitfld.long 0x20 5.--9. " REG_PHY_BOARD_LPBK_TX                      ,External board loopback testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                              "
bitfld.long 0x20 0.--4. " REG_PHY_BOARD_LPBK_RX                      ,External board loopback testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "PHY_CTRL_SLAVE_RATIO_CR,PHY control slice DLL slave ratio register"
hexmask.long.word 0x24 0.--9. 1. " REG_PHY_CTRL_SLAVE_RATIO                   ,Ratio value for address/command launches timing in PHY_CTRL macro"
line.long 0x28 "PHY_CTRL_SLAVE_FORCE_CR,PHY control slice DLL slave force register"
bitfld.long 0x28 0. " REG_PHY_CTRL_SLAVE_FORCE                   ,Overwrite the delay/tap value for address/command timing slave DLL" "Disabled,Enabled"
line.long 0x2c "PHY_CTRL_SLAVE_DELAY_CR,PHY control slice DLL slave delay register"
hexmask.long.word 0x2c 0.--8. 1. " REG_PHY_CTRL_SLAVE_DELAY                   ,Slave delay"
line.long 0x30 "PHY_DATA_SLICE_IN_USE_CR,PHY control slice in use register"
bitfld.long 0x30 0.--4. " REG_PHY_DATA_SLICE_IN_USE                  ,Data bus width selection for read FIFO RE generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PHY_LVL_NUM_OF_DQ0_CR,PHY receiver on off control register"
bitfld.long 0x34 4.--7. " REG_PHY_GATELVL_NUM_OF_DQ0                 ,The number of samples for dq0_in for each ratio increment by the gate training FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                              "
bitfld.long 0x34 0.--3. " REG_PHY_WRLVL_NUM_OF_DQ0                   ,The number of samples for dq0_in for each ratio increment by the write leveling FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "PHY_DQ_OFFSET_1_CR,Selection register of offset value from DQS to DQ"
hexmask.long.word 0x38 0.--15. 1. " REG_PHY_DQ_OFFSET1                         ,Offset value from DQS to DQ[0:15]"
line.long 0x3c "PHY_DQ_OFFSET_2_CR,Selection register of offset value from DQS to DQ"
hexmask.long.word 0x3c 0.--15. 1. " REG_PHY_DQ_OFFSET2                         ,Offset value from DQS to DQ[16:31]"
line.long 0x40 "PHY_DQ_OFFSET_3_CR,Selection register of offset value from DQS to DQ"
bitfld.long 0x40 0.--2. " REG_PHY_DQ_OFFSET3                         ,Offset value from DQS to DQ]32:34]" "0,1,2,3,4,5,6,7"
line.long 0x44 "PHY_DIS_CALIB_RST_CR,Calibration reset disabling register"
bitfld.long 0x44 0. " REG_PHY_DIS_CALIB_RST                      ,Disables the resetting of the read capture FIFO pointers with DLL_CALIB" "No,Yes"
line.long 0x48 "PHY_DLL_LOCK_DIFF_CR,Selects the maximum number of delay line taps"
bitfld.long 0x48 0. " REG_PHY_DLL_LOCK_DIFF                      ,The maximum number of delay line taps variations" "0,1"
line.long 0x4c "PHY_FIFO_WE_IN_DELAY_1_CR,Delay value for FIFO WE"
hexmask.long.word 0x4c 0.--15. 1. " REG_PHY_FIFO_WE_IN_DELAY1                  ,Delay value to be used when REG_PHY_FIFO_WE_IN_FORCEX is set to 1"
line.long 0x50 "PHY_FIFO_WE_IN_DELAY_2_CR,Delay value for FIFO WE"
hexmask.long.word 0x50 0.--15. 1. " REG_PHY_FIFO_WE_IN_DELAY2                  ,Delay value to be used when REG_PHY_FIFO_WE_IN_FORCEX is set to 1"
line.long 0x54 "PHY_FIFO_WE_IN_DELAY_3_CR,Delay value for FIFO WE"
hexmask.long.word 0x54 0.--12. 1. " REG_PHY_FIFO_WE_IN_DELAY3                  ,Delay value to be used when REG_PHY_FIFO_WE_IN_FORCEX is set to 1"
line.long 0x58 "PHY_FIFO_WE_IN_FORCE_CR,Overwriting delay value selection reg for FIFO WE"
bitfld.long 0x58 0.--4. " REG_PHY_FIFO_WE_IN_FORCE                   ,Overwrite the delay/tap value for the FIFO_WE slave DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x5c "PHY_FIFO_WE_SLAVE_RATIO_1_CR,Ratio value for FIFO WE slave DLL"
hexmask.long.word 0x5c 0.--15. 1. " REG_PHY_FIFO_WE_SLAVE_RATIO1               ,[15:0] bits of REG_PHY_FIFO_WE_SLAVE_RATIO"
line.long 0x60 "PHY_FIFO_WE_SLAVE_RATIO_1_CR,Ratio value for FIFO WE slave DLL"
hexmask.long.word 0x60 0.--15. 1. " REG_PHY_FIFO_WE_SLAVE_RATIO2               ,[31:16] bits of REG_PHY_FIFO_WE_SLAVE_RATIO"
line.long 0x64 "PHY_FIFO_WE_SLAVE_RATIO_1_CR,Ratio value for FIFO WE slave DLL"
hexmask.long.word 0x64 0.--15. 1. " REG_PHY_FIFO_WE_SLAVE_RATIO3               ,[47:32] bits of REG_PHY_FIFO_WE_SLAVE_RATIO"
line.long 0x68 "PHY_FIFO_WE_SLAVE_RATIO_1_CR,Ratio value for FIFO WE slave DLL"
hexmask.long.byte 0x68 0.--6. 1. " REG_PHY_FIFO_WE_SLAVE_RATIO4               ,[54:48] bits of REG_PHY_FIFO_WE_SLAVE_RATIO"
line.long 0x6c "PHY_GATELVL_INIT_MODE_CR,Init ratio selection register"
bitfld.long 0x6c 0. " REG_PHY_GATELVL_INIT_MODE                  ,The user programmable init ratio selection mode" "Write leveling,REG_PHY_GATELVL_INIT_RATIO"
group.long 0x270++0xaf
line.long 0x00 "PHY_GATELVL_INIT_RATIO_1_CR,Init ratio value configuration register"
hexmask.long.word 0x00 0.--15. 1. " REG_PHY_GATELVL_INIT_RATIO1                ,[15:0] of REG_PHY_GATELVL_INIT_RATIO"
line.long 0x04 "PHY_GATELVL_INIT_RATIO_2_CR,Init ratio value configuration register"
hexmask.long.word 0x04 0.--15. 1. " REG_PHY_GATELVL_INIT_RATIO2                ,[31:16] of REG_PHY_GATELVL_INIT_RATIO"
line.long 0x08 "PHY_GATELVL_INIT_RATIO_3_CR,Init ratio value configuration register"
hexmask.long.word 0x08 0.--15. 1. " REG_PHY_GATELVL_INIT_RATIO3                ,[47:32] of REG_PHY_GATELVL_INIT_RATIO"
line.long 0x0c "PHY_GATELVL_INIT_RATIO_4_CR,Init ratio value configuration register"
hexmask.long.byte 0x0c 0.--6. 1. " REG_PHY_GATELVL_INIT_RATIO4                ,[54:48] of REG_PHY_GATELVL_INIT_RATIO"
line.long 0x10 "PHY_LOCAL_ODT_CR,PHY ODT control register"
bitfld.long 0x10 2.--3. " REG_PHY_IDLE_LOCAL_ODT                     ,The user programmable initialization ratio selection mode" "Write leveling,REG_PHY_GATELVL_INIT_RATIO,?..."
textline "                                              "
bitfld.long 0x10 1. " REG_PHY_WR_LOCAL_ODT                       ,Tied to 0" "0,1"
textline "                                              "
bitfld.long 0x10 0. " REG_PHY_RD_LOCAL_ODT                       ,Tied to 0" "0,1"
line.long 0x14 "PHY_INVERT_CLKOUT_CR,NPHY DRAM clock polarity change register"
bitfld.long 0x14 0. " REG_PHY_INVERT_CLKOUT                      ,Inverts the polarity of the DRAM clock" "Disabled,Enabled"
line.long 0x18 "PHY_RD_DQS_SLAVE_DELAY_1_CR,Delay value for read DQS"
hexmask.long.word 0x18 0.--15. 1. " REG_PHY_RD_DQS_SLAVE_DELAY1                ,[15:0] bits of REG_PHY_RD_DQS_SLAVE_DELAY"
line.long 0x1c "PHY_RD_DQS_SLAVE_DELAY_2_CR,Delay value for read DQS"
hexmask.long.word 0x1c 0.--15. 1. " REG_PHY_RD_DQS_SLAVE_DELAY2                ,[31:16] bits of REG_PHY_RD_DQS_SLAVE_DELAY"
line.long 0x20 "PHY_RD_DQS_SLAVE_DELAY_3_CR,Delay value for read DQS"
hexmask.long.word 0x20 0.--12. 1. " REG_PHY_RD_DQS_SLAVE_DELAY3                ,[44:32] bits of REG_PHY_RD_DQS_SLAVE_DELAY"
line.long 0x24 "PHY_RD_DQS_SLAVE_FORCE_CR,Overwriting delay value selection reg for read DQS"
bitfld.long 0x24 0. " REG_PHY_RD_DQS_SLAVE_FORCE                 ,Overwrite the delay/tap value for read DQS slave DLL" "Disabled,Enabled"
line.long 0x28 "PHY_RD_DQS_SLAVE_RATIO_1_CR,Ratio value for read DQS slave DLL"
hexmask.long.word 0x28 0.--15. 1. " REG_PHY_RD_DQS_SLAVE_RATIO1                ,[15:0] bits of REG_PHY_RD_DQS_SLAVE_RATIO"
line.long 0x2c "PHY_RD_DQS_SLAVE_RATIO_2_CR,Ratio value for read DQS slave DLL"
hexmask.long.word 0x2c 0.--15. 1. " REG_PHY_RD_DQS_SLAVE_RATIO2                ,[31:16] bits of REG_PHY_RD_DQS_SLAVE_RATIO"
line.long 0x30 "PHY_RD_DQS_SLAVE_RATIO_3_CR,Ratio value for read DQS slave DLL"
hexmask.long.word 0x30 0.--15. 1. " REG_PHY_RD_DQS_SLAVE_RATIO3                ,[47:32] bits of REG_PHY_RD_DQS_SLAVE_RATIO"
line.long 0x34 "PHY_RD_DQS_SLAVE_RATIO_4_CR,Ratio value for read DQS slave DLL"
bitfld.long 0x34 0.--1. " REG_PHY_RD_DQS_SLAVE_RATIO                 ,[49:48] bits of REG_PHY_RD_DQS_SLAVE_RATIO" "0,1,2,3"
line.long 0x38 "PHY_WR_DQS_SLAVE_DELAY_1_CR,Delay value for write DQS"
hexmask.long.word 0x38 0.--15. 1. " REG_PHY_WR_DQS_SLAVE_DELAY1                ,[15:0] bits of REG_PHY_WR_DQS_SLAVE_DELAY"
line.long 0x3c "PHY_WR_DQS_SLAVE_DELAY_2_CR,Delay value for write DQS"
hexmask.long.word 0x3c 0.--15. 1. " REG_PHY_WR_DQS_SLAVE_DELAY2                ,[31:16] bits of REG_PHY_WR_DQS_SLAVE_DELAY"
line.long 0x40 "PHY_WR_DQS_SLAVE_DELAY_3_CR,Delay value for write DQS"
hexmask.long.word 0x40 0.--12. 1. " REG_PHY_WR_DQS_SLAVE_DELAY3                ,[44:32] bits of REG_PHY_WR_DQS_SLAVE_DELAY"
line.long 0x44 "PHY_WR_DATA_SLAVE_FORCE_CR,Overwriting delay value selection reg for write DATA"
bitfld.long 0x44 0.--4. " REG_PHY_WR_DQS_SLAVE_FORCE                 ,Overwrite the delay/tap value for read DQS slave DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x48 "PHY_WR_DATA_SLAVE_RATIO_1_CR,Ratio value for write DATA slave DLL"
hexmask.long.word 0x48 0.--15. 1. " REG_PHY_WR_DQS_SLAVE_RATIO1                ,Ratio value for read DQS slave DLL[15:0]"
line.long 0x4c "PHY_WR_DATA_SLAVE_RATIO_2_CR,Ratio value for write DATA slave DLL"
hexmask.long.word 0x4c 0.--15. 1. " REG_PHY_WR_DQS_SLAVE_RATIO2                ,Ratio value for read DQS slave DLL[31:16]"
line.long 0x50 "PHY_WR_DATA_SLAVE_RATIO_3_CR,Ratio value for write DATA slave DLL"
hexmask.long.word 0x50 0.--15. 1. " REG_PHY_WR_DQS_SLAVE_RATIO3                ,Ratio value for read DQS slave DLL[47:32]"
line.long 0x54 "PHY_WR_DATA_SLAVE_RATIO_4_CR,Ratio value for write DATA slave DLL"
bitfld.long 0x54 0.--1. " REG_PHY_WR_DQS_SLAVE_RATIO                 ,Ratio value for read DQS slave DLL[49:48]" "0,1,2,3"
line.long 0x58 "PHY_WR_DATA_SLAVE_DELAY_1_CR,Delay value for write DATA"
hexmask.long.word 0x58 0.--15. 1. " REG_PHY_WR_DATA_SLAVE_DELAY1               ,[15:0] bits of REG_PHY_WR_DATA_SLAVE_DELAY"
line.long 0x5c "PHY_WR_DATA_SLAVE_DELAY_2_CR,Delay value for write DATA"
hexmask.long.word 0x5c 0.--15. 1. " REG_PHY_WR_DATA_SLAVE_DELAY2               ,[31:16] bits of REG_PHY_WR_DATA_SLAVE_DELAY"
line.long 0x60 "PHY_WR_DATA_SLAVE_DELAY_3_CR,Delay value for write DATA"
hexmask.long.word 0x60 0.--12. 1. " REG_PHY_WR_DATA_SLAVE_DELAY3               ,[44:32] bits of REG_PHY_WR_DATA_SLAVE_DELAY"
line.long 0x64 "PHY_WR_DATA_SLAVE_FORCE_CR,Overwriting delay value selection reg for write DATA"
bitfld.long 0x64 0.--4. " REG_PHY_WR_DATA_SLAVE_FORCE                ,Overwrite the delay/tap value for write data slave DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "PHY_WR_DATA_SLAVE_RATIO_1_CR,Ratio value for write DATA slave DLL"
hexmask.long.word 0x68 0.--15. 1. " REG_PHY_WR_DATA_SLAVE_RATIO1               ,[15:0] bits of REG_PHY_WR_DATA_SLAVE_RATIO"
line.long 0x6c "PHY_WR_DATA_SLAVE_RATIO_2_CR,Ratio value for write DATA slave DLL"
hexmask.long.word 0x6c 0.--15. 1. " REG_PHY_WR_DATA_SLAVE_RATIO2               ,[31:16] bits of REG_PHY_WR_DATA_SLAVE_RATIO"
line.long 0x70 "PPHY_WR_DATA_SLAVE_RATIO_3_CR,Ratio value for write DATA slave DLL"
hexmask.long.word 0x70 0.--15. 1. " REG_PHY_WR_DATA_SLAVE_RATIO3               ,[47:32] bits of REG_PHY_WR_DATA_SLAVE_RATIO"
line.long 0x74 "PHY_WR_DATA_SLAVE_RATIO_4_CR,CRatio value for write DATA slave DLL"
bitfld.long 0x74 0.--1. " REG_PHY_WR_DATA_SLAVE_RATIO                ,[49:48] bits of REG_PHY_WR_DATA_SLAVE_RATIO" "0,1,2,3"
line.long 0x78 "PHY_WRLVL_INIT_MODE_CR,Initialization ratio selection register used by write leveling"
bitfld.long 0x78 0. " REG_PHY_WRLVL_INIT_MODE                    ,The user programmable init ratio selection mode" "REG_PHY_WRLVL_INIT_RATIO PORT,Write leveling of previous data slice"
line.long 0x7c "PHY_WRLVL_INIT_RATIO_1_CR,Configuring register for initialization ratio used by write leveling"
hexmask.long.word 0x7c 0.--15. 1. " REG_PHY_WRLVL_INIT_MODE1                   ,[15:0] bits of REG_PHY_WRLVL_INIT_MODE"
line.long 0x80 "PHY_WRLVL_INIT_RATIO_2_CR,Configuring register for initialization ratio used by write leveling"
hexmask.long.word 0x80 0.--15. 1. " REG_PHY_WRLVL_INIT_MODE2                   ,[31:16] bits of REG_PHY_WRLVL_INIT_MODE"
line.long 0x84 "PHY_WRLVL_INIT_RATIO_3_CR,Configuring register for initialization ratio used by write leveling"
hexmask.long.word 0x84 0.--15. 1. " REG_PHY_WRLVL_INIT_MODE3                   ,[47:32] bits of REG_PHY_WRLVL_INIT_MODE"
line.long 0x88 "PHY_WRLVL_INIT_RATIO_4_CR,Configuring register for initialization ratio used by write leveling"
bitfld.long 0x88 0.--1. " REG_PHY_WRLVL_INIT_MODE                    ,[49:48] bits of REG_PHY_WRLVL_INIT_MODE" "0,1,2,3"
line.long 0x8c "PHY_WR_RD_RL_CR,Configurable register for delays to read and write"
bitfld.long 0x8c 5.--9. " REG_PHY_WR_RL_DELAY                        ,The active ranks ratio logic delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8c 0.--4. "                                     REG_PHY_RD_RL_DELAY          ,The active ranks ratio logic delay for FIFO_WE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x90 "PHY_DYN_RDC_FIFO_RST_ERR_CNT_CLR_CR,Reset register for counter"
bitfld.long 0x90 0. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR           ,Clear/reset for counter RDC_FIFO_RST_ERR_CNT" "No effect,Clear"
line.long 0x94 "PHY_RDC_WE_TO_RE_DELAY_CR,Configurable register for delay between WE and RE"
bitfld.long 0x94 0.--3. " REG_PHY_RDC_WE_TO_RE_DELAY                 ,Register input - specified in number of clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "PHY_USE_FIXED_RE_CR,Selection register for generating read enable to FIFO"
bitfld.long 0x98 0. " REG_PHY_USE_FIXED_RE                       ,PHY generates FIFO read enable after fixed number of clock cycles" "Disabled,Enabled"
line.long 0x9c "PHY_USE_RANK0_DELAYS_CR,Delay selection"
bitfld.long 0x9c 0. " REG_PHY_USE_RANK0_DELAYS                   ,Delay selection" "Own delay,Rank 0"
line.long 0xa0 "PHY_USE_LVL_TRNG_LEVEL_CTRL_CR,Training control register"
bitfld.long 0xa0 2. " REG_PHY_USE_WR_LEVEL                       ,Write leveling training control" "Disabled,Enabled"
textline "                                              "
bitfld.long 0xa0 1. " REG_PHY_USE_RD_DQS_GATE_LEVEL              ,Read DQS gate training control" "Disabled,Enabled"
textline "                                              "
bitfld.long 0xa0 0. " REG_PHY_USE_RD_DATA_EYE_LEVEL              ,Read data eye training control"  "Disabled,Enabled"
line.long 0xa4 "PHY_DYN_CONFIG_CR,PHY dynamically controlled register"
bitfld.long 0xa4 4. " REG_PHY_DIS_PHY_CTRL_RSTN                  ,Disable the PHY control macro reset" "No,Yes"
textline "                                              "
bitfld.long 0xa4 3. " REG_PHY_LPDDR1                             ,The PHY is operating in LPDDR1 mode" "Disabled,Enabled"
textline "                                              "
bitfld.long 0xa4 2. " REG_PHY_BL2                                ,Burst length control" "Other,Burst length 2"
textline "                                              "
bitfld.long 0xa4 1. " REG_PHY_CLK_STALL_LEVEL                    ,The delay line clock stalls level" "Low,High"
textline "                                              "
bitfld.long 0xa4 0. " REG_PHY_CMD_LATENCY                        ,Extra command latency" "Default,1 extra cycle"
line.long 0xa8 "PHY_RD_WR_GATE_LVL_CR,Training mode selection register"
bitfld.long 0xa8 14. " REG_PHY_GATELVL_INC_MODE4                  ,Incremental read DQS gate training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 13. " REG_PHY_GATELVL_INC_MODE3                  ,Incremental read DQS gate training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 12. " REG_PHY_GATELVL_INC_MODE2                  ,Incremental read DQS gate training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 11. " REG_PHY_GATELVL_INC_MODE1                  ,Incremental read DQS gate training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 10. " REG_PHY_GATELVL_INC_MODE0                  ,Incremental read DQS gate training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 9. " REG_PHY_WRLVL_INC_MODE4                    ,Incremental write leveling mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 8. " REG_PHY_WRLVL_INC_MODE3                    ,Incremental write leveling mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 7. " REG_PHY_WRLVL_INC_MODE2                    ,Incremental write leveling mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 6. " REG_PHY_WRLVL_INC_MODE1                    ,Incremental write leveling mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 5. " REG_PHY_WRLVL_INC_MODE0                    ,Incremental write leveling mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 4. " REG_PHY_RDLVL_INC_MODE4                    ,Incremental read data eye training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 3. " REG_PHY_RDLVL_INC_MODE3                    ,Incremental read data eye training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 2. " REG_PHY_RDLVL_INC_MODE2                    ,Incremental read data eye training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 1. " REG_PHY_RDLVL_INC_MODE1                    ,Incremental read data eye training mode" "Normal,Incremental"
textline "                                              "
bitfld.long 0xa8 0. " REG_PHY_RDLVL_INC_MODE0                    ,Incremental read data eye training mode" "Normal,Incremental"
line.long 0xac "PHY_DYN_RESET_CR,This register will bring the PHY out of reset"
bitfld.long 0xac 0. " PHY_RESET                                  ,The PHY out of reset" "In reset,Out of reset"
rgroup.long 0x320++0x73
line.long 0x00 "PHY_LEVELLING_FAILURE_SR,Leveling failure status register"
bitfld.long 0x00 14. " REG_PHY_RDLVL_INC_FAIL4                    ,Incremental read leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 13. " REG_PHY_RDLVL_INC_FAIL3                    ,Incremental read leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 12. " REG_PHY_RDLVL_INC_FAIL2                    ,Incremental read leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 11. " REG_PHY_RDLVL_INC_FAIL1                    ,Incremental read leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 10. " REG_PHY_RDLVL_INC_FAIL0                    ,Incremental read leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 9. " REG_PHY_WRLVL_INC_FAIL4                    ,Incremental write leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 8. " REG_PHY_WRLVL_INC_FAIL3                    ,Incremental write leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 7. " REG_PHY_WRLVL_INC_FAIL2                    ,Incremental write leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 6. " REG_PHY_WRLVL_INC_FAIL1                    ,Incremental write leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 5. " REG_PHY_WRLVL_INC_FAIL0                    ,Incremental write leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 4. " REG_PHY_GATELVL_INC_FAIL4                  ,Incremental gate leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 3. " REG_PHY_GATELVL_INC_FAIL3                  ,Incremental gate leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 2. " REG_PHY_GATELVL_INC_FAIL2                  ,Incremental gate leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 1. " REG_PHY_GATELVL_INC_FAIL1                  ,Incremental gate leveling fail" "Passed,Failed"
textline "                                              "
bitfld.long 0x00 0. " REG_PHY_GATELVL_INC_FAIL0                  ,Incremental gate leveling fail" "Passed,Failed"
line.long 0x04 "PHY_BIST_ERROR_1_SR,BIST error status register"
bitfld.long 0x04 15. " PHY_REG_BIST_ERR15                         ,Mismatch error flag from the BIST checker 15" "No error,Error"
textline "                                              "
bitfld.long 0x04 14. " PHY_REG_BIST_ERR14                         ,Mismatch error flag from the BIST checker 14" "No error,Error"
textline "                                              "
bitfld.long 0x04 13. " PHY_REG_BIST_ERR13                         ,Mismatch error flag from the BIST checker 13" "No error,Error"
textline "                                              "
bitfld.long 0x04 12. " PHY_REG_BIST_ERR12                         ,Mismatch error flag from the BIST checker 12" "No error,Error"
textline "                                              "
bitfld.long 0x04 11. " PHY_REG_BIST_ERR11                         ,Mismatch error flag from the BIST checker 11" "No error,Error"
textline "                                              "
bitfld.long 0x04 10. " PHY_REG_BIST_ERR10                         ,Mismatch error flag from the BIST checker 10" "No error,Error"
textline "                                              "
bitfld.long 0x04 9. " PHY_REG_BIST_ERR9                          ,Mismatch error flag from the BIST checker 9" "No error,Error"
textline "                                              "
bitfld.long 0x04 8. " PHY_REG_BIST_ERR8                          ,Mismatch error flag from the BIST checker 8" "No error,Error"
textline "                                              "
bitfld.long 0x04 7. " PHY_REG_BIST_ERR7                          ,Mismatch error flag from the BIST checker 7" "No error,Error"
textline "                                              "
bitfld.long 0x04 6. " PHY_REG_BIST_ERR6                          ,Mismatch error flag from the BIST checker 6" "No error,Error"
textline "                                              "
bitfld.long 0x04 5. " PHY_REG_BIST_ERR5                          ,Mismatch error flag from the BIST checker 5" "No error,Error"
textline "                                              "
bitfld.long 0x04 4. " PHY_REG_BIST_ERR4                          ,Mismatch error flag from the BIST checker 4" "No error,Error"
textline "                                              "
bitfld.long 0x04 3. " PHY_REG_BIST_ERR3                          ,Mismatch error flag from the BIST checker 3" "No error,Error"
textline "                                              "
bitfld.long 0x04 2. " PHY_REG_BIST_ERR2                          ,Mismatch error flag from the BIST checker 2" "No error,Error"
textline "                                              "
bitfld.long 0x04 1. " PHY_REG_BIST_ERR1                          ,Mismatch error flag from the BIST checker 1" "No error,Error"
textline "                                              "
bitfld.long 0x04 0. " PHY_REG_BIST_ERR0                          ,Mismatch error flag from the BIST checker 0" "No error,Error"
line.long 0x08 "PHY_BIST_ERROR_2_SR,BIST error status register"
bitfld.long 0x08 15. " PHY_REG_BIST_ERR31                         ,Mismatch error flag from the BIST checker 31" "No error,Error"
textline "                                              "
bitfld.long 0x08 14. " PHY_REG_BIST_ERR30                         ,Mismatch error flag from the BIST checker 30" "No error,Error"
textline "                                              "
bitfld.long 0x08 13. " PHY_REG_BIST_ERR29                         ,Mismatch error flag from the BIST checker 29" "No error,Error"
textline "                                              "
bitfld.long 0x08 12. " PHY_REG_BIST_ERR28                         ,Mismatch error flag from the BIST checker 28" "No error,Error"
textline "                                              "
bitfld.long 0x08 11. " PHY_REG_BIST_ERR27                         ,Mismatch error flag from the BIST checker 27" "No error,Error"
textline "                                              "
bitfld.long 0x08 10. " PHY_REG_BIST_ERR26                         ,Mismatch error flag from the BIST checker 26" "No error,Error"
textline "                                              "
bitfld.long 0x08 9. " PHY_REG_BIST_ERR25                         ,Mismatch error flag from the BIST checker 25" "No error,Error"
textline "                                              "
bitfld.long 0x08 8. " PHY_REG_BIST_ERR24                         ,Mismatch error flag from the BIST checker 24" "No error,Error"
textline "                                              "
bitfld.long 0x08 7. " PHY_REG_BIST_ERR23                         ,Mismatch error flag from the BIST checker 23" "No error,Error"
textline "                                              "
bitfld.long 0x08 6. " PHY_REG_BIST_ERR22                         ,Mismatch error flag from the BIST checker 22" "No error,Error"
textline "                                              "
bitfld.long 0x08 5. " PHY_REG_BIST_ERR21                         ,Mismatch error flag from the BIST checker 21" "No error,Error"
textline "                                              "
bitfld.long 0x08 4. " PHY_REG_BIST_ERR20                         ,Mismatch error flag from the BIST checker 20" "No error,Error"
textline "                                              "
bitfld.long 0x08 3. " PHY_REG_BIST_ERR19                         ,Mismatch error flag from the BIST checker 19" "No error,Error"
textline "                                              "
bitfld.long 0x08 2. " PHY_REG_BIST_ERR18                         ,Mismatch error flag from the BIST checker 18" "No error,Error"
textline "                                              "
bitfld.long 0x08 1. " PHY_REG_BIST_ERR17                         ,Mismatch error flag from the BIST checker 17" "No error,Error"
textline "                                              "
bitfld.long 0x08 0. " PHY_REG_BIST_ERR16                         ,Mismatch error flag from the BIST checker 16" "No error,Error"
line.long 0x0c "PHY_BIST_ERROR_3_SR,BIST error status register"
bitfld.long 0x0C 12. " PHY_REG_BIST_ERR44                         ,Mismatch error flag from the BIST checker 44" "No error,Error"
textline "                                              "
bitfld.long 0x0C 11. " PHY_REG_BIST_ERR43                         ,Mismatch error flag from the BIST checker 43" "No error,Error"
textline "                                              "
bitfld.long 0x0C 10. " PHY_REG_BIST_ERR42                         ,Mismatch error flag from the BIST checker 42" "No error,Error"
textline "                                              "
bitfld.long 0x0C 9. " PHY_REG_BIST_ERR41                         ,Mismatch error flag from the BIST checker 41" "No error,Error"
textline "                                              "
bitfld.long 0x0C 8. " PHY_REG_BIST_ERR40                         ,Mismatch error flag from the BIST checker 40" "No error,Error"
textline "                                              "
bitfld.long 0x0C 7. " PHY_REG_BIST_ERR39                         ,Mismatch error flag from the BIST checker 39" "No error,Error"
textline "                                              "
bitfld.long 0x0C 6. " PHY_REG_BIST_ERR38                         ,Mismatch error flag from the BIST checker 38" "No error,Error"
textline "                                              "
bitfld.long 0x0C 5. " PHY_REG_BIST_ERR37                         ,Mismatch error flag from the BIST checker 37" "No error,Error"
textline "                                              "
bitfld.long 0x0C 4. " PHY_REG_BIST_ERR36                         ,Mismatch error flag from the BIST checker 36" "No error,Error"
textline "                                              "
bitfld.long 0x0C 3. " PHY_REG_BIST_ERR35                         ,Mismatch error flag from the BIST checker 35" "No error,Error"
textline "                                              "
bitfld.long 0x0C 2. " PHY_REG_BIST_ERR34                         ,Mismatch error flag from the BIST checker 34" "No error,Error"
textline "                                              "
bitfld.long 0x0C 1. " PHY_REG_BIST_ERR33                         ,Mismatch error flag from the BIST checker 33" "No error,Error"
textline "                                              "
bitfld.long 0x0C 0. " PHY_REG_BIST_ERR32                         ,Mismatch error flag from the BIST checker 32" "No error,Error"
line.long 0x10 "PHY_WRLVL_DQS_RATIO_1_SR,Write level DQS ratio status register"
hexmask.long.word 0x10 0.--15. 1. " PHY_REG_WRLVL_DQS_RATIO1                   ,[15:0] bits of PHY_REG_WRLVL_DQS_RATIO"
line.long 0x14 "PHY_WRLVL_DQS_RATIO_2_SR,Write level DQS ratio status register"
hexmask.long.word 0x14 0.--15. 1. " PHY_REG_WRLVL_DQS_RATIO2                   ,[31:16] bits of PHY_REG_WRLVL_DQS_RATIO"
line.long 0x18 "PHY_WRLVL_DQS_RATIO_3_SR,Write level DQS ratio status register"
hexmask.long.word 0x18 0.--15. 1. " PHY_REG_WRLVL_DQS_RATIO3                   ,[47:32] bits of PHY_REG_WRLVL_DQS_RATIO"
line.long 0x1c "PHY_WRLVL_DQS_RATIO_4_SR,Write level DQS ratio status register"
bitfld.long 0x1c 0.--1. " PHY_REG_WRLVL_DQS_RATIO4                   ,[49:48] bits of PHY_REG_WRLVL_DQS_RATIO" "0,1,2,3"
line.long 0x20 "PHY_WRLVL_DQ_RATIO_1_SR,Write level DQ ratio status register"
hexmask.long.word 0x20 0.--15. 1. " PHY_REG_WRLVL_DQ_RATIO1                    ,[15:0] bits of PHY_REG_WRLVL_DQ_RATIO"
line.long 0x24 "PHY_WRLVL_DQ_RATIO_2_SR,Write level DQ ratio status register"
hexmask.long.word 0x24 0.--15. 1. " PHY_REG_WRLVL_DQ_RATIO2                    ,[31:16] bits of PHY_REG_WRLVL_DQ_RATIO"
line.long 0x28 "PHY_WRLVL_DQ_RATIO_3_SR,Write level DQ ratio status register"
hexmask.long.word 0x28 0.--15. 1. " PHY_REG_WRLVL_DQ_RATIO3                    ,[47:32] bits of PHY_REG_WRLVL_DQ_RATIO"
line.long 0x2c "PHY_WRLVL_DQ_RATIO_4_SR,Write level DQ ratio status register"
bitfld.long 0x2c 0.--1. " PHY_REG_WRLVL_DQ_RATIO4                    ,[49:48] bits of PHY_REG_WRLVL_DQ_RATIO" "0,1,2,3"
line.long 0x30 "PHY_RDLVL_DQS_RATIO_1_SR,Read level DQS ratio status register"
hexmask.long.word 0x30 0.--15. 1. " PHY_REG_RDLVL_DQS_RATIO1                   ,[15:0] bits of PHY_REG_RDLVL_DQS_RATIO"
line.long 0x34 "PHY_RDLVL_DQS_RATIO_2_SR,Read level DQS ratio status register"
hexmask.long.word 0x34 0.--15. 1. " PHY_REG_RDLVL_DQS_RATIO2                   ,[31:16] bits of PHY_REG_RDLVL_DQS_RATIO"
line.long 0x38 "PHY_RDLVL_DQS_RATIO_3_SR,Read level DQS ratio status register"
hexmask.long.word 0x38 0.--15. 1. " PHY_REG_RDLVL_DQS_RATIO3                   ,[47:32] bits of PHY_REG_RDLVL_DQS_RATIO"
line.long 0x3c "PHY_RDLVL_DQS_RATIO_4_SR,Read level DQS ratio status register"
bitfld.long 0x3c 0.--1. " PHY_REG_RDLVL_DQS_RATIO4                   ,[49:48] bits of PHY_REG_RDLVL_DQS_RATIO" "0,1,2,3"
line.long 0x40 "PHY_FIFO_1_SR,FIFO status register"
hexmask.long.word 0x40 0.--15. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO1              ,[15:0] bits of PHY_REG_RDLVL_FIFOWEIN_RATIO"
line.long 0x44 "PHY_FIFO_2_SR,FIFO status register"
hexmask.long.word 0x44 0.--15. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO2              ,[31:16] bits of PHY_REG_RDLVL_FIFOWEIN_RATIO"
line.long 0x48 "PHY_FIFO_3_SR,FIFO status register"
hexmask.long.word 0x48 0.--15. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO3              ,[47:32] bits of PHY_REG_RDLVL_FIFOWEIN_RATIO"
line.long 0x4c "PHY_FIFO_4_SR,FIFO status register"
bitfld.long 0x4c 7.--10. " REG_PHY_RDC_FIFO_RST_ERR_CNT               ,Counter reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                              "
hexmask.long.byte 0x4c 0.--6. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO               ,Ratio value generated by read gate training FSM."
line.long 0x50 "PHY_MASTER_DLL_SR,Master DLL status register"
bitfld.long 0x50 8. " PHY_REG_STATUS_OF_IN_LOCK_STATE3F          ,Fine delay line lock status MDLL 3" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x50 7. " PHY_REG_STATUS_OF_IN_LOCK_STATE3C          ,Coarse delay line lock status MDLL 3" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x50 6. " PHY_REG_STATUS_OF_IN_LOCK_STATE2F          ,Fine delay line lock status MDLL 2" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x50 5. " PHY_REG_STATUS_OF_IN_LOCK_STATE2C          ,Coarse delay line lock status MDLL 2" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x50 4. " PHY_REG_STATUS_OF_IN_LOCK_STATE1F          ,Fine delay line lock status MDLL 1" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x50 3. " PHY_REG_STATUS_OF_IN_LOCK_STATE1C          ,Coarse delay line lock status MDLL 1" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x50 2. " PHY_REG_STATUS_DLL_LOCK3                   ,Status signal 3" "Not locked,Locked"
textline "                                              "
bitfld.long 0x50 1. " PHY_REG_STATUS_DLL_LOCK2                   ,Status signal 2" "Not locked,Locked"
textline "                                              "
bitfld.long 0x50 0. " PHY_REG_STATUS_DLL_LOCK1                   ,Status signal 1" "Not locked,Locked"
line.long 0x54 "PHY_DLL_SLAVE_VALUE_1_SR,Slave DLL status register"
hexmask.long.byte 0x54 9.--15. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE31           ,Coarse DLL 3 value"
textline "                                              "
bitfld.long 0x54 7.--8. " PHY_REG_STATUS_DLL_SLAVE_VALUE30           ,Fine DLL 3 value" "0,1,2,3"
textline "                                              "
hexmask.long.byte 0x54 0.--6. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE21           ,Coarse DLL 2 value"
line.long 0x58 "PHY_DLL_SLAVE_VALUE_2_SR,Slave DLL status register"
bitfld.long 0x58 9.--10. " PHY_REG_STATUS_DLL_SLAVE_VALUE20           ,Fine DLL 2 value" "0,1,2,3"
textline "                                              "
hexmask.long.byte 0x58 2.--8. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE11           ,Coarse DLL 1 value"
textline "                                              "
bitfld.long 0x58 0.--1. " PHY_REG_STATUS_DLL_SLAVE_VALUE10           ,Fine DLL 1 value" "0,1,2,3"
line.long 0x5c "PHY_STATUS_OF_IN_DELAY_VAL_1_SR,IN delay status register"
hexmask.long.byte 0x5c 9.--15. 1. " PHY_REG_STATUS_OF_IN_DELAY_VALUE31         ,Coarse DLL 3 value"
textline "                                              "
bitfld.long 0x5c 7.--8. " PHY_REG_STATUS_OF_IN_DELAY_VALUE30         ,Fine DLL 3 value" "0,1,2,3"
textline "                                              "
hexmask.long.byte 0x5c 0.--6. 1. " PHY_REG_STATUS_OF_IN_DELAY_VALUE21         ,Coarse DLL 2 value"
line.long 0x60 "PHY_STATUS_OF_IN_DELAY_VAL_2_SR,IN delay status register"
bitfld.long 0x60 9.--10. " PHY_REG_STATUS_OF_IN_DELAY_VALUE20         ,Fine DLL 2 value" "0,1,2,3"
textline "                                              "
hexmask.long.byte 0x60 2.--8. 1. " PHY_REG_STATUS_OF_IN_DELAY_VALUE11         ,Coarse DLL 1 value"
textline "                                              "
bitfld.long 0x60 0.--1. " PHY_REG_STATUS_OF_IN_DELAY_VALUE10         ,Fine DLL 1 value" "0,1,2,3"
line.long 0x64 "PHY_STATUS_OF_OUT_DELAY_VAL_1_SR,OUT delay status register"
hexmask.long.byte 0x64 9.--15. 1. " PHY_REG_STATUS_OF_OUT_DELAY_VALUE31        ,Coarse DLL 3 value"
textline "                                              "
bitfld.long 0x64 7.--8. " PHY_REG_STATUS_OF_OUT_DELAY_VALUE30        ,Fine DLL 3 value" "0,1,2,3"
textline "                                              "
hexmask.long.byte 0x64 0.--6. 1. " PHY_REG_STATUS_OF_OUT_DELAY_VALUE21        ,Coarse DLL 2 value"
line.long 0x68 "PHY_STATUS_OF_OUT_DELAY_VAL_2_SR,OUT delay status register"
bitfld.long 0x68 9.--10. " PPHY_REG_STATUS_OF_OUT_DELAY_VALUE20       ,Fine DLL 2 value" "0,1,2,3"
textline "                                              "
hexmask.long.byte 0x68 2.--8. 1. " PHY_REG_STATUS_OF_OUT_DELAY_VALUE11        ,Coarse DLL 1 value"
textline "                                              "
bitfld.long 0x68 0.--1. " PHY_REG_STATUS_OF_OUT_DELAY_VALUE10        ,Fine DLL 1 value" "0,1,2,3"
line.long 0x6c "PHY_DLL_LOCK_AND_SLAVE_VAL_SR,DLL lock status register"
bitfld.long 0x6c 9. " PHY_REG_STATUS_PHY_CTRL_DLL_LOCK           ,PHY_CTRL Master DLL Status bits" "Not locked,Locked"
textline "                                              "
hexmask.long.byte 0x6c 2.--6. 1. " PHY_REG_STATUS_PHY_CTRL_DLL_SLAVE_VALUE1   ,The current coarse delay value"
textline "                                              "
bitfld.long 0x6c 0.--1. " PHY_REG_STATUS_PHY_CTRL_DLL_SLAVE_VALUE0   ,The current fine delay value" "0,1,2,3"
line.long 0x70 "PHY_CTRL_OUTPUT_FILTER_SR,Control output filter status register"
bitfld.long 0x70 10. " PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE1  ,Fine delay line lock status" "Unlocked,Locked"
textline "                                              "
bitfld.long 0x70 9. " PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE2  ,Coarse delay line lock status" "Unlocked,Locked"
textline "                                              "
hexmask.long.byte 0x70 2.--6. 1. " PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE1 ,The current coarse delay value"
textline "                                              "
bitfld.long 0x70 0.--1. " PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE0 ,The current fine delay value" "0,1,2,3"
rgroup.long 0x398++0x33
line.long 0x00 "PHY_RD_DQS_SLAVE_DLL_VAL_1_SR,Read DQS slave DLL status register"
hexmask.long.word 0x00 0.--15. 1. " PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE1         ,[15:0] bits of PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE"
line.long 0x04 "PHY_RD_DQS_SLAVE_DLL_VAL_2_SR,Read DQS slave DLL status register"
hexmask.long.word 0x04 0.--15. 1. " PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE2         ,[31:16] bits of PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE"
line.long 0x08 "PHY_RD_DQS_SLAVE_DLL_VAL_3_SR,Read DQS slave DLL status register"
hexmask.long.word 0x08 0.--12. 1. " PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE3         ,[44:32] bits of PHY_STATUS_RD_DQS_SLAVE_DLL_VALUE"
line.long 0x0c "PHY_WR_DATA_SLAVE_DLL_VAL_1_SR,Write DATA slave DLL status register"
hexmask.long.word 0x0c 0.--15. 1. " PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE1    ,[15:0] bits of PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE"
line.long 0x10 "PHY_WR_DATA_SLAVE_DLL_VAL_2_SR,Write DATA slave DLL status register"
hexmask.long.word 0x10 0.--15. 1. " PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE2    ,[31:16] bits of PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE"
line.long 0x14 "PHY_WR_DATA_SLAVE_DLL_VAL_3_SR,Write DATA slave DLL status register"
hexmask.long.word 0x14 0.--12. 1. " PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE3    ,[44:32] bits of PHY_REG_STATUS_WR_DATA_SLAVE_DLL_VALUE"
line.long 0x18 "PHY_FIFO_WE_SLAVE_DLL_VAL_1_SR,FIFO WE slave DLL status register"
hexmask.long.word 0x18 0.--15. 1. " PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE1    ,[15:0] bits of PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE"
line.long 0x1c "PHY_FIFO_WE_SLAVE_DLL_VAL_2_SR,FIFO WE slave DLL status register"
hexmask.long.word 0x1c 0.--15. 1. " PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE2    ,[31:16] bits of PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE"
line.long 0x20 "PHY_FIFO_WE_SLAVE_DLL_VAL_3_SR,FIFO WE slave DLL status register"
hexmask.long.word 0x20 0.--12. 1. " PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE3    ,[44:32] bits of PHY_REG_STATUS_FIFO_WE_SLAVE_DLL_VALUE"
line.long 0x24 "PHY_WR_DQS_SLAVE_DLL_VAL_1_SR,Write DQS slave DLL status register"
hexmask.long.word 0x24 0.--15. 1. " PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE1     ,[15:0] bits of PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE"
line.long 0x28 "PHY_WR_DQS_SLAVE_DLL_VAL_2_SR,Write DQS slave DLL status register"
hexmask.long.word 0x28 0.--15. 1. " PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE2     ,[31:16] bits of PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE"
line.long 0x2c "PHY_WR_DQS_SLAVE_DLL_VAL_3_SR,Write DQS slave DLL status register"
hexmask.long.word 0x2c 0.--12. 1. " PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE3     ,[44:32] bits of PHY_REG_STATUS_WR_DQS_SLAVE_DLL_VALUE"
line.long 0x30 "PHY_CTRL_SLAVE_DLL_VAL_SR,DLL controller status register"
hexmask.long.word 0x30 0.--8. 1. " PHY_REG_STATUS_PHY_CTRL_SLAVE_DLL_VALUE    ,Delay value applied to write DQS slave DLL"
tree.end
width 29.
tree "DDR_FIC registers"
group.long 0x400++0x1f
line.long 0x00 "DDR_FIC_NB_ADDR_CR,Indicates the base address of the nonbufferable address region"
hexmask.long.word 0x00 0.--15. 1. " DDR_FIC_NB_ADD          ,This indicates the base address of the non-bufferable address region"
line.long 0x04 "DDR_FIC_NBRWB_SIZE_CR,Indicates the size of the non-bufferable address region"
bitfld.long 0x04 8. " DDR_FIC_WCB_SZ          ,Write buffer and read buffer size as per DDR burst size" "16 bytes,32 bytes"
bitfld.long 0x04 0.--3. "             DDR_FIC_NUBF_SZ     ,This signal indicates the size of the non-bufferable address region" "Reserved,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB"
line.long 0x08 "DDR_FIC_BUF_TIMER_CR,10-bit timer interface used to configure the timeout register"
hexmask.long.word 0x08 0.--9. 1. " DDR_FIC_TIMER           ,10-bit timer interface used to configure timeout register"
line.long 0x0c "DDR_FIC_HPD_SW_RW_EN_CR,Enable write buffer and read buffer register for AHBL master1 and master2"
bitfld.long 0x0c 6. " DDR_FIC_M1_REN          ,Enable read buffer for AHBL master1" "Disabled,Enabled"
bitfld.long 0x0c 4. "             DDR_FIC_M1_WEN      ,Enable write buffer for AHBL master1" "Disabled,Enabled"
textline "                                      "
bitfld.long 0x0c 2. " DDR_FIC_M2_REN          ,Enable read buffer for AHBL master2" "Disabled,Enabled"
bitfld.long 0x0c 0. "             DDR_FIC_M2_WEN      ,Enable write buffer for AHBL master2" "Disabled,Enabled"
line.long 0x10 "DDR_FIC_HPD_SW_RW_INVAL_CR,Invalidates write buffer and read buffer for AHBL master1 and master2"
bitfld.long 0x10 6. " DDR_FIC_FLSHM1          ,Flush read buffer for AHBL master1" "Disabled,Enabled"
bitfld.long 0x10 4. "             DDR_FIC_INVALID_M1  ,Invalidate write buffer for AHBL master1" "Disabled,Enabled"
textline "                                      "
bitfld.long 0x10 2. " DDR_FIC_FLSHM2          ,Flush write buffer for AHBL master2" "Disabled,Enabled"
bitfld.long 0x10 0. "             DDR_FIC_INVALID_M2  ,Invalidate read buffer for AHBL master2" "Disabled,Enabled"
line.long 0x14 "DDR_FIC_SW_WR_ERCLR_CR,Clear bit for error status by AHBL master1 and master2 write buffer"
bitfld.long 0x14 8. " DDR_FIC_LTO_CLR         ,Clear signal to lock timeout interrupt" "No effect,Cleared"
bitfld.long 0x14 4. "            DDR_FIC_M2_WR_ERCLR ,Clear bit for error status of AHBL master2 write buffer" "No effect,Cleared"
textline "                                      "
bitfld.long 0x14 0. " DDR_FIC_M1_WR_ERCLR     ,Clear bit for error status posted by AHBL master1 write buffer" "No effect,Cleared"
line.long 0x18 "DDR_FIC_ERR_INT_ENABLE,Used for Interrupt generation"
bitfld.long 0x18 1. " SYR_SW_WR_ERR           ,Status bit" "No error,Write request error"
bitfld.long 0x18 0. "  SYR_HPD_WR_ERR      ,Status bit" "No error,Write request error"
line.long 0x1c "DDR_FIC_NUM_AHB_MASTERS_CR,Defines whether one or two AHBL 32-bit masters are implemented in fabric"
bitfld.long 0x1c 4. " CFG_NUM_AHB_MASTERS     ,Defines whether one or two AHBL 32-bit masters are implemented in the fabric" "One,Two"
rgroup.long 0x420++0x1b
line.long 0x0 "DDR_FIC_HPB_ERR_ADDR_1_SR,Tag of write buffer for which error response is received is placed in this register"
hexmask.long.word 0x00 0.--15. 1. " DDR_FIC_M1_ERR_ADD1     ,Tag of write buffer for which error response is received"
line.long 0x4 "DDR_FIC_HPB_ERR_ADDR_2_SR,Tag of write buffer for which error response is received is placed in this register"
hexmask.long.word 0x04 0.--15. 1. " DDR_FIC_M1_ERR_ADD2     ,Tag of write buffer for which error response is received"
line.long 0x8 "DDR_FIC_SW_ERR_ADDR_1_SR,Tag of write buffer for which error response is received is placed in this register"
hexmask.long.word 0x08 0.--15. 1. " DDR_FIC_M2_ERR_ADD1     ,Tag of write buffer for which error response is received"
line.long 0xc "DDR_FIC_SW_ERR_ADDR_2_SR,Tag of write buffer for which error response is received is placed in this register"
hexmask.long.word 0x0c 0.--15. 1. " DDR_FIC_M2_ERR_ADD2     ,Tag of write buffer for which error response is received"
line.long 0x10 "DDR_FIC_HPD_SW_WRB_EMPTY_SR,Indicates valid data in read and write buffer for AHBL master1 and master2"
bitfld.long 0x10 6. " DDR_FIC_M1_RBEMPTY      ,Read buffer of AHBL master1 does not have valid data" "Not empty,Empty"
bitfld.long 0x10 4. "            DDR_FIC_M1_WBEMPTY  ,Write buffer of AHBL master1 does not have valid data" "Not empty,Empty"
textline "                                      "
bitfld.long 0x10 2. " DDR_FIC_M2_RBEMPTY      ,Read buffer of AHBL master2 does not have valid data" "Not empty,Empty"
bitfld.long 0x10 0. "            DDR_FIC_M2_WBEMPTY  ,Write buffer of AHBL master2 does not have valid data" "Not empty,Empty"
line.long 0x14 "DDR_FIC_SW_HPB_LOCKOUT_SR,Write and read buffer status register for AHBL master1 and master2"
bitfld.long 0x14 8. " DDR_FIC_LCKTOUT         ,Indicates lock counter in arbiter reached its maximum value" "0,1"
bitfld.long 0x14 6. "                    DDR_FIC_M2_WDSBL_DN ,High indicates AHBL master2 write buffer is disabled" "No,Yes"
textline "                                      "
bitfld.long 0x14 4. " DDR_FIC_M2_RDSBL_DN     ,High indicates AHBL master2 read buffer is disabled" "No,Yes"
bitfld.long 0x14 2. "                  DDR_FIC_M1_WDSBL_DN ,High indicates AHBL master1 read buffer is disabled" "No,Yes"
textline "                                      "
bitfld.long 0x14 0. " DDR_FIC_M1_RDSBL_DN     ,High indicates AHBL master1 write buffer is disabled" "No,Yes"
line.long 0x18 "DDR_FIC_SW_HPD_WERR_SR,Error response register for bufferable write request"
bitfld.long 0x18 8. " DDR_FIC_M1_WR_ERR       ,Error response is received for bufferable write request" "No error,Error"
bitfld.long 0x18 0. "             DDR_FIC_M2_WR_ERR   ,Error response is received for bufferable write request" "No error,Error"
group.long 0x440++0xb
line.long 0x00 "DDR_LOCK_TIMEOUTVAL_1_CR,Maximum number of cycles a master can hold the bus for locked transfer"
hexmask.long.word 0x00 0.--15. 1. " CFGR_LOCK_TIMEOUT_REG   ,Lock timeout 20-bit register"
line.long 0x04 "DDR_LOCK_TIMEOUTVAL_2_CR,Maximum number of cycles a master can hold the bus for locked transfer"
bitfld.long 0x04 0.--3. " CFGR_LOCK_TIMEOUT_REG   ,Lock timeout 20-bit register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DDR_FIC_LOCK_TIMEOUT_EN_CR,Lock timeout feature enable register"
bitfld.long 0x08 0. " CFGR_LOCK_TIMEOUT_EN    ,Lock timeout feature is enabled and interrupt is generated" "Not generated,Generated"
rgroup.long 0x44c++0x3
line.long 0x00 "DDR_FIC_RDWR_ERR_SR,Indicates read address of math error register"
hexmask.long.byte 0x00 0.--5. 1. " DDR_FIC_CFG_RDWR_ERR_SR ,Read address of math error register"
tree.end
width 0xb
tree.end
textline ""