; -------------------------------------------------------------------------------- ; @Title: M051DX On-Chip Peripherals ; @Props: Released ; @Author: DAB ; @Changelog: 2022-02-24 DAB ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: SVD generated, based on: M051DE_v1.svd (Ver 1.0) ; @Core: Cortex-M0 ; @Chip: M052LDE, M052ZDE, M054LDE, M054ZDE, M058LDE, M058ZDE, M0516LDE,M0516ZDE, ; M052LDN, M052ZDN, M054LDN, M054ZDN, M058LDN, M058ZDN, M0516LDN, M0516ZDN ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perm051dx.per 14385 2022-02-25 08:59:21Z kwisniewski $ config 16. 8. tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end autoindent.on center tree tree "ACMP (ACMP Register Map)" tree "ACMP01" base ad:0x400D0000 group.long 0x00++0x03 line.long 0x00 "ACMP_CR0,Analog Comparator 0 Control Register" bitfld.long 0x00 6. "ACMPOINV,Analog Comparator 0 Output Inverse Enable Control (M05xxDE Only)\n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled" bitfld.long 0x00 4. "NEGSEL,Analog Comparator 0 Negative Input Selection\n" "0: The source of the negative comparator input..,1: The internal band-gap voltage is selected as.." newline bitfld.long 0x00 2. "HYSEN,Analog Comparator 0 Hysteresis Enable Control\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled" bitfld.long 0x00 1. "ACMPIE,Analog Comparator 0 Interrupt Enable Control\n" "0: Interrupt function Disabled,1: Interrupt function Enabled" newline bitfld.long 0x00 0. "ACMPEN,Analog Comparator 0 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Analog Comparator 0 Disabled,1: Analog Comparator 0 Enabled" group.long 0x04++0x03 line.long 0x00 "ACMP_CR1,Analog Comparator 1 Control Register" bitfld.long 0x00 6. "ACMPOINV,Analog Comparator 1 Output Inverse Enable Control (M05xxDE Only)\n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled" bitfld.long 0x00 4. "NEGSEL,Analog Comparator 1 Negative Input Selection\n" "0: The source of the negative comparator input..,1: The internal band-gap voltage is selected as.." newline bitfld.long 0x00 2. "HYSEN,Analog Comparator 1 Hysteresis Enable Control\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled" bitfld.long 0x00 1. "ACMPIE,Analog Comparator 1 Interrupt Enable Control\n" "0: Interrupt function Disabled,1: Interrupt function Enabled" newline bitfld.long 0x00 0. "ACMPEN,Analog Comparator 1 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Analog comparator 1 Disabled,1: Analog comparator 1 Enabled" group.long 0x08++0x03 line.long 0x00 "ACMP_SR01,Analog Comparator 0/1 Status Register" bitfld.long 0x00 3. "ACMPO1,Analog Comparator 1 Output\n" "0: Analog comparator 1 outputs 0,1: Analog comparator 1 outputs 1" bitfld.long 0x00 2. "ACMPO0,Analog Comparator 0 Output\n" "0: Analog comparator 0 outputs 0,1: Analog comparator 0 outputs 1" newline bitfld.long 0x00 1. "ACMPF1,Analog Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state" "0: Analog comparator 1 output does not change,1: Analog comparator 1 output changed since this.." bitfld.long 0x00 0. "ACMPF0,Analog Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state" "0: Analog comparator 0 output does not change,1: Analog comparator 0 output changed since this.." tree.end tree "ACMP23" base ad:0x401D0000 group.long 0x00++0x03 line.long 0x00 "ACMP_CR2,Analog Comparator 2 Control Register (M05xxDN/DE Only)" bitfld.long 0x00 6. "ACMPOINV,Analog Comparator 2 Output Inverse Enable Control (M05xxDE Only)\n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled" bitfld.long 0x00 4. "NEGSEL,Analog Comparator 2 Negative Input Selection\n" "0: The source of the negative comparator input..,1: The internal band-gap voltage is selected as.." newline bitfld.long 0x00 2. "HYSEN,Analog Comparator 2 Hysteresis Enable Control\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled" bitfld.long 0x00 1. "ACMPIE,Analog Comparator 2 Interrupt Enable Control\n" "0: Interrupt function Disabled,1: Interrupt function Enabled" newline bitfld.long 0x00 0. "ACMPEN,Analog Comparator 2 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Analog Comparator 2 Disabled,1: Analog Comparator 2 Enabled" group.long 0x04++0x03 line.long 0x00 "ACMP_CR3,Analog Comparator 3 Control Register (M05xxDN/DE Only)" bitfld.long 0x00 6. "ACMPOINV,Analog Comparator 3 Output Inverse Enable Control (M05xxDE Only)\n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled" bitfld.long 0x00 4. "NEGSEL,Analog Comparator 3 Negative Input Selection\n" "0: The source of the negative comparator input..,1: The internal band-gap voltage is selected as.." newline bitfld.long 0x00 2. "HYSEN,Analog Comparator 3 Hysteresis Enable Control\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled" bitfld.long 0x00 1. "ACMPIE,Analog Comparator 3 Interrupt Enable Control\n" "0: Interrupt function Disabled,1: Interrupt function Enabled" newline bitfld.long 0x00 0. "ACMPEN,Analog Comparator 3 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Analog comparator 3 Disabled,1: Analog comparator 3 Enabled" group.long 0x08++0x03 line.long 0x00 "ACMP_SR23,Analog Comparator 2/3 Status Register (M05xxDN/DE Only)" bitfld.long 0x00 3. "ACMPO3,Analog Comparator 3 Output\n" "0: Analog comparator 3 outputs 0,1: Analog comparator 3 outputs 1" bitfld.long 0x00 2. "ACMPO2,Analog Comparator 2 Output\n" "0: Analog comparator 2 outputs 0,1: Analog comparator 2 outputs 1" newline bitfld.long 0x00 1. "ACMPF3,Analog Comparator 3 Flag\nThis bit is set by hardware whenever the comparator 3 output changes state" "0: Analog comparator 3 output does not change,1: Analog comparator 3 output changed since this.." bitfld.long 0x00 0. "ACMPF2,Analog Comparator 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state" "0: Analog comparator 2 output does not change,1: Analog comparator 2 output changed since this.." tree.end tree.end tree "ADC (ADC Register Map)" base ad:0x400E0000 rgroup.long 0x00++0x03 line.long 0x00 "ADDR0,ADC Data Register 0" bitfld.long 0x00 17. "VALID,Valid Flag \nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1" "0: Data in RSLT is not overwrote,1: Data in RSLT is overwrote" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC" repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 ) group.long ($2+0x04)++0x03 line.long 0x00 "ADDR$1,ADC Data Register $1" rbitfld.long 0x00 17. "VALID,Valid Flag \nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1" "0: Data in RSLT is not overwrote,1: Data in RSLT is overwrote" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC" repeat.end group.long 0x20++0x03 line.long 0x00 "ADCR,ADC Control Register" bitfld.long 0x00 31. "DMOF,Differential Input Mode Output Format\nNote: Burst mode and ADC compare function cannot suppert 2's complement output format this DMOF bit must be cleared to 0 (M05xxBN only)" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.." bitfld.long 0x00 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from two sources: software or external pin STADC" "0: Conversion stops and A/D converter enters..,1: Conversion starts" newline bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control\n" "0: Single-end analog input mode,1: Differential analog input mode" bitfld.long 0x00 8. "TRGEN,External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin" "0: External trigger Disabled,1: External trigger Enabled" newline bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge" bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nSoftware should clear TRGEN bit and ADST bit to 0 before changing TRGS.\nNote: ADC hardware trigger source does not support PWM trigger (M05xxBN only)" "0: A/D conversion is started by external STADC pin,?,?,3: A/D conversion is started by PWM trigger" newline bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode Control\nNote1: When changing the operation mode software should clear ADST bit firstly.\nNote2: In Burst mode the A/D result data always at Data Register 0" "0: Single conversion,1: Burst conversion,2: Single-cycle Scan,3: Continuous Scan" bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" newline bitfld.long 0x00 0. "ADEN,A/D Converter Enable\nNote: Before starting A/D conversion function this bit should be set to 1" "0: A/D converter Disabled,1: A/D converter Enabled" group.long 0x24++0x03 line.long 0x00 "ADCHER,ADC Channel Enable Register" bitfld.long 0x00 8.--9. "PRESEL,Analog Input Channel 7 Source Selection\nNote: When the band-gap voltage is selected as the analog input source of ADC channel 7 ADC peripheral clock rate needs to be limited to lower than 300 kHz" "0: External analog input,1: Internal band-gap voltage,2: Internal temperature sensor,3: Reserved" hexmask.long.byte 0x00 0.--7. 1. "CHEN,Analog Input Channel Enable Control\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x28)++0x03 line.long 0x00 "ADCMPR$1,ADC Compare Register $1" hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: When DIFFEN bit is set to 1 ADC comparator compares CMPD with conversion result with unsigned format (M05xxBN only)" bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be.." bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.." newline bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated.\n" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0x00 0. "CMPEN,Compare Enable Control\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.\n" "0: Compare function Disabled,1: Compare function Enabled" repeat.end group.long 0x30++0x03 line.long 0x00 "ADSR,ADC Status Register" hexmask.long.byte 0x00 16.--23. 1. "OVERRUN,Overrun Flag (Read Only)\nIt is a mirror of OVERRUN bit in ADDRx register.\nWhen ADC is in Burst mode and the FIFO is overrun all bits of OVERRUN[7:0] will be set to 1" hexmask.long.byte 0x00 8.--15. 1. "VALID,Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADDRx register.\nWhen ADC is in Burst mode and any conversion result is valid all bits of VALID[7:0] will be set to 1" newline bitfld.long 0x00 4.--6. "CHANNEL,Current Conversion Channel\nIt is read only" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "BUSY,BUSY/IDLE\nThis bit is a mirror of ADST bit in ADCR register" "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline bitfld.long 0x00 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 then this bit is set to 1 it is cleared by writing 1 to self.\n" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting" bitfld.long 0x00 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting" newline bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion" "0,1" group.long 0x44++0x03 line.long 0x00 "ADTDCR,ADC Trigger Delay Control Register \n(M05xxDN/DE Only)" hexmask.long.byte 0x00 0.--7. 1. "PTDT,PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock" tree.end tree "CLK (CLK Register Map)" base ad:0x50000200 group.long 0x00++0x03 line.long 0x00 "PWRCON,System Power-down Control Register" bitfld.long 0x00 8. "PD_WAIT_CPU,Power-down Entry Condition Control (Write Protect)\n" "0: Chip enters Power-down mode when the..,1: Chip enters Power- down mode when the both.." bitfld.long 0x00 7. "PWR_DOWN_EN,System Power-down Enable Bit (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0 then the chip enters Power-down mode immediately.." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or.." newline bitfld.long 0x00 6. "PD_WU_STS,Power-down Mode Wake-up Interrupt Status\nSet by Power-down wake-up event which indicates that resume from Power-down mode \nThe flag is set if the GPIO UART WDT ACMP or BOD wake-up occurred.\nNote: This bit works only if PD_WU_INT_EN.." "0,1" bitfld.long 0x00 5. "PD_WU_INT_EN,Power-down Mode Wake-up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "PD_WU_DLY,Wake-up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled" bitfld.long 0x00 3. "OSC10K_EN,10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)\n" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.." newline bitfld.long 0x00 2. "OSC22M_EN,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\n" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.." bitfld.long 0x00 0. "XTL12M_EN,4~24 MHz External High Speed Crystal (HXT) Enable Control (Write Protect)\nThe bit default value is set by flash controller user configuration register config0 [26:24]" "0: 4 ~ 24 MHz external high speed crystal..,1: 4 ~ 24 MHz external high speed crystal.." group.long 0x04++0x03 line.long 0x00 "AHBCLK,AHB Devices Clock Enable Control Register" bitfld.long 0x00 4. "HDIV_EN,Divider Controller Clock Enable Control (M05xxDN/DE Only)\n" "0: Divider controller peripheral clock Disabled,1: Divider controller peripheral clock Enabled" bitfld.long 0x00 3. "EBI_EN,EBI Controller Clock Enable Control\n" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled" newline bitfld.long 0x00 2. "ISP_EN,Flash ISP Controller Clock Enable Control\n" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled" group.long 0x08++0x03 line.long 0x00 "APBCLK,APB Devices Clock Enable Control Register" bitfld.long 0x00 31. "ACMP23_EN,Analog Comparator 2/3 Clock Enable Control (M051xxDN/DE Only)\n" "0: Analog Comparator 2/3 clock Disabled,1: Analog Comparator 2/3 clock Enabled" bitfld.long 0x00 30. "ACMP01_EN,Analog Comparator 0/1 Clock Enable Control\n" "0: Analog Comparator 0/1 clock Disabled,1: Analog Comparator 0/1 clock Enabled" newline bitfld.long 0x00 28. "ADC_EN,Analog-digital-converter (ADC) Clock Enable Control\n" "0: ADC peripheral clock Disabled,1: ADC peripheral clock Enabled" bitfld.long 0x00 23. "PWM67_EN,PWM_67 Clock Enable Control\n" "0: PWM67 clock Disabled,1: PWM67 clock Enabled" newline bitfld.long 0x00 22. "PWM45_EN,PWM_45 Clock Enable Control\n" "0: PWM45 clock Disabled,1: PWM45 clock Enabled" bitfld.long 0x00 21. "PWM23_EN,PWM_23 Clock Enable Control\n" "0: PWM23 clock Disabled,1: PWM23 clock Enabled" newline bitfld.long 0x00 20. "PWM01_EN,PWM_01 Clock Enable Control\n" "0: PWM01 clock Disabled,1: PWM01 clock Enabled" bitfld.long 0x00 17. "UART1_EN,UART1 Clock Enable Control\n" "0: UART1 clock Disabled,1: UART1 clock Enabled" newline bitfld.long 0x00 16. "UART0_EN,UART0 Clock Enable Control\n" "0: UART0 clock Disabled,1: UART0 clock Enabled" bitfld.long 0x00 13. "SPI1_EN,SPI1 Peripheral Clock Enable Control\n" "0: SPI1 peripheral clock Disabled,1: SPI1 peripheral clock Enabled" newline bitfld.long 0x00 12. "SPI0_EN,SPI0 Peripheral Clock Enable Control\n" "0: SPI0 peripheral clock Disabled,1: SPI0 peripheral clock Enabled" bitfld.long 0x00 9. "I2C1_EN,I2C1 Clock Enable Control (M051xxDN/DE Only)\n" "0: I2C clock Disabled,1: I2C clock Enabled" newline bitfld.long 0x00 8. "I2C0_EN,I2C0 Clock Enable Control\n" "0: I2C clock Disabled,1: I2C clock Enabled" bitfld.long 0x00 6. "FDIV_EN,Frequency Divider Output Clock Enable Control\n" "0: FDIV clock Disabled,1: FDIV clock Enabled" newline bitfld.long 0x00 5. "TMR3_EN,Timer3 Clock Enable Control\n" "0: Timer3 clock Disabled,1: Timer3 clock Enabled" bitfld.long 0x00 4. "TMR2_EN,Timer2 Clock Enable Control\n" "0: Timer2 clock Disabled,1: Timer2 clock Enabled" newline bitfld.long 0x00 3. "TMR1_EN,Timer1 Clock Enable Control\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled" bitfld.long 0x00 2. "TMR0_EN,Timer0 Clock Enable Control\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled" newline bitfld.long 0x00 0. "WDT_EN,Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled" group.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,Clock Status Monitor Register" bitfld.long 0x00 7. "CLK_SW_FAIL,Clock Switching Fail Flag\nNote1: This bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failed" rbitfld.long 0x00 4. "OSC22M_STB,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Stable Flag (Read Only)\n" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.." newline rbitfld.long 0x00 3. "OSC10K_STB,10 KHz Internal Low Speed RC Oscillator (LIRC) Stable Flag (Read Only)\n" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.." rbitfld.long 0x00 2. "PLL_STB,Internal PLL Clock Source Stable Flag (Read Only)\n" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable" newline rbitfld.long 0x00 0. "XTL12M_STB,4~24 MHz External High Speed Crystal (HXT) Stable Flag (Read Only)\n" "0: 4~24 MHz external high speed crystal (HXT)..,1: 4~24 MHz external high speed crystal (HXT).." group.long 0x10++0x03 line.long 0x00 "CLKSEL0,Clock Source Select Control Register 0" bitfld.long 0x00 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\n" "0: Clock source is from HXT,1: Reserved,2: Clock source is from HXT/2,3: Clock source is from HCLK/2,?,?,?,7: Clock source is from HIRC/2" bitfld.long 0x00 0.--2. "HCLK_S,HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]).." "0: Clock source is from HXT,1: Reserved,2: Clock source is from PLL,3: Clock source is from LIRC,?,?,?,7: Clock source is from HIRC" group.long 0x14++0x03 line.long 0x00 "CLKSEL1,Clock Source Select Control Register 1" bitfld.long 0x00 30.--31. "PWM23_S,PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 use the same peripheral clock source both of them use the same prescaler" "0: Clock source is from HXT,1: Clock source is from LIRC,2: Clock source is from HCLK,3: Clock source is from HIRC" bitfld.long 0x00 28.--29. "PWM01_S,PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same peripheral clock source both of them use the same prescaler" "0: Clock source is from HXT,1: Clock source is from LIRC,2: Clock source is from HCLK,3: Clock source is from HIRC" newline bitfld.long 0x00 24.--25. "UART_S,UART Clock Source Selection\n" "0: Clock source is from HXT,1: Clock source is from PLL,2: Reserved,3: Clock source is from HIRC" bitfld.long 0x00 20.--22. "TMR3_S,TIMER3 Clock Source Selection\n" "0: Clock source is from HXT,?,2: Clock source is from HCLK,3: Clock source is from external trigger T3,?,5: Clock source is from LIRC,?,7: Clock source is from HIRC" newline bitfld.long 0x00 16.--18. "TMR2_S,TIMER2 Clock Source Selection\n" "0: Clock source is from HXT,?,2: Clock source is from HCLK,3: Clock source is from external trigger T2,?,5: Clock source is from LIRC,?,7: Clock source is from HIRC" bitfld.long 0x00 12.--14. "TMR1_S,TIMER1 Clock Source Selection\n" "0: Clock source is from HXT,?,2: Clock source is from HCLK,3: Clock source is from external trigger T1,?,5: Clock source is from LIRC,?,7: Clock source is from HIRC" newline bitfld.long 0x00 8.--10. "TMR0_S,TIMER0 Clock Source Selection\n" "0: Clock source is from HXT,?,2: Clock source is from HCLK,3: Clock source is from external trigger T0,?,5: Clock source is from LIRC,?,7: Clock source is from HIRC" bitfld.long 0x00 5. "SPI1_S,SPI1 Clock Source Selection (M051xxDN/DE Only)\n" "0: Clock source is from PLL,1: Clock source is from HCLK" newline bitfld.long 0x00 4. "SPI0_S,SPI0 Clock Source Selection (M051xxDN/DE Only)\n" "0: Clock source is from PLL,1: Clock source is from HCLK" bitfld.long 0x00 2.--3. "ADC_S,ADC Peripheral Clock Source Selection\n" "0: Clock source is from HXT,1: Clock source is from PLL,2: Clock source is from HCLK,3: Clock source is from HIRC" newline bitfld.long 0x00 0.--1. "WDT_S,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are protected bits and programming them needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: Reserved,1: Reserved,2: Clock source is from HCLK/2048 clock,3: Clock source is from LIRC" group.long 0x18++0x03 line.long 0x00 "CLKDIV,Clock Divider Number Register" hexmask.long.byte 0x00 16.--23. 1. "ADC_N,ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n" bitfld.long 0x00 8.--11. "UART_N,UART Clock Divide Number From UART Clock Source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HCLK_N,HCLK Clock Divide Number From HCLK Clock Source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "CLKSEL2,Clock Source Select Control Register 2" bitfld.long 0x00 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection (M051xxDN/DE Only)\n" "?,?,2: Clock source is from HCLK/2048 clock,3: Clock source is from LIRC" bitfld.long 0x00 6.--7. "PWM67_S,PWM6 and PWM7 Clock Source Selection\nPWM6 and PWM7 used the same peripheral clock source both of them used the same prescaler.\n" "0: Clock source is from HXT,1: Clock source is from LIRC,2: Clock source is from HCLK,3: Clock source is from HIRC" newline bitfld.long 0x00 4.--5. "PWM45_S,PWM4 and PWM5 Clock Source Selection\nPWM4 and PWM5 use the same peripheral clock source both of them used the same prescaler.\n" "0: Clock source is from HXT,1: Clock source is from LIRC,2: Clock source is from HCLK,3: Clock source is from HIRC" bitfld.long 0x00 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\n" "0: Clock source is from HXT,1: Clock source is from LIRC,2: Clock source is from HCLK,3: Clock source is from HIRC" group.long 0x20++0x03 line.long 0x00 "PLLCON,PLL Control Register" bitfld.long 0x00 19. "PLL_SRC,PLL Source Clock Selection\n" "0: PLL source clock from HXT,1: PLL source clock from HIRC" bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Pin Control\n" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low" newline bitfld.long 0x00 17. "BP,PLL Bypass Control\n" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock.." bitfld.long 0x00 16. "PD,Power-down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too.\n" "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)" newline bitfld.long 0x00 14.--15. "OUT_DV,PLL Output Divider Control\nRefer to the formulas below the table" "0,1,2,3" bitfld.long 0x00 9.--13. "IN_DV,PLL Input Divider Control\nRefer to the formulas below the table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--8. 1. "FB_DV,PLL Feedback Divider Control\nRefer to the formulas below the table" group.long 0x24++0x03 line.long 0x00 "FRQDIV,Frequency Divider Control Register" bitfld.long 0x00 5. "DIVIDER1,Frequency Divider 1 Enable Control (M051xxDE Only) \n" "0: Divider output frequency is depended on FSEL..,1: Divider output frequency is the same as input.." bitfld.long 0x00 4. "DIVIDER_EN,Frequency Divider Enable Control\n" "0: Frequency Divider Disabled,1: Frequency Divider Enabled" newline bitfld.long 0x00 0.--3. "FSEL,Divider Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EBI (EBI Register Map)" base ad:0x50010000 group.long 0x00++0x03 line.long 0x00 "EBICON,External Bus Interface General Control Register" bitfld.long 0x00 16.--18. "ExttALE,Expand Time of ALE\nThis field is used to control the ALE pulse width (tALE) for address latch.\n" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follows:\nNote: The default value of output clock is HCLK/1" "0: MCLK frequency is HCLK/1,1: MCLK frequency is HCLK/2,2: MCLK frequency is HCLK/4,3: MCLK frequency is HCLK/8,4: MCLK frequency is HCLK/16,5: MCLK frequency is HCLK/32,?..." newline bitfld.long 0x00 1. "ExtBW16,EBI Data Width 16-bit / 8-bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n" "0: EBI data width is 8 bit,1: EBI data width is 16 bit" bitfld.long 0x00 0. "ExtEN,EBI Enable Control\nThis bit is the functional enable bit for EBI.\n" "0: EBI function Disabled,1: EBI function Enabled" group.long 0x04++0x03 line.long 0x00 "EXTIME,External Bus Interface Timing Control Register" bitfld.long 0x00 24.--27. "ExtIR2R,Idle State Cycle Between Read-read\nWhen read action is finished and the next action is going to read idle state is inserted and nCS signal return to high if ExtIR2R is not 0.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "ExtIW2X,Idle State Cycle After Write\nWhen write action is finished idle state is inserted and nCS signal return to high if ExtIW2X is not 0.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--10. "ExttAHD,EBI Data Access Hold Time\nExttAHD defines data access hold time (tAHD).\n" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--7. "ExttACC,EBI Data Access Time\nExttACC defines data access time (tACC).\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x08++0x03 line.long 0x00 "EBICON2,External Bus Interface General Control Register 2 (M05xxDN/DE Only)" bitfld.long 0x00 2. "WAHD_OFF,Access Hold Time Disable Control When Write\n" "0: tAHD is controlled by ExttAHD[2:0] when write..,1: Zero tAHD when write through EBI" bitfld.long 0x00 1. "RAHD_OFF,Access Hold Time Disable Control When Read\n" "0: tAHD is controlled by ExttAHD[2:0] when read..,1: Zero tAHD when read through EBI" newline bitfld.long 0x00 0. "WBUFF_EN,EBI Write Buffer Enable Control\nEnable this function to improve CPU and EBI access performance.\n" "0: EBI write buffer Disabled,1: EBI write buffer Enabled" tree.end tree "FMC (FMC Register Map)" base ad:0x5000C000 group.long 0x00++0x03 line.long 0x00 "ISPCON,ISP Control Register" bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself" "0,1" bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Control (Write Protect)\n" "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM" newline bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.\n" "0: ISP update User Configuration Disabled,1: ISP update User Configuration Enabled" bitfld.long 0x00 3. "APUEN,APROM Update Enable Control (Write Protect)\n" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM" newline bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM,1: Boot from LDROM" bitfld.long 0x00 0. "ISPEN,ISP Enable Control (Write Protect)\nSet this bit to enable ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled" group.long 0x04++0x03 line.long 0x00 "ISPADR,ISP Address Register" hexmask.long 0x00 0.--31. 1. "ISPADR,ISP Address \nThe M05xxBN/DN/DE has a maximum 16K x 32-bit (64 KB) of embedded Flash which supports word program only" group.long 0x08++0x03 line.long 0x00 "ISPDAT,ISP Data Register" hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data \nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation" group.long 0x0C++0x03 line.long 0x00 "ISPCMD,ISP Command Register" bitfld.long 0x00 0.--5. "ISPCMD,ISP Command \nISP commands are shown below:\n" "0: ,?,?,?,4: Read Unique ID,?,?,?,?,?,?,11: Read Company ID (0xDA),?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,33: Program,34: Page Erase,?,?,?,?,?,?,?,?,?,?,?,46: Set Vector Page Re-Map,?..." group.long 0x10++0x03 line.long 0x00 "ISPTRG,ISP Trigger Control Register" bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n" "0: ISP operation is finished,1: ISP operation is progressed" rgroup.long 0x14++0x03 line.long 0x00 "DFBADR,Data Flash Base Address" hexmask.long 0x00 0.--31. 1. "DFBADR,Data Flash Base Address\nThis register indicates Data Flash start address" group.long 0x18++0x03 line.long 0x00 "FATCON,Flash Access Time Control Register" bitfld.long 0x00 4. "LFOM,Low Frequency Optimization Mode Control (Write Protect)\nWhen chip operation frequency is lower than 25 MHz chip can work more efficiently by setting this bit to 1\n" "0: Low frequency optimization mode Disabled,1: Low frequency optimization mode Enabled" group.long 0x40++0x03 line.long 0x00 "ISPSTA,ISP Status Register (M05xxDN/DE Only)" hexmask.long.word 0x00 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}" bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination.." "0,1" newline rbitfld.long 0x00 1.--2. "CBS,Chip Boot Select (Read Only)\nThis is a mirror of CBS in CONFIG0" "0,1,2,3" rbitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0" "0: ISP operation is finished,1: ISP operation is progressed" tree.end tree "GCR (GCR Register Map)" base ad:0x50000000 rgroup.long 0x00++0x03 line.long 0x00 "PDID,Part Device Identification Number Register" hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects the device part number code" group.long 0x04++0x03 line.long 0x00 "RSTSRC,System Reset Source Register" bitfld.long 0x00 7. "RSTS_CPU,CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: Cortex-M0 core and FMC are reset by software.." bitfld.long 0x00 5. "RSTS_MCU,MCU Reset Flag\nThe RSTS_MCU flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." newline bitfld.long 0x00 4. "RSTS_BOD,Brown-out Detector Reset Flag\nThe RSTS_BOD flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.." bitfld.long 0x00 3. "RSTS_LVR,Low Voltage Reset Flag\nThe RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: The LVR controller had issued the reset.." newline bitfld.long 0x00 2. "RSTS_WDT,Watchdog Reset Flag\nThe RSTS_WDT flag is set by the reset signal from the watchdog timer to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from watchdog timer,1: The watchdog timer had issued the reset.." bitfld.long 0x00 1. "RSTS_RESET,Reset Pin Reset Flag\nThe RSTS_RESET flag is set by the reset signal from the nRST pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from the nRST pin,1: The nRST pin had issued the reset signal to.." newline bitfld.long 0x00 0. "RSTS_POR,Power-on Reset Flag\nThe RSTS_POR flag is set by the reset signal from the Power-on Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIP_RST,1: The Power-on Reset (POR) or CHIP_RST had.." group.long 0x08++0x03 line.long 0x00 "IPRSTC1,Peripheral Reset Control Register 1" bitfld.long 0x00 4. "HDIV_RST,HDIV Controller Reset (Write Protect) (M05xxDN/DE Only)\nSet this bit to 1 will generate a reset signal to the hardware divider" "0: Hardware divider controller normal operation,1: Hardware divider controller reset" bitfld.long 0x00 3. "EBI_RST,EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI" "0: EBI controller normal operation,1: EBI controller reset" newline bitfld.long 0x00 1. "CPU_RST,Cortext-m0 Core One-shot Reset (Write Protect)\nSetting this bit will only reset the Cortext-M0 core and Flash Memory Controller (FMC) and this bit will automatically return 0 after the two clock cycles.\nNote: This bit is the protected bit and.." "0: Cortext-M0 core normal operation,1: Cortext-M0 core one-shot reset" bitfld.long 0x00 0. "CHIP_RST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Cortext-M0 core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset" "0: Chip normal operation,1: Chip one-shot reset" group.long 0x0C++0x03 line.long 0x00 "IPRSTC2,Peripheral Reset Control Register 2" bitfld.long 0x00 28. "ADC_RST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset" bitfld.long 0x00 23. "ACMP23_RST,Analog Comparator B Controller Reset (M05xxDN/DE Only)\n" "0: Analog Comparator B controller normal operation,1: Analog Comparator B controller reset" newline bitfld.long 0x00 22. "ACMP01_RST,Analog Comparator A Controller Reset\n" "0: Analog Comparator A controller normal operation,1: Analog Comparator A controller reset" bitfld.long 0x00 21. "PWM47_RST,PWM47 Controller Reset\n" "0: PWM47 controller normal operation,1: PWM47 controller reset" newline bitfld.long 0x00 20. "PWM03_RST,PWM03 Controller Reset\n" "0: PWM03 controller normal operation,1: PWM03 controller reset" bitfld.long 0x00 17. "UART1_RST,UART1 Controller Reset\n" "0: UART1 controller normal operation,1: UART1 controller reset" newline bitfld.long 0x00 16. "UART0_RST,UART0 Controller Reset\n" "0: UART0 controller normal operation,1: UART0 controller reset" bitfld.long 0x00 13. "SPI1_RST,SPI1 Controller Reset\n" "0: SPI1 controller normal operation,1: SPI1 controller reset" newline bitfld.long 0x00 12. "SPI0_RST,SPI0 Controller Reset\n" "0: SPI0 controller normal operation,1: SPI0 controller reset" bitfld.long 0x00 9. "I2C1_RST,I2C1 Controller Reset (M05xxDN/DE Only)\n" "0: I2C1 controller normal operation,1: I2C1 controller reset" newline bitfld.long 0x00 8. "I2C0_RST,I2C Controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset" bitfld.long 0x00 5. "TMR3_RST,Timer3 Controller Reset\n" "0: Timer3 controller normal operation,1: Timer3 controller reset" newline bitfld.long 0x00 4. "TMR2_RST,Timer2 Controller Reset\n" "0: Timer2 controller normal operation,1: Timer2 controller reset" bitfld.long 0x00 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset" newline bitfld.long 0x00 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset" bitfld.long 0x00 1. "GPIO_RST,GPIO (P0~P4) Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset" group.long 0x18++0x03 line.long 0x00 "BODCR,Brown-out Detector Control Register" bitfld.long 0x00 7. "LVR_EN,Low Voltage Reset Enable Control (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.." bitfld.long 0x00 6. "BOD_OUT,Brown-out Detector Output Status\n" "0: Brown-out Detector output status is 0 which..,1: Brown-out Detector output status is 1 which.." newline bitfld.long 0x00 5. "BOD_LPM,Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is the protected bit and programming.." "0: BOD operated in Normal mode (default),1: BOD Low Power mode Enabled" bitfld.long 0x00 4. "BOD_INTF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.." newline bitfld.long 0x00 3. "BOD_RSTEN,Brown-out Reset Enable Control (Write Protect)\nNote1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high) BOD will assert a signal to reset chip when the detected voltage is lower.." "0: Brown-out INTERRUPT function Enabled,1: Brown-out RESET function Enabled" bitfld.long 0x00 1.--2. "BOD_VL,Brown-out Detector Threshold Voltage Select (Write Protect)\n" "0,1,2,3" newline bitfld.long 0x00 0. "BOD_EN,Brown-out Detector Enable Control (Write Protect)\nThe default value is set by flash controller user configuration register config0 bit[23]\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address.." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled" group.long 0x1C++0x03 line.long 0x00 "TEMPCR,Temperature Sensor Control Register" bitfld.long 0x00 0. "VTEMP_EN,Temperature Sensor Enable Control\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from the ADC conversion result" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled" group.long 0x24++0x03 line.long 0x00 "PORCR,Power-on Reset Controller Register" hexmask.long.word 0x00 0.--15. 1. "POR_DIS_CODE,Power-on Reset Enable Control (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again" group.long 0x30++0x03 line.long 0x00 "P0_MFP,P0 Multiple Function and Input Type Control Register" bitfld.long 0x00 25. "P0_ALT11,P0.1 Alternate Function Selection1 (M05xxDN/DE Only)\nThe pin function of P0.1 depends on P0_MFP[1] P0_ALT[1] and P0_ALT1[1].\nRefer to P0_ALT[1] for detailed description" "0,1" bitfld.long 0x00 24. "P0_ALT10,P0.0 Alternate Function Selection1 (M05xxDN/DE Only)\nThe pin function of P0.0 depends on P0_MFP[0] P0_ALT[0] and P0_ALT1[0].\nRefer to P0_ALT[0] for detailed description" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "P0_TYPEn,P0[7:0] Input Schmitt Trigger Function Enable Control\n" bitfld.long 0x00 15. "P0_ALT7,P0.7 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 14. "P0_ALT6,P0.6 Alternate Function Selection\n" "0,1" bitfld.long 0x00 13. "P0_ALT5,P0.5 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 12. "P0_ALT4,P0.4 Alternate Function Selection\n" "0,1" bitfld.long 0x00 11. "P0_ALT3,P0.3 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 10. "P0_ALT2,P0.2 Alternate Function Selection\n" "0,1" bitfld.long 0x00 9. "P0_ALT1,P0.1 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 8. "P0_ALT0,P0.0 Alternate Function Selection\n" "0,1" hexmask.long.byte 0x00 0.--7. 1. "P0_MFP,P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT for detailed description" group.long 0x34++0x03 line.long 0x00 "P1_MFP,P1 Multiple Function and Input Type Control Register" hexmask.long.byte 0x00 16.--23. 1. "P1_TYPEn,P1[7:0] Input Schmitt Trigger Function Enable Control\n" bitfld.long 0x00 15. "P1_ALT7,P1.7 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 14. "P1_ALT6,P1.6 Alternate Function Selection\n" "0,1" bitfld.long 0x00 13. "P1_ALT5,P1.5 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 12. "P1_ALT4,P1.4 Alternate Function Selection\n" "0,1" bitfld.long 0x00 11. "P1_ALT3,P1.3 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 10. "P1_ALT2,P1.2 Alternate Function Selection\n" "0,1" bitfld.long 0x00 9. "P1_ALT1,P1.1 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 8. "P1_ALT0,P1.0 Alternate Function Selection\n" "0,1" hexmask.long.byte 0x00 0.--7. 1. "P1_MFP,P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT for detailed description" group.long 0x38++0x03 line.long 0x00 "P2_MFP,P2 Multiple Function and Input Type Control Register" hexmask.long.byte 0x00 16.--23. 1. "P2_TYPEn,P2[7:0] Input Schmitt Trigger Function Enable Control\n" bitfld.long 0x00 15. "P2_ALT7,P2.7 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 14. "P2_ALT6,P2.6 Alternate Function Selection\n" "0,1" bitfld.long 0x00 13. "P2_ALT5,P2.5 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 12. "P2_ALT4,P2.4 Alternate Function Selection\n" "0,1" bitfld.long 0x00 11. "P2_ALT3,P2.3 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 10. "P2_ALT2,P2.2 Alternate Function Selection\n" "0,1" bitfld.long 0x00 9. "P2_ALT1,P2.1 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 8. "P2_ALT0,P2.0 Alternate Function Selection\n" "0,1" hexmask.long.byte 0x00 0.--7. 1. "P2_MFP,P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT for detailed description" group.long 0x3C++0x03 line.long 0x00 "P3_MFP,P3 Multiple Function and Input Type Control Register" hexmask.long.byte 0x00 16.--23. 1. "P3_TYPEn,P3[7:0] Input Schmitt Trigger Function Enable\n" bitfld.long 0x00 15. "P3_ALT7,P3.7 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 14. "P3_ALT6,P3.6 Alternate Function Selection\n" "0,1" bitfld.long 0x00 13. "P3_ALT5,P3.5 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 12. "P3_ALT4,P3.4 Alternate Function Selection\n" "0,1" bitfld.long 0x00 11. "P3_ALT3,P3.3 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 10. "P3_ALT2,P3.2 Alternate Function Selection\n" "0,1" bitfld.long 0x00 9. "P3_ALT1,P3.1 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 8. "P3_ALT0,P3.0 Alternate Function Selection\n" "0,1" hexmask.long.byte 0x00 0.--7. 1. "P3_MFP,P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT for detailed description" group.long 0x40++0x03 line.long 0x00 "P4_MFP,P4 Multiple Function and Input Type Control Register" hexmask.long.byte 0x00 16.--23. 1. "P4_TYPEn,P4[7:0] Input Schmitt Trigger Function Enable Control\n" bitfld.long 0x00 15. "P4_ALT7,P4.7 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 14. "P4_ALT6,P4.6 Alternate Function Selection\n" "0,1" bitfld.long 0x00 13. "P4_ALT5,P4.5 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 12. "P4_ALT4,P4.4 Alternate Function Selection\n" "0,1" bitfld.long 0x00 11. "P4_ALT3,P4.3 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 10. "P4_ALT2,P4.2 Alternate Function Selection\n" "0,1" bitfld.long 0x00 9. "P4_ALT1,P4.1 Alternate Function Selection\n" "0,1" newline bitfld.long 0x00 8. "P4_ALT0,P4.0 Alternate Function Selection\n" "0,1" hexmask.long.byte 0x00 0.--7. 1. "P4_MFP,P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT for detailed description" group.long 0x100++0x03 line.long 0x00 "REGWRPROT,Register Write-protection Control Register" hexmask.long.byte 0x00 0.--7. 1. "REGWRPROT,Register Write-protection Code (Write Only)\n" tree.end tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)" base ad:0x50004000 group.long 0x00++0x03 line.long 0x00 "P0_PMD,P0 I/O Mode Control" hexmask.long.word 0x00 0.--15. 1. "PMDn,Port 0-4 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).\nNote3: The initial value of this field is.." group.long 0x04++0x03 line.long 0x00 "P0_OFFD,P0 Digital Input Path Disable Control" hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-4 Pin [N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" group.long 0x08++0x03 line.long 0x00 "P0_DOUT,P0 Data Output Value" hexmask.long.word 0x00 0.--15. 1. "DOUT,Port 0-4 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" group.long 0x0C++0x03 line.long 0x00 "P0_DMASK,P0 Data Output Write Mask" hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-4 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit" rgroup.long 0x10++0x03 line.long 0x00 "P0_PIN,P0 Pin Value" hexmask.long.word 0x00 0.--15. 1. "PIN,Port 0-4 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" group.long 0x14++0x03 line.long 0x00 "P0_DBEN,P0 De-bounce Enable Control" hexmask.long.word 0x00 0.--15. 1. "DBEN,Port 0-4 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit" group.long 0x18++0x03 line.long 0x00 "P0_IMD,P0 Interrupt Mode Control" hexmask.long.word 0x00 0.--15. 1. "IMD,Port 0-4 Pin [N] Edge or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger" group.long 0x1C++0x03 line.long 0x00 "P0_IEN,P0 Interrupt Enable Control" hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-4 Pin [N] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-4 Pin [N] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" group.long 0x20++0x03 line.long 0x00 "P0_ISRC,P0 Interrupt Source Flag" hexmask.long.byte 0x00 0.--7. 1. "ISRC,Port 0-4 Pin [N] Interrupt Source Flag\nWrite :\n" group.long 0x40++0x03 line.long 0x00 "P1_PMD,P1 I/O Mode Control" hexmask.long.word 0x00 0.--15. 1. "PMDn,Port 0-4 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).\nNote3: The initial value of this field is.." group.long 0x44++0x03 line.long 0x00 "P1_OFFD,P1 Digital Input Path Disable Control" hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-4 Pin [N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" group.long 0x48++0x03 line.long 0x00 "P1_DOUT,P1 Data Output Value" hexmask.long.word 0x00 0.--15. 1. "DOUT,Port 0-4 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" group.long 0x4C++0x03 line.long 0x00 "P1_DMASK,P1 Data Output Write Mask" hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-4 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit" group.long 0x50++0x03 line.long 0x00 "P1_PIN,P1 Pin Value" hexmask.long.word 0x00 0.--15. 1. "PIN,Port 0-4 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" group.long 0x54++0x03 line.long 0x00 "P1_DBEN,P1 De-bounce Enable Control" hexmask.long.word 0x00 0.--15. 1. "DBEN,Port 0-4 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit" group.long 0x58++0x03 line.long 0x00 "P1_IMD,P1 Interrupt Mode Control" hexmask.long.word 0x00 0.--15. 1. "IMD,Port 0-4 Pin [N] Edge or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger" group.long 0x5C++0x03 line.long 0x00 "P1_IEN,P1 Interrupt Enable Control" hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-4 Pin [N] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-4 Pin [N] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" group.long 0x60++0x03 line.long 0x00 "P1_ISRC,P1 Interrupt Source Flag" hexmask.long.byte 0x00 0.--7. 1. "ISRC,Port 0-4 Pin [N] Interrupt Source Flag\nWrite :\n" group.long 0x80++0x03 line.long 0x00 "P2_PMD,P2 I/O Mode Control" hexmask.long.word 0x00 0.--15. 1. "PMDn,Port 0-4 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).\nNote3: The initial value of this field is.." group.long 0x84++0x03 line.long 0x00 "P2_OFFD,P2 Digital Input Path Disable Control" hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-4 Pin [N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" group.long 0x88++0x03 line.long 0x00 "P2_DOUT,P2 Data Output Value" hexmask.long.word 0x00 0.--15. 1. "DOUT,Port 0-4 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" group.long 0x8C++0x03 line.long 0x00 "P2_DMASK,P2 Data Output Write Mask" hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-4 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit" group.long 0x90++0x03 line.long 0x00 "P2_PIN,P2 Pin Value" hexmask.long.word 0x00 0.--15. 1. "PIN,Port 0-4 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" group.long 0x94++0x03 line.long 0x00 "P2_DBEN,P2 De-bounce Enable Control" hexmask.long.word 0x00 0.--15. 1. "DBEN,Port 0-4 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit" group.long 0x98++0x03 line.long 0x00 "P2_IMD,P2 Interrupt Mode Control" hexmask.long.word 0x00 0.--15. 1. "IMD,Port 0-4 Pin [N] Edge or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger" group.long 0x9C++0x03 line.long 0x00 "P2_IEN,P2 Interrupt Enable Control" hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-4 Pin [N] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-4 Pin [N] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" group.long 0xA0++0x03 line.long 0x00 "P2_ISRC,P2 Interrupt Source Flag" hexmask.long.byte 0x00 0.--7. 1. "ISRC,Port 0-4 Pin [N] Interrupt Source Flag\nWrite :\n" group.long 0xC0++0x03 line.long 0x00 "P3_PMD,P3 I/O Mode Control" hexmask.long.word 0x00 0.--15. 1. "PMDn,Port 0-4 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).\nNote3: The initial value of this field is.." group.long 0xC4++0x03 line.long 0x00 "P3_OFFD,P3 Digital Input Path Disable Control" hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-4 Pin [N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" group.long 0xC8++0x03 line.long 0x00 "P3_DOUT,P3 Data Output Value" hexmask.long.word 0x00 0.--15. 1. "DOUT,Port 0-4 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" group.long 0xCC++0x03 line.long 0x00 "P3_DMASK,P3 Data Output Write Mask" hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-4 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit" group.long 0xD0++0x03 line.long 0x00 "P3_PIN,P3 Pin Value" hexmask.long.word 0x00 0.--15. 1. "PIN,Port 0-4 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" group.long 0xD4++0x03 line.long 0x00 "P3_DBEN,P3 De-bounce Enable Control" hexmask.long.word 0x00 0.--15. 1. "DBEN,Port 0-4 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit" group.long 0xD8++0x03 line.long 0x00 "P3_IMD,P3 Interrupt Mode Control" hexmask.long.word 0x00 0.--15. 1. "IMD,Port 0-4 Pin [N] Edge or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger" group.long 0xDC++0x03 line.long 0x00 "P3_IEN,P3 Interrupt Enable Control" hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-4 Pin [N] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-4 Pin [N] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" group.long 0xE0++0x03 line.long 0x00 "P3_ISRC,P3 Interrupt Source Flag" hexmask.long.byte 0x00 0.--7. 1. "ISRC,Port 0-4 Pin [N] Interrupt Source Flag\nWrite :\n" group.long 0x100++0x03 line.long 0x00 "P4_PMD,P4 I/O Mode Control" hexmask.long.word 0x00 0.--15. 1. "PMDn,Port 0-4 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).\nNote3: The initial value of this field is.." group.long 0x104++0x03 line.long 0x00 "P4_OFFD,P4 Digital Input Path Disable Control" hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-4 Pin [N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" group.long 0x108++0x03 line.long 0x00 "P4_DOUT,P4 Data Output Value" hexmask.long.word 0x00 0.--15. 1. "DOUT,Port 0-4 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" group.long 0x10C++0x03 line.long 0x00 "P4_DMASK,P4 Data Output Write Mask" hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-4 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit" group.long 0x110++0x03 line.long 0x00 "P4_PIN,P4 Pin Value" hexmask.long.word 0x00 0.--15. 1. "PIN,Port 0-4 Pin [N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" group.long 0x114++0x03 line.long 0x00 "P4_DBEN,P4 De-bounce Enable Control" hexmask.long.word 0x00 0.--15. 1. "DBEN,Port 0-4 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit" group.long 0x118++0x03 line.long 0x00 "P4_IMD,P4 Interrupt Mode Control" hexmask.long.word 0x00 0.--15. 1. "IMD,Port 0-4 Pin [N] Edge or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger" group.long 0x11C++0x03 line.long 0x00 "P4_IEN,P4 Interrupt Enable Control" hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-4 Pin [N] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-4 Pin [N] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin" group.long 0x120++0x03 line.long 0x00 "P4_ISRC,P4 Interrupt Source Flag" hexmask.long.byte 0x00 0.--7. 1. "ISRC,Port 0-4 Pin [N] Interrupt Source Flag\nWrite :\n" group.long 0x180++0x03 line.long 0x00 "DBNCECON,Interrupt De-bounce Control" bitfld.long 0x00 5. "ICLK_ON,Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.." bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.." newline bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection\n" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks" group.long 0x200++0x03 line.long 0x00 "P00_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x204++0x03 line.long 0x00 "P01_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x208++0x03 line.long 0x00 "P02_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x20C++0x03 line.long 0x00 "P03_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x210++0x03 line.long 0x00 "P04_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x214++0x03 line.long 0x00 "P05_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x218++0x03 line.long 0x00 "P06_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x21C++0x03 line.long 0x00 "P07_PDIO,GPIO P0.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x220++0x03 line.long 0x00 "P10_PDIO,GPIO P1.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x224++0x03 line.long 0x00 "P11_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x228++0x03 line.long 0x00 "P12_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x22C++0x03 line.long 0x00 "P13_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x230++0x03 line.long 0x00 "P14_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x234++0x03 line.long 0x00 "P15_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x238++0x03 line.long 0x00 "P16_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x23C++0x03 line.long 0x00 "P17_PDIO,GPIO P1.n Pin Data Input/Output" group.long 0x240++0x03 line.long 0x00 "P20_PDIO,GPIO P2.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x244++0x03 line.long 0x00 "P21_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x248++0x03 line.long 0x00 "P22_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x24C++0x03 line.long 0x00 "P23_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x250++0x03 line.long 0x00 "P24_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x254++0x03 line.long 0x00 "P25_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x258++0x03 line.long 0x00 "P26_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x25C++0x03 line.long 0x00 "P27_PDIO,GPIO P2.n Pin Data Input/Output" group.long 0x260++0x03 line.long 0x00 "P30_PDIO,GPIO P3.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x264++0x03 line.long 0x00 "P31_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x268++0x03 line.long 0x00 "P32_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x26C++0x03 line.long 0x00 "P33_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x270++0x03 line.long 0x00 "P34_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x274++0x03 line.long 0x00 "P35_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x278++0x03 line.long 0x00 "P36_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x27C++0x03 line.long 0x00 "P37_PDIO,GPIO P3.n Pin Data Input/Output" group.long 0x280++0x03 line.long 0x00 "P40_PDIO,GPIO P4.n Pin Data Input/Output" bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x284++0x03 line.long 0x00 "P41_PDIO,GPIO P4.n Pin Data Input/Output" group.long 0x288++0x03 line.long 0x00 "P42_PDIO,GPIO P4.n Pin Data Input/Output" group.long 0x28C++0x03 line.long 0x00 "P43_PDIO,GPIO P4.n Pin Data Input/Output" group.long 0x290++0x03 line.long 0x00 "P44_PDIO,GPIO P4.n Pin Data Input/Output" group.long 0x294++0x03 line.long 0x00 "P45_PDIO,GPIO P4.n Pin Data Input/Output" group.long 0x298++0x03 line.long 0x00 "P46_PDIO,GPIO P4.n Pin Data Input/Output" group.long 0x29C++0x03 line.long 0x00 "P47_PDIO,GPIO P4.n Pin Data Input/Output" tree.end tree "HDIV (HDIV Register Map)" base ad:0x50014000 group.long 0x00++0x03 line.long 0x00 "DIVIDEND,Dividend Source Register" hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend Source\nThis register is given the dividend of divider before calculation starting" group.long 0x04++0x03 line.long 0x00 "DIVISOR,Divisor Source Resister" hexmask.long.word 0x00 0.--15. 1. "DIVISOR,Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculate" group.long 0x08++0x03 line.long 0x00 "DIVQUO,Quotient Result Resister" hexmask.long 0x00 0.--31. 1. "QUOTIENT,Quotient Result\nThis register holds the quotient result of divider after calculation complete" group.long 0x0C++0x03 line.long 0x00 "DIVREM,Remainder Result Register" hexmask.long.word 0x00 16.--31. 1. "REMAINDER31_16,Sign Extension of REMAINDER[15:0]\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) with sign extension (REMAINDER[31:16]) to 32-bit integer" hexmask.long.word 0x00 0.--15. 1. "REMAINDER15_0,Remainder Result\nThis register holds the remainder result of divider after calculation complete" rgroup.long 0x10++0x03 line.long 0x00 "DIVSTS,Divider Status Register" bitfld.long 0x00 1. "DIV0,Divisor Zero Warning\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written" "0: The divisor is not 0,1: The divisor is 0" tree.end tree "I2C (Inter-Integrated Circuit)" repeat 2. (list 0. 1.) (list ad:0x40020000 ad:0x40120000) tree "I2C$1" base $2 group.long 0x00++0x03 line.long 0x00 "I2CON,I2C Control Register" bitfld.long 0x00 7. "EI,I2C Interrupt Enable Control\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x00 6. "ENS1,I2C Controller Enable Control \n" "0: I2C Controller Disabled,1: I2C Controller Enabled" newline bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1" bitfld.long 0x00 4. "STO,I2C STOP Control\nIn master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1" newline bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested" "0,1" bitfld.long 0x00 2. "AA,Assert Acknowledge Control\n" "0,1" group.long 0x04++0x03 line.long 0x00 "I2CADDR0,I2C Slave Address Register0" hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode" bitfld.long 0x00 0. "GC,General Call Function Enable Control\n" "0: General Call function Disabled,1: General Call Function Enabled" group.long 0x08++0x03 line.long 0x00 "I2CDAT,I2C Data Register" hexmask.long.byte 0x00 0.--7. 1. "I2CDAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port" rgroup.long 0x0C++0x03 line.long 0x00 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x00 0.--7. 1. "I2CSTATUS,I2C Status\n" group.long 0x10++0x03 line.long 0x00 "I2CLK,I2C Clock Divided Register" hexmask.long.byte 0x00 0.--7. 1. "I2CLK,I2C Clock Divided \nNote: The minimum value of I2CLK is 4" group.long 0x14++0x03 line.long 0x00 "I2CTOC,I2C Time-out Counter Register" bitfld.long 0x00 2. "ENTI,Time-out Counter Enable Control\nNote: When the 14 bit Time-out counter is enabled it will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x00 1. "DIV4,Time-out Counter Input Clock Divided by 4 \nNote: When Enabled the time-out period is extended 4 times" "0: Time-out counter input clock divided by 4..,1: Time-out counter input clock divided by 4.." newline bitfld.long 0x00 0. "TIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1" repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 ) group.long ($2+0x18)++0x03 line.long 0x00 "I2CADDR$1,I2C Slave Address Register $1" hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode" bitfld.long 0x00 0. "GC,General Call Function Enable Control\n" "0: General Call function Disabled,1: General Call Function Enabled" repeat.end repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x24)++0x03 line.long 0x00 "I2CADM$1,I2C Slave Address Mask Register $1" hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask\n" repeat.end group.long 0x3C++0x03 line.long 0x00 "I2CWKUPCON,I2C Wake-up Control Register (M05xxDN/DE Only)" bitfld.long 0x00 0. "WKUPEN,I2C Wakeup Function Enable Control\n" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" group.long 0x40++0x03 line.long 0x00 "I2CWKUPSTS,I2C Wake-up Status Register (M05xxDN/DE Only)" bitfld.long 0x00 0. "WKUPIF,I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C this bit is set to 1" "0,1" tree.end repeat.end tree.end tree "INT (Interrupt Router)" base ad:0x50000300 rgroup.long 0x00++0x03 line.long 0x00 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ0 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ0 source is not from BOD interrupt (BOD_INT),1: IRQ0 source is from BOD interrupt (BOD_INT),?..." rgroup.long 0x04++0x03 line.long 0x00 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ1 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ1 source is not from watchdog interrupt..,1: IRQ1 source is from watchdog interrupt..,?..." rgroup.long 0x08++0x03 line.long 0x00 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ2 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ2 source is not from external signal..,1: IRQ2 source is from external signal interrupt..,?..." rgroup.long 0x0C++0x03 line.long 0x00 "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ3 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ3 source is not from external signal..,1: IRQ3 source is from external signal interrupt..,?..." rgroup.long 0x10++0x03 line.long 0x00 "IRQ4_SRC,IRQ4 (P0/1) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ4 Source Identity\nNote1: IRQ4 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ4 source is not from P1 interrupt..,1: IRQ4 source is from P1 interrupt..,?..." rgroup.long 0x14++0x03 line.long 0x00 "IRQ5_SRC,IRQ5 (P2/3/4) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ5 Source Identity\nINT_SRC[2]:\nNote1: IRQ5 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ5 source is not from P4 interrupt..,1: IRQ5 source is from P4 interrupt..,?..." rgroup.long 0x18++0x03 line.long 0x00 "IRQ6_SRC,IRQ6 (PWMA) Interrupt Source Identity" bitfld.long 0x00 0.--3. "INT_SRC,IRQ6 Source Identity\nINT_SRC[3]:\nNote1: IRQ6 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ6 source is not from PWM3(PWMA channel 3)..,1: IRQ6 source is from PWM3(PWMA channel 3)..,?..." rgroup.long 0x1C++0x03 line.long 0x00 "IRQ7_SRC,IRQ7 (PWMB) Interrupt Source Identity" bitfld.long 0x00 0.--3. "INT_SRC,IRQ7 Source Identity\nINT_SRC[3]:\nNote1: IRQ7 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ7 source is not from PWM7(PWMB channel 3)..,1: IRQ7 source is from PWM7(PWMB channel 3)..,?..." rgroup.long 0x20++0x03 line.long 0x00 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ8 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ8 source is not from Timer0 interrupt..,1: IRQ8 source is from Timer0 interrupt (TMR0_INT),?..." rgroup.long 0x24++0x03 line.long 0x00 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ9 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ9 source is not from Timer1 interrupt..,1: IRQ9 source is from Timer1 interrupt (TMR1_INT),?..." rgroup.long 0x28++0x03 line.long 0x00 "IRQ10_SRC,IRQ10 (TMR2) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ10 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ10 source is not from Timer2 interrupt..,1: IRQ10 source is from Timer2 interrupt..,?..." rgroup.long 0x2C++0x03 line.long 0x00 "IRQ11_SRC,IRQ11 (TMR3) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ11 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ11 source is not from Timer3 interrupt..,1: IRQ11 source is from Timer3 interrupt..,?..." rgroup.long 0x30++0x03 line.long 0x00 "IRQ12_SRC,IRQ12 (UART0) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ12 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ12 source is not from UART0 interrupt..,1: IRQ12 source is from UART0 interrupt..,?..." rgroup.long 0x34++0x03 line.long 0x00 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ13 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ13 source is not from UART1 interrupt..,1: IRQ13 source is from UART1 interrupt..,?..." rgroup.long 0x38++0x03 line.long 0x00 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ14 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ14 source is not from SPI0 interrupt..,1: IRQ14 source is from SPI0 interrupt (SPI0_INT),?..." rgroup.long 0x3C++0x03 line.long 0x00 "IRQ15_SRC,IRQ15 (SPI1) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ15 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ15 source is not from SPI1 interrupt..,1: IRQ15 source is from SPI1 interrupt (SPI1_INT),?..." rgroup.long 0x40++0x03 line.long 0x00 "IRQ16_SRC,Reserved" rgroup.long 0x44++0x03 line.long 0x00 "IRQ17_SRC,Reserved" rgroup.long 0x48++0x03 line.long 0x00 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ18 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ18 source is not from I2C0 interrupt..,1: IRQ18 source is from I2C0 interrupt (I2C0_INT),?..." rgroup.long 0x4C++0x03 line.long 0x00 "IRQ19_SRC,IRQ19 (I2C1) Interrupt Source Identity (M05xxDN/DE Only)" bitfld.long 0x00 0.--2. "INT_SRC,IRQ19 Source Identity (M05xxDN/DE Only)\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ19 source is not from I2C1 interrupt..,1: IRQ19 source is from I2C1 interrupt (I2C1_INT),?..." rgroup.long 0x50++0x03 line.long 0x00 "IRQ20_SRC,Reserved" rgroup.long 0x54++0x03 line.long 0x00 "IRQ21_SRC,Reserved" rgroup.long 0x58++0x03 line.long 0x00 "IRQ22_SRC,Reserved" rgroup.long 0x5C++0x03 line.long 0x00 "IRQ23_SRC,Reserved" rgroup.long 0x60++0x03 line.long 0x00 "IRQ24_SRC,Reserved" rgroup.long 0x64++0x03 line.long 0x00 "IRQ25_SRC,IRQ25 (ACMP01) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ25 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ25 source is not from ACMP01 interrupt..,1: IRQ25 source is from ACMP01 interrupt..,?..." rgroup.long 0x68++0x03 line.long 0x00 "IRQ26_SRC,IRQ26 (ACMP23) Interrupt Source Identity (M05xxDN/DE Only)" bitfld.long 0x00 0.--2. "INT_SRC,IRQ26 Source Identity (M05xxDN/DE Only)\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ26 source is not from ACMP23 interrupt..,1: IRQ26 source is from ACMP23 interrupt..,?..." rgroup.long 0x6C++0x03 line.long 0x00 "IRQ27_SRC,Reserved" rgroup.long 0x70++0x03 line.long 0x00 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ28 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ28 source is not from Power-down mode..,1: IRQ28 source is from Power-down mode Wake-up..,?..." rgroup.long 0x74++0x03 line.long 0x00 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity" bitfld.long 0x00 0.--2. "INT_SRC,IRQ29 Source Identity\nNote: When the interrupt flag is cleared the corresponding bits will be cleared automatically" "0: IRQ29 source is not from ADC interrupt..,1: IRQ29 source is from ADC interrupt (ADC_INT),?..." rgroup.long 0x78++0x03 line.long 0x00 "IRQ30_SRC,Reserved" rgroup.long 0x7C++0x03 line.long 0x00 "IRQ31_SRC,Reserved" group.long 0x80++0x03 line.long 0x00 "NMI_SEL,NMI Source Interrupt Select Control Register" bitfld.long 0x00 8. "NMI_EN,NMI Interrupt Enable Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection" "0: NMI interrupt Disabled,1: NMI interrupt Enabled" bitfld.long 0x00 0.--4. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "NVIC (NVIC Register Map)" base ad:0xE000E100 group.long 0x00++0x03 line.long 0x00 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register" hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Enable Register\nEnable one or more interrupts" group.long 0x80++0x03 line.long 0x00 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register" hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Disable Register\nDisable one or more interrupts" group.long 0x100++0x03 line.long 0x00 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register" hexmask.long 0x00 0.--31. 1. "SETPEND,Set Interrupt Pending Register\nWrite:\nRead value indicates the current pending status" group.long 0x180++0x03 line.long 0x00 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register" hexmask.long 0x00 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register\nWrite:\nRead value indicates the current pending status" group.long 0x300++0x03 line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_3,Priority of IRQ3\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_2,Priority of IRQ2\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_1,Priority of IRQ1\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_0,Priority of IRQ0\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x304++0x03 line.long 0x00 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_7,Priority of IRQ7\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_6,Priority of IRQ6\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_5,Priority of IRQ5\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_4,Priority of IRQ4\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x308++0x03 line.long 0x00 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_11,Priority of IRQ11\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_10,Priority of IRQ10\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_9,Priority of IRQ9\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_8,Priority of IRQ8\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x30C++0x03 line.long 0x00 "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_15,Priority of IRQ15\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_14,Priority of IRQ14\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_13,Priority of IRQ13\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_12,Priority of IRQ12\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x310++0x03 line.long 0x00 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_19,Priority of IRQ19\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_18,Priority of IRQ18\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_17,Priority of IRQ17\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_16,Priority of IRQ16\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x314++0x03 line.long 0x00 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_23,Priority of IRQ23\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_22,Priority of IRQ22\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_21,Priority of IRQ21\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_20,Priority of IRQ20\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x318++0x03 line.long 0x00 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_27,Priority of IRQ27\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_26,Priority of IRQ26\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_25,Priority of IRQ25\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_24,Priority of IRQ24\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" group.long 0x31C++0x03 line.long 0x00 "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register" bitfld.long 0x00 30.--31. "PRI_31,Priority of IRQ31\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_30,Priority of IRQ30\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_29,Priority of IRQ29\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" bitfld.long 0x00 6.--7. "PRI_28,Priority of IRQ28\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3" tree.end tree "PWM (Pulse-Width Modulator)" tree "PWMA" base ad:0x40040000 group.long 0x00++0x03 line.long 0x00 "PPR,PWM Prescaler Register" hexmask.long.byte 0x00 24.--31. 1. "DZI23,Dead-zone Interval for Pair of Channel 2 and Channel 3 (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n" hexmask.long.byte 0x00 16.--23. 1. "DZI01,Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n" newline hexmask.long.byte 0x00 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-timer 2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-Timer.\n" hexmask.long.byte 0x00 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-Timer\n" group.long 0x04++0x03 line.long 0x00 "CSR,PWM Clock Source Divider Select Register" bitfld.long 0x00 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" group.long 0x08++0x03 line.long 0x00 "PCR,PWM Control Register" bitfld.long 0x00 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\n" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x00 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\n" "0: Edge-aligned type,1: Center-aligned type" newline bitfld.long 0x00 27. "CH3MOD,PWM-timer 3 Auto-reload/One-shot Mode Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 26. "CH3INV,PWM-timer 3 Output Inverter Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 25. "CH3PINV,PWM-timer 3 Output Polar Inverse Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 24. "CH3EN,PWM-timer 3 Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x00 19. "CH2MOD,PWM-timer 2 Auto-reload/One-shot Mode Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 18. "CH2INV,PWM-timer 2 Output Inverter Enable Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 17. "CH2PINV,PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 16. "CH2EN,PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x00 11. "CH1MOD,PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 10. "CH1INV,PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 9. "CH1PINV,PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 8. "CH1EN,PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x00 5. "DZEN23,Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7.." "0: Disabled,1: Enabled" bitfld.long 0x00 4. "DZEN01,Dead-zone 0 Generator Enable Control (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4.." "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "CH0MOD,PWM-timer 0 Auto-reload/One-shot Mode Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 2. "CH0INV,PWM-timer 0 Output Inverter Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 1. "CH0PINV,PWM-timer 0 Output Polar Inverse Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 0. "CH0EN,PWM-timer 0 Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running" group.long 0x0C++0x03 line.long 0x00 "CNR0,PWM Counter Register 0" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x10++0x03 line.long 0x00 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" rgroup.long 0x14++0x03 line.long 0x00 "PDR0,PWM Data Register 0" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x18++0x03 line.long 0x00 "CNR1,PWM Counter Register 1" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x1C++0x03 line.long 0x00 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" group.long 0x20++0x03 line.long 0x00 "PDR1,PWM Data Register 1" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x24++0x03 line.long 0x00 "CNR2,PWM Counter Register 2" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x28++0x03 line.long 0x00 "CMR2,PWM Comparator Register 2" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" group.long 0x2C++0x03 line.long 0x00 "PDR2,PWM Data Register 2" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x30++0x03 line.long 0x00 "CNR3,PWM Counter Register 3" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x34++0x03 line.long 0x00 "CMR3,PWM Comparator Register 3" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" group.long 0x38++0x03 line.long 0x00 "PDR3,PWM Data Register 3" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x40++0x03 line.long 0x00 "PIER,PWM Interrupt Enable Register" bitfld.long 0x00 25. "INT23DTYPE,PWM23 Duty Interrupt Type Selection (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type" "0: PWMDIFx will be set if PWM counter down count..,1: PWMDIFx will be set when PWM counter up count.." bitfld.long 0x00 24. "INT01DTYPE,PWM01 Duty Interrupt Type Selection (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type" "0: PWMDIFx will be set if PWM counter down count..,1: PWMDIFx will be set when PWM counter up count.." newline bitfld.long 0x00 17. "INT23TYPE,PWM23 Interrupt Period Type Selection (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Setting INT23TYPE to 1 only works when PWM operating is in center-aligned type" "0: PWMIFx will be set if PWM counter underflow,1: PWMIFx will be set if PWM counter matches.." bitfld.long 0x00 16. "INT01TYPE,PWM01 Interrupt Period Type Selection (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Setting INT01TYPE to 1 only works when PWM operating is in center-aligned type" "0: PWMIFx will be set if PWM counter underflow,1: PWMIFx will be set if PWM counter matches.." newline bitfld.long 0x00 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 3 duty interrupt Disabled,1: PWM channel 3 duty interrupt Enabled" bitfld.long 0x00 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 2 duty interrupt Disabled,1: PWM channel 2 duty interrupt Enabled" newline bitfld.long 0x00 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 1 duty interrupt Disabled,1: PWM channel 1 duty interrupt Enabled" bitfld.long 0x00 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 0 duty interrupt Disabled,1: PWM channel 0 duty interrupt Enabled" newline bitfld.long 0x00 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable Control\n" "0: PWM channel 3 period interrupt Disabled,1: PWM channel 3 period interrupt Enabled" bitfld.long 0x00 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable Control\n" "0: PWM channel 2 period interrupt Disabled,1: PWM channel 2 period interrupt Enabled" newline bitfld.long 0x00 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable Control\n" "0: PWM channel 1 period interrupt Disabled,1: PWM channel 1 period interrupt Enabled" bitfld.long 0x00 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable Control\n" "0: PWM channel 0 period interrupt Disabled,1: PWM channel 0 period interrupt Enabled" group.long 0x44++0x03 line.long 0x00 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x00 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 3. "PWMIF3,PWM Channel 3 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 3 PWM counter equal to zero if channel 3 PWM period interrupt enable bit (PWMIE3) is 1" "0,1" bitfld.long 0x00 2. "PWMIF2,PWM Channel 2 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 2 PWM counter equal to zero if channel 2 PWM period interrupt enable bit (PWMIE2) is 1" "0,1" newline bitfld.long 0x00 1. "PWMIF1,PWM Channel 1 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 1 PWM counter equal to zero if channel 1 PWM period interrupt enable bit (PWMIE1) is 1" "0,1" bitfld.long 0x00 0. "PWMIF0,PWM Channel 0 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 0 PWM counter equal to zero if channel 0 PWM period interrupt enable bit (PWMIE0) is 1" "0,1" group.long 0x50++0x03 line.long 0x00 "CCR0,PWM Capture Control Register 0" bitfld.long 0x00 23. "CFLRI1,CFLR1 Latched Indicator\nWhen PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 22. "CRLRI1,CRLR1 Latched Indicator \nWhen PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 19. "CAPCH1EN,Channel 1 Capture Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group channel.." "0: Capture function on PWM group channel 1..,1: Capture function on PWM group channel 1 Enabled" newline bitfld.long 0x00 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x00 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x00 16. "INV1,Capture Channel 1 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" bitfld.long 0x00 7. "CFLRI0,CFLR0 Latched Indicator Control\nWhen PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 6. "CRLRI0,CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 3. "CAPCH0EN,Channel 0 Capture Function Enable Control\nNote1: When Enabled Capture latches the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group.." "0: Capture function on PWM group channel 0..,1: Capture function on PWM group channel 0 Enabled" bitfld.long 0x00 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 0 has falling transition and Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x00 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x00 0. "INV0,Capture Channel 0 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" group.long 0x54++0x03 line.long 0x00 "CCR2,PWM Capture Control Register 2" bitfld.long 0x00 23. "CFLRI3,CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 22. "CRLRI3,CRLR3 Latched Indicator \nWhen PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 20. "CAPIF3,Channel 3 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 19. "CAPCH3EN,Channel 3 Capture Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group channel.." "0: Capture function on PWM group channel 3..,1: Capture function on PWM group channel 3 Enabled" newline bitfld.long 0x00 18. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 3 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x00 17. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 3 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x00 16. "INV3,Capture Channel 3 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" bitfld.long 0x00 7. "CFLRI2,CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 6. "CRLRI2,CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 4. "CAPIF2,Channel 2 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 3. "CAPCH2EN,Channel 2 Capture Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group.." "0: Capture function on PWM group channel 2..,1: Capture function on PWM group channel 2 Enabled" bitfld.long 0x00 2. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 2 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x00 1. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 2 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x00 0. "INV2,Capture Channel 2 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" rgroup.long 0x58++0x03 line.long 0x00 "CRLR0,PWM Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" rgroup.long 0x5C++0x03 line.long 0x00 "CFLR0,PWM Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x60++0x03 line.long 0x00 "CRLR1,PWM Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" group.long 0x64++0x03 line.long 0x00 "CFLR1,PWM Capture Falling Latch Register (Channel 1)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x68++0x03 line.long 0x00 "CRLR2,PWM Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" group.long 0x6C++0x03 line.long 0x00 "CFLR2,PWM Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x70++0x03 line.long 0x00 "CRLR3,PWM Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" group.long 0x74++0x03 line.long 0x00 "CFLR3,PWM Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x78++0x03 line.long 0x00 "CAPENR,PWM Capture Input 0~3 Enable Register" bitfld.long 0x00 0.--3. "CAPENR,Capture Input Enable Register\nCAPENR\nBit 3210 for PWM group A\nBit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.0 or P4.0. User can only select one of pins by setting multi-function pin register.\nBit xx1x ( Capture.." "0: Capture input Disabled,1: Capture input Enabled,?..." group.long 0x7C++0x03 line.long 0x00 "POE,PWM Output Enable Register for Channel 0~3" bitfld.long 0x00 3. "PWM3,Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled" bitfld.long 0x00 2. "PWM2,Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled" newline bitfld.long 0x00 1. "PWM1,Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled" bitfld.long 0x00 0. "PWM0,Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled" group.long 0x80++0x03 line.long 0x00 "TCON,PWM Trigger Control Register for Channel 0~3 (M05xxDN/DE Only)" bitfld.long 0x00 11. "PWM3DTEN,Channel 3 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to match CMR3.\nAs PWM operating at.." "0: PWM channel 3 duty trigger ADC function..,1: PWM channel 3 duty trigger ADC function Enabled" bitfld.long 0x00 10. "PWM2DTEN,Channel 2 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to match CMR2.\nAs PWM operating at.." "0: PWM channel 2 duty trigger ADC function..,1: PWM channel 2 duty trigger ADC function Enabled" newline bitfld.long 0x00 9. "PWM1DTEN,Channel 1 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to match CMR1.\nAs PWM operating at.." "0: PWM channel 1 duty trigger ADC function..,1: PWM channel 1 duty trigger ADC function Enabled" bitfld.long 0x00 8. "PWM0DTEN,Channel 0 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to match CMR0.\nAs PWM operating at.." "0: PWM channel 0 duty trigger ADC function..,1: PWM channel 0 duty trigger ADC function Enabled" newline bitfld.long 0x00 3. "PWM3TEN,Channel 3 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 3 period trigger ADC function..,1: PWM channel 3 period trigger ADC function.." bitfld.long 0x00 2. "PWM2TEN,Channel 2 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 2 period trigger ADC function..,1: PWM channel 2 period trigger ADC function.." newline bitfld.long 0x00 1. "PWM1TEN,Channel 1 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 1 period trigger ADC function..,1: PWM channel 1 period trigger ADC function.." bitfld.long 0x00 0. "PWM0TEN,Channel 0 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 0 period trigger ADC function..,1: PWM channel 0 period trigger ADC function.." group.long 0x84++0x03 line.long 0x00 "TSTATUS,PWM Trigger Status Register (M05xxDN/DE Only)" bitfld.long 0x00 3. "PWM3TF,Channel 3 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 3 trigger ADC condition matched" "0,1" bitfld.long 0x00 2. "PWM2TF,Channel 2 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 2 trigger ADC condition matched" "0,1" newline bitfld.long 0x00 1. "PWM1TF,Channel 1 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 1 trigger ADC condition matched" "0,1" bitfld.long 0x00 0. "PWM0TF,Channel 0 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 0 trigger ADC condition matched" "0,1" group.long 0x98++0x03 line.long 0x00 "PSCR,PWM Synchronous Control Register (M05xxDN/DE Only)" bitfld.long 0x00 24. "PSSEN3,Channel 3 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 3 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 3 PWM-Timer Synchronous Start Disabled,1: Channel 3 PWM-Timer Synchronous Start Enabled" bitfld.long 0x00 16. "PSSEN2,Channel 2 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 2 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 2 PWM-Timer Synchronous Start Disabled,1: Channel 2 PWM-Timer Synchronous Start Enabled" newline bitfld.long 0x00 8. "PSSEN1,Channel 1 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 1 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 1 PWM-Timer Synchronous Start Disabled,1: Channel 1 PWM-Timer Synchronous Start Enabled" bitfld.long 0x00 0. "PSSEN0,Channel 0 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 0 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 0 PWM-Timer Synchronous Start Disabled,1: Channel 0 PWM-Timer Synchronous Start Enabled" tree.end tree "PWMB" base ad:0x40140000 group.long 0x00++0x03 line.long 0x00 "PPR,PWM Prescaler Register" hexmask.long.byte 0x00 24.--31. 1. "DZI23,Dead-zone Interval for Pair of Channel 2 and Channel 3 (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n" hexmask.long.byte 0x00 16.--23. 1. "DZI01,Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n" newline hexmask.long.byte 0x00 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-timer 2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-Timer.\n" hexmask.long.byte 0x00 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-Timer\n" group.long 0x04++0x03 line.long 0x00 "CSR,PWM Clock Source Divider Select Register" bitfld.long 0x00 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" group.long 0x08++0x03 line.long 0x00 "PCR,PWM Control Register" bitfld.long 0x00 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\n" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x00 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\n" "0: Edge-aligned type,1: Center-aligned type" newline bitfld.long 0x00 27. "CH3MOD,PWM-timer 3 Auto-reload/One-shot Mode Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 26. "CH3INV,PWM-timer 3 Output Inverter Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 25. "CH3PINV,PWM-timer 3 Output Polar Inverse Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 24. "CH3EN,PWM-timer 3 Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x00 19. "CH2MOD,PWM-timer 2 Auto-reload/One-shot Mode Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 18. "CH2INV,PWM-timer 2 Output Inverter Enable Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 17. "CH2PINV,PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 16. "CH2EN,PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x00 11. "CH1MOD,PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 10. "CH1INV,PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 9. "CH1PINV,PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 8. "CH1EN,PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x00 5. "DZEN23,Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7.." "0: Disabled,1: Enabled" bitfld.long 0x00 4. "DZEN01,Dead-zone 0 Generator Enable Control (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4.." "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "CH0MOD,PWM-timer 0 Auto-reload/One-shot Mode Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared" "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x00 2. "CH0INV,PWM-timer 0 Output Inverter Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x00 1. "CH0PINV,PWM-timer 0 Output Polar Inverse Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B) (M05xxDN/DE Only)\n" "0: Polar Inverter Disabled,1: Polar Inverter Enabled" bitfld.long 0x00 0. "CH0EN,PWM-timer 0 Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running" group.long 0x0C++0x03 line.long 0x00 "CNR0,PWM Counter Register 0" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x10++0x03 line.long 0x00 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" rgroup.long 0x14++0x03 line.long 0x00 "PDR0,PWM Data Register 0" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x18++0x03 line.long 0x00 "CNR1,PWM Counter Register 1" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x1C++0x03 line.long 0x00 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" group.long 0x20++0x03 line.long 0x00 "PDR1,PWM Data Register 1" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x24++0x03 line.long 0x00 "CNR2,PWM Counter Register 2" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x28++0x03 line.long 0x00 "CMR2,PWM Comparator Register 2" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" group.long 0x2C++0x03 line.long 0x00 "PDR2,PWM Data Register 2" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x30++0x03 line.long 0x00 "CNR3,PWM Counter Register 3" hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0 PWM output is always high.\nNote3: When PWM operating at center-aligned type CNR value.." group.long 0x34++0x03 line.long 0x00 "CMR3,PWM Comparator Register 3" hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle" group.long 0x38++0x03 line.long 0x00 "PDR3,PWM Data Register 3" hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter" group.long 0x40++0x03 line.long 0x00 "PIER,PWM Interrupt Enable Register" bitfld.long 0x00 25. "INT23DTYPE,PWM23 Duty Interrupt Type Selection (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type" "0: PWMDIFx will be set if PWM counter down count..,1: PWMDIFx will be set when PWM counter up count.." bitfld.long 0x00 24. "INT01DTYPE,PWM01 Duty Interrupt Type Selection (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type" "0: PWMDIFx will be set if PWM counter down count..,1: PWMDIFx will be set when PWM counter up count.." newline bitfld.long 0x00 17. "INT23TYPE,PWM23 Interrupt Period Type Selection (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Setting INT23TYPE to 1 only works when PWM operating is in center-aligned type" "0: PWMIFx will be set if PWM counter underflow,1: PWMIFx will be set if PWM counter matches.." bitfld.long 0x00 16. "INT01TYPE,PWM01 Interrupt Period Type Selection (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Setting INT01TYPE to 1 only works when PWM operating is in center-aligned type" "0: PWMIFx will be set if PWM counter underflow,1: PWMIFx will be set if PWM counter matches.." newline bitfld.long 0x00 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 3 duty interrupt Disabled,1: PWM channel 3 duty interrupt Enabled" bitfld.long 0x00 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 2 duty interrupt Disabled,1: PWM channel 2 duty interrupt Enabled" newline bitfld.long 0x00 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 1 duty interrupt Disabled,1: PWM channel 1 duty interrupt Enabled" bitfld.long 0x00 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Control (M05xxDN/DE Only)\n" "0: PWM channel 0 duty interrupt Disabled,1: PWM channel 0 duty interrupt Enabled" newline bitfld.long 0x00 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable Control\n" "0: PWM channel 3 period interrupt Disabled,1: PWM channel 3 period interrupt Enabled" bitfld.long 0x00 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable Control\n" "0: PWM channel 2 period interrupt Disabled,1: PWM channel 2 period interrupt Enabled" newline bitfld.long 0x00 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable Control\n" "0: PWM channel 1 period interrupt Disabled,1: PWM channel 1 period interrupt Enabled" bitfld.long 0x00 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable Control\n" "0: PWM channel 0 period interrupt Disabled,1: PWM channel 0 period interrupt Enabled" group.long 0x44++0x03 line.long 0x00 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x00 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 3. "PWMIF3,PWM Channel 3 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 3 PWM counter equal to zero if channel 3 PWM period interrupt enable bit (PWMIE3) is 1" "0,1" bitfld.long 0x00 2. "PWMIF2,PWM Channel 2 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 2 PWM counter equal to zero if channel 2 PWM period interrupt enable bit (PWMIE2) is 1" "0,1" newline bitfld.long 0x00 1. "PWMIF1,PWM Channel 1 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 1 PWM counter equal to zero if channel 1 PWM period interrupt enable bit (PWMIE1) is 1" "0,1" bitfld.long 0x00 0. "PWMIF0,PWM Channel 0 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 0 PWM counter equal to zero if channel 0 PWM period interrupt enable bit (PWMIE0) is 1" "0,1" group.long 0x50++0x03 line.long 0x00 "CCR0,PWM Capture Control Register 0" bitfld.long 0x00 23. "CFLRI1,CFLR1 Latched Indicator\nWhen PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 22. "CRLRI1,CRLR1 Latched Indicator \nWhen PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 19. "CAPCH1EN,Channel 1 Capture Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group channel.." "0: Capture function on PWM group channel 1..,1: Capture function on PWM group channel 1 Enabled" newline bitfld.long 0x00 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x00 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x00 16. "INV1,Capture Channel 1 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" bitfld.long 0x00 7. "CFLRI0,CFLR0 Latched Indicator Control\nWhen PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 6. "CRLRI0,CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 3. "CAPCH0EN,Channel 0 Capture Function Enable Control\nNote1: When Enabled Capture latches the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group.." "0: Capture function on PWM group channel 0..,1: Capture function on PWM group channel 0 Enabled" bitfld.long 0x00 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 0 has falling transition and Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x00 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x00 0. "INV0,Capture Channel 0 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" group.long 0x54++0x03 line.long 0x00 "CCR2,PWM Capture Control Register 2" bitfld.long 0x00 23. "CFLRI3,CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 22. "CRLRI3,CRLR3 Latched Indicator \nWhen PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 20. "CAPIF3,Channel 3 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 19. "CAPCH3EN,Channel 3 Capture Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group channel.." "0: Capture function on PWM group channel 3..,1: Capture function on PWM group channel 3 Enabled" newline bitfld.long 0x00 18. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 3 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x00 17. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 3 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x00 16. "INV3,Capture Channel 3 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" bitfld.long 0x00 7. "CFLRI2,CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 6. "CRLRI2,CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 4. "CAPIF2,Channel 2 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x00 3. "CAPCH2EN,Channel 2 Capture Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled Capture does not update CRLR and CFLR and disable PWM group.." "0: Capture function on PWM group channel 2..,1: Capture function on PWM group channel 2 Enabled" bitfld.long 0x00 2. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 2 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x00 1. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable Control\nNote: When Enabled if Capture detects PWM group channel 2 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x00 0. "INV2,Capture Channel 2 Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled" rgroup.long 0x58++0x03 line.long 0x00 "CRLR0,PWM Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" rgroup.long 0x5C++0x03 line.long 0x00 "CFLR0,PWM Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x60++0x03 line.long 0x00 "CRLR1,PWM Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" group.long 0x64++0x03 line.long 0x00 "CFLR1,PWM Capture Falling Latch Register (Channel 1)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x68++0x03 line.long 0x00 "CRLR2,PWM Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" group.long 0x6C++0x03 line.long 0x00 "CFLR2,PWM Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x70++0x03 line.long 0x00 "CRLR3,PWM Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition" group.long 0x74++0x03 line.long 0x00 "CFLR3,PWM Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition" group.long 0x78++0x03 line.long 0x00 "CAPENR,PWM Capture Input 0~3 Enable Register" bitfld.long 0x00 0.--3. "CAPENR,Capture Input Enable Register\nCAPENR\nBit 3210 for PWM group A\nBit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.0 or P4.0. User can only select one of pins by setting multi-function pin register.\nBit xx1x ( Capture.." "0: Capture input Disabled,1: Capture input Enabled,?..." group.long 0x7C++0x03 line.long 0x00 "POE,PWM Output Enable Register for Channel 0~3" bitfld.long 0x00 3. "PWM3,Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled" bitfld.long 0x00 2. "PWM2,Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled" newline bitfld.long 0x00 1. "PWM1,Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled" bitfld.long 0x00 0. "PWM0,Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled" group.long 0x80++0x03 line.long 0x00 "TCON,PWM Trigger Control Register for Channel 0~3 (M05xxDN/DE Only)" bitfld.long 0x00 11. "PWM3DTEN,Channel 3 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to match CMR3.\nAs PWM operating at.." "0: PWM channel 3 duty trigger ADC function..,1: PWM channel 3 duty trigger ADC function Enabled" bitfld.long 0x00 10. "PWM2DTEN,Channel 2 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to match CMR2.\nAs PWM operating at.." "0: PWM channel 2 duty trigger ADC function..,1: PWM channel 2 duty trigger ADC function Enabled" newline bitfld.long 0x00 9. "PWM1DTEN,Channel 1 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to match CMR1.\nAs PWM operating at.." "0: PWM channel 1 duty trigger ADC function..,1: PWM channel 1 duty trigger ADC function Enabled" bitfld.long 0x00 8. "PWM0DTEN,Channel 0 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to match CMR0.\nAs PWM operating at.." "0: PWM channel 0 duty trigger ADC function..,1: PWM channel 0 duty trigger ADC function Enabled" newline bitfld.long 0x00 3. "PWM3TEN,Channel 3 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 3 period trigger ADC function..,1: PWM channel 3 period trigger ADC function.." bitfld.long 0x00 2. "PWM2TEN,Channel 2 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 2 period trigger ADC function..,1: PWM channel 2 period trigger ADC function.." newline bitfld.long 0x00 1. "PWM1TEN,Channel 1 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 1 period trigger ADC function..,1: PWM channel 1 period trigger ADC function.." bitfld.long 0x00 0. "PWM0TEN,Channel 0 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to underflow.\nAs PWM operating at.." "0: PWM channel 0 period trigger ADC function..,1: PWM channel 0 period trigger ADC function.." group.long 0x84++0x03 line.long 0x00 "TSTATUS,PWM Trigger Status Register (M05xxDN/DE Only)" bitfld.long 0x00 3. "PWM3TF,Channel 3 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 3 trigger ADC condition matched" "0,1" bitfld.long 0x00 2. "PWM2TF,Channel 2 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 2 trigger ADC condition matched" "0,1" newline bitfld.long 0x00 1. "PWM1TF,Channel 1 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 1 trigger ADC condition matched" "0,1" bitfld.long 0x00 0. "PWM0TF,Channel 0 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 0 trigger ADC condition matched" "0,1" group.long 0x98++0x03 line.long 0x00 "PSCR,PWM Synchronous Control Register (M05xxDN/DE Only)" bitfld.long 0x00 24. "PSSEN3,Channel 3 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 3 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 3 PWM-Timer Synchronous Start Disabled,1: Channel 3 PWM-Timer Synchronous Start Enabled" bitfld.long 0x00 16. "PSSEN2,Channel 2 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 2 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 2 PWM-Timer Synchronous Start Disabled,1: Channel 2 PWM-Timer Synchronous Start Enabled" newline bitfld.long 0x00 8. "PSSEN1,Channel 1 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 1 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 1 PWM-Timer Synchronous Start Disabled,1: Channel 1 PWM-Timer Synchronous Start Enabled" bitfld.long 0x00 0. "PSSEN0,Channel 0 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1 the PWM-Timer channel 0 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in.." "0: Channel 0 PWM-Timer Synchronous Start Disabled,1: Channel 0 PWM-Timer Synchronous Start Enabled" tree.end tree.end tree "SCB (SCB Register Map)" base ad:0xE000ED00 rgroup.long 0x00++0x03 line.long 0x00 "CPUID,CPUID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer Code\n" bitfld.long 0x00 16.--19. "PART,Architecture of the Processor\nRead as 0xC for ARMv6-M parts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 4.--15. 1. "PARTNO,Part Number of the Processor\nRead as 0xC20" bitfld.long 0x00 0.--3. "REVISION,Revision Number\nRead as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.." bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.." newline bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite:\nThis bit is write-only" "0: No effect,1: Removes the pending state from the PendSV.." bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite:\n" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.." newline bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite:\nNote: This bit is write-only" "0: No effect,1: Removes the pending state from the SysTick.." bitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit\nIf set a pending exception will be serviced on exit from the debug halt state.\nThis bit is read only" "0,1" newline rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)\n" "0: Interrupt not pending,1: Interrupt pending" bitfld.long 0x00 12.--17. "VECTPENDING,Exception Number of the Highest Priority Pending Enabled Exception\n" "0: No pending exceptions,?..." newline bitfld.long 0x00 0.--5. "VECTACTIVE,Contains the Active Exception Number\n" "0: Thread mode,?..." group.long 0x0C++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWrite:\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored" bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence" "0,1" newline bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nReserved for debug use" "0,1" group.long 0x10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.." bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: Sleep mode,1: Deep Sleep mode" newline bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.." group.long 0x1C++0x03 line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "SHPR3,System Handler Priority Register 3" bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3" tree.end tree "SPI (SPI Register Map)" repeat 2. (list 0. 1.) (list ad:0x40030000 ad:0x40034000) tree "SPI$1" base $2 group.long 0x00++0x03 line.long 0x00 "SPI_CNTRL,Control and Status Register" rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_STATUS[27]" "0: Indicates that the transmit FIFO buffer is..,1: Indicates that the transmit FIFO buffer is full" rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_STATUS[26]" "0: Indicates that the transmit FIFO buffer is..,1: Indicates that the transmit FIFO buffer is.." newline rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n" "0: Indicates that the receive FIOF buffer is not..,1: Indicates that the receive FIFO buffer is full" rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]" "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty" newline bitfld.long 0x00 23. "VARCLK_EN,Variable Clock Enable Control (M05xxBN Master Mode Only)\nNote: When this VARCLK_EN bit is set the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)" "0: The bus clock output frequency is fixed and..,1: The bus clock output frequency is variable" bitfld.long 0x00 21. "FIFO,FIFO Mode Enable Control (M05xxDN/DE Only)\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth transmit FIFO" "0: FIFO Mode Disabled,1: FIFO Mode Enabled" newline bitfld.long 0x00 19.--20. "REORDER,Byte Reorder Function and Byte Suspend Function Selection\nOn M05xxBN:\nNote: Byte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits" "0: Disable both byte reorder and byte suspend..,1: Enable byte reorder function and insert a..,2: Enable byte reorder function but disable byte..,3: Disable byte reorder function but insert a.." bitfld.long 0x00 18. "SLAVE,Slave Mode Control\n" "0: Master mode,1: Slave mode" newline bitfld.long 0x00 17. "IE,Unit-transfer Interrupt Enable Control\n" "0: SPI unit-transfer interrupt Disabled,1: SPI unit-transfer interrupt Enabled" bitfld.long 0x00 16. "IF,Unit-transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer" newline bitfld.long 0x00 12.--15. "SP_CYCLE,Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transactions in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. "CLKP,Clock Polarity\n" "0: SPICLK idle low,1: SPICLK idle high" newline bitfld.long 0x00 10. "LSB,LSB First\n" "0: The MSB is transmitted/received first,1: The LSB is transmitted/received first" bitfld.long 0x00 8.--9. "TX_NUM,Numbers of Transmit/Receive Word (M05xxBN Only)\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration if TX_NUM is set to 01 the slave\nselect pin.." "0: Burst mode Disabled,1: Burst mode Enabled,2: Reserved,3: Reserved" newline bitfld.long 0x00 3.--7. "TX_BIT_LEN,Transfer Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. "TX_NEG,Transmit on Negative Edge\n" "0: The transmitted data output signal is driven..,1: The transmitted data output signal is driven.." newline bitfld.long 0x00 1. "RX_NEG,Receive on Negative Edge\n" "0: The received data input signal is latched on..,1: The received data input signal is latched on.." bitfld.long 0x00 0. "GO_BUSY,SPI Transfer Trigger and Busy Status\nOn M05xxBN:\nDuring the data transfer this bit keeps the value of 1" "0: Writing 0 to this bit to stop data transfer..,1: In Master mode writing 1 to this bit will.." group.long 0x04++0x03 line.long 0x00 "SPI_DIVIDER,Clock Divider Register" hexmask.long.word 0x00 16.--31. 1. "DIVIDER2,Clock Divider 2 (M05xxBN Master Mode Only)\nThe value in this field is the 2nd frequency divider for generating the bus clock on the output SPICLK" hexmask.long.word 0x00 0.--15. 1. "DIVIDER,Clock Divider\nOn M05xxBN:\nOnly available in Master mode" group.long 0x08++0x03 line.long 0x00 "SPI_SSR,Slave Select Register" bitfld.long 0x00 5. "LTRIG_FLAG,Level Trigger Flag\nWhen the SS_LTRIG bit is set in Slave mode this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only and only available in Slave mode" "0: The transaction number or the transferred bit..,1: The transaction number and the transferred.." bitfld.long 0x00 4. "SS_LTRIG,Slave Select Level Trigger Enable (Slave Only)\n" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger" newline bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: If this bit is cleared slave select signal..,1: If this bit is set SPISSx signal will be.." bitfld.long 0x00 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx).\n" "0: The slave select signal SPISSx is active at..,1: The slave select signal SPISSx is active at.." newline bitfld.long 0x00 0. "SSR,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared to 0 \n" "0: Set the SPISSx line to inactive state.\nKeep..,1: Set the proper SPISSx line to active.." rgroup.long 0x10++0x03 line.long 0x00 "SPI_RX0,Data Receive Register 0" hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer" group.long 0x14++0x03 line.long 0x00 "SPI_RX1,Data Receive Register 1 (M05xxBN Only)" hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer" wgroup.long 0x20++0x03 line.long 0x00 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer" group.long 0x24++0x03 line.long 0x00 "SPI_TX1,Data Transmit Register 1 (M05xxBN Only)" hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer" group.long 0x34++0x03 line.long 0x00 "SPI_VARCLK,Variable Clock Pattern Register (M05xxBN Only)" hexmask.long 0x00 0.--31. 1. "VARCLK,Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI bus clock" group.long 0x3C++0x03 line.long 0x00 "SPI_CNTRL2,Control and Status Register 2" bitfld.long 0x00 31. "BCn,Clock Configuration Backward Compatible Option (M05xxDN/DE Only)\nRefer to the description of SPI_DIVIDER register for details" "0: The clock configuration is backward..,1: The clock configuration is not backward.." bitfld.long 0x00 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option (M05xxDN/DE Only)\nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x00 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status\nThis bit dedicates if a transaction has started in Slave 3-wire mode" "0: Slave does not detect any SPI bus clock..,1: A transaction has started in Slave 3-wire mode" bitfld.long 0x00 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode" "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled" newline bitfld.long 0x00 9. "SLV_ABORT,Slave 3-wire Mode Abort Control\nIn normal operation there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN and TX_NUM" "0,1" bitfld.long 0x00 8. "NOSLVSEL,Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode" "0: The controller is 4-wire bi-direction interface,1: The controller is 3-wire bi-direction.." newline bitfld.long 0x00 0. "DIV_ONE,SPI Bus Clock Divider Control (M05xxBN Master Mode Only)\nNote: When this bit is set to 1 both the REORDER field and the VARCLK_EN field must be configured as 0" "0: The SPI bus clock rate is determined by the..,1: Enable the DIV_ONE feature" group.long 0x40++0x03 line.long 0x00 "SPI_FIFO_CTL,SPI FIFO Control Register (M05xxDN/DE Only)" bitfld.long 0x00 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0" "0,1,2,3" bitfld.long 0x00 24.--25. "RX_THRESHOLD,Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0" "0,1,2,3" newline bitfld.long 0x00 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable Control\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" bitfld.long 0x00 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Control\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" newline bitfld.long 0x00 3. "TX_INTEN,Transmit Threshold Interrupt Enable Control\n" "0: Transmit threshold interrupt Disabled,1: Transmit threshold interrupt Enabled" bitfld.long 0x00 2. "RX_INTEN,Receive Threshold Interrupt Enable Control\n" "0: Receive threshold interrupt Disabled,1: Receive threshold interrupt Enabled" newline bitfld.long 0x00 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer" bitfld.long 0x00 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer" group.long 0x44++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register (M05xxDN/DE Only)" rbitfld.long 0x00 28.--31. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n" "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full" newline rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26]" "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty" rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25]" "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full" newline rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]" "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty" bitfld.long 0x00 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No receive FIFO time-out event,1: The receive FIFO buffer is not empty and it.." newline bitfld.long 0x00 16. "IF,SPI Unit-transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16]" "0: The transfer does not finish yet,1: The SPI controller has finished one unit.." rbitfld.long 0x00 12.--15. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave 3-wire mode" "0: The transfer is not started,1: The transfer has started in Slave 3-wire mode" rbitfld.long 0x00 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." newline bitfld.long 0x00 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself" "0,1" rbitfld.long 0x00 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO..,1: The valid data count within the receive FIFO.." tree.end repeat.end tree.end tree "SYST (SYST Register Map)" base ad:0xE000E010 group.long 0x00++0x03 line.long 0x00 "SYST_CSR,SysTick Control and Status Register" bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1" bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection\n" "0: Clock source is optional refer to STCLK_S,1: Core clock used for SysTick timer" newline bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled\n" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.." bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled\n" "0: Counter Disabled,1: Counter Enabled and will operate in a.." group.long 0x04++0x03 line.long 0x00 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0" group.long 0x08++0x03 line.long 0x00 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value" tree.end tree "TIMER (Timer/Counter)" tree "TMR01" base ad:0x40010000 group.long 0x00++0x03 line.long 0x00 "TCSR0,Timer0 Control and Status Register" bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "IE,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.." newline bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.." rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "CTB,Counter Mode Enable Control\nThis bit is for external counting pin function enabled" "0: External event counter mode Disabled,1: External event counter mode Enabled" bitfld.long 0x00 23. "WAKE_EN,Wake-up Function Enable Control (M05xxDN/DE Only)\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x00 22. "CAP_SRC,Capture Pin Source Selection (M05xxDN/DE Only)\n" "0: Capture Function source is from TxEX pin,1: Capture Function source is from internal.." bitfld.long 0x00 21. "TOUT_SEL,Toggle-output Pin Selection (M05xxDN/DE Only)\n" "0: Toggle-output pin is from Tx pin,1: Toggle-output pin is from TxEx pin" newline bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable (M05xxDN/DE Only)\nIf updated TCMP value TDR TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.." bitfld.long 0x00 19. "INTR_TRG_EN,Inter-timer Trigger Mode Enable Control (M05xxDN/DE Only)\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also Timer1/3 will be in.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" newline bitfld.long 0x00 16. "TDR_EN,Data Load Enable Control\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.." hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n" group.long 0x04++0x03 line.long 0x00 "TCMPR0,Timer0 Compare Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register" group.long 0x08++0x03 line.long 0x00 "TISR0,Timer0 Interrupt Status Register" bitfld.long 0x00 1. "TWF,Timer Wake-up Flag (M05xxDN/DE Only)\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x0C++0x03 line.long 0x00 "TDR0,Timer0 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value" rgroup.long 0x10++0x03 line.long 0x00 "TCAP0,Timer0 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately" group.long 0x14++0x03 line.long 0x00 "TEXCON0,Timer0 External Control Register" bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx pin de-bounce Disabled,1: Tx pin de-bounce Enabled" bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of TxEX pin is detected with de-bounce circuit" "0: TxEX pin de-bounce Disabled,1: TxEX pin de-bounce Enabled" newline bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TxEX pin detection Interrupt Disabled,1: TxEX pin detection Interrupt Enabled" bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TxEX pin is using to save the..,1: Transition on TxEX pin is using to reset the.." newline bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n" "0: RSTCAPSEL function of TxEX pin will be ignored,1: RSTCAPSEL function of TxEX pin is active" bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TxEX pin will be..,1: A 0 to 1 transition on TxEX pin will be..,2: Either 1 to 0 or 0 to 1 transition on TxEX..,3: Reserved" newline bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n" "0: A falling edge of Tx pin will be counted,1: A rising edge of Tx pin will be counted" group.long 0x18++0x03 line.long 0x00 "TEXISR0,Timer0 External Interrupt Status Register" bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled TxEX pin selected as external capture function and a transition on TxEX pin matched the TEX_EDGE setting this flag will set.." "0: TxEX pin interrupt did not occur,1: TxEX pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TCSR1,Timer1 Control and Status Register" bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "IE,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.." newline bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.." rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "CTB,Counter Mode Enable Control\nThis bit is for external counting pin function enabled" "0: External event counter mode Disabled,1: External event counter mode Enabled" bitfld.long 0x00 23. "WAKE_EN,Wake-up Function Enable Control (M05xxDN/DE Only)\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x00 22. "CAP_SRC,Capture Pin Source Selection (M05xxDN/DE Only)\n" "0: Capture Function source is from TxEX pin,1: Capture Function source is from internal.." bitfld.long 0x00 21. "TOUT_SEL,Toggle-output Pin Selection (M05xxDN/DE Only)\n" "0: Toggle-output pin is from Tx pin,1: Toggle-output pin is from TxEx pin" newline bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable (M05xxDN/DE Only)\nIf updated TCMP value TDR TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.." bitfld.long 0x00 19. "INTR_TRG_EN,Inter-timer Trigger Mode Enable Control (M05xxDN/DE Only)\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also Timer1/3 will be in.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" newline bitfld.long 0x00 16. "TDR_EN,Data Load Enable Control\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.." hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n" group.long 0x24++0x03 line.long 0x00 "TCMPR1,Timer1 Compare Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register" group.long 0x28++0x03 line.long 0x00 "TISR1,Timer1 Interrupt Status Register" bitfld.long 0x00 1. "TWF,Timer Wake-up Flag (M05xxDN/DE Only)\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value" group.long 0x2C++0x03 line.long 0x00 "TDR1,Timer1 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value" group.long 0x30++0x03 line.long 0x00 "TCAP1,Timer1 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately" group.long 0x34++0x03 line.long 0x00 "TEXCON1,Timer1 External Control Register" bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx pin de-bounce Disabled,1: Tx pin de-bounce Enabled" bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of TxEX pin is detected with de-bounce circuit" "0: TxEX pin de-bounce Disabled,1: TxEX pin de-bounce Enabled" newline bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TxEX pin detection Interrupt Disabled,1: TxEX pin detection Interrupt Enabled" bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TxEX pin is using to save the..,1: Transition on TxEX pin is using to reset the.." newline bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n" "0: RSTCAPSEL function of TxEX pin will be ignored,1: RSTCAPSEL function of TxEX pin is active" bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TxEX pin will be..,1: A 0 to 1 transition on TxEX pin will be..,2: Either 1 to 0 or 0 to 1 transition on TxEX..,3: Reserved" newline bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n" "0: A falling edge of Tx pin will be counted,1: A rising edge of Tx pin will be counted" group.long 0x38++0x03 line.long 0x00 "TEXISR1,Timer1 External Interrupt Status Register" bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled TxEX pin selected as external capture function and a transition on TxEX pin matched the TEX_EDGE setting this flag will set.." "0: TxEX pin interrupt did not occur,1: TxEX pin interrupt occurred" tree.end tree "TMR23" base ad:0x40110000 group.long 0x00++0x03 line.long 0x00 "TCSR2,Timer2 Control and Status Register" bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "IE,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.." newline bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.." rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "CTB,Counter Mode Enable Control\nThis bit is for external counting pin function enabled" "0: External event counter mode Disabled,1: External event counter mode Enabled" bitfld.long 0x00 23. "WAKE_EN,Wake-up Function Enable Control (M05xxDN/DE Only)\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x00 22. "CAP_SRC,Capture Pin Source Selection (M05xxDN/DE Only)\n" "0: Capture Function source is from TxEX pin,1: Capture Function source is from internal.." bitfld.long 0x00 21. "TOUT_SEL,Toggle-output Pin Selection (M05xxDN/DE Only)\n" "0: Toggle-output pin is from Tx pin,1: Toggle-output pin is from TxEx pin" newline bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable (M05xxDN/DE Only)\nIf updated TCMP value TDR TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.." bitfld.long 0x00 19. "INTR_TRG_EN,Inter-timer Trigger Mode Enable Control (M05xxDN/DE Only)\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also Timer1/3 will be in.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" newline bitfld.long 0x00 16. "TDR_EN,Data Load Enable Control\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.." hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n" group.long 0x04++0x03 line.long 0x00 "TCMPR2,Timer2 Compare Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register" group.long 0x08++0x03 line.long 0x00 "TISR2,Timer2 Interrupt Status Register" bitfld.long 0x00 1. "TWF,Timer Wake-up Flag (M05xxDN/DE Only)\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x0C++0x03 line.long 0x00 "TDR2,Timer2 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value" rgroup.long 0x10++0x03 line.long 0x00 "TCAP2,Timer2 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately" group.long 0x14++0x03 line.long 0x00 "TEXCON2,Timer2 External Control Register" bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx pin de-bounce Disabled,1: Tx pin de-bounce Enabled" bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of TxEX pin is detected with de-bounce circuit" "0: TxEX pin de-bounce Disabled,1: TxEX pin de-bounce Enabled" newline bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TxEX pin detection Interrupt Disabled,1: TxEX pin detection Interrupt Enabled" bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TxEX pin is using to save the..,1: Transition on TxEX pin is using to reset the.." newline bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n" "0: RSTCAPSEL function of TxEX pin will be ignored,1: RSTCAPSEL function of TxEX pin is active" bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TxEX pin will be..,1: A 0 to 1 transition on TxEX pin will be..,2: Either 1 to 0 or 0 to 1 transition on TxEX..,3: Reserved" newline bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n" "0: A falling edge of Tx pin will be counted,1: A rising edge of Tx pin will be counted" group.long 0x18++0x03 line.long 0x00 "TEXISR2,Timer2 External Interrupt Status Register" bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled TxEX pin selected as external capture function and a transition on TxEX pin matched the TEX_EDGE setting this flag will set.." "0: TxEX pin interrupt did not occur,1: TxEX pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TCSR3,Timer3 Control and Status Register" bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "IE,Interrupt Enable Control\nIf this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.." newline bitfld.long 0x00 26. "CRST,Timer Reset\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.." rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "CTB,Counter Mode Enable Control\nThis bit is for external counting pin function enabled" "0: External event counter mode Disabled,1: External event counter mode Enabled" bitfld.long 0x00 23. "WAKE_EN,Wake-up Function Enable Control (M05xxDN/DE Only)\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x00 22. "CAP_SRC,Capture Pin Source Selection (M05xxDN/DE Only)\n" "0: Capture Function source is from TxEX pin,1: Capture Function source is from internal.." bitfld.long 0x00 21. "TOUT_SEL,Toggle-output Pin Selection (M05xxDN/DE Only)\n" "0: Toggle-output pin is from Tx pin,1: Toggle-output pin is from TxEx pin" newline bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable (M05xxDN/DE Only)\nIf updated TCMP value TDR TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.." bitfld.long 0x00 19. "INTR_TRG_EN,Inter-timer Trigger Mode Enable Control (M05xxDN/DE Only)\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also Timer1/3 will be in.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" newline bitfld.long 0x00 16. "TDR_EN,Data Load Enable Control\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.." hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n" group.long 0x24++0x03 line.long 0x00 "TCMPR3,Timer3 Compare Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register" group.long 0x28++0x03 line.long 0x00 "TISR3,Timer3 Interrupt Status Register" bitfld.long 0x00 1. "TWF,Timer Wake-up Flag (M05xxDN/DE Only)\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value" group.long 0x2C++0x03 line.long 0x00 "TDR3,Timer3 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value" group.long 0x30++0x03 line.long 0x00 "TCAP3,Timer3 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately" group.long 0x34++0x03 line.long 0x00 "TEXCON3,Timer3 External Control Register" bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx pin de-bounce Disabled,1: Tx pin de-bounce Enabled" bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled the edge detection of TxEX pin is detected with de-bounce circuit" "0: TxEX pin de-bounce Disabled,1: TxEX pin de-bounce Enabled" newline bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TxEX pin detection Interrupt Disabled,1: TxEX pin detection Interrupt Enabled" bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection\n" "0: Transition on TxEX pin is using to save the..,1: Transition on TxEX pin is using to reset the.." newline bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n" "0: RSTCAPSEL function of TxEX pin will be ignored,1: RSTCAPSEL function of TxEX pin is active" bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection\n" "0: A 1 to 0 transition on TxEX pin will be..,1: A 0 to 1 transition on TxEX pin will be..,2: Either 1 to 0 or 0 to 1 transition on TxEX..,3: Reserved" newline bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n" "0: A falling edge of Tx pin will be counted,1: A rising edge of Tx pin will be counted" group.long 0x38++0x03 line.long 0x00 "TEXISR3,Timer3 External Interrupt Status Register" bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled TxEX pin selected as external capture function and a transition on TxEX pin matched the TEX_EDGE setting this flag will set.." "0: TxEX pin interrupt did not occur,1: TxEX pin interrupt occurred" tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" repeat 2. (list 0. 1.) (list ad:0x40050000 ad:0x40150000) tree "UART$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART Controller will return an 8-bit data received from UART_RX pin (LSB first)" wgroup.long 0x00++0x03 line.long 0x00 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART Controller will send out an 8-bit data through the UART_ TX pin (LSB first)" group.long 0x04++0x03 line.long 0x00 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto-flow Control Enable Control\nNote: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto-flow control Disabled,1: CTS auto-flow control Enabled" bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto-flow Control Enable Control\nNote: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will reassert RTS signal" "0: RTS auto-flow control Disabled,1: RTS auto-flow control Enabled" newline bitfld.long 0x00 11. "TIME_OUT_EN,Time-out Counter Enable Control\n" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x00 8. "LIN_RX_BRK_IEN,LIN RX Break Field Detected Interrupt Enable Control\nNote: This bit is used for LIN function mode" "0: LIN bus RX break filed interrupt Disabled,1: LIN bus RX break filed interrupt Enabled" newline bitfld.long 0x00 6. "WAKE_EN,UART Wake-up Function Enable Control\nNote: when the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode" "0: UART wake-up function Disabled,1: UART wake-up function Enabled" bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Control\n" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x00 4. "RTO_IEN,RX Time-out Interrupt Enable Control\n" "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Control\n" "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Control\n" "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Control\n" "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Control\n" "0: RDA_INT Masked off,1: RDA_INT Enabled" group.long 0x08++0x03 line.long 0x00 "UA_FCR,UART FIFO Control Register" bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,?..." bitfld.long 0x00 8. "RX_DIS,Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled" newline bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (RDA_INT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable an interrupt will generated).\n" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..." bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles" "0: No effect,1: Reset the TX internal state machine and.." newline bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles" "0: No effect,1: Reset the RX internal state machine and.." group.long 0x0C++0x03 line.long 0x00 "UA_LCR,UART Line Control Register" bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break control Disabled,1: Break control Enabled" bitfld.long 0x00 5. "SPE,Stick Parity Enable Control\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.." newline bitfld.long 0x00 4. "EPE,Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x00 3. "PBE,Parity Bit Enable Control\n" "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x00 2. "NSB,Number of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.." bitfld.long 0x00 0.--1. "WLS,Word Length Selection\n" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit" group.long 0x10++0x03 line.long 0x00 "UA_MCR,UART Modem Control Register" rbitfld.long 0x00 13. "RTS_ST,RTS Pin Status (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n" "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic.." bitfld.long 0x00 9. "LEV_RTS,RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 664 and Figure 665 for UART function mode.\nNote2: Refer to Figure 669 and Figure 670 for RS-485 function mode" "0: RTS pin output is high level active,1: RTS pin output is low level active" newline bitfld.long 0x00 1. "RTS,RTS (Request-to-send) Signal Control\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is.." "0: RTS signal is active,1: RTS signal is inactive" group.long 0x14++0x03 line.long 0x00 "UA_MSR,UART Modem Status Register" bitfld.long 0x00 8. "LEV_CTS,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 663 for more information" "0: CTS pin input is high level active,1: CTS pin input is low level active" rbitfld.long 0x00 4. "CTS_ST,CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline bitfld.long 0x00 0. "DCTSF,Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: CTS input has not change state,1: CTS input has change state" group.long 0x18++0x03 line.long 0x00 "UA_FSR,UART FIFO Status Register" rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty" bitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty" newline rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty" rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote1: This bit is read only but can.." "0: No framing error is generated,1: Framing error is generated" newline rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit is read only but can be cleared by writing '1' to it (M05xxDN/DE Only).\nNote2: This bit is read only but.." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it" "0,1" newline bitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow" group.long 0x1C++0x03 line.long 0x00 "UA_ISR,UART Interrupt Status Register" rbitfld.long 0x00 15. "LIN_RX_BREAK_INT,LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.\n" "0: No LIN RX Break interrupt is generated,1: LIN RX Break interrupt is generated" rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated,1: buffer error interrupt is generated" newline rbitfld.long 0x00 12. "TOUT_INT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if RTO_IEN and TOUT_IF are both set to 1.\n" "0: No Time-out interrupt is generated,1: Time-out interrupt is generated" rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated" rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x00 7. "LIN_RX_BREAK_IF,LIN Bus RX Break Field Detected Flag\nThis bit is set when RX received LIN Break Field" "0: No LIN RX Break received,1: LIN RX Break received" newline rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" rbitfld.long 0x00 4. "TOUT_IF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x03 line.long 0x00 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit" hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n" group.long 0x24++0x03 line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Control\nNote1: Refer to the section 6.11.5.1 for more information.\nNote2: In IrDA function mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.." bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal 1\nNote1: Refer to the section 6.11.5.1 for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicated the baud rate divider" group.long 0x28++0x03 line.long 0x00 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x00 6. "INV_RX,Inverse RX Input Control\n" "0: No inversion,1: Inverse RX input signal" bitfld.long 0x00 5. "INV_TX,Inverse RX Output Control\n" "0: No inversion,1: Inverse TX output signal" newline bitfld.long 0x00 1. "TX_SELECT,IrDA Receiver Enable Control\n" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled" group.long 0x2C++0x03 line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode" bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Control\nThis bit is use to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode" "0: RS-485 address detection mode Disabled,1: RS-485 address detection mode Enabled" newline bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485_AAD or RS485_NMM operation mode" "0: RS-485 Auto Direction Operation Mode (AUD)..,1: RS-485 Auto Direction Operation Mode (AUD).." bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) Control\nNote: It cannot be active with RS485_NMM operation mode" "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.." newline bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).." bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Control\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break Mode Disabled,1: LIN TX Break Mode Enabled" newline bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Control \n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" bitfld.long 0x00 0.--3. "UA_LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x00 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x00 0.--1. "FUN_SEL,Function Select\nUART Controller function mode selection.\n" "0: UART function mode,1: LIN function mode,2: IrDA function mode,3: RS-485 function mode" tree.end repeat.end tree.end tree "WDT (Watchdog Timer Unit)" base ad:0x40004000 group.long 0x00++0x03 line.long 0x00 "WTCR,Watchdog Timer Control Register" bitfld.long 0x00 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 8.--10. "WTIS,Watchdog Timer Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\n" "0: 24 *TWDT,1: 26 *TWDT,2: 28 *TWDT,3: 210 *TWDT,4: 212 *TWDT,5: 214 *TWDT,6: 216 *TWDT,7: 218 *TWDT" newline bitfld.long 0x00 7. "WTE,Watchdog Timer Enable Control (Write Protect)\n" "0: WDT Disabled,1: WDT Enabled" bitfld.long 0x00 6. "WTIE,Watchdog Timer Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU.\n" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled" newline bitfld.long 0x00 5. "WTWKF,Watchdog Timer Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x00 4. "WTWKE,Watchdog Timer Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WTIF is generated to 1 and WTIE enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.." newline bitfld.long 0x00 3. "WTIF,Watchdog Timer Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred" bitfld.long 0x00 2. "WTRF,Watchdog Timer Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred" newline bitfld.long 0x00 1. "WTRE,Watchdog Timer Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: Fixed 1024 * TWDT.." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled" bitfld.long 0x00 0. "WTR,Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware" "0: No effect,1: Reset the internal 18-bit WDT up counter value" group.long 0x04++0x03 line.long 0x00 "WTCRALT,Watchdog Timer Alternative Control Register\n(M05xxDN/DE Only)" bitfld.long 0x00 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened software has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened" "0: Watchdog Timer Reset Delay Period is 1026 *..,1: Watchdog Timer Reset Delay Period is 130*..,2: Watchdog Timer Reset Delay Period is 18 *..,3: Watchdog Timer Reset Delay Period is 3 *.." tree.end tree "WWDT (WWDT Register Map)" base ad:0x40004100 wgroup.long 0x00++0x03 line.long 0x00 "WWDTRLD,Window Watchdog Timer Reload Counter Register" hexmask.long 0x00 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F" group.long 0x04++0x03 line.long 0x00 "WWDTCR,Window Watchdog Timer Control Register" bitfld.long 0x00 31. "DBGACK_WWDT,ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 16.--21. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window.\nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--11. "PERIODSEL,WWDT Counter Prescale Period Selection\n" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.." bitfld.long 0x00 1. "WWDTIE,WWDT Interrupt Enable Control\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU.\n" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled" newline bitfld.long 0x00 0. "WWDTEN,WWDT Enable Control\n" "0: WWDT counter is stopped,1: WWDT counter is starting counting" group.long 0x08++0x03 line.long 0x00 "WWDTSR,Window Watchdog Timer Status Register" bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred" bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches WINCMP value" rgroup.long 0x0C++0x03 line.long 0x00 "WWDTCVR,Window Watchdog Timer Counter Value Register" bitfld.long 0x00 0.--5. "WWDTCVAL,WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end autoindent.off newline