; -------------------------------------------------------------------------------- ; @Title: M030G On-Chip Peripherals ; @Props: Released ; @Author: PIW ; @Changelog: 2022-02-22 PIW ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: SVD generated based on: M030GAE.svd (ver. 1.0) ; @Core: Cortex-M0 ; @Chip: M030GGC1AE, M030GGD1AE, M030GTC1AE, M030GTD1AE, M031GGC2AE, M031GGD2AE, ; M031GTC2AE, M031GTD2AE ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perm030g.per 14354 2022-02-22 13:40:54Z kwisniewski $ config 16. 8. width 0x0B tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end autoindent.on center tree tree "ADC (ADC Register Map)" base ad:0x40043000 rgroup.long 0x00++0x03 line.long 0x00 "ADC_ADDR0,ADC Data Register 0" bitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC" repeat 16. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "29" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x70 ) group.long ($2+0x04)++0x03 line.long 0x00 "ADC_ADDR$1,ADC Data Register $1" rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC" repeat.end group.long 0x80++0x03 line.long 0x00 "ADC_ADCR,ADC Control Register" bitfld.long 0x00 31. "DMOF,Differential Input Mode Output Format\nIf differential input mode is enabled the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.." bitfld.long 0x00 12. "RESET,ADC RESET (Write Protect)\nIf user writes this bit the ADC analog macro will reset" "0,1" newline bitfld.long 0x00 11. "ADST,A/D Conversion Start or Calibration Start\nADST bit can be set to 1 from four sources: software external pin STADC BPWM trigger and Timer trigger" "0: Conversion stops and A/D converter enters..,1: Conversion or calibration starts" bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control\nNote: In Differential Input mode only the even number of the two corresponding channels needs to be enabled in ADCHER register" "0: Single-end analog input mode,1: Differential analog input mode" newline bitfld.long 0x00 9. "PTEN,PDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADDR0~15 ADDR29" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR0~15 ADDR29 Enabled" bitfld.long 0x00 8. "TRGEN,External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin BPWM trigger and Timer trigger" "0: External trigger Disabled,1: External trigger Enabled" newline bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge" bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits" "0: A/D conversion is started by external STADC pin,1: Timer0 ~ Timer5 overflow pulse trigger,2: A/D conversion is started by BPWM trigger,3: Reserved" newline bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode Control\n" "0: Single conversion,1: Burst conversion,2: Single-cycle Scan,3: Continuous Scan" bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" newline bitfld.long 0x00 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1" "0: A/D converter Disabled,1: A/D converter Enabled" group.long 0x84++0x03 line.long 0x00 "ADC_ADCHER,ADC Channel Enable Register" hexmask.long 0x00 0.--31. 1. "CHEN,Analog Input Channel Enable Control\nSet ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x88)++0x03 line.long 0x00 "ADC_ADCMPR$1,ADC Compare Register $1" hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)" bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register" "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled" newline bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3.--7. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,12: Channel 12 conversion result is selected to..,13: Channel 13 conversion result is selected to..,14: Channel 14 conversion result is selected to..,15: Channel 15 conversion result is selected to..,?,?,?,?,?,?,?,?,?,?,?,?,28: Floating detect channel conversion result is..,29: Band-gap voltage conversion result is..,?..." newline bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.." bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" newline bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled" repeat.end group.long 0x90++0x03 line.long 0x00 "ADC_ADSR0,ADC Status Register0" rbitfld.long 0x00 27.--31. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 24. "PWURDY,ADC Power-up Sequence Completed and Ready for Conversion (Read Only)" "0: ADC is not ready for conversion may be in..,1: ADC is ready for conversion" newline rbitfld.long 0x00 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1" "0,1" rbitfld.long 0x00 8. "VALIDF,Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1" "0,1" newline rbitfld.long 0x00 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register" "0: A/D converter is in idle state,1: A/D converter is busy at conversion" bitfld.long 0x00 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register this bit is set to 1 it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting" newline bitfld.long 0x00 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting" bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion" "0,1" rgroup.long 0x94++0x03 line.long 0x00 "ADC_ADSR1,ADC Status Register1" hexmask.long 0x00 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[29 15:0] are the mirror of the VALID bits in ADDR29[17] ADDR15[17]~ ADDR0[17]" rgroup.long 0x98++0x03 line.long 0x00 "ADC_ADSR2,ADC Status Register2" hexmask.long 0x00 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[29 15:0] are the mirror of the OVERRUN bit in ADDR29[16] ADDR15[16] ~ ADDR0[16]" group.long 0xA0++0x03 line.long 0x00 "ADC_ESMPCTL,ADC Extend Sample Time Control Register" hexmask.long.byte 0x00 0.--7. 1. "EXTSMPT,ADC Sampling Time Extend \nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.." group.long 0xA4++0x03 line.long 0x00 "ADC_CFDCTL,ADC Channel Floating Detect Control Register" bitfld.long 0x00 8. "FDETCHEN,Floating Detect Channel Enable Bit\nNote: if FDETCHEN is enabled internal channel is always turned on" "0: Floating Detect Channel Disabled,1: Floating Detect Channel Enabled" bitfld.long 0x00 1. "DISCHEN,Discharge Enable Bit\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are both enabled" "0: Channel discharge Disabled,1: Channel discharge Enabled" newline bitfld.long 0x00 0. "PRECHEN,Precharge Enable Bit\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are both enabled" "0: Channel precharge Disabled,1: Channel precharge Enabled" rgroup.long 0x100++0x03 line.long 0x00 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register" hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR15 and ADDR29 registers" group.long 0x180++0x03 line.long 0x00 "ADC_ADCALR,ADC Calibration Mode Register" bitfld.long 0x00 1. "CALIE,Calibration Interrupt Enable Bit\nIf calibration function is enabled and the calibration is finished CALIF bit will be asserted in the meanwhile if CALIE bit is set to 1 a calibration interrupt request is generated" "0: Calibration function Interrupt Disabled,1: Calibration function Interrupt Enabled" bitfld.long 0x00 0. "CALEN,Calibration Function Enable Bit\nNote: If chip is powered off calibration function should be executed again" "0: Calibration function Disabled,?..." group.long 0x184++0x03 line.long 0x00 "ADC_ADCALSTSR,ADC Calibration Status Register" bitfld.long 0x00 0. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished this flag will be set to 1" "0,1" tree.end tree "BPWM (BPWM Register Map)" base ad:0x4005B000 group.long 0x00++0x03 line.long 0x00 "BPWM_CTL0,BPWM Control Register 0" bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." newline bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." newline bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." newline bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" newline bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" newline bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" group.long 0x04++0x03 line.long 0x00 "BPWM_CTL1,BPWM Control Register 1" bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved" group.long 0x10++0x03 line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register" bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWM1_CLK,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,5: TIMER4 overflow,6: TIMER5 overflow,?..." group.long 0x14++0x03 line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register" hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler" group.long 0x20++0x03 line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register" bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running" group.long 0x24++0x03 line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register" bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H" group.long 0x30++0x03 line.long 0x00 "BPWM_PERIOD,BPWM Period Register" hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD" repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x50)++0x03 line.long 0x00 "BPWM_CMPDAT$1,BPWM Comparator Register $1" hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 are denoted as 6 independent BPWM_CH0~5 compared points" repeat.end rgroup.long 0x90++0x03 line.long 0x00 "BPWM_CNT,BPWM Counter Register" bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down counting,1: Counter is UP counting" hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter" group.long 0xB0++0x03 line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0" bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down counter type" "0: Do nothing,1: BPWM period point output Low,2: BPWM period point output High,3: BPWM period point output Toggle" bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down counter type" "0: Do nothing,1: BPWM period point output Low,2: BPWM period point output High,3: BPWM period point output Toggle" newline bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down counter type" "0: Do nothing,1: BPWM period point output Low,2: BPWM period point output High,3: BPWM period point output Toggle" bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down counter type" "0: Do nothing,1: BPWM period point output Low,2: BPWM period point output High,3: BPWM period point output Toggle" newline bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down counter type" "0: Do nothing,1: BPWM period point output Low,2: BPWM period point output High,3: BPWM period point output Toggle" bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter is operating in up-down counter type" "0: Do nothing,1: BPWM period point output Low,2: BPWM period point output High,3: BPWM period point output Toggle" newline bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle" bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle" newline bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle" bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle" newline bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle" bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle" group.long 0xB4++0x03 line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1" bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle" bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle" newline bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle" bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle" newline bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle" bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle" newline bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle" bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle" newline bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle" bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle" newline bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle" bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle" group.long 0xB8++0x03 line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register" bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.." bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.." newline bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.." bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.." newline bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.." bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.." group.long 0xBC++0x03 line.long 0x00 "BPWM_MSK,BPWM Mask Data Register" bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn" bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn" newline bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn" bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn" newline bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn" bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn" group.long 0xD4++0x03 line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register" bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled" bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled" newline bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled" bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled" newline bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled" bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled" group.long 0xD8++0x03 line.long 0x00 "BPWM_POEN,BPWM Output Enable Register" bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode" bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode" newline bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode" bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode" newline bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode" bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode" group.long 0xE0++0x03 line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register" bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" group.long 0xE8++0x03 line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register" bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" newline bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" newline bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" newline bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" newline bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" newline bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1" newline bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag\nThis bit is set by hardware when BPWM counter reaches BPWM_PERIOD software can write 1 to clear this bit to 0" "0,1" bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag\nThis bit is set by hardware when BPWM counter reaches 0 software can write 1 to clear this bit to 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "BPWM_DACTRGEN,BPWM Trigger DAC Enable Register" bitfld.long 0x00 29. "CDTRGE5,BPWM Compare Down Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.\n" "0: BPWM Compare Down count point trigger DAC..,1: BPWM Compare Down count point trigger DAC.." bitfld.long 0x00 28. "CDTRGE4,BPWM Compare Down Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.\n" "0: BPWM Compare Down count point trigger DAC..,1: BPWM Compare Down count point trigger DAC.." newline bitfld.long 0x00 27. "CDTRGE3,BPWM Compare Down Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.\n" "0: BPWM Compare Down count point trigger DAC..,1: BPWM Compare Down count point trigger DAC.." bitfld.long 0x00 26. "CDTRGE2,BPWM Compare Down Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.\n" "0: BPWM Compare Down count point trigger DAC..,1: BPWM Compare Down count point trigger DAC.." newline bitfld.long 0x00 25. "CDTRGE1,BPWM Compare Down Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.\n" "0: BPWM Compare Down count point trigger DAC..,1: BPWM Compare Down count point trigger DAC.." bitfld.long 0x00 24. "CDTRGE0,BPWM Compare Down Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.\n" "0: BPWM Compare Down count point trigger DAC..,1: BPWM Compare Down count point trigger DAC.." newline bitfld.long 0x00 21. "CUTRGE5,BPWM Compare Up Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.\nNote: This bit should keep at 0 when BPWM counter operating in down counter type" "0: BPWM Compare Up point trigger DAC function..,1: BPWM Compare Up point trigger DAC function.." bitfld.long 0x00 20. "CUTRGE4,BPWM Compare Up Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.\nNote: This bit should keep at 0 when BPWM counter operating in down counter type" "0: BPWM Compare Up point trigger DAC function..,1: BPWM Compare Up point trigger DAC function.." newline bitfld.long 0x00 19. "CUTRGE3,BPWM Compare Up Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.\nNote: This bit should keep at 0 when BPWM counter operating in down counter type" "0: BPWM Compare Up point trigger DAC function..,1: BPWM Compare Up point trigger DAC function.." bitfld.long 0x00 18. "CUTRGE2,BPWM Compare Up Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.\nNote: This bit should keep at 0 when BPWM counter operating in down counter type" "0: BPWM Compare Up point trigger DAC function..,1: BPWM Compare Up point trigger DAC function.." newline bitfld.long 0x00 17. "CUTRGE1,BPWM Compare Up Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.\nNote: This bit should keep at 0 when BPWM counter operating in down counter type" "0: BPWM Compare Up point trigger DAC function..,1: BPWM Compare Up point trigger DAC function.." bitfld.long 0x00 16. "CUTRGE0,BPWM Compare Up Count Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.\nNote: This bit should keep at 0 when BPWM counter operating in down counter type" "0: BPWM Compare Up point trigger DAC function..,1: BPWM Compare Up point trigger DAC function.." newline bitfld.long 0x00 8. "PTE,BPWM Period Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: BPWM period point trigger DAC function Disabled,1: BPWM period point trigger DAC function Enabled" bitfld.long 0x00 0. "ZTE,BPWM Zero Point Trigger DAC Enable Bits\nBPWM can trigger DAC to start action when BPWM counter down count to zero if this bit is set to1" "0: BPWM period point trigger DAC function Disabled,1: BPWM period point trigger DAC function Enabled" group.long 0xF8++0x03 line.long 0x00 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0" bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0: BPWM_CH3 Trigger EADC function Disabled,1: BPWM_CH3 Trigger EADC function Enabled" bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..." newline bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0: BPWM_CH2 Trigger EADC function Disabled,1: BPWM_CH2 Trigger EADC function Enabled" bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..." newline bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0: BPWM_CH1 Trigger EADC function Disabled,1: BPWM_CH1 Trigger EADC function Enabled" bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..." newline bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0: BPWM_CH0 Trigger EADC function Disabled,1: BPWM_CH0 Trigger EADC function Enabled" bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..." group.long 0xFC++0x03 line.long 0x00 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1" bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0: BPWM_CH5 Trigger EADC function Disabled,1: BPWM_CH5 Trigger EADC function Enabled" bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..." newline bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0: BPWM_CH4 Trigger EADC function Disabled,1: BPWM_CH4 Trigger EADC function Enabled" bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..." group.long 0x120++0x03 line.long 0x00 "BPWM_STATUS,BPWM Status Register" bitfld.long 0x00 21. "ADCTRG5,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.." bitfld.long 0x00 20. "ADCTRG4,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.." newline bitfld.long 0x00 19. "ADCTRG3,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.." bitfld.long 0x00 18. "ADCTRG2,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.." newline bitfld.long 0x00 17. "ADCTRG1,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.." bitfld.long 0x00 16. "ADCTRG0,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.." newline bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value" group.long 0x200++0x03 line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register" bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled" bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled" newline bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled" bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled" newline bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled" bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled" group.long 0x204++0x03 line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register" bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" newline bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" newline bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" newline bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled" bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled" newline bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled" bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled" newline bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled" bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled" rgroup.long 0x208++0x03 line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register" bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1" bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1" newline bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1" bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1" newline bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1" bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1" newline bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1" bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1" newline bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1" bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1" newline bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1" bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1" rgroup.long 0x20C++0x03 line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register" rgroup.long 0x210++0x03 line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register" group.long 0x214++0x03 line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register" group.long 0x218++0x03 line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register" group.long 0x21C++0x03 line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register" group.long 0x220++0x03 line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register" group.long 0x224++0x03 line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register" group.long 0x228++0x03 line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register" group.long 0x22C++0x03 line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register" group.long 0x230++0x03 line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register" group.long 0x234++0x03 line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register" group.long 0x238++0x03 line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register" group.long 0x250++0x03 line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register" bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..." bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..." group.long 0x254++0x03 line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register" bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." rgroup.long 0x304++0x03 line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer" hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register" rgroup.long 0x31C++0x03 line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register" group.long 0x320++0x03 line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register" group.long 0x324++0x03 line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register" group.long 0x328++0x03 line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register" group.long 0x32C++0x03 line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register" group.long 0x330++0x03 line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register" tree.end tree "CLK (CLK Register Map)" base ad:0x40000200 group.long 0x00++0x03 line.long 0x00 "CLK_PWRCTL,System Power-down Control Register" bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instantly or.." bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nWhen set by 'Power-down wake-up event' it indicates that resume from Power-down mode" "0,1" newline bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\n" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled" bitfld.long 0x00 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 512 clock cycles when chip works at internal.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled" newline bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Internal high speed RC oscillator (HIRC)..,1: Internal high speed RC oscillator (HIRC).." group.long 0x04++0x03 line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register" bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled" bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled" newline bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled" group.long 0x08++0x03 line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0" bitfld.long 0x00 28. "ADCCKEN,ADC Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled" bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled" newline bitfld.long 0x00 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled" bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled" newline bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled" bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled" newline bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled" bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled" newline bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled" bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled" newline bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\n" "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled" group.long 0x0C++0x03 line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1" bitfld.long 0x00 29. "TMR5CKEN,Timer5 Clock Enable Bit" "0: Timer5 clock Disabled,1: Timer5 clock Enabled" bitfld.long 0x00 28. "TMR4CKEN,Timer4 Clock Enable Bit" "0: Timer4 clock Disabled,1: Timer4 clock Enabled" newline bitfld.long 0x00 24. "MANCHCKEN,Manchester Codec Clock Enable Bit" "0: Manchester Codec clock Disabled,1: Manchester Codec clock Enabled" bitfld.long 0x00 19. "BPWM1CKEN,BPWM1 Clock Enable Bit" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled" newline bitfld.long 0x00 13. "DAC23CKEN,DAC23 Clock Enable Bit" "0: DAC23 clock Disabled,1: DAC23 clock Enabled" bitfld.long 0x00 12. "DAC01CKEN,DAC01 Clock Enable Bit" "0: DAC01 clock Disabled,1: DAC01 clock Enabled" group.long 0x10++0x03 line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0" bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect)\n" "?,?,?,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2" bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\n" "?,?,2: Clock source from PLL,?,?,?,?,7: Clock source from HIRC" group.long 0x14++0x03 line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1" bitfld.long 0x00 24.--26. "UART0SEL,UART0 Clock Source Selection" "?,1: Clock source from PLL,?,3: Clock source from internal high speed RC..,4: Clock source from PCLK0,5: Clock source from internal low speed RC..,?..." bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "?,?,2: Clock source from PCLK1,3: Clock source from external clock TM3 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." newline bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "?,?,2: Clock source from PCLK1,3: Clock source from external clock TM2 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "?,?,2: Clock source from PCLK0,3: Clock source from external clock T1 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." newline bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "?,?,2: Clock source from PCLK0,3: Clock source from external clock T0 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." bitfld.long 0x00 4.--6. "CLKOSEL,Clock Divider Clock Source Selection" "?,?,2: Clock source from HCLK,3: Clock source from internal high speed RC..,4: Clock source from internal low speed RC..,5: Clock source from internal high speed RC..,6: Clock source from PLL,?..." newline bitfld.long 0x00 2.--3. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)" "?,?,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.." bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\n" "?,?,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.." group.long 0x18++0x03 line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2" bitfld.long 0x00 20.--21. "ADCSEL,ADC Clock Source Selection" "?,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from internal high speed RC.." bitfld.long 0x00 16.--18. "TMR5SEL,TIMER5 Clock Source Selection" "?,?,2: Clock source from PCLK0,3: Clock source from external clock TM5 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." newline bitfld.long 0x00 12.--14. "TMR4SEL,TIMER4 Clock Source Selection" "?,?,2: Clock source from PCLK0,3: Clock source from external clock TM4 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." bitfld.long 0x00 9. "BPWM1SEL,BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL" "0: Clock source from PLL,1: Clock source from PCLK1" newline bitfld.long 0x00 4.--5. "SPI0SEL,SPI0 Clock Source Selection" "?,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from internal high speed RC.." group.long 0x20++0x03 line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0" hexmask.long.byte 0x00 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source" bitfld.long 0x00 8.--11. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x03 line.long 0x00 "CLK_PCLKDIV,APB Clock Divider Register" bitfld.long 0x00 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "CLK_PLLCTL,PLL Control Register" bitfld.long 0x00 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected" "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 16128 PLL source clock.." bitfld.long 0x00 18. "OE,PLL OE Pin Control (Write Protect)\nNote: This bit is write protected" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low" newline bitfld.long 0x00 17. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN" bitfld.long 0x00 16. "PD,Power-down Mode (Write Protect)\nIf setting the PDEN bit to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.\nNote: This bit is write protected" "0: PLL is in normal mode,1: PLL is in Power-down mode (default)" newline bitfld.long 0x00 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" "0,1,2,3" bitfld.long 0x00 9.--13. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" rgroup.long 0x50++0x03 line.long 0x00 "CLK_STATUS,Clock Status Monitor Register" bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure" bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: Internal high speed RC oscillator (HIRC)..,1: Internal high speed RC oscillator (HIRC).." newline bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: Internal low speed RC oscillator (LIRC) clock..,1: Internal low speed RC oscillator (LIRC) clock.." bitfld.long 0x00 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled" group.long 0x60++0x03 line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register" bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.." bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled" newline bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "CRC (CRC Register Map)" base ad:0x40031000 group.long 0x00++0x03 line.long 0x00 "CRC_CTL,CRC Control Register" bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode" bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..." newline bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled" bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled" newline bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled" bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.." newline bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.." bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled" group.long 0x04++0x03 line.long 0x00 "CRC_DAT,CRC Write Data Register" hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.." group.long 0x08++0x03 line.long 0x00 "CRC_SEED,CRC Seed Register" hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])" rgroup.long 0x0C++0x03 line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register" hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result" group.long 0x10++0x03 line.long 0x00 "CRC_POLYNOMIAL,CRC Polynomial Register" hexmask.long 0x00 0.--31. 1. "POLYNOMIAL,CRC Polynomial Value Results\nThis field indicates the value of CRC polynomial" tree.end tree "DAC (DAC Register Map)" tree "DAC" base ad:0x40047000 group.long 0x00++0x03 line.long 0x00 "DAC0_CTL,DAC0 Control Register" bitfld.long 0x00 24. "RETEN,DAC Reset Retention Select (Write Protect)\n" "0: DAC controller registers reset by POR NRESET..,1: DAC controller registers reset by POR LVR BOD.." bitfld.long 0x00 16. "GRPEN,DAC Group Mode Enable Bit" "0: DAC0 and DAC1 are not grouped,1: DAC0 and DAC1 are grouped" newline bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?..." bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger" newline bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enabled Bit" "0: Right alignment,1: Left alignment" bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled" newline bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: Timer 2 trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 3 trigger,5: Timer 4 trigger,6: BPWM 1 trigger,7: Timer 5 trigger" bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled" newline bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled" bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled" newline bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled" bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled" group.long 0x04++0x03 line.long 0x00 "DAC0_SWTRG,DAC0 Software Trigger Control Register" bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled" group.long 0x08++0x03 line.long 0x00 "DAC0_DAT,DAC0 Data Holding Register" hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output" rgroup.long 0x0C++0x03 line.long 0x00 "DAC0_DATOUT,DAC0 Data Output Register" hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC0_DAT register and user cannot write it directly" group.long 0x10++0x03 line.long 0x00 "DAC0_STATUS,DAC0 Status Register" rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion" bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: Write 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred" newline bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish" group.long 0x14++0x03 line.long 0x00 "DAC0_TCTL,DAC0 Timing Control Register" hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Conversion Cycles \nUser software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion setting time.." group.long 0x1C++0x03 line.long 0x00 "DAC0_ADGCTL,DAC0 Auto Data Generator Control Register" bitfld.long 0x00 2.--3. "SAMPSEL,Sample Points Step Selection" "0: No samples,1: 8 sample points per MANCH_TXD carrier cycle,2: 16 sample points per MANCH_TXD carrier cycle,3: 32 sample points per MANCH_TXD carrier cycle" bitfld.long 0x00 1. "CPOSEL,Carrier Polarity Selection" "0: Auto data update for DAC when MANCH_TXD data..,1: Auto data update for DAC when MANCH_TXD data.." newline bitfld.long 0x00 0. "AUTOEN,DAC Auto Data Generation Mode Enable Bit" "0: DAC auto data generation mode Disabled,1: DAC auto data generation mode Enabled" group.long 0x40++0x03 line.long 0x00 "DAC1_CTL,DAC1 Control Register" bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?..." bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger" newline bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enable Control" "0: Right alignment,1: Left alignment" bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled" newline bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: Timer 2 trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 3 trigger,5: Timer 4 trigger,6: BPWM 1 trigger,7: Timer 5 trigger" bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled" newline bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled" bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled" newline bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled" bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled" group.long 0x44++0x03 line.long 0x00 "DAC1_SWTRG,DAC1 Software Trigger Control Register" bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically Reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled" group.long 0x48++0x03 line.long 0x00 "DAC1_DAT,DAC1 Data Holding Register" hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output" rgroup.long 0x4C++0x03 line.long 0x00 "DAC1_DATOUT,DAC1 Data Output Register" hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC1_DAT register and user cannot write it directly" group.long 0x50++0x03 line.long 0x00 "DAC1_STATUS,DAC1 Status Register" rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for the next conversion,1: DAC is busy in conversion" bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: Write 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred" newline bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finished" group.long 0x54++0x03 line.long 0x00 "DAC1_TCTL,DAC1 Timing Control Register" hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Conversion Cycles \nUser software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion settling time.." repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x60)++0x03 line.long 0x00 "DAC_ADCTL$1,DAC Auto Data Control Register $1" hexmask.long.word 0x00 0.--11. 1. "AUTODATA,Data Input of Auto Data Generation Function\nUser software needs to write appropriate data value to these bits for DAC auto data generation" repeat.end repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA0)++0x03 line.long 0x00 "DAC_ADCTL$1,DAC Auto Data Control Register $1" hexmask.long.word 0x00 0.--11. 1. "AUTODATA,Data Input of Auto Data Generation Function\nUser software needs to write appropriate data value to these bits for DAC auto data generation" repeat.end tree.end tree "DAC2" base ad:0x4004B000 group.long 0x00++0x03 line.long 0x00 "DAC2_CTL,DAC2 Control Register" bitfld.long 0x00 24. "RETEN,DAC Reset Retention Select (Write Protect)\n" "0: DAC controller registers reset by POR NRESET..,1: DAC controller registers reset by POR LVR BOD.." bitfld.long 0x00 16. "GRPEN,DAC Group Mode Enable Bit" "0: DAC2 and DAC3 are not grouped,1: DAC2 and DAC3 are grouped" newline bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?..." bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger" newline bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enabled Bit" "0: Right alignment,1: Left alignment" bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled" newline bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: Timer 2 trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 3 trigger,5: Timer 4 trigger,6: BPWM 1 trigger,7: Timer 5 trigger" bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled" newline bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled" bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled" newline bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled" bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled" group.long 0x04++0x03 line.long 0x00 "DAC2_SWTRG,DAC2 Software Trigger Control Register" bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled" group.long 0x08++0x03 line.long 0x00 "DAC2_DAT,DAC2 Data Holding Register" hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output" rgroup.long 0x0C++0x03 line.long 0x00 "DAC2_DATOUT,DAC2 Data Output Register" hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC2_DAT register and user cannot write it directly" group.long 0x10++0x03 line.long 0x00 "DAC2_STATUS,DAC2 Status Register" rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion" bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: Write 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred" newline bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish" group.long 0x14++0x03 line.long 0x00 "DAC2_TCTL,DAC2 Timing Control Register" hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Conversion Cycles \nUser software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion setting time.." group.long 0x40++0x03 line.long 0x00 "DAC3_CTL,DAC3 Control Register" bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?..." bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger" newline bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enable Control" "0: Right alignment,1: Left alignment" bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled" newline bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: Timer 2 trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 3 trigger,5: Timer 4 trigger,6: BPWM 1 trigger,7: Timer 5 trigger" bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled" newline bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled" bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled" newline bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled" bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled" group.long 0x44++0x03 line.long 0x00 "DAC3_SWTRG,DAC3 Software Trigger Control Register" bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled" group.long 0x48++0x03 line.long 0x00 "DAC3_DAT,DAC3 Data Holding Register" hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output" rgroup.long 0x4C++0x03 line.long 0x00 "DAC3_DATOUT,DAC3 Data Output Register" hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC3_DAT register and user cannot write it directly" group.long 0x50++0x03 line.long 0x00 "DAC3_STATUS,DAC3 Status Register" rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for the next conversion,1: DAC is busy in conversion" bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: Write 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred" newline bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finished" group.long 0x54++0x03 line.long 0x00 "DAC3_TCTL,DAC3 Timing Control Register" hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Conversion Cycles \nUser software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion settling time.." tree.end tree.end tree "FMC (FMC Register Map)" base ad:0x4000C000 group.long 0x00++0x03 line.long 0x00 "FMC_ISPCTL,ISP Control Register" bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when user triggers ISPGO (FMC_ISPTRG[0]) and meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nCode is executed from APROM and tries to write APROM.." "0,1" bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected" "0: LDROM cannot be updated,1: LDROM can be updated" newline bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: CONFIG cannot be updated,1: CONFIG can be updated" bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.." newline bitfld.long 0x00 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: SPROM cannot be updated,1: SPROM can be updated" bitfld.long 0x00 1. "BS,Boot Selection (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM" "0: Booting from APROM,1: Booting from LDROM" newline bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: ISP function Disabled,1: ISP function Enabled" group.long 0x04++0x03 line.long 0x00 "FMC_ISPADDR,ISP Address Register" hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThis chip is equipped with embedded Flash" group.long 0x08++0x03 line.long 0x00 "FMC_ISPDAT,ISP Data Register" hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation" group.long 0x0C++0x03 line.long 0x00 "FMC_ISPCMD,ISP Command Register" hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP CMD\nISP command table is shown below:\nThe other commands are invalid" group.long 0x10++0x03 line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register" bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished" "0: ISP operation is finished,1: ISP is progressed" rgroup.long 0x14++0x03 line.long 0x00 "FMC_DFBA,Data Flash Base Address" hexmask.long 0x00 0.--31. 1. "DFBA,Data Flash Base Address (Read Only)\nThis register indicates Data Flash start address.\nThe Data Flash is shared with APROM" group.long 0x18++0x03 line.long 0x00 "FMC_FTCTL,Flash Access Time Control Register" bitfld.long 0x00 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\nThis chip supports adjustable Flash access timing to optimize the Flash access cycles in different system working frequency.\nFor 32/64 Kbytes Flash:\nNote: This bit is write-protected" "0: Frequency is less than or equal to 48 MHz,1: Frequency is less than or equal to 24 MHz,?,?,?,5: Frequency is less than or equal to 72 MHz,?..." group.long 0x40++0x03 line.long 0x00 "FMC_ISPSTS,ISP Status Register" bitfld.long 0x00 31. "SCODE,Security Code Active Flag\nThis bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation" "0: SPROM secured code is inactive,1: SPROM secured code is active" hexmask.long.tbyte 0x00 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF} except SPROM.\nVECMAP [18:12] should be 0" newline bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when user triggers ISPGO (FMC_ISPTRG[0]) and meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nCode is executed from APROM and tries to write APROM.." "0,1" rbitfld.long 0x00 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened" "0: LDROM with IAP mode,1: LDROM without IAP mode,2: APROM with IAP mode,3: APROM without IAP mode" newline rbitfld.long 0x00 0. "ISPBUSY,ISP BUSY (Read Only)" "0: ISP operation is finished,1: ISP operation is busy" tree.end tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)" base ad:0x40004000 group.long 0x00++0x03 line.long 0x00 "PA_MODE,PA I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x04++0x03 line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x08++0x03 line.long 0x00 "PA_DOUT,PA Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x0C++0x03 line.long 0x00 "PA_DATMSK,PA Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x10++0x03 line.long 0x00 "PA_PIN,PA Pin Value" bitfld.long 0x00 15. "PIN15,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 14. "PIN14,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 13. "PIN13,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 12. "PIN12,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 11. "PIN11,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 10. "PIN10,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 9. "PIN9,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 8. "PIN8,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 7. "PIN7,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 6. "PIN6,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 5. "PIN5,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 4. "PIN4,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 3. "PIN3,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 2. "PIN2,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline bitfld.long 0x00 1. "PIN1,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" bitfld.long 0x00 0. "PIN0,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" group.long 0x14++0x03 line.long 0x00 "PA_DBEN,PA De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x18++0x03 line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x1C++0x03 line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0x20++0x03 line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0x30++0x03 line.long 0x00 "PA_PUSEL,PA Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 14. "PUSEL14,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 13. "PUSEL13,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 12. "PUSEL12,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 11. "PUSEL11,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 10. "PUSEL10,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 9. "PUSEL9,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 8. "PUSEL8,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 7. "PUSEL7,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 6. "PUSEL6,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 5. "PUSEL5,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 4. "PUSEL4,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 3. "PUSEL3,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 2. "PUSEL2,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 1. "PUSEL1,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 0. "PUSEL0,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" group.long 0x40++0x03 line.long 0x00 "PB_MODE,PB I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x44++0x03 line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x48++0x03 line.long 0x00 "PB_DOUT,PB Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x4C++0x03 line.long 0x00 "PB_DATMSK,PB Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" group.long 0x50++0x03 line.long 0x00 "PB_PIN,PB Pin Value" rbitfld.long 0x00 15. "PIN15,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 14. "PIN14,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 13. "PIN13,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 12. "PIN12,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 11. "PIN11,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 10. "PIN10,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 9. "PIN9,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 8. "PIN8,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 7. "PIN7,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 6. "PIN6,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 5. "PIN5,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 4. "PIN4,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 3. "PIN3,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 2. "PIN2,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 1. "PIN1,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 0. "PIN0,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" group.long 0x54++0x03 line.long 0x00 "PB_DBEN,PB De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x58++0x03 line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x5C++0x03 line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0x60++0x03 line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0x70++0x03 line.long 0x00 "PB_PUSEL,PB Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 14. "PUSEL14,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 13. "PUSEL13,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 12. "PUSEL12,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 11. "PUSEL11,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 10. "PUSEL10,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 9. "PUSEL9,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 8. "PUSEL8,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 7. "PUSEL7,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 6. "PUSEL6,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 5. "PUSEL5,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 4. "PUSEL4,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 3. "PUSEL3,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 2. "PUSEL2,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 1. "PUSEL1,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 0. "PUSEL0,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" group.long 0x80++0x03 line.long 0x00 "PC_MODE,PC I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x84++0x03 line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x88++0x03 line.long 0x00 "PC_DOUT,PC Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x8C++0x03 line.long 0x00 "PC_DATMSK,PC Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" group.long 0x90++0x03 line.long 0x00 "PC_PIN,PC Pin Value" rbitfld.long 0x00 15. "PIN15,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 14. "PIN14,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 13. "PIN13,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 12. "PIN12,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 11. "PIN11,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 10. "PIN10,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 9. "PIN9,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 8. "PIN8,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 7. "PIN7,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 6. "PIN6,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 5. "PIN5,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 4. "PIN4,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 3. "PIN3,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 2. "PIN2,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 1. "PIN1,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 0. "PIN0,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" group.long 0x94++0x03 line.long 0x00 "PC_DBEN,PC De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x98++0x03 line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x9C++0x03 line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0xA0++0x03 line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0xB0++0x03 line.long 0x00 "PC_PUSEL,PC Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 14. "PUSEL14,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 13. "PUSEL13,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 12. "PUSEL12,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 11. "PUSEL11,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 10. "PUSEL10,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 9. "PUSEL9,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 8. "PUSEL8,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 7. "PUSEL7,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 6. "PUSEL6,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 5. "PUSEL5,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 4. "PUSEL4,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 3. "PUSEL3,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 2. "PUSEL2,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 1. "PUSEL1,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 0. "PUSEL0,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" group.long 0x140++0x03 line.long 0x00 "PF_MODE,PF I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A B C F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x144++0x03 line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A B C F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x148++0x03 line.long 0x00 "PF_DOUT,PF Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A B C F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x14C++0x03 line.long 0x00 "PF_DATMSK,PF Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A B C F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" group.long 0x150++0x03 line.long 0x00 "PF_PIN,PF Pin Value" rbitfld.long 0x00 15. "PIN15,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 14. "PIN14,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 13. "PIN13,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 12. "PIN12,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 11. "PIN11,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 10. "PIN10,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 9. "PIN9,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 8. "PIN8,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 7. "PIN7,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 6. "PIN6,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 5. "PIN5,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 4. "PIN4,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 3. "PIN3,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 2. "PIN2,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" newline rbitfld.long 0x00 1. "PIN1,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" rbitfld.long 0x00 0. "PIN0,Port A B C F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1" group.long 0x154++0x03 line.long 0x00 "PF_DBEN,PF De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A B C F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x158++0x03 line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A B C F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x15C++0x03 line.long 0x00 "PF_INTEN,PF Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A B C F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A B C F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0x160++0x03 line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A B C F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0x170++0x03 line.long 0x00 "PF_PUSEL,PF Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 14. "PUSEL14,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 13. "PUSEL13,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 12. "PUSEL12,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 11. "PUSEL11,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 10. "PUSEL10,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 9. "PUSEL9,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 8. "PUSEL8,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 7. "PUSEL7,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 6. "PUSEL6,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 5. "PUSEL5,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 4. "PUSEL4,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 3. "PUSEL3,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 2. "PUSEL2,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" newline bitfld.long 0x00 1. "PUSEL1,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" bitfld.long 0x00 0. "PUSEL0,Port A B C F Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up Disabled,1: Px.n pull-up Enabled" group.long 0x440++0x03 line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control Register" bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.." bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4.." newline bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks" group.long 0x444++0x03 line.long 0x00 "GPIO_RET,GPIO Retention Control Register" bitfld.long 0x00 0. "RETEN,GPIO Reset Retention Select (Write Protect)\nNote: This bit is write protected" "0: GPIO registers can be reset by POR NRESET WDT..,1: GPIO registers can be reset only by POR LVR.." group.long 0x800++0x03 line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x804++0x03 line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x808++0x03 line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x80C++0x03 line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x810++0x03 line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x814++0x03 line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x818++0x03 line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x81C++0x03 line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x820++0x03 line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x824++0x03 line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x828++0x03 line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x82C++0x03 line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x830++0x03 line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x834++0x03 line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x838++0x03 line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x83C++0x03 line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x840++0x03 line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x844++0x03 line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x848++0x03 line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x84C++0x03 line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x850++0x03 line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x854++0x03 line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x858++0x03 line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x85C++0x03 line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x860++0x03 line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x864++0x03 line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x868++0x03 line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x86C++0x03 line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x870++0x03 line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x874++0x03 line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x878++0x03 line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x87C++0x03 line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x880++0x03 line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x884++0x03 line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x888++0x03 line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x88C++0x03 line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x890++0x03 line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x894++0x03 line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x898++0x03 line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x89C++0x03 line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8A0++0x03 line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8A4++0x03 line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8A8++0x03 line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8AC++0x03 line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8B0++0x03 line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8B4++0x03 line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8B8++0x03 line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x940++0x03 line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x944++0x03 line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x948++0x03 line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x94C++0x03 line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x950++0x03 line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x954++0x03 line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x958++0x03 line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x95C++0x03 line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x960++0x03 line.long 0x00 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x964++0x03 line.long 0x00 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x968++0x03 line.long 0x00 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x96C++0x03 line.long 0x00 "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x970++0x03 line.long 0x00 "PF12_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x974++0x03 line.long 0x00 "PF13_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x978++0x03 line.long 0x00 "PF14_PDIO,GPIO PF.n Pin Data Input/Output Register" group.long 0x97C++0x03 line.long 0x00 "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register" tree.end tree "I2C (Inter-Integrated Circuit)" repeat 2. (list 0. 1.) (list ad:0x40080000 ad:0x40081000) tree "I2C$1" base $2 group.long 0x00++0x03 line.long 0x00 "I2C_CTL0,I2C Control Register 0" bitfld.long 0x00 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address is matched with read command.\nNote: This bit is cleared by writing 1 to it" "0,1" bitfld.long 0x00 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count is equal to DPBITSEL setting" "0,1" newline bitfld.long 0x00 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled" bitfld.long 0x00 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled" newline bitfld.long 0x00 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal..,2: When I2C is transfer data and bit count equal..,3: When I2C is transfer data and bit count equal.." bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" newline bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled" bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 will enter Master mode and the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1" newline bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO will transmit a STOP condition to bus and then I2C controller will check the bus condition if a STOP condition is detected" "0,1" bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1" newline bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1" group.long 0x04++0x03 line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0" hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode" bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" group.long 0x08++0x03 line.long 0x00 "I2C_DAT,I2C Data Register" hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port" rgroup.long 0x0C++0x03 line.long 0x00 "I2C_STATUS0,I2C Status Register 0" hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status" group.long 0x10++0x03 line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register" hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4" group.long 0x14++0x03 line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register" bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled" newline bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1" repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 ) group.long ($2+0x18)++0x03 line.long 0x00 "I2C_ADDR$1,I2C Slave Address Register $1" hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode" bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" repeat.end repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x24)++0x03 line.long 0x00 "I2C_ADDRMSK$1,I2C Slave Address Mask Register $1" hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask registers" repeat.end group.long 0x3C++0x03 line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register" bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not cleared" "0: I2C holds bus after wake-up,1: I2C does not hold bus after wake-up" bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" group.long 0x40++0x03 line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register" rbitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit" "0: Write command be record on the address match..,1: Read command be record on the address match.." bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF" "0: The ACK bit cycle of address match frame is..,1: The ACK bit cycle of address match frame is.." newline bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1" group.long 0x44++0x03 line.long 0x00 "I2C_CTL1,I2C Control Register 1" bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.." bitfld.long 0x00 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer" "0: Two-level buffer Disabled,1: Two-level buffer Enabled" newline bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA" bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" group.long 0x48++0x03 line.long 0x00 "I2C_STATUS1,I2C Status Register 1" rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicate that a communication is in progress on the bus" "0: The bus is idle (both SCLK and SDA High),1: The bus is busy" group.long 0x4C++0x03 line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode" hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs" tree.end repeat.end tree.end tree "MANCHESTER (Manchester Register Map)" base ad:0x400BC000 group.long 0x00++0x03 line.long 0x00 "MANCH_CTL,Manchester Function Control Register" abitfld.long 0x00 20.--31. "BITREFDIV,Manchester Bit Reference Clock Divider\nThe bits field indicates the reference clock frequency for Manchester bit sample.\nFor example if the PCLK0 is 72 MHz the BITREFDIV can be set as 0x23 (BITREFDIV+1)" "0x001=1: The BITREFDIV minimum value is 0x03.\n,0x002=2: It is suggested that minimize the.." bitfld.long 0x00 19. "MANCHTEN,Manchester Transmit Enable" "0: Manchester Transmit Disabled,1: Manchester Transmit Enabled" newline bitfld.long 0x00 17. "MTXE2TEN,Manchester Coded Edge Output Enable Bit" "0: Manchester coded edge signal outputs to Timer..,1: Manchester coded edge signal outputs to Timer.." bitfld.long 0x00 12.--14. "DEGDIV,Manchester Deglitch Clock Divider\nThe bits field indicates the deglitched clock frequency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "CRBNULEN,Current Received Bit Clock Number Auto Upload Enable Bit" "0: CRBITNUM is not updated in each received byte..,1: CRBITNUM is updated in each received byte.." bitfld.long 0x00 10. "RBNULEN,Received Bit Clock Number Auto Upload Enable Bit" "0: RBITNUM is not updated by CRBITNUM at each..,1: RBITNUM is updated by CRBITNUM at each data.." newline bitfld.long 0x00 9. "RXINV,Receive Signal Invert" "0: The received data is not inverted,1: The received data is inverted" bitfld.long 0x00 8. "TXINV,Transmit Signal Invert" "0: The transmitting data is not inverted,1: The transmitting data is inverted" newline bitfld.long 0x00 6. "LSB,Manchester Code LSB First\nNote: This bit should be configured before MODSEL" "0: Manchester code is MSB first,1: Manchester code is LSB first" bitfld.long 0x00 5. "MECT,Manchester Encoding Type\nLevel" "0: G.E Thomas format,1: IEEE 802.3 format" newline bitfld.long 0x00 2.--4. "DEGSEL,Received Deglitch Selection\nThe bits field is used to define how much width of glitch would be filtered" "0: disable to the Manchester deglitch selection,1: Filter the glitches that the width is 0.25us..,2: Filter the glitches that the width is 0.50us..,3: Filter the glitches that the width is 0.75us..,4: Filter the glitches that the width is 1.00us..,5: Filter the glitches that the width is 1.25us..,?..." bitfld.long 0x00 0.--1. "MODESEL,Manchester Mode Selection\nNote: All the change of function setting shall be during Manchester Controller disabled" "0: Manchester function is disabled,1: Mode 1 modulation signal format is selected,2: Mode 2 modulation signal format is selected,3: The other modulation signal format is selected" group.long 0x04++0x03 line.long 0x00 "MANCH_PREAM,Manchester Preamble Register" abitfld.long 0x00 24.--31. "FMTNUM,Modulation Format Transmit Number\nThe bits field defines the number of transmitted byte number in current selected mode.\nIf MODESEL is 0x1 the FMTNUM will be forced as 0x1E.\nIf MODESEL is 0x2 the FMTNUM will be forced as 0x40.\nIf MODESEL is.." "0x01=1: If FMTNUM is 0x00 which indicates the..,0x02=2: The value of FMTNUM must be greater than..,0x03=3: The minimum value of FMTNUM must be.." hexmask.long.byte 0x00 16.--23. 1. "IDLEPAT,Idle Pattern\nThe bits field indicates the bus idle pattern.\nIf it is 0x00 it indicates that the bus idle default is low.\nIf it is 0xFF it indicates that the bus idle default is high.\nExcept the bus idle state is LOW the bits field must be.." newline bitfld.long 0x00 8.--12. "PRENUM,Preamble Number\nThe bits field defines the number of preamble in the modulation signal format.\n00000: means there are 32 preamble patterns.\n00001: means there is 1 preamble pattern.\n00010: means there are 2 preamble patterns.\n00011: means.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble Format\nThe bits field defines the preamble pattern in the modulation signal format.\nIf MODESEL is 2'b10 the PREAMBLE will be set as 0x7E" group.long 0x0C++0x03 line.long 0x00 "MANCH_FIFOCTL,Manchester FIFO Control Register" rbitfld.long 0x00 16.--18. "MTXFCNT,Manchester Transmit Encoded FIFO Count (Read Only)\nThe bits field indicates the current counter number of transmitted encoded FIFO for encoded data" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 12.--14. "RXFCNT,Received FIFO Count (Read Only)\nThe bits field indicates the current counter number of received FIFO for decoded data" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 8.--10. "TXFCNT,Transmitted FIFO Count (Read Only)\nThe bits field indicates the current counter number of transmitted FIFO for transmitting data" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. "RXCLR,Received FIFO Clear\nNote: The received control includes the FIFO and receive state machine" "0: Received control is not cleared,1: Received control is cleared" newline bitfld.long 0x00 0. "TXCLR,Transmit FIFO Clear" "0: Both of Transmit FIFO and Manchester Transmit..,1: Both of Transmit FIFO and Manchester Transmit.." group.long 0x10++0x03 line.long 0x00 "MANCH_DMAC,Manchester DMA Control Register" bitfld.long 0x00 2. "RXDMAEN,Received DMA Enable Bit" "0: Received DMA Disabled,1: Received DMA Enabled" bitfld.long 0x00 1. "TXDMAEN,Transmit DMA Enable Bit" "0: Transmit DMA Disabled,1: Transmit DMA Enabled" newline bitfld.long 0x00 0. "MTXDMAEN,Manchester Code Transmit DMA Enable Bit" "0: Manchester Code Transmit DMA Disabled,1: Manchester Code Transmit DMA Enabled" group.long 0x14++0x03 line.long 0x00 "MANCH_INTEN,Manchester Interrupt Enable Register" bitfld.long 0x00 7. "IDLERRIE,IDLE Pattern Error Interrupt Enable Bit" "0: The Idle pattern error detected interrupt..,1: The Idle pattern error detected interrupt.." bitfld.long 0x00 4. "BITERRIE,Bit Detect Error Interrupt Enable Bit" "0: The Manchester bit error detected interrupt..,1: The Manchester bit error detected interrupt.." newline bitfld.long 0x00 3. "RXOVERIE,Receive FIFO Overflow Interrupt Enable Bit" "0: Receive FIFO overflow interrupt Disabled,1: Receive FIFO overflow interrupt Enabled" bitfld.long 0x00 2. "RXDONEIE,Receive Frame Done Interrupt Enable Bit" "0: Receive frame done interrupt Disabled,1: Receive frame done interrupt Enabled" newline bitfld.long 0x00 0. "TXDONEIE,Transmit Done Interrupt Enable Bit" "0: Transmit frame done interrupt Disabled,1: Transmit frame done interrupt Enabled" group.long 0x18++0x03 line.long 0x00 "MANCH_STS,Manchester Status Register" bitfld.long 0x00 31. "RXBUSY,Receive Busy Flag" "0: The received bus is not busy,1: The received bus is busy" hexmask.long.byte 0x00 16.--23. 1. "RXCNT,Receive Frame Data Current Count" newline bitfld.long 0x00 15. "MTXFULL,Manchester Transmit Encoded FIFO Full" "0: The Manchester transmit encoded FIFO is not..,1: The Manchester transmit encoded FIFO is full" bitfld.long 0x00 14. "MTXEMPTY,Manchester Transmit Encoded FIFO Empty" "0: The Manchester transmit encoded FIFO is not..,1: The Manchester transmit encoded FIFO is empty" newline bitfld.long 0x00 11. "RXFULL,Received FIFO Full" "0: The received FIFO is not full,1: The received FIFO is full" bitfld.long 0x00 10. "RXEMPTY,Received FIFO Empty" "0: The received FIFO is not empty,1: The received FIFO is empty" newline bitfld.long 0x00 9. "TXFULL,Transmit FIFO Full" "0: The transmit FIFO is not full,1: The transmit FIFO is full" bitfld.long 0x00 8. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty" newline bitfld.long 0x00 7. "IDLERR,IDLE Error\nNote: This bit can be cleared by writing 1 to it" "0: The receive Idle pattern error is not detected,1: The receive Idle pattern error is detected" bitfld.long 0x00 6. "TXUNDER,Transmit FIFO Underrun\nNote: This bit can be cleared by writing 1 to it" "0: The transmit FIFO is not underrun,1: The transmit FIFO is underrun" newline bitfld.long 0x00 5. "PRENERR,Preamble Number Error\nNote: This bit can be cleared by writing 1 to it" "0: The receive preamble number error is not..,1: The receive preamble number error is detected" bitfld.long 0x00 4. "BITERR,Manchester Bit Error\nNote: This bit can be cleared by writing 1 to it" "0: The Manchester bit error is not detected,1: The Manchester bit error is detected" newline bitfld.long 0x00 3. "RXOVER,Receive FIFO Overflow\nNote: This bit can be cleared by writing 1 to it" "0: The receive FIFO is not overflow,1: The receive FIFO is overflow" bitfld.long 0x00 2. "RXDONE,Receive Frame Done\nNote: This bit can be cleared by writing 1 to it" "0: Receive frame is not done,1: Receive frame is done" newline bitfld.long 0x00 0. "TXDONE,Transmit Frame Done\nNote: When the MANCHTEN is set this bit will keep 0 until the data frame transmission is done" "0: Transmit frame is not done,1: Transmit frame is done" group.long 0x1C++0x03 line.long 0x00 "MANCH_BITCNT,Manchester Bit Count Register" bitfld.long 0x00 24.--26. "RBERRTN,Manchester Receive Bit Error Tolerance Number \nThe bits field indicates the tolerance range of RBITNUM for received bit to detect the bit error event" "0: 1/4 RBITNUM as the bit error tolerance,1: 1/8 RBITNUM as the bit error tolerance,2: 1/16 RBITNUM as the bit error tolerance,3: 1/32 RBITNUM as the bit error tolerance,4: 1/64 RBITNUM as the bit error tolerance,5: 1/128 RBITNUM as the bit error tolerance,?..." hexmask.long.byte 0x00 16.--23. 1. "CRBITNUM,Manchester Current Receive Reference Frequency Number per Bit (Read Only)\nThe bits field indicates the current number of reference frequency (Bit_Ref_Clock) for each received bit" newline abitfld.long 0x00 8.--15. "RBITNUM,Manchester Receive Reference Clock Number per Bit \nThe bits field indicates the number of reference clock (Bit_Ref_Clock) for received bit.\nIf there is not BITERR event user can refer to the CRBITNUM to revise the RBITNUM.\n" "0x01=1: The value of this bits field cannot be..,0x02=2: The bits can be updated at the start of..,0x03=3: It is suggested that the RBITNUM value.." abitfld.long 0x00 0.--7. "TBITNUM,Manchester Transmit Reference Clock Number per Bit \nThe bits field indicates the number of reference clock (Bit_Ref_Clock) for transmit bit.\n" "0x01=1: The value of this bits field cannot be..,0x02=2: It is suggested the TBITNUM value is not.." group.long 0x20++0x03 line.long 0x00 "MANCH_TXDAT,Manchester Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. "TXDAT,Manchester Transmit Data \nThe bits field indicates the transmit data" rgroup.long 0x24++0x03 line.long 0x00 "MANCH_RXDAT,Manchester Receive Data Register" hexmask.long.byte 0x00 0.--7. 1. "RXDAT,Manchester Receive Data \nThe bits field indicates the received data" rgroup.long 0x28++0x03 line.long 0x00 "MANCH_MTXDAT,Manchester Transmit Encoded Data Register" hexmask.long.word 0x00 0.--15. 1. "MTXDAT,Manchester Encoded Data \nThe bits field indicates the current Manchester encoded data in FIFO" tree.end tree "NMI (NMI Register Map)" base ad:0x40000300 group.long 0x00++0x03 line.long 0x00 "NMIEN,NMI Source Interrupt Enable Register" bitfld.long 0x00 14. "UART0_INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled" bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.7 pin NMI source..,1: External interrupt from PB.7 pin NMI source.." newline bitfld.long 0x00 12. "EINT4,External Interrupt From PB.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.6 pin NMI source..,1: External interrupt from PB.6 pin NMI source.." bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.2 pin NMI source..,1: External interrupt from PB.2 pin NMI source.." newline bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.3 pin NMI source..,1: External interrupt from PB.3 pin NMI source.." bitfld.long 0x00 9. "EINT1,External Interrupt From PB.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.4 pin NMI source..,1: External interrupt from PB.4 pin NMI source.." newline bitfld.long 0x00 8. "EINT0,External Interrupt From PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.5 pin NMI source..,1: External interrupt from PB.5 pin NMI source.." bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled" newline bitfld.long 0x00 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: BOD NMI source Disabled,1: BOD NMI source Enabled" rgroup.long 0x04++0x03 line.long 0x00 "NMISTS,NMI Source Interrupt Status Register" bitfld.long 0x00 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART0 interrupt is deasserted,1: UART0 interrupt is asserted" bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.7 interrupt is..,1: External Interrupt from PB.7 interrupt is.." newline bitfld.long 0x00 12. "EINT4,External Interrupt From PB.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.6 interrupt is..,1: External Interrupt from PB.6 interrupt is.." bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.2 interrupt is..,1: External Interrupt from PB.2 interrupt is.." newline bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.3 interrupt is..,1: External Interrupt from PB.3 interrupt is.." bitfld.long 0x00 9. "EINT1,External Interrupt From PB.4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.4 interrupt is..,1: External Interrupt from PB.4 interrupt is.." newline bitfld.long 0x00 8. "EINT0,External Interrupt From PB.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.5 interrupt is..,1: External Interrupt from PB.5 interrupt is.." bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted" newline bitfld.long 0x00 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted" tree.end tree "NVIC (NVIC Register Map)" base ad:0xE000E100 group.long 0x00++0x03 line.long 0x00 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register" hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0 registers enable interrupts and show which interrupts are enabled\nWrite Operation" group.long 0x80++0x03 line.long 0x00 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register" hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0 registers disable interrupts and show which interrupts are enabled.\nWrite Operation" group.long 0x100++0x03 line.long 0x00 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register" hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation" group.long 0x180++0x03 line.long 0x00 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register" hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation" group.long 0x200++0x03 line.long 0x00 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register" hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active" tree.end tree "PDMA (PDMA Register Map)" base ad:0x40008000 group.long 0x00++0x03 line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x10++0x03 line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x20++0x03 line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x30++0x03 line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x40++0x03 line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x50++0x03 line.long 0x00 "PDMA_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x60++0x03 line.long 0x00 "PDMA_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1)" bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x04++0x03 line.long 0x00 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x14++0x03 line.long 0x00 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x24++0x03 line.long 0x00 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x34++0x03 line.long 0x00 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x44++0x03 line.long 0x00 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x54++0x03 line.long 0x00 "PDMA_DSCT5_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x64++0x03 line.long 0x00 "PDMA_DSCT6_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x08++0x03 line.long 0x00 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x18++0x03 line.long 0x00 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x28++0x03 line.long 0x00 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x38++0x03 line.long 0x00 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x48++0x03 line.long 0x00 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x58++0x03 line.long 0x00 "PDMA_DSCT5_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x68++0x03 line.long 0x00 "PDMA_DSCT6_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x0C++0x03 line.long 0x00 "PDMA_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." group.long 0x1C++0x03 line.long 0x00 "PDMA_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." group.long 0x2C++0x03 line.long 0x00 "PDMA_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." group.long 0x3C++0x03 line.long 0x00 "PDMA_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." group.long 0x4C++0x03 line.long 0x00 "PDMA_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." group.long 0x5C++0x03 line.long 0x00 "PDMA_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." group.long 0x6C++0x03 line.long 0x00 "PDMA_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.." rgroup.long 0x100++0x03 line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.." repeat 6. (strings "1" "2" "3" "4" "5" "6" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 ) group.long ($2+0x104)++0x03 line.long 0x00 "PDMA_CURSCAT$1,Current Scatter-gather Descriptor Table Address of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.." repeat.end group.long 0x400++0x03 line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register" bitfld.long 0x00 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x00 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" wgroup.long 0x404++0x03 line.long 0x00 "PDMA_PAUSE,PDMA Transfer Pause Control Register" bitfld.long 0x00 6. "PAUSE6,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x00 5. "PAUSE5,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x00 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x00 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x00 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x00 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x00 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" wgroup.long 0x408++0x03 line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register" bitfld.long 0x00 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" bitfld.long 0x00 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" newline bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" newline bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" newline bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" rgroup.long 0x40C++0x03 line.long 0x00 "PDMA_TRGSTS,PDMA Channel Request Status Register" bitfld.long 0x00 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x00 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" group.long 0x410++0x03 line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register" bitfld.long 0x00 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x00 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." wgroup.long 0x414++0x03 line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register" bitfld.long 0x00 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x00 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" group.long 0x418++0x03 line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Register" bitfld.long 0x00 6. "INTEN6,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x00 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" group.long 0x41C++0x03 line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register" bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear these bits.\nNote: Please disable time-out function before clearing this bit" "0: No request time-out,1: Peripheral request time-out" bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear these bits.\nNote: Please disable time-out function before clearing this bit" "0: No request time-out,1: Peripheral request time-out" newline rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission" "0: Not finished yet,1: PDMA channel has finished transmission" newline rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received" group.long 0x420++0x03 line.long 0x00 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register" bitfld.long 0x00 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." bitfld.long 0x00 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." newline bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." newline bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." newline bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThese bits indicate which PDMA controller has target abort error" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." group.long 0x424++0x03 line.long 0x00 "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register" bitfld.long 0x00 6. "TDIF6,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0x00 5. "TDIF5,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThese bits indicate whether PDMA controller channel transfer has been finished or not" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" group.long 0x428++0x03 line.long 0x00 "PDMA_ALIGN,PDMA Transfer Alignment Status Register" bitfld.long 0x00 6. "ALIGN6,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." bitfld.long 0x00 5. "ALIGN5,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." newline bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." newline bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." newline bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag\nThese bits indicate whether source and destination address both follow transfer width setting" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." rgroup.long 0x42C++0x03 line.long 0x00 "PDMA_TACTSTS,PDMA Transfer Active Flag Register" bitfld.long 0x00 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" bitfld.long 0x00 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" newline bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" newline bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" newline bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is active" "0: PDMA channel is finished,1: PDMA channel is active" group.long 0x430++0x03 line.long 0x00 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register" bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.." bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.." group.long 0x434++0x03 line.long 0x00 "PDMA_TOUTEN,PDMA Time-out Enable Register" bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled" bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled" group.long 0x438++0x03 line.long 0x00 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register" bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled" bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled" group.long 0x43C++0x03 line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register" hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode this is the base address for calculating the next link - list address" group.long 0x440++0x03 line.long 0x00 "PDMA_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register" hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1" hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0" group.long 0x460++0x03 line.long 0x00 "PDMA_CHRST,PDMA Channel Reset Register" hexmask.long.byte 0x00 0.--6. 1. "CHnRST,Channel n Reset" group.long 0x480++0x03 line.long 0x00 "PDMA_REQSEL0_3,PDMA Request Source Select Register 0" bitfld.long 0x00 24.--29. "REQSRC3,Channel 3 Request Source Selection\nThis field defines which peripheral is connected to PDMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. "REQSRC2,Channel 2 Request Source Selection\nThis field defines which peripheral is connected to PDMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. "REQSRC1,Channel 1 Request Source Selection\nThis field defines which peripheral is connected to PDMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "REQSRC0,Channel 0 Request Source Selection\nThis field defines which peripheral is connected to PDMA channel 0" "0: Disable PDMA peripheral request,1: Reserved,2: Reserved,3: Reserved,4: Channel connects to UART0_TX,5: Channel connects to UART0_RX,6: Reserved,7: Reserved,8: Reserved,9: Reserved,10: Reserved,11: Reserved,12: Reserved,13: Reserved,14: Reserved,15: Reserved,16: Reserved,17: Reserved,18: Channel connects to SPI0_TX,19: Channel connects to SPI0_RX,20: Channel connects to ADC_RX,21: Reserved,22: Reserved,23: Reserved,24: Reserved,25: Reserved,26: Reserved,27: Reserved,28: Channel connects to I2C0_TX,29: Channel connects to I2C0_RX,30: Channel connects to I2C1_TX,31: Channel connects to I2C1_RX,32: Channel connects to TMR0,33: Channel connects to TMR1,34: Channel connects to TMR2,35: Channel connects to TMR3,36: Reserved,37: Reserved,38: Reserved,39: Reserved,40: Reserved,41: Reserved,42: Reserved,43: Reserved,44: Reserved,45: Reserved,46: Channel connects to DAC0 TX,47: Channel connects to DAC1 TX,48: Channel connects to DAC2 TX,49: Channel connects to DAC3 TX,50: Channel connects to TMR4,51: Channel connects to TMR5,52: Channel connects to MANCH MTX,53: Channel connects to MANCH TX,54: Channel connects to MANCH RX,?..." group.long 0x484++0x03 line.long 0x00 "PDMA_REQSEL4_6,PDMA Request Source Select Register 1" bitfld.long 0x00 16.--21. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "SPI (SPI Register Map)" base ad:0x40061000 group.long 0x00++0x03 line.long 0x00 "SPIx_CTL,SPI Control Register" bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction" bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled" newline bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode" bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled" newline bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled" bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer" newline bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.." bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high" newline bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.." bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.." newline bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled" group.long 0x04++0x03 line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register" hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master" group.long 0x08++0x03 line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register" bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled" bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled" newline bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled" bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled" newline bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled" bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.." newline bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.." group.long 0x0C++0x03 line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register" bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.." bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" group.long 0x10++0x03 line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is greater than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer" bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer" newline bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled" bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\n" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.." newline bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled" newline bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled" bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled" newline bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.." bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit" group.long 0x14++0x03 line.long 0x00 "SPIx_STATUS,SPI Status Register" rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST" bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.." newline rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled" newline bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun" newline rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.." rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" newline rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred" newline bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred" rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1" newline bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred" bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred" newline bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer" rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state" wgroup.long 0x20++0x03 line.long 0x00 "SPIx_TX,SPI Data Transmit Register" hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers" rgroup.long 0x30++0x03 line.long 0x00 "SPIx_RX,SPI Data Receive Register" hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller" tree.end tree "SYS (SYS Register Map)" base ad:0x40000000 rgroup.long 0x00++0x03 line.long 0x00 "SYS_PDID,Part Device Identification Number Register" hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code" group.long 0x04++0x03 line.long 0x00 "SYS_RSTSTS,System Reset Status Register" bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\n" "0: No reset from CPU lockup happened,1: The Cortex-M0 lockup happened and chip is reset" bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by.." newline bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex- M0 had issued the reset signal to.." bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.." newline bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.." bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\n" "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.." newline bitfld.long 0x00 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.." bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.." group.long 0x08++0x03 line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0" bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset" bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset" newline bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset" bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset" group.long 0x0C++0x03 line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1" bitfld.long 0x00 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset" bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset" newline bitfld.long 0x00 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset" bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset" newline bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset" bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset" newline bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset" bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset" newline bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset" bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset" group.long 0x10++0x03 line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2" bitfld.long 0x00 31. "TSRST,Temperature Sensor Reset" "0: Temperature Sensor normal operation,1: Temperature Sensor reset" bitfld.long 0x00 29. "TMR5RST,Timer5 Controller Reset" "0: Timer5 controller normal operation,1: Timer5 controller reset" newline bitfld.long 0x00 28. "TMR4RST,Timer4 Controller Reset" "0: Timer4 controller normal operation,1: Timer4 controller reset" bitfld.long 0x00 24. "MANCHRST,Manchester Codec Reset" "0: Manchester codec normal operation,1: Manchester codec reset" newline bitfld.long 0x00 19. "BPWMRST,BPWM Controller Reset" "0: BPWM controller normal operation,1: BPWM controller reset" bitfld.long 0x00 13. "DAC23RST,DAC23 Controller Reset" "0: DAC2 and DAC3 controller normal operation,1: DAC2 and DAC3 controller reset" newline bitfld.long 0x00 12. "DAC01RST,DAC01 Controller Reset" "0: DAC0 and DAC1 controller normal operation,1: DAC0 and DAC1 controller reset" group.long 0x18++0x03 line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register" bitfld.long 0x00 16. "BODVL,Brown-out Detector Threshold Voltage Select (Write Protect)\n" "0: Brown-Out Detector threshold voltage is 2.5V,1: Brown-Out Detector threshold voltage is 2.7V" bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: Without de-glitch function,1: 64 system clock (HCLK),2: 128 system clock (HCLK),3: 256 system clock (HCLK),4: 512 system clock (HCLK),5: 1024 system clock (HCLK),6: 2048 system clock (HCLK),7: 4096 system clock (HCLK)" newline bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by LIRC/4 clock,1: 64 system clock (HCLK),2: 128 system clock (HCLK),3: 256 system clock (HCLK),4: 512 system clock (HCLK),5: 1024 system clock (HCLK),6: 2048 system clock (HCLK),7: 4096 system clock (HCLK)" bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled" newline bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1" bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\n" "0: BOD operate in normal mode (Default),1: BOD low power mode Enabled" newline bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.." bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\n" "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled" newline bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\n" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled" group.long 0x24++0x03 line.long 0x00 "SYS_PORCTL,Power-On-reset Controller Register" hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again" group.long 0x28++0x03 line.long 0x00 "SYS_VREFCTL,Voltage Reference Control Register" bitfld.long 0x00 8. "SCPDIS,VREF Short Circuit Protection Disable Control (Write Protect)" "0: VREF Short Circuit Protection function Enabled,1: VREF Short Circuit Protection function Disabled" bitfld.long 0x00 6. "PRELOADEN,VREF Pre-load Enable Bit (Write Protect)\nThis bit is set automatically if software set VREFEN (SYS_VREFCTL[0]) to 1.\n" "0: VREF Pre-load function Disabled,1: VREF Pre-load function Enabled" newline bitfld.long 0x00 1. "VREFSEL,VREF Output Voltage Select (Write Protect)\nNote: This bit is write protected" "0: VREF output voltage value is 2.048V,1: VREF output voltage value is 2.5V" bitfld.long 0x00 0. "VREFEN,VREF Enable Bit (Write Protect)\nNote: This bit is write protected" "0: VREF function Disabled,1: VREF function Enabled" group.long 0x30++0x03 line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register" bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x03 line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register" bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x03 line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register" bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x03 line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register" bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register" bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x58++0x03 line.long 0x00 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register" bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC0++0x03 line.long 0x00 "SYS_MODCTL,Modulation Control Register" bitfld.long 0x00 29. "MANCHMODL5,Manchester Modulation at Data Low\nEach of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low" "0: Manchester modulation with BPWM1_CHn at..,1: Manchester modulation with BPWM1_CHn at.." bitfld.long 0x00 28. "MANCHMODL4,Manchester Modulation at Data Low\nEach of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low" "0: Manchester modulation with BPWM1_CHn at..,1: Manchester modulation with BPWM1_CHn at.." newline bitfld.long 0x00 27. "MANCHMODL3,Manchester Modulation at Data Low\nEach of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low" "0: Manchester modulation with BPWM1_CHn at..,1: Manchester modulation with BPWM1_CHn at.." bitfld.long 0x00 26. "MANCHMODL2,Manchester Modulation at Data Low\nEach of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low" "0: Manchester modulation with BPWM1_CHn at..,1: Manchester modulation with BPWM1_CHn at.." newline bitfld.long 0x00 25. "MANCHMODL1,Manchester Modulation at Data Low\nEach of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low" "0: Manchester modulation with BPWM1_CHn at..,1: Manchester modulation with BPWM1_CHn at.." bitfld.long 0x00 24. "MANCHMODL0,Manchester Modulation at Data Low\nEach of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low" "0: Manchester modulation with BPWM1_CHn at..,1: Manchester modulation with BPWM1_CHn at.." newline bitfld.long 0x00 21. "MANCHMODEN5,Manchester Modulation Function Enable\nEach of these bits is used to enable Manchester modulation function with BPWM1_CHn output" "0: Modulation Function Disabled,1: Modulation Function Enabled" bitfld.long 0x00 20. "MANCHMODEN4,Manchester Modulation Function Enable\nEach of these bits is used to enable Manchester modulation function with BPWM1_CHn output" "0: Modulation Function Disabled,1: Modulation Function Enabled" newline bitfld.long 0x00 19. "MANCHMODEN3,Manchester Modulation Function Enable\nEach of these bits is used to enable Manchester modulation function with BPWM1_CHn output" "0: Modulation Function Disabled,1: Modulation Function Enabled" bitfld.long 0x00 18. "MANCHMODEN2,Manchester Modulation Function Enable\nEach of these bits is used to enable Manchester modulation function with BPWM1_CHn output" "0: Modulation Function Disabled,1: Modulation Function Enabled" newline bitfld.long 0x00 17. "MANCHMODEN1,Manchester Modulation Function Enable\nEach of these bits is used to enable Manchester modulation function with BPWM1_CHn output" "0: Modulation Function Disabled,1: Modulation Function Enabled" bitfld.long 0x00 16. "MANCHMODEN0,Manchester Modulation Function Enable\nEach of these bits is used to enable Manchester modulation function with BPWM1_CHn output" "0: Modulation Function Disabled,1: Modulation Function Enabled" group.long 0xD0++0x03 line.long 0x00 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register" bitfld.long 0x00 7. "PDMABIST,PDMA SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA SRAM\nNote: This bit is write protected" "0: PDMA SRAM BIST Disabled,1: PDMA SRAM BIST Enabled" bitfld.long 0x00 0. "SRBIST,System SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for System SRAM\nNote: This bit is write protected" "0: System SRAM BIST Disabled,1: System SRAM BIST Enabled" rgroup.long 0xD4++0x03 line.long 0x00 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register" bitfld.long 0x00 23. "PDMAEND,PDMA SRAM BIST Test Finish" "0: PDMA SRAM BIST is active,1: PDMA SRAM BIST test finish" bitfld.long 0x00 16. "SRBEND,System SRAM BIST Test Finish" "0: System SRAM BIST active,1: System SRAM BIST finish" newline bitfld.long 0x00 7. "PDMABISTF,PDMA SRAM BIST Failed Flag" "0: PDMA SRAM BIST pass,1: PDMA SRAM BIST failed" bitfld.long 0x00 0. "SRBISTFF,System SRAM BIST Fail Flag" "0: System SRAM BIST test pass,1: System SRAM BIST test fail" group.long 0x100++0x03 line.long 0x00 "SYS_REGLCTL,Register Lock Control Register" hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Lock Control Code\nSome registers have write-protection function" group.long 0x140++0x03 line.long 0x00 "SYS_TSCTL,Temperature Sensor Control Register" group.long 0x144++0x03 line.long 0x00 "SYS_TSDATA,Temperature Sensor Data Register" hexmask.long.word 0x00 16.--27. 1. "TSDATA,Temperature Sensor Conversion Data Bits (Read Only)\nThis field present the conversion result of Temperature Sensor ranges from -40C to 105C.\nNote: Negative temperature is represented by 2's complement format and per LSB difference is equivalent.." bitfld.long 0x00 0. "TSEOC,Temperature Sensor Conversion Finish Flag\nThis bit indicates the end of temperature sensor conversion.\nNote: Write 1 to clear this bit to 0" "0,1" group.long 0x1E8++0x03 line.long 0x00 "SYS_POR18DISAN,Analog POR18 Disable Control Register" hexmask.long.word 0x00 0.--15. 1. "POR18OFFAN,LDO Power-on Reset Enable Bit (Write Protect)\nAfter powered on user can turn off internal analog POR18 circuit to save power by writing 0x5AA5 to this field.\nThe analog POR18 circuit will be active again when this field is set to another.." tree.end tree "SYST_SCR (SYST_SCR Register Map)" base ad:0xE000E000 group.long 0x10++0x03 line.long 0x00 "SYST_CTRL,SysTick Control and Status Register" bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1" bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick" newline bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.." bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner" group.long 0x14++0x03 line.long 0x00 "SYST_LOAD,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0" group.long 0x18++0x03 line.long 0x00 "SYST_VAL,SysTick Current Value Register" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value" group.long 0xD04++0x03 line.long 0x00 "ICSR,Interrupt Control and State Register" bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception is not pending,1: Change NMI exception state to pending.\nNMI.." bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Change PendSV exception state to.." newline bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Remove the pending state from the PendSV.." bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Change SysTick exception state to.." newline bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Remove the pending state from the SysTick.." rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1" newline rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt is not pending,1: Interrupt is pending" bitfld.long 0x00 12.--17. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but does not include any.." "0: No pending exceptions,?..." newline bitfld.long 0x00 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions" "0: There are preempted active exceptions to..,1: There are no active exceptions or the.." bitfld.long 0x00 0.--5. "VECTACTIVE,Number of the Current Active Exception" "0: Thread mode,?..." group.long 0xD08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected security state" group.long 0xD0C++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.." bitfld.long 0x00 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian" newline bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1" newline bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting this bit to 1 will clear all active state information for fixed and configurable exceptions.\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1" bitfld.long 0x00 0. "VECTRESET,Reserved" "0,1" group.long 0xD10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.." bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl whether the processor uses Sleep or Deep Sleep as its Low Power Mode" "0: Sleep,1: Deep sleep" newline bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicates Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an.." group.long 0xD18++0x03 line.long 0x00 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x00 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault" hexmask.long.byte 0x00 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault" newline hexmask.long.byte 0x00 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage" group.long 0xD1C++0x03 line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3" group.long 0xD20++0x03 line.long 0x00 "SHPR3,System Handler Priority Register 3" bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3" tree.end tree "TIMER (Timer/Counter)" tree "TMR01" base ad:0x40050000 group.long 0x00++0x03 line.long 0x00 "TIMER0_CTL,Timer0 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." newline bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from LIRC" bitfld.long 0x00 11. "MTRGTMEN,Manchester Edge Trigger Timer Enable Bit" "0: Manchester Edge Trigger Timer Disabled,1: Manchester Edge Trigger Timer Enabled" newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also Timer1/3/5 will be in.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled" newline bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x04++0x03 line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x08++0x03 line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" rgroup.long 0x0C++0x03 line.long 0x00 "TIMER0_CNT,Timer0 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" rgroup.long 0x10++0x03 line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x14++0x03 line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register" bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "?,?,?,?,?,5: Capture Function source is from LIRC,?..." newline bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~5) pin de-bounce Disabled,1: TMx (x= 0~5) pin de-bounce Enabled" bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~5) pin de-bounce Disabled,1: TMx_EXT (x= 0~5) pin de-bounce Enabled" newline bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~5) pin or LIRC detection..,1: TMx_EXT (x= 0~5) pin or LIRC detection.." bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" newline bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~5) pin or..,1: A Rising edge on TMx_EXT (x= 0~5) pin or LIRC..,2: Either Rising or Falling edge on TMx_EXT (x=..,3: Reserved" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x18++0x03 line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~5) pin interrupt did not occur,1: TMx_EXT (x= 0~5) pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TIMER1_CTL,Timer1 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." newline bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from LIRC" bitfld.long 0x00 11. "MTRGTMEN,Manchester Edge Trigger Timer Enable Bit" "0: Manchester Edge Trigger Timer Disabled,1: Manchester Edge Trigger Timer Enabled" newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also Timer1/3/5 will be in.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled" newline bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x24++0x03 line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x28++0x03 line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" group.long 0x2C++0x03 line.long 0x00 "TIMER1_CNT,Timer1 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" group.long 0x30++0x03 line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x34++0x03 line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register" bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "?,?,?,?,?,5: Capture Function source is from LIRC,?..." newline bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~5) pin de-bounce Disabled,1: TMx (x= 0~5) pin de-bounce Enabled" bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~5) pin de-bounce Disabled,1: TMx_EXT (x= 0~5) pin de-bounce Enabled" newline bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~5) pin or LIRC detection..,1: TMx_EXT (x= 0~5) pin or LIRC detection.." bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" newline bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~5) pin or..,1: A Rising edge on TMx_EXT (x= 0~5) pin or LIRC..,2: Either Rising or Falling edge on TMx_EXT (x=..,3: Reserved" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x38++0x03 line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~5) pin interrupt did not occur,1: TMx_EXT (x= 0~5) pin interrupt occurred" tree.end tree "TMR23" base ad:0x40051000 group.long 0x00++0x03 line.long 0x00 "TIMER2_CTL,Timer2 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." newline bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from LIRC" bitfld.long 0x00 11. "MTRGTMEN,Manchester Edge Trigger Timer Enable Bit" "0: Manchester Edge Trigger Timer Disabled,1: Manchester Edge Trigger Timer Enabled" newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also Timer1/3/5 will be in.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled" newline bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x04++0x03 line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x08++0x03 line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" rgroup.long 0x0C++0x03 line.long 0x00 "TIMER2_CNT,Timer2 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" rgroup.long 0x10++0x03 line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x14++0x03 line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register" bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "?,?,?,?,?,5: Capture Function source is from LIRC,?..." newline bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~5) pin de-bounce Disabled,1: TMx (x= 0~5) pin de-bounce Enabled" bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~5) pin de-bounce Disabled,1: TMx_EXT (x= 0~5) pin de-bounce Enabled" newline bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~5) pin or LIRC detection..,1: TMx_EXT (x= 0~5) pin or LIRC detection.." bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" newline bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~5) pin or..,1: A Rising edge on TMx_EXT (x= 0~5) pin or LIRC..,2: Either Rising or Falling edge on TMx_EXT (x=..,3: Reserved" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x18++0x03 line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~5) pin interrupt did not occur,1: TMx_EXT (x= 0~5) pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TIMER3_CTL,Timer3 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." newline bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from LIRC" bitfld.long 0x00 11. "MTRGTMEN,Manchester Edge Trigger Timer Enable Bit" "0: Manchester Edge Trigger Timer Disabled,1: Manchester Edge Trigger Timer Enabled" newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also Timer1/3/5 will be in.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled" newline bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x24++0x03 line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x28++0x03 line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" group.long 0x2C++0x03 line.long 0x00 "TIMER3_CNT,Timer3 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" group.long 0x30++0x03 line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x34++0x03 line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register" bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "?,?,?,?,?,5: Capture Function source is from LIRC,?..." newline bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~5) pin de-bounce Disabled,1: TMx (x= 0~5) pin de-bounce Enabled" bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~5) pin de-bounce Disabled,1: TMx_EXT (x= 0~5) pin de-bounce Enabled" newline bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~5) pin or LIRC detection..,1: TMx_EXT (x= 0~5) pin or LIRC detection.." bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" newline bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~5) pin or..,1: A Rising edge on TMx_EXT (x= 0~5) pin or LIRC..,2: Either Rising or Falling edge on TMx_EXT (x=..,3: Reserved" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x38++0x03 line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~5) pin interrupt did not occur,1: TMx_EXT (x= 0~5) pin interrupt occurred" tree.end tree "TMR45" base ad:0x40052000 group.long 0x00++0x03 line.long 0x00 "TIMER4_CTL,Timer4 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." newline bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from LIRC" bitfld.long 0x00 11. "MTRGTMEN,Manchester Edge Trigger Timer Enable Bit" "0: Manchester Edge Trigger Timer Disabled,1: Manchester Edge Trigger Timer Enabled" newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also Timer1/3/5 will be in.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled" newline bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x04++0x03 line.long 0x00 "TIMER4_CMP,Timer4 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x08++0x03 line.long 0x00 "TIMER4_INTSTS,Timer4 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" rgroup.long 0x0C++0x03 line.long 0x00 "TIMER4_CNT,Timer4 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" rgroup.long 0x10++0x03 line.long 0x00 "TIMER4_CAP,Timer4 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x14++0x03 line.long 0x00 "TIMER4_EXTCTL,Timer4 External Control Register" bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "?,?,?,?,?,5: Capture Function source is from LIRC,?..." newline bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~5) pin de-bounce Disabled,1: TMx (x= 0~5) pin de-bounce Enabled" bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~5) pin de-bounce Disabled,1: TMx_EXT (x= 0~5) pin de-bounce Enabled" newline bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~5) pin or LIRC detection..,1: TMx_EXT (x= 0~5) pin or LIRC detection.." bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" newline bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~5) pin or..,1: A Rising edge on TMx_EXT (x= 0~5) pin or LIRC..,2: Either Rising or Falling edge on TMx_EXT (x=..,3: Reserved" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x18++0x03 line.long 0x00 "TIMER4_EINTSTS,Timer4 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~5) pin interrupt did not occur,1: TMx_EXT (x= 0~5) pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TIMER5_CTL,Timer5 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." newline bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from LIRC" bitfld.long 0x00 11. "MTRGTMEN,Manchester Edge Trigger Timer Enable Bit" "0: Manchester Edge Trigger Timer Disabled,1: Manchester Edge Trigger Timer Enabled" newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also Timer1/3/5 will be in.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled" newline bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x24++0x03 line.long 0x00 "TIMER5_CMP,Timer5 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x28++0x03 line.long 0x00 "TIMER5_INTSTS,Timer5 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" group.long 0x2C++0x03 line.long 0x00 "TIMER5_CNT,Timer5 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" group.long 0x30++0x03 line.long 0x00 "TIMER5_CAP,Timer5 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x34++0x03 line.long 0x00 "TIMER5_EXTCTL,Timer5 External Control Register" bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "?,?,?,?,?,5: Capture Function source is from LIRC,?..." newline bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~5) pin de-bounce Disabled,1: TMx (x= 0~5) pin de-bounce Enabled" bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~5) pin de-bounce Disabled,1: TMx_EXT (x= 0~5) pin de-bounce Enabled" newline bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~5) pin or LIRC detection..,1: TMx_EXT (x= 0~5) pin or LIRC detection.." bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" newline bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~5) pin or..,1: A Rising edge on TMx_EXT (x= 0~5) pin or LIRC..,2: Either Rising or Falling edge on TMx_EXT (x=..,3: Reserved" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x38++0x03 line.long 0x00 "TIMER5_EINTSTS,Timer5 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~5) pin interrupt did not occur,1: TMx_EXT (x= 0~5) pin interrupt occurred" tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x40070000 group.long 0x00++0x03 line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register" bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1" hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO" group.long 0x04++0x03 line.long 0x00 "UART_INTEN,UART Interrupt Enable Register" bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled" bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" newline bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled" bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled" newline bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled" bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled" newline bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" newline bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled" bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled" newline bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.." newline bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" group.long 0x08++0x03 line.long 0x00 "UART_FIFO,UART FIFO Control Register" bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,?..." bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled" newline bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,?..." bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.." newline bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.." group.long 0x0C++0x03 line.long 0x00 "UART_LINE,UART Line Control Register" bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled" bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled" newline bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically by software.\n" "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software" bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled" newline bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled" bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled" bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When selecting 5-bit word length 1.5 'STOP.." newline bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits" group.long 0x10++0x03 line.long 0x00 "UART_MODEM,UART Modem Control Register" rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.." bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active" newline bitfld.long 0x00 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive" group.long 0x14++0x03 line.long 0x00 "UART_MODEMSTS,UART Modem Status Register" bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active" rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.." newline bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state" group.long 0x18++0x03 line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register" rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active" rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle" newline rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to be logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 1 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty" newline rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 1 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty" rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.." newline bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow" group.long 0x1C++0x03 line.long 0x00 "UART_INTSTS,UART Interrupt Status Register" rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated" rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated" newline rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.." rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode" newline rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode" rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode" newline rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.." bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated" newline rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.." rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.." newline rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode" rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode" newline bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.." rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated" newline rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated" newline rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated" newline rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated" rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated" newline rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated" rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated" rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x03 line.long 0x00 "UART_TOUT,UART Time-out Register" hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit" hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator" group.long 0x24++0x03 line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register" bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1" bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1" newline bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider" group.long 0x28++0x03 line.long 0x00 "UART_IRDA,UART IrDA Control Register" bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" group.long 0x2C++0x03 line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register" hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode" bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.." newline bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection is finished or the auto-baud rate counter is overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated" newline bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.." newline bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." group.long 0x30++0x03 line.long 0x00 "UART_FUNCSEL,UART Function Select Register" bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled" bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..." group.long 0x40++0x03 line.long 0x00 "UART_WKCTL,UART Wake-up Control Register" bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled" bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled" group.long 0x44++0x03 line.long 0x00 "UART_WKSTS,UART Wake-up Status Register" bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.." group.long 0x48++0x03 line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register" hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThe bits field indicates how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.." tree.end tree "WDT (Watchdog Timer Unit)" base ad:0x40040000 group.long 0x00++0x03 line.long 0x00 "WDT_CTL,WDT Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled" rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.." newline bitfld.long 0x00 8.--11. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK,8: 220 * WDT_CLK,?..." bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\n" "0: WDT Disabled (This action will reset the..,1: WDT Enabled" newline bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled" bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\n" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." newline bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.." bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred" newline bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred" bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled" group.long 0x04++0x03 line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register" bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select a.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK" wgroup.long 0x08++0x03 line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register" hexmask.long 0x00 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active" tree.end tree "WWDT (WWDT Register Map)" base ad:0x40040100 wgroup.long 0x00++0x03 line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register" hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.." group.long 0x04++0x03 line.long 0x00 "WWDT_CTL,WWDT Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.." bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled" newline bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting" group.long 0x08++0x03 line.long 0x00 "WWDT_STATUS,WWDT Status Register" bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred" bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT" rgroup.long 0x0C++0x03 line.long 0x00 "WWDT_CNT,WWDT Counter Value Register" bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end autoindent.off newline