; -------------------------------------------------------------------------------- ; @Title: LPC8xx On-Chip Peripherals ; @Props: Released ; @Author: GAJ, KKW, DPR, KOB, BUM, KMW ; @Changelog: 2015-12-01 KKW ; 2016-05-09 GAJ ; 2017-10-10 KOB ; 2018-11-06 KMW ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: UM10800.pdf (Rev.1 2014-09) ; UM10601.pdf (Rev.1.6 2014-04) ; LPC81XM.pdf (Rev.4.4 2015-06) ; UM11029.pdf (Rev.1.3 2017-08) ; UM11021.pdf (Rev.1.6 2014-02) ; UM11074-rev1.1.pdf (Rev.1.1 2017-12) ; UM11065-rev1.2.pdf (Rev.1.2 2018-03) ; UM11045-rev1.3.pdf (Rev.1.3 2018-03) ; LPC800-UserManual-20121109-1.pdf (Rev.1 2012-11) ; @Chip: LPC812M101JD20, LPC812M101JDH16, LPC812M101JTB16, LPC812M101JDH20 ; LPC822M101JDH20, LPC822M101JHI33, LPC824M201JDH20, LPC824M201JHI33 ; LPC811M001JDH16, LPC832M101FDH20, LPC844M201JBD48, LPC844M201JBD64 ; LPC844M201JHI33, LPC834M101FHI33, LPC844M201JHI48, LPC845M301JBD48 ; LPC845M301JBD64, LPC845M301JHI33, LPC845M301JHI48, LPC802M001JDH16 ; LPC802M001JDH20, LPC802M001JHI33, LPC802M011JDH20, LPC804M101JDH20 ; LPC804M101JDH24, LPC804M101JHI33, LPC804M111JDH24, LPC8N04 ; @Core: Cortex-M0P ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perlpc8xx.per 9875 2018-11-06 14:54:19Z psurmacki $ ; Known problems: ; - SPI - base address for SPI1 in memory map does not match base address ; given in "Chapter 17: LPC800 SPI0/1" ; - WWDT - base address for WWDT in memory map does not match base address ; given in "Chapter 12: LPC800 Windowed Watchdog Timer (WWDT)" ; - FLASH CONTROLLER - for flash_con.ph missing access type for some bitlfds, ; - FSTAT and FBWST registers have the same offset, ; - INT_ENABLE & INT_STATUS - differences in addresses given in ; Memory Map and Register Descriptions ; - FPTR: TR and EN_T have the same bit (11), ; also register has different access type in table 145 and table 150 ; - FMSW - bitflds in register overlaps each other ; - RFID/NFC - differences in addresses given in Memory Map and Register Descriptions ; - CT32B - base address in memory map is different than one that appears in register overview ; - EEPROM - INT_STATUS differences in addresses given in Memory Map and Register Descriptions config 16. 8. tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end sif (cpuis("LPC84*")) tree "SYSCON (System Configuration)" base ad:0x40048000 width 17. group.long 0x00++0x03 line.long 0x00 "SYSMEMREMAP,System Memory Remap Register" bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,?..." sif cpuis("LPC11E*") group.long 0x04++0x03 line.long 0x00 "PRESETCTRL,Peripheral Reset Control Register" sif cpuis("LPC11E6*") bitfld.long 0x00 10. " SCT1_RST_N ,SCT1 reset control" "Reset,No reset" bitfld.long 0x00 9. " SCT0_RST_N ,SCT0 reset control" "Reset,No reset" bitfld.long 0x00 8. " USART4_RST_N ,USART4 reset control" "Reset,No reset" newline bitfld.long 0x00 7. " USART3_RST_N ,USART3 reset control" "Reset,No reset" bitfld.long 0x00 6. " USART2_RST_N ,USART2 reset control" "Reset,No reset" bitfld.long 0x00 5. " USART1_RST_N ,USART1 reset control" "Reset,No reset" newline bitfld.long 0x00 4. " FRG_RST_N ,FRG reset control" "Reset,No reset" bitfld.long 0x00 3. " I2C1_RST_N ,I2C1 reset control" "Reset,No reset" bitfld.long 0x00 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset" else bitfld.long 0x00 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset" endif newline bitfld.long 0x00 1. " I2C0_RST_N ,I2C0 reset control" "Reset,No reset" bitfld.long 0x00 0. " SSP0_RST_N ,SSP0 reset control" "Reset,No reset" endif group.long 0x08++0x03 line.long 0x00 "SYSPLLCTRL,System PLL Control Register" bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8" bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" rgroup.long 0x0C++0x03 line.long 0x00 "SYSPLLSTAT,System PLL Status Register" bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked" sif cpuis("LPC11E6*") group.long 0x10++0x03 line.long 0x00 "USBPLLCTRL,USB PLL Control Register" bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8" bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" rgroup.long 0x14++0x03 line.long 0x00 "USBPLLSTAT,USB PLL Status Register" bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked" group.long 0x1C++0x03 line.long 0x00 "RTCOSCCTRL,RTC Oscillator 32 kHz Output Control Register" bitfld.long 0x00 0. " RTCOSCEN ,RTC 32 kHz output enable" "Disabled,Enabled" endif group.long 0x20++0x07 line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register" bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz" bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled" line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register" bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency" "0 MHz,0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz" bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" sif cpuis("LPC11E*") group.long 0x28++0x03 line.long 0x00 "IRCCTRL,Internal Resonant Crystal Control Register" hexmask.long.byte 0x00 0.--7. 1. " TRIM ,Trim value" group.long 0x30++0x03 line.long 0x00 "SYSRSTSTAT,System Reset Status Register" eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset" eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset" eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset" newline eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset" eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset" else group.long 0x28++0x03 line.long 0x00 "FROOSCCTRL, FRO Oscillator Control Register" bitfld.long 0x00 17. " FRO_DIRECT ,FRO direct clock select" "fro_oscout /2 or /16,FRO oscillator" group.long 0x30++0x03 line.long 0x00 "FRODIRECTCLKUEN, FRO Direct Clock Source Update Enable Register" bitfld.long 0x00 0. " ENA ,FRO clock source update enable" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "SYSRSTSTAT,System Reset Status Register" eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset" eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset" eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset" newline eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset" eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset" endif group.long 0x40++0x07 line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" sif cpuis("LPC11E6*") bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,SYSOSC,,32kHz clock" elif cpuis("LPC11E1*")||cpuis("LPC11E3*") bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,SYSOSC,?..." else bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "FRO,External clock,Watchdog oscillator,FRO DIV" endif line.long 0x04 "SYSPLLCLKUEN,System PLL Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled" sif cpuis("LPC11E*") sif cpuis("LPC11E6*") group.long 0x48++0x07 line.long 0x00 "USBPLLCLKSEL,USB PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,USB PLL clock source" "IRC oscillator,SYSOSC,?..." line.long 0x04 "USBPLLCLKUEN,USB PLL Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,USB PLL clock source update enable" "Disabled,Enabled" endif group.long 0x70++0x0B line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,PLL input,Watchdog oscillator,PLL output" line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,Main PLL clock source update enable" "Disabled,Enabled" line.long 0x08 "SYSAHBCLKDIV,System Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values" group.long 0x80++0x03 line.long 0x00 "SYSAHBCLKCTRL,System Clock Control Register" sif cpuis("LPC11E6*") bitfld.long 0x00 31. " SCT0_1 , SCT0 and SCT1 clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " RTC , RTC register interface clock enable" "Disabled,Enabled" bitfld.long 0x00 29. " DMA ,DMA clock enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " CRC ,CRC clock enable" "Disabled,Enabled" bitfld.long 0x00 27. " USBSRAM ,USB SRAM/SRAM2 block enable" "Disabled,Enabled" bitfld.long 0x00 26. " RAM1 ,SRAM1 clock enable" "Disabled,Enabled" else bitfld.long 0x00 27. " USBSRAM ,USB SRAM/SRAM2 block enable" "Disabled,Enabled" bitfld.long 0x00 26. " RAM1 ,SRAM1 clock enable" "Disabled,Enabled" endif newline sif cpuis("LPC11E6*") bitfld.long 0x00 25. " I2C1 ,I2C1 clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " GROUP1INT ,GPIO GROUP1 interrupt register clock enable" "Disabled,Enabled" bitfld.long 0x00 23. " GROUP0INT ,GPIO GROUP0 interrupt register clock enable" "Disabled,Enabled" else bitfld.long 0x00 24. " GROUP1INT ,GPIO GROUP1 interrupt register clock enable" "Disabled,Enabled" bitfld.long 0x00 23. " GROUP0INT ,GPIO GROUP0 interrupt register clock enable" "Disabled,Enabled" endif newline sif cpuis("LPC11E6*") bitfld.long 0x00 22. " USART3_4 ,USART3 and USART4 register interfaces clock enable" "Disabled,Enabled" bitfld.long 0x00 21. " USART2 ,USART2 register interface clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " USART1 ,USART1 register interface clock enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " PINT ,GPIO pin interrupt register interface clock enable" "Disabled,Enabled" bitfld.long 0x00 18. " SSP1 ,SSP1 clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " IOCON ,I/O configuration block clock enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " WWDT ,WWDT clock enable" "Disabled,Enabled" sif cpuis("LPC11E6*") bitfld.long 0x00 14. " USB ,USB register interface clock enable" "Disabled,Enabled" bitfld.long 0x00 13. " ADC ,ADC clock enable" "Disabled,Enabled" else bitfld.long 0x00 13. " ADC ,ADC clock enable" "Disabled,Enabled" endif newline bitfld.long 0x00 12. " USART0 ,USART0 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " SSP0 ,SSP0 clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CT32B1 ,32-bit counter/timer 1 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " CT32B0 ,32-bit counter/timer 0 clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CT16B1 ,16-bit counter/timer 1 clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " CT16B0 ,16-bit counter/timer 0 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " GPIO ,GPIO port registers clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " I2C0 ,I2C0 clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " FLASHARRAY ,Flash access clock enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FLASHREG ,Flash register interface clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " RAM0 ,Main SRAM0 clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " ROM ,ROM clock enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " SYS ,Clock for AHB/APB bridge/Cortex-M0/SYSCON/Reset control/SRAM0/PMU enable" ",Enabled" group.long 0x94++0x0B line.long 0x00 "SSP0CLKDIV,SSP0 Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,SPI0_PCLK clock divider values" line.long 0x04 "USART0CLKDIV,USART0 Clock Divider" hexmask.long.byte 0x04 0.--7. 1. " DIV ,USART_PCLK clock divider values" line.long 0x08 "SSP1CLKDIV,SSP1 Clock Divider" hexmask.long.byte 0x08 0.--7. 1. " DIV ,SSP1_PCLK clock divider values" sif cpuis("LPC11E6*") group.long 0xA0++0x03 line.long 0x00 "FRGCLKDIV,UART Fractional Baud Rate Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,USART fractional baud rate generator clock divider values" group.long 0xC0++0x0B line.long 0x00 "USBCLKSEL,USB Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,USB clock source" "USB PLL out,Main clock,?..." line.long 0x04 "USBCLKUEN,USB Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,USB clock source update enable" "Disabled,Enabled" line.long 0x08 "USBCLKDIV,USB Clock Source Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,USB clock divider values" endif group.long 0xE0++0x0B line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,SYSOSC,Watchdog oscillator,Main clock" line.long 0x04 "CLKOUTUEN,CLKOUT Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled" line.long 0x08 "CLKOUTDIV,CLKOUT Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values" sif cpuis("LPC11E6*") group.long 0xF0++0x07 line.long 0x00 "UARTFRGDIV,USART Fractional Generator Divider Value Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider" line.long 0x04 "UARTFRGMULT,USART Fractional Generator Multiplier Value Register" hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider" group.long 0xFC++0x03 line.long 0x00 "EXTTRACECMD,External Trace Buffer Command Register" bitfld.long 0x00 1. " STOP ,Trace stop command" "No effect,Stopped" bitfld.long 0x00 0. " START ,Trace start command" "No effect,Started" endif else group.long 0x48++0x13 line.long 0x00 "MAINCLKPLLSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "main_clk_pre_pll,SYS PLL,?..." line.long 0x04 "MAINCLKPLLUEN, Main Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,Main clock source update. enable" "Disabled,Enabled" line.long 0x08 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x08 0.--1. " SEL ,Clock source for main clock pre pll" "FRO,External clock,Watchdog oscillator,FRO DIV" line.long 0x0C "MAINCLKUEN,Main Clock Source Update Enable Register" bitfld.long 0x0C 0. " ENA ,Enable main clock source update" "Disabled,Enabled" line.long 0x10 "SYSAHBCLKDIV,System AHB Clock Divider Register" hexmask.long.byte 0x10 0.--7. 1. " DIV ,System AHB clock divider values" group.long 0x60++0x17 line.long 0x00 "CAPTCLKSEL,CAPT Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Clock source for CAPT clock" "FRO,main clock,SYS PLL,FRO_DIV,Watchdog oscillator,?..." line.long 0x04 "ADCCLKSEL,ADC Clock Source Select Register" bitfld.long 0x04 0.--1. " SEL ,Clock source for ADC clock" "FRO,SYS PLL,?..." line.long 0x08 "ADCCLKDIV,ADC Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,ADC clock divider values" line.long 0x0C "SCTCLKSEL,SCT Clock Source Select Register" bitfld.long 0x0C 0.--1. " SEL ,Clock source for SCT clock" "FRO,Main clock,SYS PLL,?..." line.long 0x10 "SCTCLKDIV,SCT Clock Divider Register" hexmask.long.byte 0x10 0.--7. 1. " DIV ,SCT clock divider values" line.long 0x14 "EXTCLKSEL,External Clock Source Select Register" bitfld.long 0x14 0. " SEL ,Clock source for external clock" "System oscillator,CLK_IN" newline group.long 0x80++0x3B line.long 0x00 "SYSAHBCLKCTRL0,System Clock Control 0 Register" bitfld.long 0x00 31. " UART4 ,Clock for UART4 enable" "Disabled,Enabled" bitfld.long 0x00 30. " UART3 ,Clock for UART3 enable" "Disabled,Enabled" bitfld.long 0x00 29. " DMA ,Clock for DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " GPIO_INT ,Clock for GPIO pin interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " DAC0 ,Clock for DAC0 enable" "Disabled,Enabled" bitfld.long 0x00 26. " MTB ,Clock for MTB enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " CTIMER0 ,Clock for CTIMER0 enable" "Disabled,Enabled" bitfld.long 0x00 24. " ADC ,Clock for ADC enable" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3 ,Clock for I2C3 enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " I2C2 ,Clock for I2C2 enable" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1 ,Clock for I2C1 enable" "Disabled,Enabled" bitfld.long 0x00 20. " GPIO1 ,Clock for GPIO1 port registers enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " ACMP ,Clock to analog comparator enable" "Disabled,Enabled" bitfld.long 0x00 18. " IOCON ,Clock for IOCON block enable" "Disabled,Enabled" bitfld.long 0x00 17. " WWDT ,Clock for WWDT enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " UART2 ,Clock for USART2 enable" "Disabled,Enabled" bitfld.long 0x00 15. " UART1 ,Clock for USART1 enable" "Disabled,Enabled" bitfld.long 0x00 14. " UART0 ,Clock for USART0 enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " CRC ,Clock for CRC enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPI1 ,Clock for SPI1 enable" "Disabled,Enabled" bitfld.long 0x00 11. " SPI0 ,Clock for SPI0 enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " MRT ,Clock for multi-rate timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " WKT ,Clock for self wake-up timer enable" "Disabled,Enabled" bitfld.long 0x00 8. " SCT ,Clock for state configurable timer enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SWM ,Clock for switch matrix enable" "Disabled,Enabled" bitfld.long 0x00 6. " GPIO0 ,Clock for GPIO0 port registers enable" "Disabled,Enabled" bitfld.long 0x00 5. " I2C0 ,Clock for I2C0 enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FLASH ,Clock for flash enable" "Disabled,Enabled" bitfld.long 0x00 2. " RAM0_1 ,Clock for SRAM0/SRAM1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " SYS ,Clock for AHB to APB bridge enable" ",Enabled" line.long 0x04 "SYSAHBCLKCTRL1,System Clock Control 1 Register" bitfld.long 0x04 1. " CAPT ,Clock for CAPT enable" "Disabled,Enabled" bitfld.long 0x04 0. " DAC1 ,Clock for DAC1 enable" "Disabled,Enabled" line.long 0x08 "PRESETCTRL0,Peripheral Reset Control 0 Register" bitfld.long 0x08 31. " UART4_RST_N ,UART4 reset control" "Assert,Clear" bitfld.long 0x08 30. " UART3_RST_N ,UART3 reset control" "Assert,Clear" bitfld.long 0x08 29. " DMA_RST_N ,DMA reset control" "Assert,Clear" newline bitfld.long 0x08 28. " GPIOINT_RST_N ,GPIOINT reset control" "Assert,Clear" bitfld.long 0x08 27. " DAC0_RST_N ,DAC0 reset control" "Assert,Clear" bitfld.long 0x08 25. " CTIMER0_RST_N ,CTIMER reset control" "Assert,Clear" newline bitfld.long 0x08 24. " ADC_RST_N ,ADC reset control" "Assert,Clear" bitfld.long 0x08 23. " I2C3_RST_N ,I2C3 reset control" "Assert,Clear" bitfld.long 0x08 22. " I2C2_RST_N ,I2C2 reset control" "Assert,Clear" newline bitfld.long 0x08 21. " I2C1_RST_N ,I2C1 reset control" "Assert,Clear" bitfld.long 0x08 20. " GPIO1_RST_N ,GPIO1 reset control" "Assert,Clear" bitfld.long 0x08 19. " ACMP_RST_N ,Analog comparator reset control" "Assert,Clear" newline bitfld.long 0x08 18. " IOCON_RST_N ,IOCON reset control" "Assert,Clear" bitfld.long 0x08 16. " UART2_RST_N ,UART2 reset control" "Assert,Clear" bitfld.long 0x08 15. " UART1_RST_N ,UART1 reset control" "Assert,Clear" newline bitfld.long 0x08 14. " UART0_RST_N ,UART0 reset control" "Assert,Clear" bitfld.long 0x08 13. " CRC_RST_N ,CRC reset control" "Assert,Clear" bitfld.long 0x08 12. " SPI1_RST_N ,SPI1 reset control" "Assert,Clear" newline bitfld.long 0x08 11. " SPI0_RST_N ,SPI0 reset control" "Assert,Clear" bitfld.long 0x08 10. " MRT_RST_N ,Multi-rate timer reset control" "Assert,Clear" bitfld.long 0x08 9. " WKT_RST_N ,Self-wake-up timer reset control" "Assert,Clear" newline bitfld.long 0x08 8. " SCT_RST_N ,SCT reset control" "Assert,Clear" bitfld.long 0x08 7. " SWM_RST_N ,SWM reset control" "Assert,Clear" bitfld.long 0x08 6. " GPIO0_RST_N ,GPIO0 reset control" "Assert,Clear" newline bitfld.long 0x08 5. " I2C0_RST_N ,I2C0 reset control" "Assert,Clear" bitfld.long 0x08 4. " FLASH_RST_N ,Flash controller reset control" "Assert,Clear" line.long 0x0C "PRESETCTRL1,Peripheral Reset Control 1 Register" bitfld.long 0x0C 4. " FRG1_RST_N ,Fractional baud rate generator 1 reset control" "Assert,Clear" bitfld.long 0x0C 3. " FRG0_RST_N ,Fractional baud rate generator 0 reset control" "Assert,Clear" bitfld.long 0x0C 1. " DAC1_RST_N ,DAC1 reset control" "Assert,Clear" bitfld.long 0x0C 0. " CAPT_RST_N ,Capacitive Touch reset control" "Assert,Clear" line.long 0x10 "UART0CLKSEL,UART0 Clock Source Select Register" bitfld.long 0x10 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x14 "UART1CLKSEL,UART1 Clock Source Select Register" bitfld.long 0x14 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x18 "UART2CLKSEL,UART2 Clock Source Select Register" bitfld.long 0x18 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x1C "UART3CLKSEL,UART3 Clock Source Select Register" bitfld.long 0x1C 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x20 "UART4CLKSEL,UART4 Clock Source Select Register" bitfld.long 0x20 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x24 "I2C0CLKSEL,I2C0 Clock Source Select Register" bitfld.long 0x24 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x28 "I2C1CLKSEL,I2C1 Clock Source Select Register" bitfld.long 0x28 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x2C "I2C2CLKSEL,I2C2 Clock Source Select Register" bitfld.long 0x2C 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x30 "I2C3CLKSEL,I2C3 Clock Source Select Register" bitfld.long 0x30 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x34 "SPI0CLKSEL,SPI0 Clock Source Select Register" bitfld.long 0x34 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" line.long 0x38 "SPI1CLKSEL,SPI1 Clock Source Select Register" bitfld.long 0x38 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,FRG1 clock,FRO_DIV,,,None" newline group.long 0xD0++0x0B line.long 0x00 "FRG0DIV,Fractional Generator 0 Divider Value Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider" line.long 0x04 "FRG0MULT,Fractional Generator 0 Multiplier Value Register" hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider" line.long 0x08 "FRG0CLKSEL,FRG0 Clock Source Select Register" bitfld.long 0x08 0.--1. " SEL ,FRG0_SRC clock source" "FRO,Main clock,SYS PLL,None" group.long 0xE0++0x0B line.long 0x00 "FRG1DIV,Fractional Generator 1 Divider Value Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider" line.long 0x04 "FRG1MULT,Fractional Generator 1 Multiplier Value Register" hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider" line.long 0x08 "FRG1CLKSEL,FRG0 Clock source Select Register" bitfld.long 0x08 0.--1. " SEL ,FRG0_SRC clock source" "FRO,Main clock,SYS PLL,None" group.long 0xF0++0x0B line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,CLKOUT clock source" "FRO,Main clock,SYS PLL,External clock,Watchdog oscillator,None,None,None" line.long 0x04 "CLKOUTDIV,CLKOUT Clock Divider Registers" hexmask.long.byte 0x04 0.--7. 1. " DIV ,CLKOUT clock divider values" group.long 0xFC++0x03 line.long 0x00 "EXTTRACECMD,External Trace Buffer Command Register" bitfld.long 0x00 1. " STOP ,Trace stop command" "Not stopped,Stopped" bitfld.long 0x00 0. " START ,Trace start command" "Not started,Started" newline endif newline rgroup.long 0x100++0x07 line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0" sif cpuis("LPC11E*") bitfld.long 0x00 23. " PIO0_23 ,State of PIO0_23 at power-on reset" "Low,High" newline else bitfld.long 0x00 31. " PIO0_31 ,State of PIO0_31 at power-on reset" "Low,High" bitfld.long 0x00 30. " PIO0_30 ,State of PIO0_30 at power-on reset" "Low,High" bitfld.long 0x00 29. " PIO0_29 ,State of PIO0_29 at power-on reset" "Low,High" newline bitfld.long 0x00 28. " PIO0_28 ,State of PIO0_28 at power-on reset" "Low,High" bitfld.long 0x00 27. " PIO0_27 ,State of PIO0_27 at power-on reset" "Low,High" bitfld.long 0x00 26. " PIO0_26 ,State of PIO0_26 at power-on reset" "Low,High" newline bitfld.long 0x00 25. " PIO0_25 ,State of PIO0_25 at power-on reset" "Low,High" bitfld.long 0x00 24. " PIO0_24 ,State of PIO0_24 at power-on reset" "Low,High" bitfld.long 0x00 23. " PIO0_23 ,State of PIO0_23 at power-on reset" "Low,High" newline endif bitfld.long 0x00 22. " PIO0_22 ,State of PIO0_22 at power-on reset" "Low,High" bitfld.long 0x00 21. " PIO0_21 ,State of PIO0_21 at power-on reset" "Low,High" bitfld.long 0x00 20. " PIO0_20 ,State of PIO0_20 at power-on reset" "Low,High" newline bitfld.long 0x00 19. " PIO0_19 ,State of PIO0_19 at power-on reset" "Low,High" bitfld.long 0x00 18. " PIO0_18 ,State of PIO0_18 at power-on reset" "Low,High" bitfld.long 0x00 17. " PIO0_17 ,State of PIO0_17 at power-on reset" "Low,High" newline bitfld.long 0x00 16. " PIO0_16 ,State of PIO0_16 at power-on reset" "Low,High" bitfld.long 0x00 15. " PIO0_15 ,State of PIO0_15 at power-on reset" "Low,High" bitfld.long 0x00 14. " PIO0_14 ,State of PIO0_14 at power-on reset" "Low,High" newline bitfld.long 0x00 13. " PIO0_13 ,State of PIO0_13 at power-on reset" "Low,High" bitfld.long 0x00 12. " PIO0_12 ,State of PIO0_12 at power-on reset" "Low,High" bitfld.long 0x00 11. " PIO0_11 ,State of PIO0_11 at power-on reset" "Low,High" newline bitfld.long 0x00 10. " PIO0_10 ,State of PIO0_10 at power-on reset" "Low,High" bitfld.long 0x00 9. " PIO0_9 ,State of PIO0_9 at power-on reset" "Low,High" bitfld.long 0x00 8. " PIO0_8 ,State of PIO0_8 at power-on reset" "Low,High" newline bitfld.long 0x00 7. " PIO0_7 ,State of PIO0_7 at power-on reset" "Low,High" bitfld.long 0x00 6. " PIO0_6 ,State of PIO0_6 at power-on reset" "Low,High" bitfld.long 0x00 5. " PIO0_5 ,State of PIO0_5 at power-on reset" "Low,High" newline bitfld.long 0x00 4. " PIO0_4 ,State of PIO0_4 at power-on reset" "Low,High" bitfld.long 0x00 3. " PIO0_3 ,State of PIO0_3 at power-on reset" "Low,High" bitfld.long 0x00 2. " PIO0_2 ,State of PIO0_2 at power-on reset" "Low,High" newline bitfld.long 0x00 1. " PIO0_1 ,State of PIO0_1 at power-on reset" "Low,High" bitfld.long 0x00 0. " PIO0_0 ,State of PIO0_0 at power-on reset" "Low,High" line.long 0x04 "PIOPORCAP1,POR Captured PIO Status Register 1" bitfld.long 0x04 31. " PIO1_31 ,State of PIO1_31 at power-on reset" "Low,High" bitfld.long 0x04 30. " PIO1_30 ,State of PIO1_30 at power-on reset" "Low,High" bitfld.long 0x04 29. " PIO1_29 ,State of PIO1_29 at power-on reset" "Low,High" newline bitfld.long 0x04 28. " PIO1_28 ,State of PIO1_28 at power-on reset" "Low,High" bitfld.long 0x04 27. " PIO1_27 ,State of PIO1_27 at power-on reset" "Low,High" bitfld.long 0x04 26. " PIO1_26 ,State of PIO1_26 at power-on reset" "Low,High" newline bitfld.long 0x04 25. " PIO1_25 ,State of PIO1_25 at power-on reset" "Low,High" bitfld.long 0x04 24. " PIO1_24 ,State of PIO1_24 at power-on reset" "Low,High" bitfld.long 0x04 23. " PIO1_23 ,State of PIO1_23 at power-on reset" "Low,High" newline bitfld.long 0x04 22. " PIO1_22 ,State of PIO1_22 at power-on reset" "Low,High" bitfld.long 0x04 21. " PIO1_21 ,State of PIO1_21 at power-on reset" "Low,High" bitfld.long 0x04 20. " PIO1_20 ,State of PIO1_20 at power-on reset" "Low,High" newline bitfld.long 0x04 19. " PIO1_19 ,State of PIO1_19 at power-on reset" "Low,High" bitfld.long 0x04 18. " PIO1_18 ,State of PIO1_18 at power-on reset" "Low,High" bitfld.long 0x04 17. " PIO1_17 ,State of PIO1_17 at power-on reset" "Low,High" newline bitfld.long 0x04 16. " PIO1_16 ,State of PIO1_16 at power-on reset" "Low,High" bitfld.long 0x04 15. " PIO1_15 ,State of PIO1_15 at power-on reset" "Low,High" bitfld.long 0x04 14. " PIO1_14 ,State of PIO1_14 at power-on reset" "Low,High" newline bitfld.long 0x04 13. " PIO1_13 ,State of PIO1_13 at power-on reset" "Low,High" bitfld.long 0x04 12. " PIO1_12 ,State of PIO1_12 at power-on reset" "Low,High" bitfld.long 0x04 11. " PIO1_11 ,State of PIO1_11 at power-on reset" "Low,High" newline bitfld.long 0x04 10. " PIO1_10 ,State of PIO1_10 at power-on reset" "Low,High" bitfld.long 0x04 9. " PIO1_9 ,State of PIO1_9 at power-on reset" "Low,High" bitfld.long 0x04 8. " PIO1_8 ,State of PIO1_8 at power-on reset" "Low,High" newline bitfld.long 0x04 7. " PIO1_7 ,State of PIO1_7 at power-on reset" "Low,High" bitfld.long 0x04 6. " PIO1_6 ,State of PIO1_6 at power-on reset" "Low,High" bitfld.long 0x04 5. " PIO1_5 ,State of PIO1_5 at power-on reset" "Low,High" newline bitfld.long 0x04 4. " PIO1_4 ,State of PIO1_4 at power-on reset" "Low,High" bitfld.long 0x04 3. " PIO1_3 ,State of PIO1_3 at power-on reset" "Low,High" bitfld.long 0x04 2. " PIO1_2 ,State of PIO1_2 at power-on reset" "Low,High" newline bitfld.long 0x04 1. " PIO1_1 ,State of PIO1_1 at power-on reset" "Low,High" bitfld.long 0x04 0. " PIO1_0 ,State of PIO1_0 at power-on reset" "Low,High" sif cpuis("LPC11E6*") rgroup.long 0x108++0x03 line.long 0x00 "PIOPORCAP2,POR Captured PIO Status Register 2" bitfld.long 0x00 23. " PIO0_23 ,State of PIO0_23 at power-on reset" "Low,High" newline bitfld.long 0x00 22. " PIO0_22 ,State of PIO0_22 at power-on reset" "Low,High" bitfld.long 0x00 21. " PIO0_21 ,State of PIO0_21 at power-on reset" "Low,High" bitfld.long 0x00 20. " PIO0_20 ,State of PIO0_20 at power-on reset" "Low,High" newline bitfld.long 0x00 19. " PIO0_19 ,State of PIO0_19 at power-on reset" "Low,High" bitfld.long 0x00 18. " PIO0_18 ,State of PIO0_18 at power-on reset" "Low,High" bitfld.long 0x00 17. " PIO0_17 ,State of PIO0_17 at power-on reset" "Low,High" newline bitfld.long 0x00 16. " PIO0_16 ,State of PIO0_16 at power-on reset" "Low,High" bitfld.long 0x00 15. " PIO0_15 ,State of PIO0_15 at power-on reset" "Low,High" bitfld.long 0x00 14. " PIO0_14 ,State of PIO0_14 at power-on reset" "Low,High" newline bitfld.long 0x00 13. " PIO0_13 ,State of PIO0_13 at power-on reset" "Low,High" bitfld.long 0x00 12. " PIO0_12 ,State of PIO0_12 at power-on reset" "Low,High" bitfld.long 0x00 11. " PIO0_11 ,State of PIO0_11 at power-on reset" "Low,High" newline bitfld.long 0x00 10. " PIO0_10 ,State of PIO0_10 at power-on reset" "Low,High" bitfld.long 0x00 9. " PIO0_9 ,State of PIO0_9 at power-on reset" "Low,High" bitfld.long 0x00 8. " PIO0_8 ,State of PIO0_8 at power-on reset" "Low,High" newline bitfld.long 0x00 7. " PIO0_7 ,State of PIO0_7 at power-on reset" "Low,High" bitfld.long 0x00 6. " PIO0_6 ,State of PIO0_6 at power-on reset" "Low,High" bitfld.long 0x00 5. " PIO0_5 ,State of PIO0_5 at power-on reset" "Low,High" newline bitfld.long 0x00 4. " PIO0_4 ,State of PIO0_4 at power-on reset" "Low,High" bitfld.long 0x00 3. " PIO0_3 ,State of PIO0_3 at power-on reset" "Low,High" bitfld.long 0x00 2. " PIO0_2 ,State of PIO0_2 at power-on reset" "Low,High" newline bitfld.long 0x00 1. " PIO0_1 ,State of PIO0_1 at power-on reset" "Low,High" bitfld.long 0x00 0. " PIO0_0 ,State of PIO0_0 at power-on reset" "Low,High" endif newline sif cpuis("LPC11E6*") group.long 0x134++0x03 line.long 0x00 "IOCONCLKDIV6,IOCON Glitch Filter Clock Divider Register 6" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x138++0x03 line.long 0x00 "IOCONCLKDIV5,IOCON Glitch Filter Clock Divider Register 5" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x13C++0x03 line.long 0x00 "IOCONCLKDIV4,IOCON Glitch Filter Clock Divider Register 4" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x140++0x03 line.long 0x00 "IOCONCLKDIV3,IOCON Glitch Filter Clock Divider Register 3" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x144++0x03 line.long 0x00 "IOCONCLKDIV2,IOCON Glitch Filter Clock Divider Register 2" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x148++0x03 line.long 0x00 "IOCONCLKDIV1,IOCON Glitch Filter Clock Divider Register 1" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x14C++0x03 line.long 0x00 "IOCONCLKDIV0,IOCON Glitch Filter Clock Divider Register 0" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" endif newline group.long 0x150++0x07 line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" sif cpuis("LPC11E*") sif cpuis("LPC11E6*") bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",,Level 2,Level 3" else bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",Level 1,Level 2,Level 3" endif bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "Level 0,Level 1,Level 2,Level 3" else newline bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",Level 1,Level 2,Level 3" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" ",Level 1,Level 2,Level 3" endif line.long 0x04 "SYSTCKCAL,System Tick Counter Calibration Register" hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value" group.long 0x170++0x07 line.long 0x00 "IRQLATENCY,IRQ Latency Register" hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value" line.long 0x04 "NMISRC,NMI Source Selection Register" bitfld.long 0x04 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled" sif cpuis("LPC11E*") bitfld.long 0x04 0.--4. " IRQN ,IRQ number of the interrupt" "PIN_INT0,PIN_INT1,PIN_INT2,PIN_INT3,PIN_INT4,PIN_INT5,PIN_INT6,PIN_INT7,GINT0,GINT1,I2C1,USART1_4,USART2_3,SCT0_1,SSP1,I2C0,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART0,USB_IRQ,USB_FIQ,ADC_A,RTC,BOD_WDT,FLASH,DMA,ADC_B,ADC_WAKEUP,?..." else newline bitfld.long 0x04 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0_IRQ,SPI1_IRQ,DAC0_IRQ,UART0_IRQ,UART1_IRQ,UART2_IRQ,,I2C1_IRQ,I2C0_IRQ,SCT_IRQ,MRT_IRQ,CMP_IRQ/CAPT_IRQ,WDT_IRQ,BOD_IRQ,FLASH_IRQ,WKT_IRQ,ADC_SEQA_IRQ,ADC_SEQB_IRQ,ADC_THCMP_IRQ,ADC_OVR_IRQ,DMA_IRQ,I2C2_IRQ,I2C3_IRQ,CT32B0_IRQ,PININT0_IRQ,PININT1_IRQ,PININT2_IRQ,PININT3_IRQ,PININT4_IRQ,PININT5_IRQ/DAC1_IRQ,PININT6_IRQ/USART3_IRQ,PININT7_IRQ/USART4_IRQ" endif newline group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" sif cpuis("LPC11E*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,PIO0_31,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31" endif newline sif cpuis("LPC11E6*") group.long 0x198++0x03 line.long 0x00 "USBCLKCTRL,USB Clock Control Register" bitfld.long 0x00 1. " POL_CLK ,USB polarity clock control" "Falling edge,Rising edge" bitfld.long 0x00 0. " AP_CLK ,USB signal clock control" "Hardware,Forced" rgroup.long 0x19C++0x03 line.long 0x00 "USBCLKST,USB Clock Status Register" bitfld.long 0x00 0. " NEED_CLKST ,USB need_clock signal status" "Low,High" endif newline group.long 0x204++0x03 line.long 0x00 "STARTERP0,Start Logic 0 Interrupt Wake-Up Enable Register 0" bitfld.long 0x00 7. " PINT7 ,GPIO pin interrupt 7 wake-up" "Disabled,Enabled" bitfld.long 0x00 6. " PINT6 ,GPIO pin interrupt 6 wake-up" "Disabled,Enabled" bitfld.long 0x00 5. " PINT5 ,GPIO pin interrupt 5 wake-up" "Disabled,Enabled" newline bitfld.long 0x00 4. " PINT4 ,GPIO pin interrupt 4 wake-up" "Disabled,Enabled" bitfld.long 0x00 3. " PINT3 ,GPIO pin interrupt 3 wake-up" "Disabled,Enabled" bitfld.long 0x00 2. " PINT2 ,GPIO pin interrupt 2 wake-up" "Disabled,Enabled" newline bitfld.long 0x00 1. " PINT1 ,GPIO pin interrupt 1 wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " PINT0 ,GPIO pin interrupt 0 wake-up" "Disabled,Enabled" sif cpuis("LPC11E*") group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-Up Enable Register 1" bitfld.long 0x00 24. " USART2_3 ,Combined USART2 and USART3 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 23. " USART1_4 ,Combined USART1 and USART4 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 21. " GROUP1INT ,GPIO GROUP1 interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 20. " GROUP0INT ,GPIO GROUP0 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 19. " USB_WAKEUP ,USB need_clock signal wake-up" "Disabled,Enabled" bitfld.long 0x00 13. " WWDT_BODINT ,Combined WWDT interrupt or BOD interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 12. " RTCINT ,RTC interrupt wake-up" "Disabled,Enabled" else group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1" bitfld.long 0x00 31. " USART4 ,USART4 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 30. " USART3 ,USART3 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 22. " I2C3 ,I2C3 interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 21. " I2C2 ,I2C2 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 15. " WKT ,Self wake-up timer wake-up" "Disabled,Enabled" bitfld.long 0x00 13. " BOD ,BOD interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 12. " WWDT ,WWDT interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 11. " Cap_Touch ,Cap Touch interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 8. " I2C0 ,I2C0 interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 7. " I2C1 ,I2C1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 5. " USART2 ,USART2 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 4. " USART1 ,USART1 interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 3. " USART0 ,USART0 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 1. " SPI1 ,SPI1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " SPI0 ,SPI0 interrupt wake-up" "Disabled,Enabled" endif newline group.long 0x230++0x03 line.long 0x00 "PDSLEEPCFG,Deep-sleep Configuration Register" bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down" sif cpuis("LPC11E*") group.long 0x234++0x07 line.long 0x00 "PDAWAKECFG,Wake-up Configuration Register" sif cpuis("LPC11E6*") bitfld.long 0x00 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down" bitfld.long 0x00 10. " USBPAD_PD ,USB transceiver wake-up configuration" "Powered,Powered down" bitfld.long 0x00 8. " USBPLL_PD ,USB PLL wake-up configuration" "Powered,Powered down" newline endif bitfld.long 0x00 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down" bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x00 5. " SYSOSC_PD ,Crystal oscillator wake-up configuration" "Powered,Powered down" newline bitfld.long 0x00 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down" bitfld.long 0x00 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down" newline bitfld.long 0x00 1. " IRC_PD ,IRC oscillator power-down wake-up configuration" "Powered,Powered down" bitfld.long 0x00 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down" line.long 0x04 "PDRUNCFG,Power Configuration Register" sif cpuis("LPC11E6*") bitfld.long 0x04 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down" bitfld.long 0x04 10. " USBPAD_PD ,USB transceiver power-down configuration" "Powered,Powered down" bitfld.long 0x04 8. " USBPLL_PD ,USB PLL power-down configuration" "Powered,Powered down" newline endif bitfld.long 0x04 7. " SYSPLL_PD ,System PLL power-down configuration" "Powered,Powered down" bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator power-down configuration" "Powered,Powered down" bitfld.long 0x04 5. " SYSOSC_PD ,Crystal oscillator power-down configuration" "Powered,Powered down" newline bitfld.long 0x04 4. " ADC_PD ,ADP power-down configuration" "Powered,Powered down" bitfld.long 0x04 3. " BOD_PD ,BOD power-down configuration" "Powered,Powered down" bitfld.long 0x04 2. " FLASH_PD ,Flash power-down configuration" "Powered,Powered down" newline bitfld.long 0x04 1. " IRC_PD ,IRC oscillator power-down configuration" "Powered,Powered down" bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output power-down configuration" "Powered,Powered down" else group.long 0x234++0x07 line.long 0x00 "PDAWAKECFG,Wake-up Configuration Register" bitfld.long 0x00 15. " ACMP ,Analog comparator wake-up configuration" "Powered,Powered down" bitfld.long 0x00 14. " DAC1 ,DAC1 wake-up configuration" "Powered,Powered down" bitfld.long 0x00 13. " DAC0 ,DAC0 wake-up configuration" "Powered,Powered down" newline bitfld.long 0x00 10. " VREF2_PD ,VREF2 wake-up configuration" "Powered,Powered down" bitfld.long 0x00 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down" bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down" newline bitfld.long 0x00 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x00 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down" newline bitfld.long 0x00 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down" bitfld.long 0x00 1. " FRO_PD ,FRO oscillator power-down wake-up configuration" "Powered,Powered down" bitfld.long 0x00 0. " FROOUT_PD ,FRO oscillator output wake-up configuration" "Powered,Powered down" line.long 0x04 "PDRUNCFG,Power Configuration Register" bitfld.long 0x04 15. " ACMP ,Analog comparator power down" "Powered,Powered down" bitfld.long 0x04 14. " DAC1 ,DAC1 power down" "Powered,Powered down" bitfld.long 0x04 13. " DAC0 ,DAC0 power down" "Powered,Powered down" newline bitfld.long 0x04 7. " SYSPLL_PD ,System PLL power down" "Powered,Powered down" bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator power down" "Powered,Powered down" bitfld.long 0x04 5. " SYSOSC_PD ,Crystal oscillator power down" "Powered,Powered down" newline bitfld.long 0x04 4. " ADC_PD ,ADC power down" "Powered,Powered down" bitfld.long 0x04 3. " BOD_PD ,BOD power down" "Powered,Powered down" bitfld.long 0x04 2. " FLASH_PD ,Flash power down" "Powered,Powered down" newline bitfld.long 0x04 1. " FRO_PD ,FRO oscillator power down" "Powered,Powered down" bitfld.long 0x04 0. " FROOUT_PD ,FRO oscillator output power down" "Powered,Powered down" endif sif cpuis("LPC11E*") newline rgroup.long 0x3F8++0x03 line.long 0x00 "DEVICE_ID,Device ID" endif width 0x0B tree.end elif (cpuis("LPC80*")) tree "SYSCON (System Configuration)" base ad:0x40048000 width 16. group.long 0x00++0x03 line.long 0x00 "SYSMEMREMAP,System Memory Remap Register" bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Bootloader,RAM,Flash,?..." group.long 0x38++0x03 line.long 0x00 "SYSRSTSTAT,System Reset Status Register" eventfld.long 0x00 4. " SYSRST ,Software system reset status" "No reset,Reset" eventfld.long 0x00 2. " WDT ,Watchdog reset status" "No reset,Reset" eventfld.long 0x00 1. " EXTRST ,External reset status" "No reset,Reset" eventfld.long 0x00 0. " POR_BOD ,POR and BOD reset status" "No reset,Reset" group.long 0x50++0x0B line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock pre pll" "FRO,External clock,Low power oscillator,FRO_DIV" line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled" line.long 0x08 "SYSAHBCLKDIV,System Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values" sif (cpuis("LPC804M*")) group.long 0x60++0x03 line.long 0x00 "CAPTCLKSEL,CAPT Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,,FRO_DIV=FRO/2,Low power oscillator,,,None" endif group.long 0x64++0x07 line.long 0x00 "ADCCLKSEL,ADC Clock Source Select Register" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--1. " SEL ,Clock source for ADC clock" "FRO,External clock,,None" else bitfld.long 0x00 0.--1. " SEL ,Clock source for ADC clock" "FRO,External clock,None,None" endif line.long 0x04 "ADCCLKDIV,ADC Clock Divider Register" hexmask.long.byte 0x04 0.--7. 1. " DIV ,ADC clock divider values" group.long 0x7C++0x07 line.long 0x00 "LPOSCCLKEN, WDT And Wake Timer Clock Enable Control Register" bitfld.long 0x00 1. " WKT ,Enable clock for Wake Timer" "Disabled,Enabled" bitfld.long 0x00 0. " WDT ,Enable clock for WDT" "Disabled,Enabled" line.long 0x04 "SYSAHBCLKCTRL0,System Clock Control 0 Register" bitfld.long 0x04 28. " GPIO_INT ,Clock for GPIO pin interrupt enable" "Disabled,Enabled" newline sif (cpuis("LPC804M*")) bitfld.long 0x04 27. " DAC ,Clock for DAC enable" "Disabled,Enabled" newline endif bitfld.long 0x04 25. " CTIMER0 ,Clock for CTIMER0 enable" "Disabled,Enabled" bitfld.long 0x04 24. " ADC ,Clock for ADC enable" "Disabled,Enabled" newline sif (cpuis("LPC804M*")) bitfld.long 0x04 21. " I2C1 ,Clock for I2C1 enable" "Disabled,Enabled" newline endif bitfld.long 0x04 19. " ACMP ,Clock to analog comparator enable" "Disabled,Enabled" bitfld.long 0x04 18. " IOCON ,Clock for IOCON block enable" "Disabled,Enabled" bitfld.long 0x04 17. " WWDT ,Clock for WWDT enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " UART1 ,Clock for USART1 enable" "Disabled,Enabled" bitfld.long 0x04 14. " UART0 ,Clock for USART0 enable" "Disabled,Enabled" bitfld.long 0x04 13. " CRC ,Clock for CRC enable" "Disabled,Enabled" bitfld.long 0x04 11. " SPI0 ,Clock for SPI0 enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " MRT ,Clock for multi-rate timer enable" "Disabled,Enabled" bitfld.long 0x04 9. " WKT ,Clock for self wake-up timer enable" "Disabled,Enabled" bitfld.long 0x04 7. " SWM ,Clock for switch matrix enable" "Disabled,Enabled" bitfld.long 0x04 6. " GPIO0 ,Clock for GPIO0 port registers enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " I2C0 ,Clock for I2C0 enable" "Disabled,Enabled" bitfld.long 0x04 4. " FLASH ,Clock for flash enable" "Disabled,Enabled" bitfld.long 0x04 2. " RAM0 ,Clock for SRAM0 enable" "Disabled,Enabled" bitfld.long 0x04 1. " ROM ,Clock for ROM enable" "Disabled,Enabled" newline rbitfld.long 0x04 0. " SYS ,Clock for AHB to APB bridge enable" ",Enabled" sif (cpuis("LPC804M*")) group.long 0x84++0x03 line.long 0x00 "SYSAHBCLKCTRL1,System Clock Control Register 1" bitfld.long 0x00 5. " PLU ,Clock for PLU enable" "Disabled,Enabled" bitfld.long 0x00 0. " CAPT ,Clock for CAPT enable" "Disabled,Enabled" endif group.long 0x88++0x07 line.long 0x00 "PRESETCTRL0,Peripheral Reset Control 0 Register" bitfld.long 0x00 28. " GPIOINT_RST_N ,GPIOINT reset control" "Assert,Clear" newline sif (cpuis("LPC804M*")) bitfld.long 0x00 27. " DAC0_RST_N ,DAC0 reset control" "Assert,Clear" newline endif bitfld.long 0x00 25. " CTIMER0_RST_N ,CTIMER reset control" "Assert,Clear" bitfld.long 0x00 24. " ADC_RST_N ,ADC reset control" "Assert,Clear" newline sif (cpuis("LPC804M*")) bitfld.long 0x00 21. " I2C1_RST_N ,I2C1 reset control" "Assert,Clear" newline endif bitfld.long 0x00 19. " ACMP_RST_N ,Analog comparator reset control" "Assert,Clear" bitfld.long 0x00 18. " IOCON_RST_N ,IOCON reset control" "Assert,Clear" bitfld.long 0x00 15. " UART1_RST_N ,UART1 reset control" "Assert,Clear" newline bitfld.long 0x00 14. " UART0_RST_N ,UART0 reset control" "Assert,Clear" bitfld.long 0x00 13. " CRC_RST_N ,CRC reset control" "Assert,Clear" bitfld.long 0x00 11. " SPI0_RST_N ,SPI0 reset control" "Assert,Clear" bitfld.long 0x00 10. " MRT_RST_N ,Multi-rate timer reset control" "Assert,Clear" newline bitfld.long 0x00 9. " WKT_RST_N ,Self-wake-up timer reset control" "Assert,Clear" bitfld.long 0x00 7. " SWM_RST_N ,SWM reset control" "Assert,Clear" bitfld.long 0x00 6. " GPIO0_RST_N ,GPIO0 reset control" "Assert,Clear" bitfld.long 0x00 5. " I2C0_RST_N ,I2C0 reset control" "Assert,Clear" newline bitfld.long 0x00 4. " FLASH_RST_N ,Flash controller reset control" "Assert,Clear" line.long 0x04 "PRESETCTRL1,Peripheral Reset Control 1 Register" sif (cpuis("LPC804M*")) bitfld.long 0x04 5. " PLU_RST_N ,PLU reset control" "Assert,Clear" newline endif bitfld.long 0x04 3. " FRG0_RST_N ,Fractional baud rate generator 0 reset control" "Assert,Clear" sif (cpuis("LPC804M*")) newline bitfld.long 0x04 0. " CAPT_RST_N ,Capacitive touch reset control" "Assert,Clear" endif sif (cpuis("LPC804M*")) group.long 0x90++0x07 line.long 0x00 "UART0CLKSEL,UART0 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,,FRO_DIV,,,None" line.long 0x04 "UART1CLKSEL,UART1 Clock Source Select Register" bitfld.long 0x04 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,,FRO_DIV,,,None" group.long 0xA4++0x03 line.long 0x00 "I2C0CLKSEL,I2C0 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,,FRO_DIV,,,None" group.long 0x80A8++0x03 line.long 0x00 "I2C1CLKSEL,I2C1 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,,FRO_DIV,,,None" group.long 0xB4++0x03 line.long 0x00 "SPI0CLKSEL,SPI0 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,,FRO_DIV,,,None" else group.long 0x90++0x07 line.long 0x00 "UART0CLKSEL,UART0 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,None,FRO_DIV,,,None" line.long 0x04 "UART1CLKSEL,UART1 Clock Source Select Register" bitfld.long 0x04 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,None,FRO_DIV,,,None" group.long 0xA4++0x03 line.long 0x00 "I2C0CLKSEL,I2C0 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,None,FRO_DIV,,,None" group.long 0xB4++0x03 line.long 0x00 "SPI0CLKSEL,SPI0 Clock Source Select Register" bitfld.long 0x00 0.--2. " SEL ,Peripheral clock source" "FRO,Main clock,FRG0 clock,None,FRO_DIV,,,None" endif group.long 0xD0++0x0B line.long 0x00 "FRG0DIV,Fractional Generator 0 Divider Value Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider" line.long 0x04 "FRG0MULT,Fractional Generator 0 Multiplier Value Register" hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider" line.long 0x08 "FRG0CLKSEL,FRG0 Clock Source Select Register" sif (cpuis("LPC804M*")) bitfld.long 0x08 0.--1. " SEL ,FRG0_SRC clock source" "FRO,Main clock,,None" else bitfld.long 0x08 0.--1. " SEL ,FRG0_SRC clock source" "FRO,Main clock,None,None" endif group.long 0xF0++0x0B line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--2. " SEL ,CLKOUT clock source" "FRO,Main clock,,External clock,Low power oscillator,,,None" else bitfld.long 0x00 0.--2. " SEL ,CLKOUT clock source" "FRO,Main clock,None,External clock,Low power oscillator,None,None,None" endif line.long 0x04 "CLKOUTDIV,CLKOUT Clock Divider Registers" hexmask.long.byte 0x04 0.--7. 1. " DIV ,CLKOUT clock divider values" rgroup.long 0x100++0x03 line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0" sif (cpuis("LPC804M*")) bitfld.long 0x00 30. " PIOSTAT[30] ,State of PIO0_30 at power-on reset" "Low,High" newline bitfld.long 0x00 29. " [29] ,State of PIO0_29 at power-on reset" "Low,High" bitfld.long 0x00 28. " [28] ,State of PIO0_28 at power-on reset" "Low,High" bitfld.long 0x00 27. " [27] ,State of PIO0_27 at power-on reset" "Low,High" newline bitfld.long 0x00 26. " [26] ,State of PIO0_26 at power-on reset" "Low,High" bitfld.long 0x00 25. " [25] ,State of PIO0_25 at power-on reset" "Low,High" bitfld.long 0x00 24. " [24] ,State of PIO0_24 at power-on reset" "Low,High" newline bitfld.long 0x00 23. " [23] ,State of PIO0_23 at power-on reset" "Low,High" bitfld.long 0x00 22. " [22] ,State of PIO0_22 at power-on reset" "Low,High" bitfld.long 0x00 21. " [21] ,State of PIO0_21 at power-on reset" "Low,High" newline bitfld.long 0x00 20. " [20] ,State of PIO0_20 at power-on reset" "Low,High" bitfld.long 0x00 19. " [19] ,State of PIO0_19 at power-on reset" "Low,High" bitfld.long 0x00 18. " [18] ,State of PIO0_18 at power-on reset" "Low,High" newline bitfld.long 0x00 17. " [17] ,State of PIO0_17 at power-on reset" "Low,High" else bitfld.long 0x00 17. " PIOSTAT[17] ,State of PIO0_17 at power-on reset" "Low,High" endif bitfld.long 0x00 16. " [16] ,State of PIO0_16 at power-on reset" "Low,High" bitfld.long 0x00 15. " [15] ,State of PIO0_15 at power-on reset" "Low,High" newline bitfld.long 0x00 14. " [14] ,State of PIO0_14 at power-on reset" "Low,High" bitfld.long 0x00 13. " [13] ,State of PIO0_13 at power-on reset" "Low,High" bitfld.long 0x00 12. " [12] ,State of PIO0_12 at power-on reset" "Low,High" newline bitfld.long 0x00 11. " [11] ,State of PIO0_11 at power-on reset" "Low,High" bitfld.long 0x00 10. " [10] ,State of PIO0_10 at power-on reset" "Low,High" bitfld.long 0x00 9. " [9] ,State of PIO0_9 at power-on reset" "Low,High" newline bitfld.long 0x00 8. " [8] ,State of PIO0_8 at power-on reset" "Low,High" bitfld.long 0x00 7. " [7] ,State of PIO0_7 at power-on reset" "Low,High" bitfld.long 0x00 5. " [5] ,State of PIO0_5 at power-on reset" "Low,High" newline bitfld.long 0x00 4. " [4] ,State of PIO0_4 at power-on reset" "Low,High" bitfld.long 0x00 3. " [3] ,State of PIO0_3 at power-on reset" "Low,High" bitfld.long 0x00 2. " [2] ,State of PIO0_2 at power-on reset" "Low,High" newline bitfld.long 0x00 1. " [1] ,State of PIO0_1 at power-on reset" "Low,High" bitfld.long 0x00 0. " [0] ,State of PIO0_0 at power-on reset" "Low,High" group.long 0x150++0x07 line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",Level 1,Level 2,Level 3" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "Level 0,?..." line.long 0x04 "SYSTCKCAL,System Tick Timer Calibration Register" hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value" group.long 0x170++0x07 line.long 0x00 "IRQLATENCY,IRQ Latency Register" hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value" line.long 0x04 "NMISRC,NMI Source Selection Register" bitfld.long 0x04 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled" sif (cpuis("LPC804M*")) bitfld.long 0x04 0.--4. " IRQN ,IRQ number of the interrupt" "SPI0_IRQ,,DAC0_IRQ,UART0_IRQ,UART1_IRQ,,,I2C1_IRQ,I2C0_IRQ,,MRT_IRQ,CMP_IRQ/CAPT_IRQ,WDT_IRQ,BOD_IRQ,,WKT_IRQ,ADC_SEQA_IRQ,ADC_SEQB_IRQ,ADC_THCMP_IRQ,ADC_OVR_IRQ,,,,CT32B0_IRQ,PININT0_IRQ,PININT1_IRQ,PININT2_IRQ,PININT3_IRQ,PININT4_IRQ,PININT5_IRQ,PININT6_IRQ,PININT7_IRQ" else bitfld.long 0x04 0.--4. " IRQN ,IRQ number of the interrupt" "SPI0_IRQ,,,UART0_IRQ,UART1_IRQ,,,,I2C0_IRQ,,MRT_IRQ,CMP_IRQ,WDT_IRQ,BOD_IRQ,,WKT_IRQ,ADC_SEQA_IRQ,ADC_SEQB_IRQ,ADC_THCMP_IRQ,ADC_OVR_IRQ,,,,CT32B0_IRQ,PININT0_IRQ,PININT1_IRQ,PININT2_IRQ,PININT3_IRQ,PININT4_IRQ,PININT5_IRQ,PININT6_IRQ,PININT7_IRQ" endif group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" sif (cpuis("LPC804M*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,PIO0_29,PIO0_30,?..." else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." endif group.long 0x204++0x03 line.long 0x00 "STARTERP0,Start Logic Signal Enable Register 0" bitfld.long 0x00 7. " PINT7 ,GPIO pin interrupt 7 wake-up" "Disabled,Enabled" bitfld.long 0x00 6. " PINT6 ,GPIO pin interrupt 6 wake-up" "Disabled,Enabled" bitfld.long 0x00 5. " PINT5 ,GPIO pin interrupt 5 wake-up" "Disabled,Enabled" newline bitfld.long 0x00 4. " PINT4 ,GPIO pin interrupt 4 wake-up" "Disabled,Enabled" bitfld.long 0x00 3. " PINT3 ,GPIO pin interrupt 3 wake-up" "Disabled,Enabled" bitfld.long 0x00 2. " PINT2 ,GPIO pin interrupt 2 wake-up" "Disabled,Enabled" newline bitfld.long 0x00 1. " PINT1 ,GPIO pin interrupt 1 wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " PINT0 ,GPIO pin interrupt 0 wake-up" "Disabled,Enabled" group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1" bitfld.long 0x00 15. " WKT ,Self wake-up timer wake-up" "Disabled,Enabled" bitfld.long 0x00 13. " BOD ,BOD interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 12. " WWDT ,WWDT interrupt wake-up" "Disabled,Enabled" newline sif (cpuis("LPC804M*")) bitfld.long 0x00 11. " CAPT ,CAPT interrupt wake-up" "Disabled,Enabled" newline endif bitfld.long 0x00 8. " I2C0 ,I2C0 interrupt wake-up" "Disabled,Enabled" newline sif (cpuis("LPC804M*")) bitfld.long 0x00 7. " I2C1 ,I2C1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 6. " PLU ,PLU interrupt wake-up" "Disabled,Enabled" newline endif bitfld.long 0x00 4. " USART1 ,USART1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 3. " USART0 ,USART0 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " SPI0 ,SPI0 interrupt wake-up" "Disabled,Enabled" group.long 0x230++0x0B line.long 0x00 "PDSLEEPCFG,Deep-sleep Configuration Register" bitfld.long 0x00 6. " LPOSC_PD ,Low power oscillator power-down control" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down" line.long 0x04 "PDAWAKECFG,Wake-up Configuration Register" bitfld.long 0x04 15. " ACMP ,Analog comparator wake-up configuration" "Powered,Powered down" sif (cpuis("LPC804M*")) newline bitfld.long 0x04 13. " DAC0 ,DAC0 wake-up configuration" "Powered,Powered down" endif newline bitfld.long 0x04 6. " LPOSC_PD ,Low power oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down" bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down" newline bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down" bitfld.long 0x04 1. " FRO_PD ,FRO oscillator power-down wake-up configuration" "Powered,Powered down" bitfld.long 0x04 0. " FROOUT_PD ,FRO oscillator output wake-up configuration" "Powered,Powered down" line.long 0x08 "PDRUNCFG,Power Configuration Register" bitfld.long 0x08 15. " ACMP ,Analog comparator power down" "Powered,Powered down" sif (cpuis("LPC804M*")) newline bitfld.long 0x08 13. " DAC0 ,DAC0 wake-up configuration" "Powered,Powered down" endif newline bitfld.long 0x08 6. " LPOSC_PD ,Low power oscillator power down" "Powered,Powered down" bitfld.long 0x08 4. " ADC_PD ,ADC power down" "Powered,Powered down" bitfld.long 0x08 3. " BOD_PD ,BOD power down" "Powered,Powered down" newline bitfld.long 0x08 2. " FLASH_PD ,Flash power down" "Powered,Powered down" bitfld.long 0x08 1. " FRO_PD ,FRO oscillator power down" "Powered,Powered down" bitfld.long 0x08 0. " FROOUT_PD ,FRO oscillator output power down" "Powered,Powered down" rgroup.long 0x3F8++0x03 line.long 0x00 "DEVICEID ,Part Identification Number" width 0x0B tree.end elif (cpuis("LPC8N04")) tree "SYSCON (System Configuration)" base ad:0x40048000 width 16. group.long 0x00++0x07 line.long 0x00 "SYSMEMREMAP,System Memory Remap Register" hexmask.long.byte 0x00 1.--5. 0x02 " OFFSET ,System memory remap offset" bitfld.long 0x00 0. " MAP ,Interrupt vector remap" "Flash,SRAM" line.long 0x04 "PRESETCTRL, Peripheral Reset Control Register" bitfld.long 0x04 3. " NFC_RST_N ,NFC shared memory reset control" "Reset,No reset" bitfld.long 0x04 2. " EE_RST_N ,EEPROM NVMC reset control" "Reset,No reset" bitfld.long 0x04 1. " I2C_RST_N ,I2C-bus reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP_RST_N ,SPI/SSP reset control" "Reset,No reset" group.long 0x20++0x07 line.long 0x00 "SYSCLKCTRL,System Clock Control Register" bitfld.long 0x00 16.--21. " SYSCLKTRIM ,SFRO trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--3. " SYSCLKDIV ,System clock divider" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "SYSCLKUEN, System Clock Update Enable Register" bitfld.long 0x04 0. " ENA ,Enable system clock source update" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "SYSRSTSTAT,System Reset Status Register" bitfld.long 0x00 3. " SYSRST ,Status of software system reset" "No reset,Reset" bitfld.long 0x00 2. " WDT ,Status of the Watchdog reset" "No reset,Reset" bitfld.long 0x00 1. " EXTRST ,Status of external RESETn pin" "No reset,Reset" bitfld.long 0x00 0. " POR ,Status of external RESETN pin" "No reset,Reset" group.long 0x80++0x03 line.long 0x00 "SYSAHBCLKCTRL,AHB Clock Control Register" bitfld.long 0x00 19.--20. " EEREG/EEARRAY ,Enable clock for EEPROM register interface and array access" "Disabled,Enabled,Enabled,Enabled" bitfld.long 0x00 18. " IOCON ,Enable clock for I/O configuration block" "Disabled,Enabled" bitfld.long 0x00 12. " TSEN ,Enable clock for temperature sensor" "Disabled,Enabled" bitfld.long 0x00 11. " WDT ,Enable clock for watchdog timer" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RTC ,Enable clock for RTC" "Disabled,Enabled" bitfld.long 0x00 9. " CT32B ,Enable clock for 32-bit timer" "Disabled,Enabled" bitfld.long 0x00 8. " CT16B ,Enable clock for 16-bit timer" "Disabled,Enabled" bitfld.long 0x00 7. " SPISSP ,Enable clock for SPI/SSP" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " GPIO ,Enable clock for GPIO" "Disabled,Enabled" bitfld.long 0x00 5. " I2C ,Enable clock for I2C-bus" "Disabled,Enabled" bitfld.long 0x00 3.--4. " FLASHREG/FLASHARRAY ,Enable clock for Flash register interface and array access" "Disabled,Enabled,Enabled,Enabled" bitfld.long 0x00 2. " RAM ,Enable clock for RAM" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "SSPCLKDIV,SPI/SSP Clock Divider Control Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,SPI_CLK clock divider values" group.long 0xD0++0x0F line.long 0x00 "WDTCLKSEL,Watchdog Timer Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,WDT clock source" "system FRO,,Disabled,?..." line.long 0x04 "WDTCLKUEN,WDT Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,WDT clock source update enable" "Disabled,Enabled" line.long 0x08 "WDTCLKDIV,WDT Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,WDT clock divider values" group.long 0xE8++0x03 line.long 0x00 "CLKOUTEN,Clock Output Enable Register" bitfld.long 0x00 1.--2. " CLKOUTSRC ,Clock output source" "SFRO,System clock,TFRO,NFC clock" bitfld.long 0x00 0. " CLKOUTEN ,Clock output enable" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "SYSTCKCAL,System Tick Counter Calibration Register" hexmask.long 0x00 0.--25. 1. " CAL ,System tick timer calibration value" group.long 0x200++0x0F line.long 0x00 "STARTAPRP0,Start Logic Edge Control Register 0" bitfld.long 0x00 10. " APRPIO_10 ,Edge select for start logic input PIO0_10" "Falling,Rising" bitfld.long 0x00 9. " APRPIO_9 ,Edge select for start logic input PIO0_9" "Falling,Rising" bitfld.long 0x00 8. " APRPIO_8 ,Edge select for start logic input PIO0_8" "Falling,Rising" bitfld.long 0x00 7. " APRPIO_7 ,Edge select for start logic input PIO0_7" "Falling,Rising" textline " " bitfld.long 0x00 6. " APRPIO_6 ,Edge select for start logic input PIO0_6" "Falling,Rising" bitfld.long 0x00 5. " APRPIO_5 ,Edge select for start logic input PIO0_5" "Falling,Rising" bitfld.long 0x00 4. " APRPIO_4 ,Edge select for start logic input PIO0_4" "Falling,Rising" bitfld.long 0x00 3. " APRPIO_3 ,Edge select for start logic input PIO0_3" "Falling,Rising" textline " " bitfld.long 0x00 2. " APRPIO_2 ,Edge select for start logic input PIO0_2" "Falling,Rising" bitfld.long 0x00 1. " APRPIO_1 ,Edge select for start logic input PIO0_1" "Falling,Rising" bitfld.long 0x00 0. " APRPIO_0 ,Edge select for start logic input PIO0_0" "Falling,Rising" line.long 0x04 "STARTERP0,Start Logic Signal Enable Register 0" bitfld.long 0x04 12. " ERTMR ,Enable start signal for start logic input RTC timer" "Disabled,Enabled" bitfld.long 0x04 11. " ERRFID ,Enable start signal for start logic input RFID" "Disabled,Enabled" bitfld.long 0x04 10. " ERPIO_10 ,Enable start signal for start logic input PIO0_10" "Disabled,Enabled" bitfld.long 0x04 9. " ERPIO_9 ,Enable start signal for start logic input PIO0_9" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " ERPIO_8 ,Enable start signal for start logic input PIO0_8" "Disabled,Enabled" bitfld.long 0x04 7. " ERPIO_7 ,Enable start signal for start logic input PIO0_7" "Disabled,Enabled" bitfld.long 0x04 6. " ERPIO_6 ,Enable start signal for start logic input PIO0_6" "Disabled,Enabled" bitfld.long 0x04 5. " ERPIO_5 ,Enable start signal for start logic input PIO0_5" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " ERPIO_4 ,Enable start signal for start logic input PIO0_4" "Disabled,Enabled" bitfld.long 0x04 3. " ERPIO_3 ,Enable start signal for start logic input PIO0_3" "Disabled,Enabled" bitfld.long 0x04 2. " ERPIO_2 ,Enable start signal for start logic input PIO0_2" "Disabled,Enabled" bitfld.long 0x04 1. " ERPIO_1 ,Enable start signal for start logic input PIO0_1" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ERPIO_0 ,Enable start signal for start logic input PIO0_0" "Disabled,Enabled" line.long 0x08 "STARTRSRP0CLR,Start Logic Reset Register 0" bitfld.long 0x08 12. " RSRTMR ,Start signal reset for start logic input wake-up timer" "No reset,Reset" bitfld.long 0x08 11. " RSRRFID ,Start signal reset for start logic input RFID" "No reset,Reset" bitfld.long 0x08 10. " RSRPIO_10 ,Start signal reset for start logic input PIO0_10" "No reset,Reset" bitfld.long 0x08 9. " RSRPIO_9 ,Start signal reset for start logic input PIO0_9" "No reset,Reset" textline " " bitfld.long 0x08 8. " RSRPIO_8 ,Start signal reset for start logic input PIO0_8" "No reset,Reset" bitfld.long 0x08 7. " RSRPIO_7 ,Start signal reset for start logic input PIO0_7" "No reset,Reset" bitfld.long 0x08 6. " RSRPIO_6 ,Start signal reset for start logic input PIO0_6" "No reset,Reset" bitfld.long 0x08 5. " RSRPIO_5 ,Start signal reset for start logic input PIO0_5" "No reset,Reset" textline " " bitfld.long 0x08 4. " RSRPIO_4 ,Start signal reset for start logic input PIO0_4" "No reset,Reset" bitfld.long 0x08 3. " RSRPIO_3 ,Start signal reset for start logic input PIO0_3" "No reset,Reset" bitfld.long 0x08 2. " RSRPIO_2 ,Start signal reset for start logic input PIO0_2" "No reset,Reset" bitfld.long 0x08 1. " RSRPIO_1 ,Start signal reset for start logic input PIO0_1" "No reset,Reset" textline " " bitfld.long 0x08 0. " RSRPIO_0 ,Start signal reset for start logic input PIO0_0" "No reset,Reset" line.long 0x0C "STARTSRP0,Start logic status register 0" bitfld.long 0x0C 12. " SRTMR ,Start signal status for start logic input wake-up timer" "Not received,Received" bitfld.long 0x0C 11. " SRRFID ,Start signal status for start logic input RFID" "Not received,Received" bitfld.long 0x0C 10. " SRPIO_10 ,Start signal status for start logic input PIO0_10" "Not received,Received" bitfld.long 0x0C 9. " SRPIO_9 ,Start signal status for start logic input PIO0_9" "Not received,Received" textline " " bitfld.long 0x0C 8. " SRPIO_8 ,Start signal status for start logic input PIO0_8" "Not received,Received" bitfld.long 0x0C 7. " SRPIO_7 ,Start signal status for start logic input PIO0_7" "Not received,Received" bitfld.long 0x0C 6. " SRPIO_6 ,Start signal status for start logic input PIO0_6" "Not received,Received" bitfld.long 0x0C 5. " SRPIO_5 ,Start signal status for start logic input PIO0_5" "Not received,Received" textline " " bitfld.long 0x0C 4. " SRPIO_4 ,Start signal status for start logic input PIO0_4" "Not received,Received" bitfld.long 0x0C 3. " SRPIO_3 ,Start signal status for start logic input PIO0_3" "Not received,Received" bitfld.long 0x0C 2. " SRPIO_2 ,Start signal status for start logic input PIO0_2" "Not received,Received" bitfld.long 0x0C 1. " SRPIO_1 ,Start signal status for start logic input PIO0_1" "Not received,Received" textline " " bitfld.long 0x0C 0. " SRPIO_0 ,Start signal status for start logic input PIO0_0" "Not received,Received" group.long 0x234++0x07 line.long 0x00 "PDWAKECFG,Wake-up Configuration Register" bitfld.long 0x00 0. " FLASH_PD ,Flash addresses remapped to SRAM after Deep-sleep mode" "No,Yes" line.long 0x04 "PDRUNCFG,Power-down Configuration Register" bitfld.long 0x04 3. " EEPROM_PD ,EEPROM power down" "Powered,Power-down" bitfld.long 0x04 1. " TSEN_PD ,Temperature sensor power down" "Powered,Power-down" bitfld.long 0x04 0. " FLASH_PD ,Flash power down" "Powered,Power-down" rgroup.long 0x3F4++0x03 line.long 0x00 "DEVICE_ID ,Device ID Register" width 0x0B tree.end else tree "SYSCON (System Configuration)" base ad:0x40048000 width 15. group.long 0x00++0x0B line.long 0x00 "SYSMEMREMAP,System Memory Remap Register" sif ((cpu()=="LPC1102")) bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,User Flash Mode" else bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,?..." endif line.long 0x04 "PRESETCTRL,Peripheral Reset Control Register" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") sif (cpuis("LPC82*")) bitfld.long 0x04 16. " I2C3_RST_N ,I2C3 reset control" "Reset,No reset" bitfld.long 0x04 15. " I2C2_RST_N ,I2C2 reset control" "Reset,No reset" bitfld.long 0x04 14. " I2C1_RST_N ,I2C1 reset control" "Reset,No reset" textline " " endif bitfld.long 0x04 12. " ACMP_RST_N ,Analog comparator reset control" "Reset,No reset" bitfld.long 0x04 11. " FLASH_RST_N ,Flash controller reset control" "Reset,No reset" bitfld.long 0x04 10. " GPIO_RST_N , GPIO and GPIO pin interrupt reset control" "Reset,No reset" textline " " bitfld.long 0x04 9. " WKT_RST_N ,Self wake-up timer (WKT) reset control" "Reset,No reset" bitfld.long 0x04 8. " SCT_RST_N ,SCT reset control" "Reset,No reset" bitfld.long 0x04 7. " MRT_RST_N ,Multi-rate timer (MRT) reset control" "Reset,No reset" textline " " bitfld.long 0x04 6. " I2C_RST_N ,I2C reset control" "Reset,No reset" textline " " sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") bitfld.long 0x04 5. " UART2_RST_N ,USART2 reset control" "Reset,No reset" bitfld.long 0x04 4. " UART1_RST_N ,USART1 reset control" "Reset,No reset" bitfld.long 0x04 3. " USART0_RST_N ,USART0 reset control" "Reset,No reset" textline " " bitfld.long 0x04 2. " UARTFRG_RST_N ,USART fractional baud rate generator" "Reset,No reset" bitfld.long 0x04 1. " SPI1_RST_N ,SPI1 reset control" "Reset,No reset" bitfld.long 0x04 0. " SPI0_RST_N ,SPI0 reset control" "Reset,No reset" else bitfld.long 0x04 4. " UART1_RST_N ,USART1 reset control" "Reset,No reset" bitfld.long 0x04 3. " USART0_RST_N ,USART0 reset control" "Reset,No reset" bitfld.long 0x04 2. " UARTFRG_RST_N ,USART fractional baud rate generator" "Reset,No reset" textline " " bitfld.long 0x04 0. " SPI0_RST_N ,SPI0 reset control" "Reset,No reset" endif elif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x04 29. " DMA_RST_N ,DMA reset control" "Reset,No reset" bitfld.long 0x04 24. " ADC_RST_N ,ADC reset control" "Reset,No reset" bitfld.long 0x04 11. " FLASH_RST_N ,GFlash controller reset control" "Reset,No reset" textline " " bitfld.long 0x04 10. " GPIO_RST_N ,GPIO and GPIO pin interrupt reset control" "Reset,No reset" bitfld.long 0x04 9. " WKT_RST_N ,Self-wake-up timer reset control" "Reset,No reset" bitfld.long 0x04 8. " SCT_RST_N ,SCT reset control" "Reset,No reset" textline " " bitfld.long 0x04 7. " MRT_RST_N ,Multi-rate timer reset control" "Reset,No reset" bitfld.long 0x04 6. " I2C0_RST_N ,I2C0 reset control" "Reset,No reset" bitfld.long 0x04 3. " UART0_RST_N ,USART0 reset control" "Reset,No reset" textline " " bitfld.long 0x04 2. " UARTFRG_RST_N ,USART fractional baud rate generator reset control" "Reset,No reset" bitfld.long 0x04 1. " SPI1_RST_N ,SPI1 reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP0_RST_N ,SSP1 reset control" "Reset,No reset" elif (cpuis("LPC11U6*")) bitfld.long 0x04 10. " SCT1_RST_N ,SCT1 reset control" "Reset,No reset" bitfld.long 0x04 9. " SCT0_RST_N ,SCT0 reset control" "Reset,No reset" bitfld.long 0x04 8. " USART4_RST_N ,USART4 reset control" "Reset,No reset" textline " " bitfld.long 0x04 7. " USART3_RST_N ,USART3 reset control" "Reset,No reset" bitfld.long 0x04 6. " USART2_RST_N ,USART2 reset control" "Reset,No reset" bitfld.long 0x04 5. " USART1_RST_N ,USART1 reset control" "Reset,No reset" textline " " bitfld.long 0x04 4. " FRG_RST_N ,FRG reset control" "Reset,No reset" bitfld.long 0x04 3. " I2C1_RST_N ,I2C1 reset control" "Reset,No reset" bitfld.long 0x04 2. " SSP1_RST_N ,SSP0 reset control" "Reset,No reset" textline " " bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP0_RST_N ,SSP1 reset control" "Reset,No reset" elif (cpuis("LPC11U3*")) bitfld.long 0x04 2. " SSP1_RST_N ,SSP0 reset control" "Reset,No reset" bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP0_RST_N ,SSP1 reset control" "Reset,No reset" else sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") bitfld.long 0x04 11. " ADC_RST_N ,ADC reset control" "Reset,No reset" bitfld.long 0x04 10. " DAC_RST_N ,DAC reset control" "Reset,No reset" bitfld.long 0x04 9. " ACOMP_RST_N ,Analog comparator reset control" "Reset,No reset" textline " " bitfld.long 0x04 8. " CT32B1_RST_N ,CT32B1 reset control" "Reset,No reset" bitfld.long 0x04 7. " CT32B0_RST_N ,CT32B0 reset control" "Reset,No reset" bitfld.long 0x04 6. " CT16B1_RST_N ,CT16B1 reset control" "Reset,No reset" textline " " bitfld.long 0x04 5. " CT16B0_RST_N ,CT16B0 reset control" "Reset,No reset" bitfld.long 0x04 4. " UART_RST_N ,UART reset control" "Reset,No reset" textline " " endif sif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14") bitfld.long 0x04 3. " CAN_RST_N ,C_CAN reset control" "Reset,No reset" textline " " endif sif (cpu()!="LPC1102") bitfld.long 0x04 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset" textline " " bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP0_RST_N ,SSP reset control" "Reset,No reset" else bitfld.long 0x04 0. " SSP0_RST_N ,SSP reset control" "Reset,No reset" endif endif line.long 0x08 "SYSPLLCTRL,System PLL Control Register" bitfld.long 0x08 5.--6. " PSEL ,Post divider ratio" "1,2,4,8" bitfld.long 0x08 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" rgroup.long 0x0C++0x03 line.long 0x00 "SYSPLLSTAT,System PLL Status Register" bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked" sif (cpuis("LPC11U*")) group.long 0x10++0x03 line.long 0x00 "USBPLLCTRL,USB PLL Control Register" bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8" bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" rgroup.long 0x14++0x03 line.long 0x00 "USBPLLSTAT,USB PLL Status Register" bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked" endif sif (cpuis("LPC11U6*")) group.long 0x1C++0x03 line.long 0x00 "RTCOSCCTRL,RTC Oscillator 32 kHz Output Control Register" bitfld.long 0x00 0. " RTCOSCEN ,RTC 32 kHz output enable" "Disabled,Enabled" endif sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") group.long 0x24++0x0F line.long 0x00 "WDTOSCCTRL,Watchdog Oscillator Control Register" bitfld.long 0x00 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency(Fclkana)" ",0.5 MHz,0.8 MHz,1.1 MHz,1.4 MHz,1.6 MHz,1.8 MHz,2.0 MHz,2.2 MHz,2.4 MHz,2.6 MHz,2.7 MHz,2.9 MHz,3.1 MHz,3.2 MHz,3.4 MHz" bitfld.long 0x00 0.--4. " DIVSEL ,Select divider for Fclkana." "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" elif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0x20++0x07 line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register" bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz" bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled" line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register" bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency(Fclkana)" ",0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz" bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana." "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" else group.long 0x20++0x07 line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register" bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz" bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled" line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register" bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency(Fclkana)" ",0.5 MHz,0.8 MHz,1.1 MHz,1.4 MHz,1.6 MHz,1.8 MHz,2.0 MHz,2.2 MHz,2.4 MHz,2.6 MHz,2.7 MHz,2.9 MHz,3.1 MHz,3.2 MHz,3.4 MHz" bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana." "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" endif sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"||cpuis("LPC82*")&&cpu()!="LPC811M001JDH16") group.long 0x28++0x03 line.long 0x00 "IRCCTRL,Internal Resonant Crystal Control Register" hexmask.long.byte 0x00 0.--7. 1. " TRIM ,Trim value" elif (cpuis("LPC11U3*")||cpuis("LPC11U6*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") group.long 0x28++0x03 line.long 0x00 "IRCCTRL,Internal Resonant Crystal Control Register" hexmask.long.byte 0x00 0.--7. 1. " TRIM ,Trim value" endif sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") group.long 0x2C++0x03 line.long 0x00 "LFOSCCTRL,LF Oscillator Control Register" bitfld.long 0x00 5.--8. " FREQSEL ,Select watchdog oscillator analog output frequency" "Undefinded,0.5 MHz,0.8 MHz,1.1 MHz,1.4 MHz,1.6 MHz,1.8 MHz,2.0 MHz,2.2 MHz,2.4 MHz,2.6 MHz,2.7 MHz,2.9 MHz,3.1 MHz,3.2 MHz,3.4 MHz" bitfld.long 0x00 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" endif group.long 0x30++0x03 line.long 0x00 "SYSRSTSTAT,System Reset Status Register" eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset" eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset" eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset" textline " " eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset" eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset" group.long 0x40++0x07 sif (cpu()=="LPC1110"||cpu()=="LPC1102LV"||cpu()=="LPC1102"||cpuis("LPC1111*")||cpu()=="LPC1112LV"||cpuis("LPC1112*")||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14") line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,System oscillator,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,Crystal Oscillator,CLKIN pin,?..." elif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,Crystal Oscillator,,CLKIN pin" elif (cpuis("LPC11U6*")) line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,Crystal Oscillator,,32 kHz clock" else line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC oscillator,Crystal Oscillator,?..." endif line.long 0x04 "SYSPLLCLKUEN,System PLL Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled" sif (cpuis("LPC11U*")) group.long 0x48++0x07 line.long 0x00 "USBPLLCLKSEL,USB PLL Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,USB PLL clock source" "IRC oscillator,System oscillator,?..." line.long 0x04 "USBPLLCLKUEN,USB PLL Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,USB PLL clock source update enable" "Disabled,Enabled" endif group.long 0x70++0x0B sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,Input clock to system PLL,LF Oscillator,System PLL clock out" elif (cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,PLL input,Watchdog oscillator,PLL output" else line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC oscillator,PLL input,WDT oscillator,PLL output" endif line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled" line.long 0x08 "SYSAHBCLKDIV,System AHB Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values" group.long 0x80++0x03 line.long 0x00 "SYSAHBCLKCTRL,System AHB Clock Control Register" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") sif (cpuis("LPC82*")) bitfld.long 0x00 29. " DMA ,Clock for DMA enable" "Disabled,Enabled" bitfld.long 0x00 26. " MTB ,Clock for MTB enable" "Disabled,Enabled" bitfld.long 0x00 24. " ADC ,Clock for ADC enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " I2C3 ,Clock for I2C3 enable" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2 ,Clock for I2C2 enable" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1 ,Clock for I2C1 enable" "Disabled,Enabled" textline " " endif sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x00 19. " ADC ,Clock for ADC enable" "Disabled,Enabled" else bitfld.long 0x00 19. " ACMP ,Clock to analog comparator enable" "Disabled,Enabled" endif bitfld.long 0x00 18. " IOCON ,Clock for IOCON block enable" "Disabled,Enabled" bitfld.long 0x00 17. " WWDT ,Clock for WWDT enable" "Disabled,Enabled" textline " " sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") bitfld.long 0x00 16. " UART2 ,Clock for USART2 enable" "Disabled,Enabled" textline " " endif sif (cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33") bitfld.long 0x00 15. " UART1 ,Clock for USART1 enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 14. " UART0 ,Clock for USART0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " CRC ,Clock for CRC enable" "Disabled,Enabled" sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x00 12. " SPI1 ,Clock for SPI1 enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 11. " SPI0 ,Clock for SPI0 enable" "Disabled,Enabled" bitfld.long 0x00 10. " MRT ,Clock for multi-rate timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " WKT ,Clock for self wake-up timer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SCT ,Clock for state configurable timer enable" "Disabled,Enabled" bitfld.long 0x00 7. " SWM ,Clock for switch matrix enable" "Disabled,Enabled" bitfld.long 0x00 6. " GPIO ,Clock for GPIO port/pin interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " I2C ,Clock for I1C enable" "Disabled,Enabled" bitfld.long 0x00 4. " FLASH ,Clock for flash enable" "Disabled,Enabled" else sif (cpuis("LPC11U*")) sif (cpuis("LPC11U6*")) bitfld.long 0x00 31. " SCT0_1 ,Clock for SCT0 and SCT1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " RTC ,Clock for RTC register interface enable" "Disabled,Enabled" bitfld.long 0x00 29. " DMA ,Clock for DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CRC ,Clock for CRC enable" "Disabled,Enabled" bitfld.long 0x00 27. " USBSRAM ,USB SRAM/SRAM2 block enable" "Disabled,Enabled" textline " " else bitfld.long 0x00 27. " USBRAM ,USB SRAM block enable" "Disabled,Enabled" textline " " endif sif cpuis("LPC11U35FET48")||cpuis("LPC11U35FHI33")||cpuis("LPC11U37H*") bitfld.long 0x00 26. " RAM1 ,Block for SRAM1 enable" "Disabled,Enabled" textline " " elif cpuis("LPC11U6*") bitfld.long 0x00 26. " RAM1 ,Block for SRAM1 enable" "Disabled,Enabled" bitfld.long 0x00 25. " I2C1 ,Clock for I2C1 enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 24. " GROUP1INT ,Clock to GPIO GROUP1 interrupt register interface enable" "Disabled,Enabled" bitfld.long 0x00 23. " GROUP0INT ,Clock to GPIO GROUP0 interrupt register interface enable" "Disabled,Enabled" textline " " sif (cpuis("LPC11U6*")) bitfld.long 0x00 22. " USART3_4 ,Enables clock to USART3 and USART4 register interfaces." "Disabled,Enabled" bitfld.long 0x00 21. " USART2 ,Enables clock to USART2 register interface" "Disabled,Enabled" bitfld.long 0x00 20. " USART1 ,Enables clock to USART1 register interface" "Disabled,Enabled" textline " " endif bitfld.long 0x00 19. " PINT ,Clock to GPIO Pin interrupts register interface enable" "Disabled,Enabled" bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " WWDT ,Clock for WWDT enable" "Disabled,Enabled" bitfld.long 0x00 14. " USB ,Clock to the USB register interface enable" "Disabled,Enabled" elif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&cpu()!="LPC1112LV"&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC1114LV"&&!cpuis("LPC1115*")&&cpu()!="LPC11D14") sif cpuis("LPC11E3*") bitfld.long 0x00 27. " RAM2 ,Enables clock for the SRAM2" "Disabled,Enabled" textline " " endif bitfld.long 0x00 26. " RAM1 ,Enables clock for the SRAM1" "Disabled,Enabled" bitfld.long 0x00 24. " GROUP1INT ,Clock to GPIO GROUP1 interrupt register interface enable" "Disabled,Enabled" bitfld.long 0x00 23. " GROUP0INT ,Clock to GPIO GROUP1 interrupt register interface enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PINT ,Clock to GPIO Pin interrupts register interface enable" "Disabled,Enabled" bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " WWDT ,Clock for WWDT enable" "Disabled,Enabled" elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") bitfld.long 0x00 24. " P1INT ,GPIO Port 1interrupt" "Disabled,Enabled" bitfld.long 0x00 23. " P0INT ,GPIO Port 0 interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " DAC ,Enables clock for DAC" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " DAC ,Enables clock for DAC" "Disabled,Enabled" bitfld.long 0x00 20. " ACOMP ,Enables clock for ACOMP" "Disabled,Enabled" bitfld.long 0x00 19. " PINT ,GPIO Pin interrupts" "Disabled,Enabled" elif (cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14") textline " " bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled" bitfld.long 0x00 17. " CAN ,Clock for C_CAN enable" "Disabled,Enabled" bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled" elif (cpu()=="LPC1102") textline " " bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled" bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled" else textline " " bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled" bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 13. " ADC ,Clock for ADC enable" "Disabled,Enabled" textline " " sif (cpuis("LPC11U3*")) bitfld.long 0x00 12. " USART ,Clock for UART enable" "Disabled,Enabled" textline " " elif (cpuis("LPC11U6*")) bitfld.long 0x00 12. " USART0 ,Enables clock for USART0" "Disabled,Enabled" textline " " else bitfld.long 0x00 12. " UART ,Clock for UART enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 11. " SSP0 ,Clock for SPI0 enable" "Disabled,Enabled" bitfld.long 0x00 10. " CT32B1 ,Clock for 32-bit counter/timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 9. " CT32B0 ,Clock for 32-bit counter/timer 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " CT16B1 ,Clock for 16-bit counter/timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 7. " CT16B0 ,Clock for 16-bit counter/timer 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " GPIO ,Clock for GPIO enable" "Disabled,Enabled" textline " " sif (cpuis("LPC11U6*")) bitfld.long 0x00 5. " I2C0 ,Clock for I2C enable" "Disabled,Enabled" textline " " elif (cpu()!="LPC1102") bitfld.long 0x00 5. " I2C ,Clock for I2C enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " FLASHARRAY ,Clock for flash array access enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 3. " FLASHREG ,Clock for flash register interface enable" "Disabled,Enabled" sif (cpuis("LPC11U3*")||cpuis("LPC11U6*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 2. " RAM0 ,Clock for SRAM0 enable" "Disabled,Enabled" else bitfld.long 0x00 2. " RAM ,Clock for RAM enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SYS ,Clock for AHB to APB bridge enable" ",Enabled" sif (cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0x94++0x03 line.long 0x00 "UARTCLKDIV,UART Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,UART_PCLK clock divider values" elif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20") group.long 0x94++0x03 line.long 0x00 "SSP0CLKDIV,SPI0 Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,SSP0_PCLK clock divider values" endif sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC811M001JDH16") group.long 0x98++0x03 sif (cpuis("LPC11U6*")) line.long 0x00 "USART0CLKDIV,UART Clock Divider Register" else line.long 0x00 "UARTCLKDIV,UART Clock Divider Register" endif hexmask.long.byte 0x00 0.--7. 1. " DIV ,UART_PCLK clock divider values" endif sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33") group.long 0x9C++0x03 line.long 0x00 "SSP1CLKDIV,SPI1 Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,SSP1_PCLK clock divider values" endif sif (cpuis("LPC11U6*")) group.long 0xA0++0x03 line.long 0x00 "FRGCLKDIV,UART Fractional Baud Rate Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,USART fractional baud rate generator clock divider values" endif sif (cpuis("LPC11U*")) group.long 0xC0++0x0B line.long 0x00 "USBCLKSEL,USBClock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,USB clock source" "USB PLL out,Main clock,?..." line.long 0x04 "USBCLKUEN,USB Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,USB clock source update enable" "Disabled,Enabled" line.long 0x08 "USBCLKDIV,USB Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,USB clock divider values" endif sif (!cpuis("LPC11U*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC811M001JDH16") group.long 0xd0++0x0B line.long 0x00 "WDTCLKSEL,WDT Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,WDT clock source" "IRC oscillator,Main clock,Watchdog oscillator,?..." line.long 0x04 "WDTCLKUEN,WDT Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,WDT clock source update enable" "Disabled,Enabled" line.long 0x08 "WDTCLKDIV,WDT Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,WDT clock divider values" endif sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&!cpuis("LPC11U3*")&&!cpuis("LPC11U6*")) group.long 0xE0++0x0B line.long 0x00 "CLKOUTCLKSEL,CLKOUT Clock Source Select Register" sif cpuis("LPC11E*") bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,System oscillator,LF oscillator,Main clock" else bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,Crystal oscillator,Watchdog oscillator,Main clock" endif line.long 0x04 "CLKOUTCLKUEN,CLKOUT Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled" line.long 0x08 "CLKOUTCLKDIV,CLKOUT Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values" elif (cpuis("LPC11U3*")||cpuis("LPC11U6*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0xE0++0x0B line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,System oscillator,WDT oscillator,Main clock" line.long 0x04 "CLKOUTUEN,CLKOUT Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled" line.long 0x08 "CLKOUTDIV,CLKOUT Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values" endif sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U6*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0xF0++0x07 line.long 0x00 "UARTFRGDIV,USART Fractional Generator Divide Value Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider" line.long 0x04 "UARTFRGMULT,USART Fractional Generator Multiplier Value Register" hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider" group.long 0xFC++0x03 line.long 0x00 "EXTTRACECMD,External Trace Buffer Command Register" bitfld.long 0x00 1. " STOP ,Trace stop command" "Not stopped,Stopped" bitfld.long 0x00 0. " START ,Trace start command" "Not started,Started" endif textline " " rgroup.long 0x100++0x03 line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") sif cpu()!="LPC810M021FN8" sif (cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FDH16") bitfld.long 0x00 17. " CAPPIO0_17 ,Raw reset status input PIO0_17" "Low,High" bitfld.long 0x00 16. " CAPPIO0_16 ,Raw reset status input PIO0_16" "Low,High" bitfld.long 0x00 15. " CAPPIO0_15 ,Raw reset status input PIO0_15" "Low,High" textline " " endif bitfld.long 0x00 14. " CAPPIO0_14 ,Raw reset status input PIO0_14" "Low,High" bitfld.long 0x00 13. " CAPPIO0_13 ,Raw reset status input PIO0_13" "Low,High" bitfld.long 0x00 12. " CAPPIO0_12 ,Raw reset status input PIO0_12" "Low,High" textline " " bitfld.long 0x00 11. " CAPPIO0_11 ,Raw reset status input PIO0_11" "Low,High" bitfld.long 0x00 10. " CAPPIO0_10 ,Raw reset status input PIO0_10" "Low,High" bitfld.long 0x00 9. " CAPPIO0_9 ,Raw reset status input PIO0_9" "Low,High" textline " " bitfld.long 0x00 8. " CAPPIO0_8 ,Raw reset status input PIO0_8" "Low,High" bitfld.long 0x00 7. " CAPPIO0_7 ,Raw reset status input PIO0_7" "Low,High" bitfld.long 0x00 6. " CAPPIO0_6 ,Raw reset status input PIO0_6" "Low,High" textline " " endif bitfld.long 0x00 5. " CAPPIO0_5 ,Raw reset status input PIO0_5" "Low,High" bitfld.long 0x00 4. " CAPPIO0_4 ,Raw reset status input PIO0_4" "Low,High" bitfld.long 0x00 3. " CAPPIO0_3 ,Raw reset status input PIO0_3" "Low,High" textline " " bitfld.long 0x00 2. " CAPPIO0_2 ,Raw reset status input PIO0_2" "Low,High" bitfld.long 0x00 1. " CAPPIO0_1 ,Raw reset status input PIO0_1" "Low,High" bitfld.long 0x00 0. " CAPPIO0_0 ,Raw reset status input PIO0_0" "Low,High" else sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C22"||cpu()=="LPC11C24") bitfld.long 0x00 31. " CAPPIO2_7 ,Raw reset status input PIO2_7" "Low,High" bitfld.long 0x00 30. " CAPPIO2_6 ,Raw reset status input PIO2_6" "Low,High" bitfld.long 0x00 29. " CAPPIO2_5 ,Raw reset status input PIO2_5" "Low,High" textline " " bitfld.long 0x00 28. " CAPPIO2_4 ,Raw reset status input PIO2_4" "Low,High" bitfld.long 0x00 27. " CAPPIO2_3 ,Raw reset status input PIO2_3" "Low,High" bitfld.long 0x00 26. " CAPPIO2_2 ,Raw reset status input PIO2_2" "Low,High" textline " " bitfld.long 0x00 25. " CAPPIO2_1 ,Raw reset status input PIO2_1" "Low,High" bitfld.long 0x00 24. " CAPPIO2_0 ,Raw reset status input PIO2_0" "Low,High" textline " " elif (cpu()=="LPC11C12"||cpu()=="LPC11C14") bitfld.long 0x00 31. " CAPPIO2_7 ,Raw reset status input PIO2_7" "Low,High" bitfld.long 0x00 30. " CAPPIO2_6 ,Raw reset status input PIO2_6" "Low,High" bitfld.long 0x00 27. " CAPPIO2_3 ,Raw reset status input PIO2_3" "Low,High" textline " " bitfld.long 0x00 26. " CAPPIO2_2 ,Raw reset status input PIO2_2" "Low,High" bitfld.long 0x00 25. " CAPPIO2_1 ,Raw reset status input PIO2_1" "Low,High" bitfld.long 0x00 24. " CAPPIO2_0 ,Raw reset status input PIO2_0" "Low,High" textline " " endif sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&!cpuis("LPC11U*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")) bitfld.long 0x00 23. " CAPPIO1_11 ,Raw reset status input PIO1_11" "Low,High" bitfld.long 0x00 22. " CAPPIO1_10 ,Raw reset status input PIO1_10" "Low,High" bitfld.long 0x00 21. " CAPPIO1_9 ,Raw reset status input PIO1_9" "Low,High" textline " " bitfld.long 0x00 20. " CAPPIO1_8 ,Raw reset status input PIO1_8" "Low,High" bitfld.long 0x00 19. " CAPPIO1_7 ,Raw reset status input PIO1_7" "Low,High" bitfld.long 0x00 18. " CAPPIO1_6 ,Raw reset status input PIO1_6" "Low,High" textline " " bitfld.long 0x00 17. " CAPPIO1_5 ,Raw reset status input PIO1_5" "Low,High" bitfld.long 0x00 16. " CAPPIO1_4 ,Raw reset status input PIO1_4" "Low,High" bitfld.long 0x00 15. " CAPPIO1_3 ,Raw reset status input PIO1_3" "Low,High" textline " " bitfld.long 0x00 14. " CAPPIO1_2 ,Raw reset status input PIO1_2" "Low,High" bitfld.long 0x00 13. " CAPPIO1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x00 12. " CAPPIO1_0 ,Raw reset status input PIO1_0" "Low,High" textline " " bitfld.long 0x00 11. " CAPPIO0_11 ,Raw reset status input PIO0_11" "Low,High" bitfld.long 0x00 10. " CAPPIO0_10 ,Raw reset status input PIO0_10" "Low,High" bitfld.long 0x00 9. " CAPPIO0_9 ,Raw reset status input PIO0_9" "Low,High" textline " " bitfld.long 0x00 8. " CAPPIO0_8 ,Raw reset status input PIO0_8" "Low,High" bitfld.long 0x00 7. " CAPPIO0_7 ,Raw reset status input PIO0_7" "Low,High" bitfld.long 0x00 6. " CAPPIO0_6 ,Raw reset status input PIO0_6" "Low,High" textline " " bitfld.long 0x00 5. " CAPPIO0_5 ,Raw reset status input PIO0_5" "Low,High" bitfld.long 0x00 4. " CAPPIO0_4 ,Raw reset status input PIO0_4" "Low,High" bitfld.long 0x00 3. " CAPPIO0_3 ,Raw reset status input PIO0_3" "Low,High" textline " " bitfld.long 0x00 2. " CAPPIO0_2 ,Raw reset status input PIO0_2" "Low,High" bitfld.long 0x00 1. " CAPPIO0_1 ,Raw reset status input PIO0_1" "Low,High" bitfld.long 0x00 0. " CAPPIO0_0 ,Raw reset status input PIO0_0" "Low,High" elif (!cpuis("LPC11U*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC11E*")) bitfld.long 0x00 19. " CAPPIO1_7 ,Raw reset status input PIO1_7" "Low,High" bitfld.long 0x00 18. " CAPPIO1_6 ,Raw reset status input PIO1_6" "Low,High" bitfld.long 0x00 15. " CAPPIO1_3 ,Raw reset status input PIO1_3" "Low,High" textline " " bitfld.long 0x00 14. " CAPPIO1_2 ,Raw reset status input PIO1_2" "Low,High" bitfld.long 0x00 13. " CAPPIO1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x00 12. " CAPPIO1_0 ,Raw reset status input PIO1_0" "Low,High" textline " " bitfld.long 0x00 11. " CAPPIO0_11 ,Raw reset status input PIO0_11" "Low,High" bitfld.long 0x00 10. " CAPPIO0_10 ,Raw reset status input PIO0_10" "Low,High" bitfld.long 0x00 9. " CAPPIO0_9 ,Raw reset status input PIO0_9" "Low,High" textline " " bitfld.long 0x00 8. " CAPPIO0_8 ,Raw reset status input PIO0_8" "Low,High" bitfld.long 0x00 0. " CAPPIO0_0 ,Raw reset status input PIO0_0" "Low,High" elif (cpuis("LPC11U*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")) sif (!cpuis("LPC11E*")&&!cpuis("LPC11U*")) bitfld.long 0x00 31. " PIOSTATP0_31 ,Raw reset status input PIO0_31" "Low,High" bitfld.long 0x00 30. " PIOSTATP0_30 ,Raw reset status input PIO0_30" "Low,High" bitfld.long 0x00 29. " PIOSTATP0_29 ,Raw reset status input PIO0_29" "Low,High" textline " " bitfld.long 0x00 28. " PIOSTATP0_28 ,Raw reset status input PIO0_28" "Low,High" bitfld.long 0x00 27. " PIOSTATP0_27 ,Raw reset status input PIO0_27" "Low,High" bitfld.long 0x00 26. " PIOSTATP0_26 ,Raw reset status input PIO0_26" "Low,High" textline " " bitfld.long 0x00 25. " PIOSTATP0_25 ,Raw reset status input PIO0_25" "Low,High" bitfld.long 0x00 24. " PIOSTATP0_24 ,Raw reset status input PIO0_24" "Low,High" textline " " endif bitfld.long 0x00 23. " PIOSTATP0_23 ,Raw reset status input PIO0_23" "Low,High" bitfld.long 0x00 22. " PIOSTATP0_22 ,Raw reset status input PIO0_22" "Low,High" bitfld.long 0x00 21. " PIOSTATP0_21 ,Raw reset status input PIO0_21" "Low,High" textline " " bitfld.long 0x00 20. " PIOSTATP0_20 ,Raw reset status input PIO0_20" "Low,High" bitfld.long 0x00 19. " PIOSTATP0_19 ,Raw reset status input PIO0_19" "Low,High" bitfld.long 0x00 18. " PIOSTATP0_18 ,Raw reset status input PIO0_18" "Low,High" textline " " bitfld.long 0x00 17. " PIOSTATP0_17 ,Raw reset status input PIO0_17" "Low,High" bitfld.long 0x00 16. " PIOSTATP0_16 ,Raw reset status input PIO0_16" "Low,High" bitfld.long 0x00 15. " PIOSTATP0_15 ,Raw reset status input PIO0_15" "Low,High" textline " " bitfld.long 0x00 14. " PIOSTATP0_14 ,Raw reset status input PIO0_14" "Low,High" bitfld.long 0x00 13. " PIOSTATP0_13 ,Raw reset status input PIO0_13" "Low,High" bitfld.long 0x00 12. " PIOSTATP0_12 ,Raw reset status input PIO0_12" "Low,High" textline " " bitfld.long 0x00 11. " PIOSTATP0_11 ,Raw reset status input PIO0_11" "Low,High" bitfld.long 0x00 10. " PIOSTATP0_10 ,Raw reset status input PIO0_10" "Low,High" bitfld.long 0x00 9. " PIOSTATP0_9 ,Raw reset status input PIO0_9" "Low,High" textline " " bitfld.long 0x00 8. " PIOSTATP0_8 ,Raw reset status input PIO0_8" "Low,High" bitfld.long 0x00 7. " PIOSTATP0_7 ,Raw reset status input PIO0_7" "Low,High" bitfld.long 0x00 6. " PIOSTATP0_6 ,Raw reset status input PIO0_6" "Low,High" textline " " bitfld.long 0x00 5. " PIOSTATP0_5 ,Raw reset status input PIO0_5" "Low,High" bitfld.long 0x00 4. " PIOSTATP0_4 ,Raw reset status input PIO0_4" "Low,High" bitfld.long 0x00 3. " PIOSTATP0_3 ,Raw reset status input PIO0_3" "Low,High" textline " " bitfld.long 0x00 2. " PIOSTATP0_2 ,Raw reset status input PIO0_2" "Low,High" bitfld.long 0x00 1. " PIOSTATP0_1 ,Raw reset status input PIO0_1" "Low,High" bitfld.long 0x00 0. " PIOSTATP0_0 ,Raw reset status input PIO0_0" "Low,High" endif endif sif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14"||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24") rgroup.long 0x104++0x03 line.long 0x00 "PIOPORCAP1,POR Captured PIO Status Register 1" bitfld.long 0x00 9. " CAPPIO3_5 ,Raw reset status input PIO2_5" "Low,High" bitfld.long 0x00 8. " CAPPIO3_4 ,Raw reset status input PIO2_4" "Low,High" bitfld.long 0x00 7. " CAPPIO3_3 ,Raw reset status input PIO2_3" "Low,High" textline " " bitfld.long 0x00 6. " CAPPIO3_2 ,Raw reset status input PIO2_2" "Low,High" bitfld.long 0x00 5. " CAPPIO3_1 ,Raw reset status input PIO2_1" "Low,High" bitfld.long 0x00 4. " CAPPIO3_0 ,Raw reset status input PIO2_0" "Low,High" textline " " bitfld.long 0x00 3. " CAPPIO2_11 ,Raw reset status input PIO2_11" "Low,High" bitfld.long 0x00 2. " CAPPIO2_10 ,Raw reset status input PIO2_10" "Low,High" bitfld.long 0x00 1. " CAPPIO2_9 ,Raw reset status input PIO2_9" "Low,High" textline " " bitfld.long 0x00 0. " CAPPIO2_8 ,Raw reset status input PIO2_8" "Low,High" elif cpuis("LPC11U6*") rgroup.long 0x104++0x03 line.long 0x00 "PIOPORCAP1,POR Captured PIO Status Register 1" sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 30. " PIOSTATP1_30 ,Raw reset status input PIO1_30" "Low,High" bitfld.long 0x00 29. " PIOSTATP1_29 ,Raw reset status input PIO1_29" "Low,High" bitfld.long 0x00 28. " PIOSTATP1_28 ,Raw reset status input PIO1_28" "Low,High" textline " " bitfld.long 0x00 27. " PIOSTATP1_27 ,Raw reset status input PIO1_27" "Low,High" bitfld.long 0x00 26. " PIOSTATP1_26 ,Raw reset status input PIO1_26" "Low,High" bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" textline " " bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" bitfld.long 0x00 21. " PIOSTATP1_21 ,Raw reset status input PIO1_21" "Low,High" bitfld.long 0x00 20. " PIOSTATP1_20 ,Raw reset status input PIO1_20" "Low,High" textline " " bitfld.long 0x00 19. " PIOSTATP1_19 ,Raw reset status input PIO1_19" "Low,High" bitfld.long 0x00 13. " PIOSTATP1_13 ,Raw reset status input PIO1_13" "Low,High" bitfld.long 0x00 10. " PIOSTATP1_10 ,Raw reset status input PIO1_10" "Low,High" textline " " bitfld.long 0x00 9. " PIOSTATP1_9 ,Raw reset status input PIO1_9" "Low,High" bitfld.long 0x00 7. " PIOSTATP1_7 ,Raw reset status input PIO1_7" "Low,High" bitfld.long 0x00 0. " PIOSTATP1_0 ,Raw reset status input PIO1_0" "Low,High" else sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 31. " PIOSTATP1_31 ,Raw reset status input PIO1_31" "Low,High" bitfld.long 0x00 30. " PIOSTATP1_30 ,Raw reset status input PIO1_30" "Low,High" bitfld.long 0x00 29. " PIOSTATP1_29 ,Raw reset status input PIO1_29" "Low,High" textline " " bitfld.long 0x00 28. " PIOSTATP1_28 ,Raw reset status input PIO1_28" "Low,High" bitfld.long 0x00 27. " PIOSTATP1_27 ,Raw reset status input PIO1_27" "Low,High" bitfld.long 0x00 26. " PIOSTATP1_26 ,Raw reset status input PIO1_26" "Low,High" textline " " bitfld.long 0x00 25. " PIOSTATP1_25 ,Raw reset status input PIO1_25" "Low,High" bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" textline " " bitfld.long 0x00 22. " PIOSTATP1_22 ,Raw reset status input PIO1_22" "Low,High" bitfld.long 0x00 21. " PIOSTATP1_21 ,Raw reset status input PIO1_21" "Low,High" bitfld.long 0x00 20. " PIOSTATP1_20 ,Raw reset status input PIO1_20" "Low,High" textline " " bitfld.long 0x00 19. " PIOSTATP1_19 ,Raw reset status input PIO1_19" "Low,High" bitfld.long 0x00 18. " PIOSTATP1_18 ,Raw reset status input PIO1_18" "Low,High" bitfld.long 0x00 17. " PIOSTATP1_17 ,Raw reset status input PIO1_17" "Low,High" textline " " bitfld.long 0x00 16. " PIOSTATP1_16 ,Raw reset status input PIO1_16" "Low,High" bitfld.long 0x00 15. " PIOSTATP1_15 ,Raw reset status input PIO1_15" "Low,High" bitfld.long 0x00 14. " PIOSTATP1_14 ,Raw reset status input PIO1_14" "Low,High" textline " " bitfld.long 0x00 13. " PIOSTATP1_13 ,Raw reset status input PIO1_13" "Low,High" bitfld.long 0x00 12. " PIOSTATP1_12 ,Raw reset status input PIO1_12" "Low,High" bitfld.long 0x00 11. " PIOSTATP1_11 ,Raw reset status input PIO1_11" "Low,High" textline " " bitfld.long 0x00 10. " PIOSTATP1_10 ,Raw reset status input PIO1_10" "Low,High" bitfld.long 0x00 9. " PIOSTATP1_9 ,Raw reset status input PIO1_9" "Low,High" bitfld.long 0x00 8. " PIOSTATP1_8 ,Raw reset status input PIO1_8" "Low,High" textline " " bitfld.long 0x00 7. " PIOSTATP1_7 ,Raw reset status input PIO1_7" "Low,High" bitfld.long 0x00 6. " PIOSTATP1_6 ,Raw reset status input PIO1_6" "Low,High" bitfld.long 0x00 5. " PIOSTATP1_5 ,Raw reset status input PIO1_5" "Low,High" textline " " bitfld.long 0x00 4. " PIOSTATP1_4 ,Raw reset status input PIO1_4" "Low,High" bitfld.long 0x00 3. " PIOSTATP1_3 ,Raw reset status input PIO1_3" "Low,High" bitfld.long 0x00 2. " PIOSTATP1_2 ,Raw reset status input PIO1_2" "Low,High" textline " " bitfld.long 0x00 1. " PIOSTATP1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x00 0. " PIOSTATP1_0 ,Raw reset status input PIO1_0" "Low,High" else bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" bitfld.long 0x00 21. " PIOSTATP1_21 ,Raw reset status input PIO1_21" "Low,High" textline " " bitfld.long 0x00 20. " PIOSTATP1_20 ,Raw reset status input PIO1_20" "Low,High" bitfld.long 0x00 13. " PIOSTATP1_13 ,Raw reset status input PIO1_13" "Low,High" endif endif elif cpuis("LPC11U3*") rgroup.long 0x104++0x03 line.long 0x00 "PIOPORCAP1,POR Captured PIO Status Register 1" sif cpuis("LPC11U3?F??48") sif cpuis("LPC11U3?FBD48") bitfld.long 0x00 31. " PIOSTATP1_31 ,Raw reset status input PIO1_31" "Low,High" endif textline " " bitfld.long 0x00 29. " PIOSTATP1_29 ,Raw reset status input PIO1_29" "Low,High" bitfld.long 0x00 28. " PIOSTATP1_28 ,Raw reset status input PIO1_28" "Low,High" bitfld.long 0x00 27. " PIOSTATP1_27 ,Raw reset status input PIO1_27" "Low,High" textline " " bitfld.long 0x00 26. " PIOSTATP1_26 ,Raw reset status input PIO1_26" "Low,High" bitfld.long 0x00 25. " PIOSTATP1_25 ,Raw reset status input PIO1_25" "Low,High" bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" textline " " bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" bitfld.long 0x00 22. " PIOSTATP1_22 ,Raw reset status input PIO1_22" "Low,High" bitfld.long 0x00 21. " PIOSTATP1_21 ,Raw reset status input PIO1_21" "Low,High" textline " " bitfld.long 0x00 20. " PIOSTATP1_20 ,Raw reset status input PIO1_20" "Low,High" bitfld.long 0x00 19. " PIOSTATP1_19 ,Raw reset status input PIO1_19" "Low,High" bitfld.long 0x00 16. " PIOSTATP1_16 ,Raw reset status input PIO1_16" "Low,High" textline " " bitfld.long 0x00 15. " PIOSTATP1_15 ,Raw reset status input PIO1_15" "Low,High" bitfld.long 0x00 14. " PIOSTATP1_14 ,Raw reset status input PIO1_14" "Low,High" bitfld.long 0x00 13. " PIOSTATP1_13 ,Raw reset status input PIO1_13" "Low,High" sif cpuis("LPC11U3?FET48") textline " " bitfld.long 0x00 5. " PIOSTATP1_5 ,Raw reset status input PIO1_5" "Low,High" endif else sif !cpuis("LPC11U3?FH?33") bitfld.long 0x00 29. " PIOSTATP1_29 ,Raw reset status input PIO1_29" "Low,High" bitfld.long 0x00 28. " PIOSTATP1_28 ,Raw reset status input PIO1_28" "Low,High" bitfld.long 0x00 27. " PIOSTATP1_27 ,Raw reset status input PIO1_27" "Low,High" textline " " bitfld.long 0x00 26. " PIOSTATP1_26 ,Raw reset status input PIO1_26" "Low,High" bitfld.long 0x00 25. " PIOSTATP1_25 ,Raw reset status input PIO1_25" "Low,High" bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" textline " " bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" bitfld.long 0x00 22. " PIOSTATP1_22 ,Raw reset status input PIO1_22" "Low,High" bitfld.long 0x00 21. " PIOSTATP1_21 ,Raw reset status input PIO1_21" "Low,High" textline " " bitfld.long 0x00 20. " PIOSTATP1_20 ,Raw reset status input PIO1_20" "Low,High" bitfld.long 0x00 19. " PIOSTATP1_19 ,Raw reset status input PIO1_19" "Low,High" bitfld.long 0x00 18. " PIOSTATP1_18 ,Raw reset status input PIO1_18" "Low,High" textline " " bitfld.long 0x00 17. " PIOSTATP1_17 ,Raw reset status input PIO1_17" "Low,High" bitfld.long 0x00 16. " PIOSTATP1_16 ,Raw reset status input PIO1_16" "Low,High" bitfld.long 0x00 15. " PIOSTATP1_15 ,Raw reset status input PIO1_15" "Low,High" textline " " bitfld.long 0x00 14. " PIOSTATP1_14 ,Raw reset status input PIO1_14" "Low,High" bitfld.long 0x00 13. " PIOSTATP1_13 ,Raw reset status input PIO1_13" "Low,High" bitfld.long 0x00 12. " PIOSTATP1_12 ,Raw reset status input PIO1_12" "Low,High" textline " " bitfld.long 0x00 11. " PIOSTATP1_11 ,Raw reset status input PIO1_11" "Low,High" bitfld.long 0x00 10. " PIOSTATP1_10 ,Raw reset status input PIO1_10" "Low,High" bitfld.long 0x00 9. " PIOSTATP1_9 ,Raw reset status input PIO1_9" "Low,High" textline " " bitfld.long 0x00 8. " PIOSTATP1_8 ,Raw reset status input PIO1_8" "Low,High" bitfld.long 0x00 7. " PIOSTATP1_7 ,Raw reset status input PIO1_7" "Low,High" bitfld.long 0x00 6. " PIOSTATP1_6 ,Raw reset status input PIO1_6" "Low,High" textline " " bitfld.long 0x00 5. " PIOSTATP1_5 ,Raw reset status input PIO1_5" "Low,High" bitfld.long 0x00 4. " PIOSTATP1_4 ,Raw reset status input PIO1_4" "Low,High" bitfld.long 0x00 3. " PIOSTATP1_3 ,Raw reset status input PIO1_3" "Low,High" textline " " bitfld.long 0x00 2. " PIOSTATP1_2 ,Raw reset status input PIO1_2" "Low,High" bitfld.long 0x00 1. " PIOSTATP1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x00 0. " PIOSTATP1_0 ,Raw reset status input PIO1_0" "Low,High" else bitfld.long 0x00 19. " PIOSTATP1_19 ,Raw reset status input PIO1_19" "Low,High" bitfld.long 0x00 15. " PIOSTATP1_15 ,Raw reset status input PIO1_15" "Low,High" endif endif elif (cpuis("LPC11U*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")) rgroup.long 0x104++0x03 line.long 0x00 "PIOPORCAP1,POR Captured PIO Status Register 1" sif (cpuis("LPC11E*")||cpuis("LPC11U*")) sif cpu()!="LPC11E11" sif (cpuis("LPC11U*")||cpuis("LPC11E*")) bitfld.long 0x00 31. " PIOSTATP1_31 ,Raw reset status input PIO1_31" "Low,High" bitfld.long 0x00 29. " PIOSTATP1_29 ,Raw reset status input PIO1_29" "Low,High" textline " " else bitfld.long 0x00 31. " PIOSTATP1_31 ,Raw reset status input PIO1_31" "Low,High" bitfld.long 0x00 30. " PIOSTATP1_30 ,Raw reset status input PIO1_30" "Low,High" bitfld.long 0x00 29. " PIOSTATP1_29 ,Raw reset status input PIO1_29" "Low,High" endif textline " " bitfld.long 0x00 28. " PIOSTATP1_28 ,Raw reset status input PIO1_28" "Low,High" bitfld.long 0x00 27. " PIOSTATP1_27 ,Raw reset status input PIO1_27" "Low,High" bitfld.long 0x00 26. " PIOSTATP1_26 ,Raw reset status input PIO1_26" "Low,High" textline " " endif sif cpu()=="LPC11E11" bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" textline " " else textline " " bitfld.long 0x00 25. " PIOSTATP1_25 ,Raw reset status input PIO1_25" "Low,High" bitfld.long 0x00 24. " PIOSTATP1_24 ,Raw reset status input PIO1_24" "Low,High" bitfld.long 0x00 23. " PIOSTATP1_23 ,Raw reset status input PIO1_23" "Low,High" textline " " endif sif cpu()!="LPC11E11" bitfld.long 0x00 22. " PIOSTATP1_22 ,Raw reset status input PIO1_22" "Low,High" bitfld.long 0x00 21. " PIOSTATP1_21 ,Raw reset status input PIO1_21" "Low,High" bitfld.long 0x00 20. " PIOSTATP1_20 ,Raw reset status input PIO1_20" "Low,High" textline " " endif bitfld.long 0x00 19. " PIOSTATP1_19 ,Raw reset status input PIO1_19" "Low,High" sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13") bitfld.long 0x00 18. " PIOSTATP1_18 ,Raw reset status input PIO1_18" "Low,High" bitfld.long 0x00 17. " PIOSTATP1_17 ,Raw reset status input PIO1_17" "Low,High" endif textline " " sif cpu()=="LPC11E11" bitfld.long 0x00 15. " PIOSTATP1_15 ,Raw reset status input PIO1_15" "Low,High" else bitfld.long 0x00 16. " PIOSTATP1_16 ,Raw reset status input PIO1_16" "Low,High" bitfld.long 0x00 15. " PIOSTATP1_15 ,Raw reset status input PIO1_15" "Low,High" bitfld.long 0x00 14. " PIOSTATP1_14 ,Raw reset status input PIO1_14" "Low,High" endif sif cpu()!="LPC11E11" textline " " bitfld.long 0x00 13. " PIOSTATP1_13 ,Raw reset status input PIO1_13" "Low,High" sif cpu()!="LPC11E12"&&cpu()!="LPC11E13" textline " " sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")) bitfld.long 0x00 12. " PIOSTATP1_12 ,Raw reset status input PIO1_12" "Low,High" bitfld.long 0x00 11. " PIOSTATP1_11 ,Raw reset status input PIO1_11" "Low,High" bitfld.long 0x00 10. " PIOSTATP1_10 ,Raw reset status input PIO1_10" "Low,High" textline " " endif endif endif endif sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13"&&!cpuis("LPC11U6?FBD48")) sif !cpuis("LPC11U6?JBD64") bitfld.long 0x00 9. " PIOSTATP1_9 ,Raw reset status input PIO1_9" "Low,High" bitfld.long 0x00 8. " PIOSTATP1_8 ,Raw reset status input PIO1_8" "Low,High" bitfld.long 0x00 7. " PIOSTATP1_7 ,Raw reset status input PIO1_7" "Low,High" textline " " bitfld.long 0x00 6. " PIOSTATP1_6 ,Raw reset status input PIO1_6" "Low,High" textline " " else bitfld.long 0x00 9. " PIOSTATP1_9 ,Raw reset status input PIO1_9" "Low,High" bitfld.long 0x00 7. " PIOSTATP1_7 ,Raw reset status input PIO1_7" "Low,High" textline " " endif endif sif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13") sif !cpuis("LPC11U3?FBD48")&&!cpuis("LPC11U3?FHN33")&&!cpuis("LPC11U6?FBD*") bitfld.long 0x00 5. " PIOSTATP1_5 ,Raw reset status input PIO1_5" "Low,High" textline " " endif endif sif cpuis("LPC11U3?FBD64")||(cpuis("LPC11U6*")&&!cpuis("LPC11U6?FBD48")) sif !(cpuis("LPC11U6?FBD64")) bitfld.long 0x00 4. " PIOSTATP1_4 ,Raw reset status input PIO1_4" "Low,High" bitfld.long 0x00 3. " PIOSTATP1_3 ,Raw reset status input PIO1_3" "Low,High" bitfld.long 0x00 2. " PIOSTATP1_2 ,Raw reset status input PIO1_2" "Low,High" textline " " bitfld.long 0x00 1. " PIOSTATP1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x00 0. " PIOSTATP1_0 ,Raw reset status input PIO1_0" "Low,High" textline " " else bitfld.long 0x00 0. " PIOSTATP1_0 ,Raw reset status input PIO1_0" "Low,High" endif elif (!cpuis("LPC11U12*")&&!cpuis("LPC11U13*")&&!cpuis("LPC11U14*")&&!cpuis("LPC11U23*")&&!cpuis("LPC11U34*")&&cpu()!="LPC11E11"&&cpu()!="LPC11E12"&&cpu()!="LPC11E13") textline " " bitfld.long 0x00 4. " PIOSTATP1_4 ,Raw reset status input PIO1_4" "Low,High" bitfld.long 0x00 3. " PIOSTATP1_3 ,Raw reset status input PIO1_3" "Low,High" bitfld.long 0x00 2. " PIOSTATP1_2 ,Raw reset status input PIO1_2" "Low,High" textline " " bitfld.long 0x00 1. " PIOSTATP1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x00 0. " PIOSTATP1_0 ,Raw reset status input PIO1_0" "Low,High" endif endif sif cpuis("LPC11U6*") rgroup.long 0x108++0x03 line.long 0x00 "PIOPORCAP2,POR Captured PIO Status 2 Register" sif !cpuis("LPC11U6?FBD48") sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 23. " PIOSTAT_23 ,Raw reset status input PIO2_23" "Low,High" bitfld.long 0x00 22. " PIOSTAT_22 ,Raw reset status input PIO2_22" "Low,High" bitfld.long 0x00 21. " PIOSTAT_21 ,Raw reset status input PIO2_21" "Low,High" textline " " bitfld.long 0x00 20. " PIOSTAT_20 ,Raw reset status input PIO2_20" "Low,High" textline " " endif bitfld.long 0x00 19. " PIOSTAT_19 ,Raw reset status input PIO2_19" "Low,High" bitfld.long 0x00 18. " PIOSTAT_18 ,Raw reset status input PIO2_18" "Low,High" sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 17. " PIOSTAT_17 ,Raw reset status input PIO2_17" "Low,High" textline " " bitfld.long 0x00 16. " PIOSTAT_16 ,Raw reset status input PIO2_16" "Low,High" endif textline " " bitfld.long 0x00 15. " PIOSTAT_15 ,Raw reset status input PIO2_15" "Low,High" sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 14. " PIOSTAT_14 ,Raw reset status input PIO2_14" "Low,High" bitfld.long 0x00 13. " PIOSTAT_13 ,Raw reset status input PIO2_13" "Low,High" textline " " bitfld.long 0x00 12. " PIOSTAT_12 ,Raw reset status input PIO2_12" "Low,High" bitfld.long 0x00 11. " PIOSTAT_11 ,Raw reset status input PIO2_11" "Low,High" bitfld.long 0x00 10. " PIOSTAT_10 ,Raw reset status input PIO2_10" "Low,High" textline " " bitfld.long 0x00 9. " PIOSTAT_9 ,Raw reset status input PIO2_9" "Low,High" bitfld.long 0x00 8. " PIOSTAT_8 ,Raw reset status input PIO2_8" "Low,High" endif endif textline " " bitfld.long 0x00 7. " PIOSTAT_7 ,Raw reset status input PIO2_7" "Low,High" sif !cpuis("LPC11U6?FBD48") bitfld.long 0x00 6. " PIOSTAT_6 ,Raw reset status input PIO2_6" "Low,High" textline " " endif bitfld.long 0x00 5. " PIOSTAT_5 ,Raw reset status input PIO2_5" "Low,High" textline " " sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 4. " PIOSTAT_4 ,Raw reset status input PIO2_4" "Low,High" bitfld.long 0x00 3. " PIOSTAT_3 ,Raw reset status input PIO2_3" "Low,High" textline " " endif bitfld.long 0x00 2. " PIOSTAT_2 ,Raw reset status input PIO2_2" "Low,High" textline " " bitfld.long 0x00 1. " PIOSTAT_1 ,Raw reset status input PIO2_1" "Low,High" bitfld.long 0x00 0. " PIOSTAT_0 ,Raw reset status input PIO2_0" "Low,High" endif textline " " sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U6*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0x134++0x1B line.long 0x0 "IOCONCLKDIV6,IOCON Glitch Filter Clock Divider Register 6" hexmask.long.byte 0x0 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" line.long 0x4 "IOCONCLKDIV5,IOCON Glitch Filter Clock Divider Register 5" hexmask.long.byte 0x4 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" line.long 0x8 "IOCONCLKDIV4,IOCON Glitch Filter Clock Divider Register 4" hexmask.long.byte 0x8 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" line.long 0xC "IOCONCLKDIV3,IOCON Glitch Filter Clock Divider Register 3" hexmask.long.byte 0xC 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" line.long 0x10 "IOCONCLKDIV2,IOCON Glitch Filter Clock Divider Register 2" hexmask.long.byte 0x10 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" line.long 0x14 "IOCONCLKDIV1,IOCON Glitch Filter Clock Divider Register 1" hexmask.long.byte 0x14 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" line.long 0x18 "IOCONCLKDIV0,IOCON Glitch Filter Clock Divider Register 0" hexmask.long.byte 0x18 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" endif group.long 0x150++0x07 sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") line.long 0x00 "BODR,Brown-Out Detect Register" bitfld.long 0x00 6. " BODINT ,BOD interrupt request" "Not requested,Requested" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" ",,2.52V/2.66V,2.80V/2.90V" elif (cpuis("LPC82*")||cpuis("LPC812M101J*")) line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" ",Level 1,Level 2,Level 3" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" ",Level 1,Level 2,Level 3" elif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" ",Level 1,Level 2,Level 3" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "Level 0,Level 1,Level 2,Level 3" elif cpuis("LPC11U6*") line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level)" ",,Level 2,Level 3" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "Level 0,Level 1,Level 2,Level 3" elif cpuis("LPC11U3*") line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" ",2.22V/2.35V,2.52V/2.66V,2.80V/2.90V" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "1.46V/1.63V,2.06V/2.15V,2.35V/2.43V,2.63V/2.71V" elif (cpuis("LPC11U*")||cpuis("LPC11E*")) line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" ",2.22V/2.35V,2.52V/2.66V,2.80V/2.90V" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "1.46V/1.63V,2.06V/2.15V,2.35V/2.43V,2.63V/2.71V" else line.long 0x00 "BODCTRL,BOD Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level (assertion/de-assertion)" "1.65V/1.80V,2.22V/2.35V,2.52V/2.66V,2.80V/2.90V" bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "1.46V/1.63V,2.06V/2.15V,2.35V/2.43V,2.63V/2.71V" endif line.long 0x04 "SYSTCKCAL,System Tick Timer Calibration Register" hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value" sif (cpuis("LPC11E*")||cpuis("LPC11U*")||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0x170++0x3 line.long 0x00 "IRQLATENCY,IRQ Latency Register" hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value" endif sif (cpu()!="LPC1102") group.long 0x174++0x23 line.long 0x0 "NMISRC,NMI Source Selection Register" bitfld.long 0x0 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled" textline " " sif cpuis("LPC11U3*") bitfld.long 0x00 0.--4. " IRQNO ,IRQ number of the interrupt" "GPIO pin 0,GPIO pin 1,GPIO pin 2,GPIO pin 3,GPIO pin 4,GPIO pin 5,GPIO pin 6,GPIO pin 7,GPIO GROUP0,GPIO GROUP1,,,,,SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART,USB_IRQ,USB_FIQ,ADC,WWDT,BOD,Flash,,,USB_WAKEUP,IOH" elif cpuis("LPC11U6*") bitfld.long 0x00 0.--4. " IRQNO ,IRQ number of the interrupt" "GPIO pin 0,GPIO pin 1,GPIO pin 2,GPIO pin 3,GPIO pin 4,GPIO pin 5,GPIO pin 6,GPIO pin 7,GPIO GROUP0,GPIO GROUP1,I2C1,USART1_4,USART2_3,SCT0_1,SSP1,I2C0,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART0,USB_IRQ,USB_FIQ,ADC_A,RTC,BOD_WDT,FLASH,DMA,ADC_B,USB_WAKEUP,?..." elif (cpuis("LPC11U*")) bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "GPIO pin 0,GPIO pin 1,GPIO pin 2,GPIO pin 3,GPIO pin 4,GPIO pin 5,GPIO pin 6,GPIO pin 7,GPIO GROUP0,GPIO GROUP1,,,,,SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART,USB_IRQ,USB_FIQ,ADC,WWDT,BOD,Flash,,,USB_WAKEUP,?..." elif (cpuis("LPC82*")) bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0,SPI1,,UART0,UART1,UART2,,I2C1,I2C0,SCT,MRT,CMP,WDT,BOD,FLASH,WKT,ADC_SEQA,ADC_SEQB,ADC_THCMP,ADC_OVR,DMA,I2C2,I2C3,,PININT0,PININT1,PININT2,PININT3,PININT4,PININT5,PININT6,PININT7" elif (cpuis("LPC812M101J*")) bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0,SPI1,,UART0,UART1,UART2,,,I2C,SCT,MRT,CMP,WDT,BOD,FLASH,WKT,,,,,,,,,PININT0,PININT1,PININT2,PININT3,PININT4,PININT5,PININT6,PININT7" elif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0,SPI1,,UART0,UART1,UART2,,,I2C0,SCT,MRT,CMP,WDT,BOD,,WKT,,,,,,,,,PININT0,PININT1,PININT2,PININT3,PININT4,PININT5,PININT6,PININT7" elif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0,SPI1,,UART0,,,,,I2C0,SCT,MRT,,WDT,BOD,,WKT,ADC_SEQA,ADC_SEQB,ADC_THCMP,ADC_OVR,DMA,,,,PININT0,PININT1,PININT2,PININT3,PININT4,PININT5,PININT6,PININT7" elif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20") bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "SPI0,,,UART0,UART1,,,,I2C0,SCT,MRT,CMP,WDT,BOD,,WKT,,,,,,,,,PININT0,PININT1,PININT2,PININT3,PININT4,PININT5,PININT6,PININT7" elif cpuis("LPC11E*") bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "PIN_INT0,PIN_INT1,PIN_INT2,PIN_INT3,PIN_INT4,PIN_INT5,PIN_INT6,PIN_INT7,GPIO GROUP0,GPIO GROUP1,,,,,SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART,,,ADC,WWDT,BOD,Flash,?..." elif (cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11D14") bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO1_0,C_CAN,SPI/SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,UART,,,ADC,WDT,BOD,,PIO_3,PIO_2,PIO_1,PIO_0" else bitfld.long 0x0 0.--4. " IRQNO ,IRQ number of the interrupt" "GPIO,GPIO,GPIO,GPIO,GPIO,GPIO,GPIO,GPIO,GPIO,GPIO,AC,DAC,,,SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART,,,ADC,WDT,BOD,Flash,?..." endif sif cpuis("LPC11U6*") group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" elif cpuis("LPC11U3*") group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." elif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpu()!="LPC1110"&&!cpuis("LPC1111*")&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&!cpuis("LPC1115*")&&cpu()!="LPC11D14") if (((per.l((ad:0x40048000+0x178)))&0x20)==0x20) group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x17C)))&0x20)==0x20) group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x180)))&0x20)==0x20) group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x184)))&0x20)==0x20) group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x188)))&0x20)==0x20) group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x18C)))&0x20)==0x20) group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x190)))&0x20)==0x20) group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif if (((per.l((ad:0x40048000+0x194)))&0x20)==0x20) group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif else group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" sif (!cpuis("LPC11U*")&&!cpuis("LPC11E*")&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x00 5. " INTPORT ,Port select" "Port 0,Port 1" endif sif (cpu()=="LPC11A12"||cpu()=="LPC11A14") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpu()=="LPC11A11"||cpu()=="LPC11A13") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,-,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04") bitfld.long 0x00 0.--4. " INTPIN ,Pin number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO0_24,PIO0_25,PIO0_26,PIO0_27,PIO0_28,?..." elif (cpuis("LPC812M101J*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,?..." elif (cpu()=="LPC11E11") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_15,-,-,-,PIO1_19,-,-,-,PIO1_23,PIO1_24,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC11E12")||(cpu()=="LPC11E13") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U24*")||cpuis("LPC11U35*")||cpuis("LPC11U36*")||cpuis("LPC11U37*")||cpuis("LPC11E*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U14*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,PIO1_5,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpuis("LPC11U12*")||cpuis("LPC11U13*")||cpuis("LPC11U23*")||cpuis("LPC11U34*")) bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,-,-,-,-,-,-,-,-,-,-,-,-,-,PIO1_13,PIO1_14,PIO1_15,PIO1_16,-,-,PIO1_19,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,-,PIO1_31,-,-,-,-,-,?..." elif (cpu()=="LPC810M021FN8") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 0.--5. " INTPIN ,Pin number" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif endif endif endif sif (cpuis("LPC11U*")) group.long 0x198++0x03 line.long 0x00 "USBCLKCTRL,USB Clock Control Register" bitfld.long 0x00 1. " POL_CLK ,USB need_clock edge polarity" "Falling,Rising" bitfld.long 0x00 0. " AP_CLK ,USB need_clock signal control" "Hardware,Forced high" rgroup.long 0x19C++0x03 line.long 0x00 "USBCLKST,USB Clock Status Register" bitfld.long 0x00 0. " NEED_CLKST ,USB need_clock signal status" "Low,High" endif sif (cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14") sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*")&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC811M001JDH16") sif (!cpuis("LPC11U*")&&cpu()!="LPC11A02"&&cpu()!="LPC11A04"&&cpu()!="LPC11A11"&&cpu()!="LPC11A12"&&cpu()!="LPC11A13"&&cpu()!="LPC11A14"&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")) group.long 0x200++0x03 line.long 0x00 "STARTAPRP0,Start Logic Edge Control Register 0" bitfld.long 0x00 12. " APRPIO1_0 ,Edge select for start logic input PIO1_0" "Falling,Rising" bitfld.long 0x00 11. " APRPIO0_11 ,Edge select for start logic input PIO0_11" "Falling,Rising" bitfld.long 0x00 10. " APRPIO0_10 ,Edge select for start logic input PIO0_10" "Falling,Rising" textline " " bitfld.long 0x00 9. " APRPIO0_9 ,Edge select for start logic input PIO0_9" "Falling,Rising" bitfld.long 0x00 8. " APRPIO0_8 ,Edge select for start logic input PIO0_8" "Falling,Rising" sif (cpu()!="LPC1102") bitfld.long 0x00 7. " APRPIO0_7 ,Edge select for start logic input PIO0_7" "Falling,Rising" textline " " bitfld.long 0x00 6. " APRPIO0_6 ,Edge select for start logic input PIO0_6" "Falling,Rising" bitfld.long 0x00 5. " APRPIO0_5 ,Edge select for start logic input PIO0_5" "Falling,Rising" bitfld.long 0x00 4. " APRPIO0_4 ,Edge select for start logic input PIO0_4 " "Falling,Rising" textline " " bitfld.long 0x00 3. " APRPIO0_3 ,Edge select for start logic input PIO0_3" "Falling,Rising" bitfld.long 0x00 2. " APRPIO0_2 ,Edge select for start logic input PIO0_2" "Falling,Rising" bitfld.long 0x00 1. " APRPIO0_1 ,Edge select for start logic input PIO0_1" "Falling,Rising" endif textline " " bitfld.long 0x00 0. " APRPIO0_0 ,Edge select for start logic input PIO0_0" "Falling,Rising" endif sif (!cpuis("LPC11U*")&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")) group.long 0x204++0x03 line.long 0x00 "STARTERP0,Start Logic Signal Enable Register 0" bitfld.long 0x00 12. " ERPIO1_0 ,Start signal for start logic input PIO1_0 enable" "Disabled,Enabled" bitfld.long 0x00 11. " ERPIO0_11 ,Start signal for start logic input PIO0_11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " ERPIO0_10 ,Start signal for start logic input PIO0_10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ERPIO0_9 ,Start signal for start logic input PIO0_9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " ERPIO0_8 ,Start signal for start logic input PIO0_8 enable" "Disabled,Enabled" sif (cpu()!="LPC1102") bitfld.long 0x00 7. " ERPIO0_7 ,Start signal for start logic input PIO0_7 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " ERPIO0_6 ,Start signal for start logic input PIO0_6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " ERPIO0_5 ,Start signal for start logic input PIO0_5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " ERPIO0_4 ,Start signal for start logic input PIO0_4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ERPIO0_3 ,Start signal for start logic input PIO0_3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " ERPIO0_2 ,Start signal for start logic input PIO0_2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ERPIO0_1 ,Start signal for start logic input PIO0_1 enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 0. " ERPIO0_0 ,Start signal for start logic input PIO0_0 enable" "Disabled,Enabled" wgroup.long 0x208++0x03 line.long 0x00 "STARTRSRP0CLR,Start Logic Reset Register 0" bitfld.long 0x00 12. " RSRPIO1_0 ,Start signal reset for start logic input PIO1_0" "-,Reset" bitfld.long 0x00 11. " RSRPIO0_11 ,Start signal reset for start logic input PIO0_11" "-,Reset" bitfld.long 0x00 10. " RSRPIO0_10 ,Start signal reset for start logic input PIO0_10" "-,Reset" textline " " bitfld.long 0x00 9. " RSRPIO0_9 ,Start signal reset for start logic input PIO0_9" "-,Reset" bitfld.long 0x00 8. " RSRPIO0_8 ,Start signal reset for start logic input PIO0_8" "-,Reset" sif (cpu()!="LPC1102") bitfld.long 0x00 7. " RSRPIO0_7 ,Start signal reset for start logic input PIO0_7" "-,Reset" textline " " bitfld.long 0x00 6. " RSRPIO0_6 ,Start signal reset for start logic input PIO0_6" "-,Reset" bitfld.long 0x00 5. " RSRPIO0_5 ,Start signal reset for start logic input PIO0_5" "-,Reset" bitfld.long 0x00 4. " RSRPIO0_4 ,Start signal reset for start logic input PIO0_4" "-,Reset" textline " " bitfld.long 0x00 3. " RSRPIO0_3 ,Start signal reset for start logic input PIO0_3" "-,Reset" bitfld.long 0x00 2. " RSRPIO0_2 ,Start signal reset for start logic input PIO0_2" "-,Reset" bitfld.long 0x00 1. " RSRPIO0_1 ,Start signal reset for start logic input PIO0_1" "-,Reset" endif textline " " bitfld.long 0x00 0. " RSRPIO0_0 ,Start signal reset for start logic input PIO0_0" "-,Reset" rgroup.long 0x20C++0x03 line.long 0x00 "STARTSRP0,Start Logic Status Register 0" bitfld.long 0x00 12. " SRPIO1_0 ,Start signal status for start logic input PIO1_0" "Not started,Started" bitfld.long 0x00 11. " SRPIO0_11 ,Start signal status for start logic input PIO0_11" "Not started,Started" bitfld.long 0x00 10. " SRPIO0_10 ,Start signal status for start logic input PIO0_10" "Not started,Started" textline " " bitfld.long 0x00 9. " SRPIO0_9 ,Start signal status for start logic input PIO0_9" "Not started,Started" bitfld.long 0x00 8. " SRPIO0_8 ,Start signal status for start logic input PIO0_8" "Not started,Started" sif (cpu()!="LPC1102"&&cpu()!="LPC1102LV") bitfld.long 0x00 7. " SRPIO0_7 ,Start signal status for start logic input PIO0_7" "Not started,Started" textline " " bitfld.long 0x00 6. " SRPIO0_6 ,Start signal status for start logic input PIO0_6" "Not started,Started" bitfld.long 0x00 5. " SRPIO0_5 ,Start signal status for start logic input PIO0_5" "Not started,Started" bitfld.long 0x00 4. " SRPIO0_4 ,Start signal status for start logic input PIO0_4" "Not started,Started" textline " " bitfld.long 0x00 3. " SRPIO0_3 ,Start signal status for start logic input PIO0_3" "Not started,Started" bitfld.long 0x00 2. " SRPIO0_2 ,Start signal status for start logic input PIO0_2" "Not started,Started" bitfld.long 0x00 1. " SRPIO0_1 ,Start signal status for start logic input PIO0_1" "Not started,Started" endif textline " " bitfld.long 0x00 0. " SRPIO0_0 ,Start signal status for start logic input PIO0_0" "Not started,Started" endif endif sif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0x204++0x03 line.long 0x00 "STARTERP0,Start Logic 0 Interrupt Wake-up Enable Register 0" bitfld.long 0x00 7. " PINT7 ,Pin interrupt 7 wake-up" "Disabled,Enabled" bitfld.long 0x00 6. " PINT6 ,Pin interrupt 6 wake-up" "Disabled,Enabled" bitfld.long 0x00 5. " PINT5 ,Pin interrupt 5 wake-up" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PINT4 ,Pin interrupt 4 wake-up" "Disabled,Enabled" bitfld.long 0x00 3. " PINT3 ,Pin interrupt 3 wake-up" "Disabled,Enabled" bitfld.long 0x00 2. " PINT2 ,Pin interrupt 2 wake-up" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PINT1 ,Pin interrupt 1 wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " PINT0 ,Pin interrupt 0 wake-up" "Disabled,Enabled" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1" bitfld.long 0x00 15. " WKT ,Self wake-up timer wake-up" "Disabled,Enabled" bitfld.long 0x00 13. " BOD ,BOD interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 12. " WWDT ,WWDT interrupt wake-up" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " I2C ,I2C interrupt wake-up" "Disabled,Enabled" textline " " sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") bitfld.long 0x00 5. " USART2 ,USART2 interrupt wake-up" "Disabled,Enabled" textline " " endif sif (cpu()!="LPC832M101FDH20"&&cpu()=="LPC834M101FHI33") bitfld.long 0x00 4. " USART1 ,USART1 interrupt wake-up" "Disabled,Enabled" textline " " endif bitfld.long 0x00 3. " USART0 ,USART0 interrupt wake-up" "Disabled,Enabled" textline " " sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101J*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") bitfld.long 0x00 1. " SPI1 ,SPI1 interrupt wake-up" "Disabled,Enabled" textline " " endif bitfld.long 0x00 0. " SPI0 ,SPI0 interrupt wake-up" "Disabled,Enabled" elif (cpuis("LPC82*")) group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1" bitfld.long 0x00 22. " I2C3 ,I2C3 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 21. " I2C2 ,I2C2 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 15. " WKT ,Self wake-up timer wake-up" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " BOD ,BOD interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 12. " WWDT ,WWDT interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 8. " I2C0 ,I2C0 interrupt wake-up" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " I2C1 ,I2C1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 5. " USART2 ,USART2 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 4. " USART1 ,USART1 interrupt wake-up" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " USART0 ,USART0 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 1. " SPI1 ,SPI1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " SPI0 ,SPI0 interrupt wake-up" "Disabled,Enabled" elif (cpuis("LPC11U6*")) group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1" bitfld.long 0x00 24. " USART2_3 ,Combined USART2 and USART3 interrupt wake-up enable" "Disabled,Enabled" bitfld.long 0x00 23. " USART1_4 ,Combined USART1 and USART4 interrupt wake-up enable" "Disabled,Enabled" bitfld.long 0x00 21. " GROUP1INT ,GPIO GROUP1 interrupt wake-up enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " GROUP0INT ,GPIO GROUP0 interrupt wake-up enable" "Disabled,Enabled" bitfld.long 0x00 19. " USB_WAKEUP ,USB need_clock signal wake-up enable" "Disabled,Enabled" bitfld.long 0x00 13. " WWDT_BODINT ,Combined WWDT interrupt or BOD interrupt wake-up enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " RTCINT ,RTC interrupt wake-up enable" "Disabled,Enabled" else group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-up Enable Register 1" bitfld.long 0x00 21. " GPIOINT1 ,GPIO GROUP1 interrupt wake-up enable" "Disabled,Enabled" bitfld.long 0x00 20. " GPIOINT0 ,GPIO GROUP0 interrupt wake-up enable" "Disabled,Enabled" sif !cpuis("LPC11E*") bitfld.long 0x00 19. " USB_WAKEUP ,USB need_clock signal wake-up enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 13. " BODINT ,Brown Out Detect (BOD) interrupt wake-up enable" "Disabled,Enabled" bitfld.long 0x00 12. " WWDTINT ,WWDT interrupt wake-up enable" "Disabled,Enabled" endif endif group.long 0x230++0x0B line.long 0x00 "PDSLEEPCFG,Deep-sleep Configuration Register" bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down" line.long 0x04 "PDAWAKECFG,Wake-up Configuration Register" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") bitfld.long 0x04 15. " ACMP ,Analog comparator wake-up configuration" "Powered,Powered down" textline " " endif sif cpuis("LPC11U6*") bitfld.long 0x04 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down" textline " " endif sif (cpuis("LPC11U*")) bitfld.long 0x04 10. " USBPAD_PD ,USB transceiver wake-up configuration" "Powered,Powered down" bitfld.long 0x04 8. " USBPLL_PD ,USB PLL wake-up configuration" "Powered,Powered down" textline " " endif bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down" bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down" textline " " sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down" textline " " endif bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down" bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down" textline " " bitfld.long 0x04 1. " IRC_PD ,IRC oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down" line.long 0x08 "PDRUNCFG,Power-down Configuration Register" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") bitfld.long 0x08 15. " ACMP ,Analog comparator power down" "Powered,Powered down" textline " " endif sif (cpuis("LPC11U6*")) bitfld.long 0x08 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down" textline " " endif sif (cpuis("LPC11U*")) bitfld.long 0x08 10. " USBPAD_PD ,USB transceiver power-down configuration" "Powered,Powered down" bitfld.long 0x08 8. " USBPLL_PD ,USB PLL power-down" "Powered,Powered down" textline " " endif bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down" bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down" bitfld.long 0x08 5. " SYSOSC_PD ,System oscillator power-down" "Powered,Powered down" textline " " sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC812M101J*")&&cpu()!="LPC811M001JDH16") bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down" textline " " endif bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down" bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down" bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down" textline " " bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down" endif sif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14") group.long 0x238++0x3 line.long 0x00 "PDRUNCFG,Power Configuration Register" bitfld.long 0x00 16. " ACOMP_PD ,Analog Comparator power-down" "Powered,Powered down" bitfld.long 0x00 15. " TS_PD ,Temperature Sensor power-down" "Powered,Powered down" bitfld.long 0x00 14. " DAC_PD ,DAC power-down" "Powered,Powered down" textline " " bitfld.long 0x00 13. " LFOSC_PD ,Low frequency oscillator power-down" "Powered,Powered down" bitfld.long 0x00 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down" bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down" textline " " bitfld.long 0x00 5. " SYSOSC_PD ,System oscillator power-down" "Powered,Powered down" bitfld.long 0x00 4. " ADC_PD ,ADC power-down" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD power-down" "Powered,Powered down" textline " " bitfld.long 0x00 2. " FLASH_PD ,Flash power-down" "Powered,Powered down" bitfld.long 0x00 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down" bitfld.long 0x00 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down" endif sif (cpuis("LPC11U6*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16") rgroup.long 0x3F8++0x3 line.long 0x00 "DEVICE_ID,Device ID Register" hexmask.long 0x00 0.--31. 1. " DEVICEID ,Device ID" else rgroup.long 0x3F4++0x3 line.long 0x00 "DEVICE_ID,Device ID Register" hexmask.long 0x00 0.--31. 1. " DEVICEID ,Device ID" endif width 0x0B tree.end endif sif (cpuis("LPC80*")) tree "PMU (Reduced Power Modes and Power Management)" base ad:0x40020000 width 13. group.long 0x00++0x03 line.long 0x00 "PCON,Power Control Register" eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not entered,Entered" eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not entered,Entered" bitfld.long 0x00 3. " NODPD ,No Deep power-down mode enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep power-down,?..." sif cpuis("LPC11E*") group.long 0x4++0x03 line.long 0x00 "GPREG0,General Purpose Register 0" group.long 0x8++0x03 line.long 0x00 "GPREG1,General Purpose Register 1" group.long 0xC++0x03 line.long 0x00 "GPREG2,General Purpose Register 2" group.long 0x10++0x03 line.long 0x00 "GPREG3,General Purpose Register 3" sif cpuis("LPC11E6*") group.long 0x14++0x03 line.long 0x00 "GPREG4,General Purpose Register 4" hexmask.long.tbyte 0x00 12.--31. 1. " GPDATA ,Data retained during deep power-down mode" bitfld.long 0x00 11. " WAKEPAD_DISABLE ,WAKEUP pin disable" "Enabled,Disabled" bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis for enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "GPREG4,General Purpose Register 4" hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during deep power-down mode" bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis for enable" "Disabled,Enabled" endif else group.long 0x4++0x03 line.long 0x00 "GPREG0,General Purpose Register 0" group.long 0x8++0x03 line.long 0x00 "GPREG1,General Purpose Register 1" group.long 0xC++0x03 line.long 0x00 "GPREG2,General Purpose Register 2" group.long 0x10++0x03 line.long 0x00 "GPREG3,General Purpose Register 3" group.long 0x14++0x03 line.long 0x00 "GPREG4,General Purpose Register 4" endif sif !cpuis("LPC11E*") group.long 0x20++0x07 line.long 0x00 "WUSRCREG,Deep Power Down Wake Up Source Status Register" eventfld.long 0x00 7. " WUSRCREG[7] ,Pin wake-up status of PIO0_10" "No effect,Wake-up" eventfld.long 0x00 6. " [6] ,Pin wake-up status of PIO0_11" "No effect,Wake-up" eventfld.long 0x00 5. " [5] ,Pin wake-up status of PIO0_4" "No effect,Wake-up" eventfld.long 0x00 4. " [4] ,Pin wake-up status of PIO0_13" "No effect,Wake-up" newline eventfld.long 0x00 3. " [3] ,Pin wake-up status of PIO0_17" "No effect,Wake-up" eventfld.long 0x00 2. " [2] ,Pin wake-up status of PIO0_8" "No effect,Wake-up" eventfld.long 0x00 1. " [1] ,Pin wake-up status of PIO0_9" "No effect,Wake-up" eventfld.long 0x00 0. " [0] ,Pin wake-up status of PIO0_15" "No effect,Wake-up" line.long 0x04 "WUENAREG,Deep Power Down Wake Up Enable Register" bitfld.long 0x04 7. " WUENAREG[7] ,Pin wake-up enable for PIO0_10" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Pin wake-up enable for PIO0_11" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,Pin wake-up enable for PIO0_4" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Pin wake-up enable for PIO0_13" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,Pin wake-up enable for PIO0_17" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pin wake-up enable for PIO0_8" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pin wake-up enable for PIO0_9" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pin wake-up enable for PIO0_15" "Disabled,Enabled" endif width 0x0B tree.end elif (cpuis("LPC8N04")) tree "PMU (Power Management Unit)" base ad:0x40038000 width 12. if (((per.l(ad:0x40030000+0x00))&0x2000)==0x00) group.long 0x00++0x03 line.long 0x00 "PCON,Power Control Register" bitfld.long 0x00 19. " WAKEUP ,Enable the WAKEUP function on pin PIO0_0" "Disabled,Enabled" bitfld.long 0x00 17.--18. " FORCEVBAT/FORCEVNFC ,Force the power source selection" ",VBAT/External,NFC,Autoswitch" bitfld.long 0x00 15. " BODEN ,Brown-out detector enable" "Disabled,Enabled" bitfld.long 0x00 14. " VBAT ,Battery switch control" "Automatic,Force off" textline " " bitfld.long 0x00 13. " PMULPM ,PMU ultra-low-power-mode automatic switching enable" "Yes,No" eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not occurred,Occurred" eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not occurred,Occurred" bitfld.long 0x00 1. " DPEN ,Deep power-down mode enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "PCON,Power Control Register" bitfld.long 0x00 19. " WAKEUP ,Enable the WAKEUP function on pin PIO0_0" "Disabled,Enabled" bitfld.long 0x00 17.--18. " FORCEVBAT/FORCEVNFC ,Force the power source selection" ",VBAT/External,NFC,?..." bitfld.long 0x00 15. " BODEN ,Brown-out detector enable" "Disabled,Enabled" bitfld.long 0x00 14. " VBAT ,Battery switch control" "Automatic,Force off" textline " " bitfld.long 0x00 13. " PMULPM ,PMU ultra-low-power-mode automatic switching enable" "Yes,No" eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not occurred,Occurred" eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not occurred,Occurred" bitfld.long 0x00 1. " DPEN ,Deep power-down mode enable" "Disabled,Enabled" endif group.long 0x4++0x03 line.long 0x00 "GPREG0,General Purpose Register 0" group.long 0x8++0x03 line.long 0x00 "GPREG1,General Purpose Register 1" group.long 0xC++0x03 line.long 0x00 "GPREG2,General Purpose Register 2" group.long 0x10++0x03 line.long 0x00 "GPREG3,General Purpose Register 3" if (((per.l(ad:0x40030000+0x00))&0x800)==0x800) group.long 0x18++0x03 line.long 0x00 "PSTAT,Power Status Register" bitfld.long 0x00 7. " RFPOW ,RF field detected" "No,RF" bitfld.long 0x00 5. " BOD1V8 ,BOD detected" "VDD>=1.8 V,VDD<1.8 V" bitfld.long 0x00 3.--4. " DPDEXIT ,Exit from deep-power down" "POR/RESETN,LDO enabled,RTC timer event,WAKEUP pin negative edge detected" textline " " bitfld.long 0x00 1. " PSWBAT ,Status of battery power selection switch" "Disabled,Enabled" bitfld.long 0x00 0. " PSWNFC ,Status of NFC power selection switch " "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "PSTAT,Power Status Register" bitfld.long 0x00 7. " RFPOW ,RF field detected" "No,RF" bitfld.long 0x00 5. " BOD1V8 ,BOD detected" "VDD>=1.8 V,VDD<1.8 V" textline " " bitfld.long 0x00 1. " PSWBAT ,Status of battery power selection switch" "Disabled,Enabled" bitfld.long 0x00 0. " PSWNFC ,Status of NFC power selection switch " "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "ACCSTAT,Access Status Register" bitfld.long 0x00 0. " PMU_READY ,PMU access" "Not possible,Possible" group.long 0x2C++0x07 line.long 0x00 "TMRCLKCTRL,Timer Clock Control Register" bitfld.long 0x00 22.--23. " TMRCURRLVL ,Timer FRO current level selector bits" "0,1,2,3" bitfld.long 0x00 16.--21. " TMRCLKTRIM ,Timer FRO trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " TMREN ,RTC clock source" "No clock,32 kHZ GRO" line.long 0x04 "IMSC,PMU Interrupt Mask Set And Clear Register" bitfld.long 0x04 1. " RFPOWI ,RF power interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " BODI ,BOD trigger interrupt enable" "Disabled,Enabled" rgroup.long 0x34++0x07 line.long 0x00 "RIS,PMU Raw Interrupt Status Register" bitfld.long 0x00 1. " RFPOWRI ,Raw RF power interrupt level" "Low,High" bitfld.long 0x00 0. " BODRI ,Raw BOD interrupt level" "Low,High" line.long 0x04 "MIS,PMU Masked Interrupt Status Register" bitfld.long 0x04 1. " RFPOWRI ,Raw RF power interrupt level" "Low,High" bitfld.long 0x04 0. " BODRI ,Raw BOD interrupt level" "Low,High" wgroup.long 0x3C++0x03 line.long 0x00 "ICR,PMU Interrupt Clear Register" bitfld.long 0x00 1. " RFPOWC ,RF power clear" "Not cleared,Cleared" bitfld.long 0x00 0. " BODC ,BOD trigger clear" "Not cleared,Cleared" width 0x0B tree.end else tree "PMU (Power Management Unit)" base ad:0x40020000 width 9. group.long 0x00++0x03 line.long 0x00 "PCON,Power Control Register" eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not entered,Entered" sif (cpu()=="EM773"||cpu()=="LPC11D14"||cpu()=="LPC1102LV"||cpu()=="LPC1102"||cpuis("LPC1111*")||cpu()=="LPC1110"||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC1124"||cpu()=="LPC1125"||cpu()=="LPC1126"||cpu()=="LPC1127"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U3*")||cpuis("LPC11U6*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not entered,Entered" endif textline " " sif (cpuis("LPC11U*")||cpuis("LPC11E*")||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " NODPD ,No Deep power-down mode enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep-power down,?..." else textline " " bitfld.long 0x00 1. " DPDEN ,Deep power-down mode enable" "Disabled,Enabled" endif group.long 0x4++0x03 line.long 0x00 "GPREG0,General Purpose Register 0" group.long 0x8++0x03 line.long 0x00 "GPREG1,General Purpose Register 1" group.long 0xC++0x03 line.long 0x00 "GPREG2,General Purpose Register 2" group.long 0x10++0x03 line.long 0x00 "GPREG3,General Purpose Register 3" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")) group.long 0x10++0x03 line.long 0x00 "DPDCTRL,Deep Power Down Control Register" sif (cpuis("LPC82*")) hexmask.long 0x00 6.--31. 1. " GPDATA ,Data retained during Deep power-down mode" textline " " bitfld.long 0x00 5. " WAKECLKPAD_DISABLE ,Disable the external clock input for the self-wake-up time" "No,Yes" bitfld.long 0x00 4. " WAKEUPCLKHYS ,External clock input for the self-wake-up timer WKTCLKIN hysteresis enable" "Disabled,Enabled" else hexmask.long 0x00 4.--31. 1. " GPDATA ,Data retained during Deep power-down mode" endif textline " " bitfld.long 0x00 3. " LPOSCDPDEN ,Deep power-down mode low-power oscillator enable" "Disabled,Enabled" bitfld.long 0x00 2. " LPOSCEN ,10 kHz self wake-up timer low-power oscillator use enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes" bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" elif (cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) group.long 0x14++0x03 line.long 0x00 "DPDCTRL,Deep Power Down Control Register" sif (cpuis("LPC84*")) bitfld.long 0x00 7. " RESET_DISABLE ,RESET pin disable" "No,Yes" bitfld.long 0x00 6. " RESETHYS ,RESET pin hysteresis enable" "Disabled,Enabled" textline " " endif sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 5. " WAKECLKPAD_DISABLE ,Disable the external clock input for the self-wake-up time" "No,Yes" bitfld.long 0x00 4. " WAKEUPCLKHYS ,External clock input for the self-wake-up timer WKTCLKIN hysteresis enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 3. " LPOSCDPDEN ,Deep power-down mode low-power oscillator enable" "Disabled,Enabled" bitfld.long 0x00 2. " LPOSCEN ,10 kHz self wake-up timer low-power oscillator use enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes" bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" else sif cpuis("LPC11U6*") group.long 0x10++0x03 line.long 0x00 "GPREG4,General Purpose Register 4" hexmask.long.tbyte 0x00 12.--31. 1. " GPDATA ,Data retained during Deep power-down mode" textline " " bitfld.long 0x00 11. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes" bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" elif (cpu()!="LPC1224"&&cpu()!="LPC1225"&&cpu()!="LPC1226"&&cpu()!="LPC1227") group.long 0x10++0x03 line.long 0x00 "GPREG4,General Purpose Register 4" hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during Deep power-down mode" bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "SYSCFG,System Configuration Register" bitfld.long 0x00 11.--14. " RTCCLK ,RTC clock source select" "1 Hz clock,delayed 1 Hz clock,,,RTC PCLK,RTC PCLK,RTC PCLK,RTC PCLK,,,1 kHz clock,1 kHz clock,?..." textline " " bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" endif endif width 0x0B tree.end endif sif (cpuis("LPC80*")||cpuis("LPC8N04")) tree "IOCON (I/O Configuration)" base ad:0x40044000 width 9. sif (cpuis("LPC804*")) group.long 0x0++0x03 line.long 0x00 "PIO0_17,Pin 17 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x4++0x03 line.long 0x00 "PIO0_13,Pin 13 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x8++0x03 line.long 0x00 "PIO0_12,Pin 12 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0xC++0x03 line.long 0x00 "PIO0_5,Pin 5 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x10++0x03 line.long 0x00 "PIO0_4,Pin 4 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x14++0x03 line.long 0x00 "PIO0_3,Pin 3 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x18++0x03 line.long 0x00 "PIO0_2,Pin 2 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x1C++0x03 line.long 0x00 "PIO0_11,Pin 11 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x20++0x03 line.long 0x00 "PIO0_10,Pin 10 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x24++0x03 line.long 0x00 "PIO0_16,Pin 16 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x28++0x03 line.long 0x00 "PIO0_15,Pin 15 Input/Output Configuration Register" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x2C++0x03 line.long 0x00 "PIO0_1,Pin 1 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x30++0x03 line.long 0x00 "PIO0_21,Pin 21 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x34++0x03 line.long 0x00 "PIO0_9,Pin 9 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x38++0x03 line.long 0x00 "PIO0_8,Pin 8 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x3C++0x03 line.long 0x00 "PIO0_7,Pin 7 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x40++0x03 line.long 0x00 "PIO0_29,Pin 29 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x44++0x03 line.long 0x00 "PIO0_0,Pin 0 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x48++0x03 line.long 0x00 "PIO0_14,Pin 14 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x4C++0x03 line.long 0x00 "PIO0_28,Pin 28 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x50++0x03 line.long 0x00 "PIO0_27,Pin 27 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x54++0x03 line.long 0x00 "PIO0_26,Pin 26 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x58++0x03 line.long 0x00 "PIO0_20,Pin 20 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x5C++0x03 line.long 0x00 "PIO0_30,Pin 30 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x60++0x03 line.long 0x00 "PIO0_19,Pin 19 Input/Output Configuration Register" bitfld.long 0x00 16. " DACMODE ,DAC mode enable" "Disabled,Enabled" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" textline " " bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x64++0x03 line.long 0x00 "PIO0_25,Pin 25 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x68++0x03 line.long 0x00 "PIO0_24,Pin 24 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x6C++0x03 line.long 0x00 "PIO0_23,Pin 23 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x70++0x03 line.long 0x00 "PIO0_22,Pin 22 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x74++0x03 line.long 0x00 "PIO0_18,Pin 18 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" elif (cpuis("LPC802*")) group.long 0x0++0x03 line.long 0x00 "PIO0_17,Pin 17 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x4++0x03 line.long 0x00 "PIO0_13,Pin 13 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x8++0x03 line.long 0x00 "PIO0_12,Pin 12 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0xC++0x03 line.long 0x00 "PIO0_5,Pin 5 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x10++0x03 line.long 0x00 "PIO0_4,Pin 4 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x14++0x03 line.long 0x00 "PIO0_3,Pin 3 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x18++0x03 line.long 0x00 "PIO0_2,Pin 2 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x1C++0x03 line.long 0x00 "PIO0_11,Pin 11 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x20++0x03 line.long 0x00 "PIO0_10,Pin 10 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x24++0x03 line.long 0x00 "PIO0_16,Pin 16 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x28++0x03 line.long 0x00 "PIO0_15,Pin 15 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x2C++0x03 line.long 0x00 "PIO0_1,Pin 1 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x34++0x03 line.long 0x00 "PIO0_9,Pin 9 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x38++0x03 line.long 0x00 "PIO0_8,Pin 8 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x3C++0x03 line.long 0x00 "PIO0_7,Pin 7 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x44++0x03 line.long 0x00 "PIO0_0,Pin 0 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x48++0x03 line.long 0x00 "PIO0_14,Pin 14 Input/Output Configuration Register" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" elif (cpuis("LPC8N04*")) group.long 0x00++0x2F line.long 0x00 "PIO0_0,Pin 0 Input/Output Configuration Register" bitfld.long 0x00 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_0,Wake up,?..." line.long 0x04 "PIO0_1,Pin 1 Input/Output Configuration Register" bitfld.long 0x04 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_1,CLKOUT,?..." line.long 0x08 "PIO0_2,Pin 2 Input/Output Configuration Register" bitfld.long 0x08 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_2,SPI/SSP SSEL,?..." line.long 0x0C "PIO0_3,Pin 3 Input/Output Configuration Register" hexmask.long.byte 0x0C 16.--23. 1. " IHI ,Output low value" hexmask.long.byte 0x0C 8.--15. 1. " ILO ,Output high value" bitfld.long 0x0C 7. " DDRIVE ,Digital drive strength" "High,Ultra-high" bitfld.long 0x0C 6. " CDRIVE ,Select pint output driver" "Fixed voltage,Programmable current" textline " " bitfld.long 0x0C 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_3,CT16B_M0,?..." line.long 0x10 "PIO0_4,Pin 4 Input/Output Configuration Register" bitfld.long 0x10 8.--9. " I2CMODE ,Selects the output mode of the pad" "I2C-bus,Open-drain,?..." bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C-bus SCL,?..." line.long 0x14 "PIO0_5,Pin 5 Input/Output Configuration Register" bitfld.long 0x14 8.--9. " I2CMODE ,Selects the output mode of the pad" "I2C-bus,Open-drain,?..." bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C-bus SDA,?..." line.long 0x18 "PIO0_6,Pin 6 Input/Output Configuration Register" bitfld.long 0x18 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO0_6,SPI/SSP SCLK,?..." line.long 0x1C "PIO0_7,Pin 7 Input/Output Configuration Register" hexmask.long.byte 0x1C 16.--23. 1. " IHI ,Output low value" hexmask.long.byte 0x1C 8.--15. 1. " ILO ,Output high value" bitfld.long 0x1C 7. " DDRIVE ,Digital drive strength" "High,Ultra-high" bitfld.long 0x1C 6. " CDRIVE ,Select pint output driver" "Fixed voltage,Programmable current" textline " " bitfld.long 0x1C 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x1C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x1C 0.--2. " FUNC ,Selects pin function" "PIO0_7,CT16B_M1,?..." line.long 0x20 "PIO0_8,Pin 8 Input/Output Configuration Register" bitfld.long 0x20 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x20 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x20 0.--2. " FUNC ,Selects pin function" "PIO0_8,SPI/SSP MISO,?..." line.long 0x24 "PIO0_9,Pin 9 Input/Output Configuration Register" bitfld.long 0x24 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x24 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x24 0.--2. " FUNC ,Selects pin function" "PIO0_9,SPI/SSP MOSI,?..." line.long 0x28 "PIO0_10,Pin 10 Input/Output Configuration Register" hexmask.long.byte 0x28 16.--23. 1. " IHI ,Output low value" hexmask.long.byte 0x28 8.--15. 1. " ILO ,Output high value" bitfld.long 0x28 7. " DDRIVE ,Digital drive strength" "High,Ultra-high" bitfld.long 0x28 6. " CDRIVE ,Select pint output driver" "Fixed voltage,Programmable current" textline " " bitfld.long 0x28 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x28 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x28 0.--2. " FUNC ,Selects pin function" "PIO0_10,CT32B_M0,SWCLK,?..." line.long 0x2C "PIO0_11,Pin 11 Input/Output Configuration Register" hexmask.long.byte 0x2C 16.--23. 1. " IHI ,Output low value" hexmask.long.byte 0x2C 8.--15. 1. " ILO ,Output high value" bitfld.long 0x2C 7. " DDRIVE ,Digital drive strength" "High,Ultra-high" bitfld.long 0x2C 6. " CDRIVE ,Select pint output driver" "Fixed voltage,Programmable current" textline " " bitfld.long 0x2C 5. " LPF ,Low-pass filter" "Disabled,Enabled" bitfld.long 0x2C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x2C 0.--2. " FUNC ,Selects pin function" "PIO0_11,CT32B_M1,SWDIO,?..." endif width 0x0B tree.end else tree "IOCON (I/O Configuration)" base ad:0x40044000 width 9. sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpuis("LPC822M101JDH20")||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16"||cpuis("LPC84*")) group.long 0x00++0x03 line.long 0x00 "PIO0_17,I/O Configuration For Pin PIO0_17" sif cpuis("LPC84*") bitfld.long 0x00 16. " DACMODE ,DAC mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif sif cpu()!="LPC810M021FN8" group.long 0x04++0x07 line.long 0x00 "PIO0_13,I/O Configuration For Pin PIO0_13" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_12,I/O Configuration For Pin PIO0_12" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif group.long 0x0C++0x0F line.long 0x00 "PIO0_5,I/O Configuration For Pin PIO0_5/!RESET" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_4,I/O Configuration For Pin PIO0_4" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x08 "PIO0_3,I/O Configuration For Pin PIO0_3/SWCLK" bitfld.long 0x08 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x08 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x0C "PIO0_2,I/O Configuration For Pin PIO0_2/SWDIO" bitfld.long 0x0C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x0C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" sif cpu()!="LPC810M021FN8" group.long 0x1C++0x07 line.long 0x00 "PIO0_11,I/O Configuration For Pin PIO0_11" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" textline " " bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode select" "Standard/Fast-mode I2C,Standard I/O,Fast-mode plus I2C,?..." bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" line.long 0x04 "PIO0_10,I/O Configuration For Pin PIO0_10" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" textline " " bitfld.long 0x04 8.--9. " I2CMODE ,I2C mode select" "Standard/Fast-mode I2C,Standard I/O,Fast-mode plus I2C,?..." bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC822M101JDH20")||cpuis("LPC824M201JDH20")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16"||cpuis("LPC84*")) sif (!cpuis("LPC822M101JDH20")&&!cpuis("LPC824M201JDH20")) group.long 0x24++0x03 line.long 0x00 "PIO0_16,I/O Configuration For Pin PIO0_16" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif group.long 0x28++0x03 line.long 0x00 "PIO0_15,I/O Configuration For Pin PIO0_15" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif group.long 0x2C++0x03 line.long 0x00 "PIO0_1,I/O Configuration For Pin PIO0_1/ACMP_I1/CLKIN" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" sif cpu()!="LPC810M021FN8" group.long 0x34++0x07 line.long 0x00 "PIO0_9,I/O Configuration For Pin PIO0_9/XTALOUT" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_8,I/O Configuration For Pin PIO0_8/XTALIN" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" sif (!cpuis("LPC822M101JDH20")&&!cpuis("LPC824M201JDH20")) group.long 0x3C++0x07 line.long 0x00 "PIO0_7,I/O Configuration For Pin PIO0_7" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_6,I/O Configuration For Pin PIO0_6/VDDCMP" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif endif group.long 0x44++0x03 line.long 0x00 "PIO0_0,I/O Configuration For Pin PIO0_0/ACMP_I0" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpuis("LPC822M101JDH20")||cpuis("LPC824M201JDH20")||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16"||cpuis("LPC84*")) group.long 0x48++0x03 line.long 0x00 "PIO0_14,I/O Configuration For Pin PIO0_14" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) group.long 0x50++0x07 line.long 0x00 "PIO0_28,I/O Configuration For Pin PIO0_28" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_27,I/O Configuration For Pin PIO0_27" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x58++0x07 line.long 0x00 "PIO0_26,I/O Configuration For Pin PIO0_26" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_25,I/O Configuration For Pin PIO0_25" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x60++0x03 line.long 0x00 "PIO0_24,I/O Configuration For Pin PIO0_24" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif sif (cpuis("LPC822M101JDH20")||cpuis("LPC824M201JDH20")||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) group.long 0x64++0x07 line.long 0x00 "PIO0_23,I/O Configuration For Pin PIO0_23" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_22,I/O Configuration For Pin PIO0_22" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x6C++0x07 line.long 0x00 "PIO0_21,I/O Configuration For Pin PIO0_21" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_20,I/O Configuration For Pin PIO0_20" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" group.long 0x74++0x07 line.long 0x00 "PIO0_19,I/O Configuration For Pin PIO0_19" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO0_18,I/O Configuration For Pin PIO0_18" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif sif cpuis("LPC84*") group.long 0x7C++0x63 line.long 0x00 "PIO1_8,I/O Configuration For Pin PIO1_8" bitfld.long 0x00 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x00 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x04 "PIO1_9,I/O Configuration For Pin PIO1_9" bitfld.long 0x04 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x04 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x08 "PIO1_12,I/O Configuration For Pin PIO1_12" bitfld.long 0x08 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x08 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x0C "PIO1_13,I/O Configuration For Pin PIO1_13" bitfld.long 0x0C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x0C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x10 "PIO0_31,I/O Configuration For Pin PIO0_31" bitfld.long 0x10 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x10 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x10 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x14 "PIO1_0,I/O Configuration For Pin PIO1_0" bitfld.long 0x14 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x14 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x14 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x14 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x14 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x18 "PIO1_1,I/O Configuration For Pin PIO1_1" bitfld.long 0x18 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x18 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x18 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x18 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x18 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x1C "PIO1_2,I/O Configuration For Pin PIO1_2" bitfld.long 0x1C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x1C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x1C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x1C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x1C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x20 "PIO1_14,I/O Configuration For Pin PIO1_14" bitfld.long 0x20 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x20 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x20 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x20 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x20 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x20 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x24 "PIO1_15,I/O Configuration For Pin PIO1_15" bitfld.long 0x24 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x24 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x24 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x24 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x24 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x24 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x28 "PIO1_3,I/O Configuration For Pin PIO1_3" bitfld.long 0x28 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x28 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x28 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x28 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x28 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x28 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x2C "PIO1_4,I/O Configuration For Pin PIO1_4" bitfld.long 0x2C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x2C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x2C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x2C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x2C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x30 "PIO1_5,I/O Configuration For Pin PIO1_5" bitfld.long 0x30 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x30 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x30 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x30 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x30 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x30 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x34 "PIO1_16,I/O Configuration For Pin PIO1_16" bitfld.long 0x34 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x34 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x34 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x34 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x34 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x34 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x38 "PIO1_17,I/O Configuration For Pin PIO1_17" bitfld.long 0x38 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x38 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x38 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x38 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x38 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x38 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x3C "PIO1_6,I/O Configuration For Pin PIO1_6" bitfld.long 0x3C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x3C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x3C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x3C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x3C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x3C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x40 "PIO1_18,I/O Configuration For Pin PIO1_18" bitfld.long 0x40 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x40 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x40 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x40 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x40 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x40 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x44 "PIO1_19,I/O Configuration For Pin PIO1_19" bitfld.long 0x44 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x44 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x44 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x44 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x44 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x44 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x48 "PIO1_7,I/O Configuration For Pin PIO1_7" bitfld.long 0x48 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x48 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x48 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x48 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x48 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x48 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x4C "PIO0_29,I/O Configuration For Pin PIO0_29" bitfld.long 0x4C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x4C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x4C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x4C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x4C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x4C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x50 "PIO1_30,I/O Configuration For Pin PIO1_30" bitfld.long 0x50 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x50 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x50 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x50 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x50 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x50 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x54 "PIO1_20,I/O Configuration For Pin PIO1_20" bitfld.long 0x54 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x54 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x54 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x54 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x54 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x54 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x58 "PIO1_21,I/O Configuration For Pin PIO1_21" bitfld.long 0x58 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x58 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x58 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x58 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x58 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x58 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x5C "PIO1_11,I/O Configuration For Pin PIO1_11" bitfld.long 0x5C 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x5C 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x5C 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x5C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x5C 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x5C 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" line.long 0x60 "PIO1_10,I/O Configuration For Pin PIO1_10" bitfld.long 0x60 13.--15. " CLK_DIV ,Input filter sampling clock peripheral clock divider" "IOCONCLKDIV0,IOCONCLKDIV1,IOCONCLKDIV2,IOCONCLKDIV3,IOCONCLKDIV4,IOCONCLKDIV5,IOCONCLKDIV6,?..." bitfld.long 0x60 11.--12. " S_MODE ,Digital filter sampling mode" "Bypass,1 clock cycle,2 clock cycles,3 clock cycles" bitfld.long 0x60 10. " OD ,Pseudo open-drain mode enable" "Disabled,Enabled" textline " " bitfld.long 0x60 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x60 5. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x60 3.--4. " MODE ,Function mode select" "Inactive,Pull-down,Pull-up,Repeater" endif width 0x0B tree.end endif tree "GPIO (General Purpose Input/Output)" sif (cpuis("LPC822M101JDH20")||cpuis("LPC824M201JDH20")||cpu()=="LPC832M101FDH20") base ad:0xA0000000 width 7. tree "Byte Pin Registers Port 0" group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin PIO0_23" bitfld.byte 0x00 0. " PBYTE ,PIO0_23 pin state" "Low,High" tree.end tree "Word Pin Registers Port 0" group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Registers Port 0 Pin PIO0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Registers Port 0 Pin PIO0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Registers Port 0 Pin PIO0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Registers Port 0 Pin PIO0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Registers Port 0 Pin PIO0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Registers Port 0 Pin PIO0_5" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Registers Port 0 Pin PIO0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Registers Port 0 Pin PIO0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Registers Port 0 Pin PIO0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Registers Port 0 Pin PIO0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Registers Port 0 Pin PIO0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Registers Port 0 Pin PIO0_13" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Registers Port 0 Pin PIO0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Registers Port 0 Pin PIO0_15" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Registers Port 0 Pin PIO0_17" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Registers Port 0 Pin PIO0_23" tree.end textline " " group.long 0x2000++0x03 line.long 0x00 "DIR0,Direction Registers Port 0" bitfld.long 0x00 23. " DIRP0_23 ,Pin direction for pin PIO0_23" "Input,Output" bitfld.long 0x00 17. " DIRP0_17 ,Pin direction for pin PIO0_17" "Input,Output" bitfld.long 0x00 15. " DIRP0_15 ,Pin direction for pin PIO0_15" "Input,Output" bitfld.long 0x00 14. " DIRP0_14 ,Pin direction for pin PIO0_14" "Input,Output" textline " " bitfld.long 0x00 13. " DIRP0_13 ,Pin direction for pin PIO0_13" "Input,Output" bitfld.long 0x00 12. " DIRP0_12 ,Pin direction for pin PIO0_12" "Input,Output" bitfld.long 0x00 11. " DIRP0_11 ,Pin direction for pin PIO0_11" "Input,Output" bitfld.long 0x00 10. " DIRP0_10 ,Pin direction for pin PIO0_10" "Input,Output" textline " " bitfld.long 0x00 9. " DIRP0_9 ,Pin direction for pin PIO0_9" "Input,Output" bitfld.long 0x00 8. " DIRP0_8 ,Pin direction for pin PIO0_8" "Input,Output" bitfld.long 0x00 5. " DIRP0_5 ,Pin direction for pin PIO0_5" "Input,Output" bitfld.long 0x00 4. " DIRP0_4 ,Pin direction for pin PIO0_4" "Input,Output" textline " " bitfld.long 0x00 3. " DIRP0_3 ,Pin direction for pin PIO0_3" "Input,Output" bitfld.long 0x00 2. " DIRP0_2 ,Pin direction for pin PIO0_2" "Input,Output" bitfld.long 0x00 1. " DIRP0_1 ,Pin direction for pin PIO0_1" "Input,Output" bitfld.long 0x00 0. " DIRP0_0 ,Pin direction for pin PIO0_0" "Input,Output" group.long 0x2080++0x03 line.long 0x00 "MASK0,GPIO Mask Port 0 Register" bitfld.long 0x00 23. " MASKP0_23 ,Write via MPORT enable for pin PIO0_23" "Not masked,Masked" bitfld.long 0x00 17. " MASKP0_17 ,Write via MPORT enable for pin PIO0_17" "Not masked,Masked" bitfld.long 0x00 15. " MASKP0_15 ,Write via MPORT enable for pin PIO0_15" "Not masked,Masked" bitfld.long 0x00 14. " MASKP0_14 ,Write via MPORT enable for pin PIO0_14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MASKP0_13 ,Write via MPORT enable for pin PIO0_13" "Not masked,Masked" bitfld.long 0x00 12. " MASKP0_12 ,Write via MPORT enable for pin PIO0_12" "Not masked,Masked" bitfld.long 0x00 11. " MASKP0_11 ,Write via MPORT enable for pin PIO0_11" "Not masked,Masked" bitfld.long 0x00 10. " MASKP0_10 ,Write via MPORT enable for pin PIO0_10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MASKP0_9 ,Write via MPORT enable for pin PIO0_9" "Not masked,Masked" bitfld.long 0x00 8. " MASKP0_8 ,Write via MPORT enable for pin PIO0_8" "Not masked,Masked" bitfld.long 0x00 5. " MASKP0_5 ,Write via MPORT enable for pin PIO0_5" "Not masked,Masked" bitfld.long 0x00 4. " MASKP0_4 ,Write via MPORT enable for pin PIO0_4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MASKP0_3 ,Write via MPORT enable for pin PIO0_3" "Not masked,Masked" bitfld.long 0x00 2. " MASKP0_2 ,Write via MPORT enable for pin PIO0_2" "Not masked,Masked" bitfld.long 0x00 1. " MASKP0_1 ,Write via MPORT enable for pin PIO0_1" "Not masked,Masked" bitfld.long 0x00 0. " MASKP0_0 ,Write via MPORT enable for pin PIO0_0" "Not masked,Masked" group.long 0x2100++0x03 line.long 0x00 "PIN0,GPIO Port 0 Pin Register" bitfld.long 0x00 23. " PORT0_23 ,Pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 17. " PORT0_17 ,Pin state for pin PIO0_17" "Low,High" bitfld.long 0x00 15. " PORT0_15 ,Pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " PORT0_14 ,Pin state for pin PIO0_14" "Low,High" textline " " bitfld.long 0x00 13. " PORT0_13 ,Pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " PORT0_12 ,Pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " PORT0_11 ,Pin state for pin PIO0_11" "Low,High" bitfld.long 0x00 10. " PORT0_10 ,Pin state for pin PIO0_10" "Low,High" textline " " bitfld.long 0x00 9. " PORT0_9 ,Pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " PORT0_8 ,Pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 5. " PORT0_5 ,Pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " PORT0_4 ,Pin state for pin PIO0_4" "Low,High" textline " " bitfld.long 0x00 3. " PORT0_3 ,Pin state for pin PIO0_3" "Low,High" bitfld.long 0x00 2. " PORT0_2 ,Pin state for pin PIO0_2" "Low,High" bitfld.long 0x00 1. " PORT0_1 ,Pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " PORT0_0 ,Pin state for pin PIO0_0" "Low,High" group.long 0x2180++0x03 line.long 0x00 "MPIN0,GPIO Masked Port 0 Pin Register" bitfld.long 0x00 23. " MPORTP0_23 ,Masked pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 17. " MPORTP0_17 ,Masked pin state for pin PIO0_17" "Low,High" bitfld.long 0x00 15. " MPORTP0_15 ,Masked pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " MPORTP0_14 ,Masked pin state for pin PIO0_14" "Low,High" textline " " bitfld.long 0x00 13. " MPORTP0_13 ,Masked pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " MPORTP0_12 ,Masked pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " MPORTP0_11 ,Masked pin state for pin PIO0_11" "Low,High" bitfld.long 0x00 10. " MPORTP0_10 ,Masked pin state for pin PIO0_10" "Low,High" textline " " bitfld.long 0x00 9. " MPORTP0_9 ,Masked pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " MPORTP0_8 ,Masked pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 5. " MPORTP0_5 ,Masked pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " MPORTP0_4 ,Masked pin state for pin PIO0_4" "Low,High" textline " " bitfld.long 0x00 3. " MPORTP0_3 ,Masked pin state for pin PIO0_3" "Low,High" bitfld.long 0x00 2. " MPORTP0_2 ,Masked pin state for pin PIO0_2" "Low,High" bitfld.long 0x00 1. " MPORTP0_1 ,Masked pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " MPORTP0_0 ,Masked pin state for pin PIO0_0" "Low,High" group.long 0x2200++0x03 line.long 0x00 "SET0,GPIO Set Port 0 Pin Register" bitfld.long 0x00 23. " SETP0_23 ,Set pin PIO0_23" "No effect,Set" bitfld.long 0x00 17. " SETP0_17 ,Set pin PIO0_17" "No effect,Set" bitfld.long 0x00 15. " SETP0_15 ,Set pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " SETP0_14 ,Set pin PIO0_14" "No effect,Set" textline " " bitfld.long 0x00 13. " SETP0_13 ,Set pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " SETP0_12 ,Set pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " SETP0_11 ,Set pin PIO0_11" "No effect,Set" bitfld.long 0x00 10. " SETP0_10 ,Set pin PIO0_10" "No effect,Set" textline " " bitfld.long 0x00 9. " SETP0_9 ,Set pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " SETP0_8 ,Set pin PIO0_8" "No effect,Set" bitfld.long 0x00 5. " SETP0_5 ,Set pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " SETP0_4 ,Set pin PIO0_4" "No effect,Set" textline " " bitfld.long 0x00 3. " SETP0_3 ,Set pin PIO0_3" "No effect,Set" bitfld.long 0x00 2. " SETP0_2 ,Set pin PIO0_2" "No effect,Set" bitfld.long 0x00 1. " SETP0_1 ,Set pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " SETP0_0 ,Set pin PIO0_0" "No effect,Set" wgroup.long 0x2800++0x03 line.long 0x00 "CLR0,GPIO Clear Port 0 Pin Register" bitfld.long 0x00 23. " CLRP0_23 ,Set pin PIO0_23" "No effect,Clear" bitfld.long 0x00 17. " CLRP0_17 ,Set pin PIO0_17" "No effect,Clear" bitfld.long 0x00 15. " CLRP0_15 ,Set pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " CLRP0_14 ,Set pin PIO0_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " CLRP0_13 ,Set pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " CLRP0_12 ,Set pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " CLRP0_11 ,Set pin PIO0_11" "No effect,Clear" bitfld.long 0x00 10. " CLRP0_10 ,Set pin PIO0_10" "No effect,Clear" textline " " bitfld.long 0x00 9. " CLRP0_9 ,Set pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " CLRP0_8 ,Set pin PIO0_8" "No effect,Clear" bitfld.long 0x00 5. " CLRP0_5 ,Set pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " CLRP0_4 ,Set pin PIO0_4" "No effect,Clear" textline " " bitfld.long 0x00 3. " CLRP0_3 ,Set pin PIO0_3" "No effect,Clear" bitfld.long 0x00 2. " CLRP0_2 ,Set pin PIO0_2" "No effect,Clear" bitfld.long 0x00 1. " CLRP0_1 ,Set pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " CLRP0_0 ,Set pin PIO0_0" "No effect,Clear" wgroup.long 0x2300++0x03 line.long 0x00 "NOT0,GPIO Toggle Port 0 Register" bitfld.long 0x00 23. " NOTP0_23 ,Toggle pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 17. " NOTP0_17 ,Toggle pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 15. " NOTP0_15 ,Toggle pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " NOTP0_14 ,Toggle pin PIO0_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " NOTP0_13 ,Toggle pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " NOTP0_12 ,Toggle pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " NOTP0_11 ,Toggle pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " NOTP0_10 ,Toggle pin PIO0_10" "No effect,Toggle" textline " " bitfld.long 0x00 9. " NOTP0_9 ,Toggle pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " NOTP0_8 ,Toggle pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 5. " NOTP0_5 ,Toggle pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " NOTP0_4 ,Toggle pin PIO0_4" "No effect,Toggle" textline " " bitfld.long 0x00 3. " NOTP0_3 ,Toggle pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " NOTP0_2 ,Toggle pin PIO0_2" "No effect,Toggle" bitfld.long 0x00 1. " NOTP0_1 ,Toggle pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " NOTP0_0 ,Toggle pin PIO0_0" "No effect,Toggle" width 9. textline " " wgroup.long 0x2380++0x03 line.long 0x00 "DIRSET0,GPIO Port 0 Direction Set Register" bitfld.long 0x00 23. " DIRSETP0_23 ,Set direction pin PIO0_23" "No effect,Set" bitfld.long 0x00 17. " DIRSETP0_17 ,Set direction pin PIO0_17" "No effect,Set" bitfld.long 0x00 15. " DIRSETP0_15 ,Set direction pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " DIRSETP0_14 ,Set direction pin PIO0_14" "No effect,Set" textline " " bitfld.long 0x00 13. " DIRSETP0_13 ,Set direction pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " DIRSETP0_12 ,Set direction pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " DIRSETP0_11 ,Set direction pin PIO0_11" "No effect,Set" bitfld.long 0x00 10. " DIRSETP0_10 ,Set direction pin PIO0_10" "No effect,Set" textline " " bitfld.long 0x00 9. " DIRSETP0_9 ,Set direction pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " DIRSETP0_8 ,Set direction pin PIO0_8" "No effect,Set" bitfld.long 0x00 5. " DIRSETP0_5 ,Set direction pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " DIRSETP0_4 ,Set direction pin PIO0_4" "No effect,Set" textline " " bitfld.long 0x00 3. " DIRSETP0_3 ,Set direction pin PIO0_3" "No effect,Set" bitfld.long 0x00 2. " DIRSETP0_2 ,Set direction pin PIO0_2" "No effect,Set" bitfld.long 0x00 1. " DIRSETP0_1 ,Set direction pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " DIRSETP0_0 ,Set direction pin PIO0_0" "No effect,Set" wgroup.long 0x2400++0x03 line.long 0x00 "DIRCLR0,GPIO Port 0 Direction Clear Register" bitfld.long 0x00 23. " DIRCLRP0_23 ,Clear direction pin PIO0_23" "No effect,Clear" bitfld.long 0x00 17. " DIRCLRP0_17 ,Clear direction pin PIO0_17" "No effect,Clear" bitfld.long 0x00 15. " DIRCLRP0_15 ,Clear direction pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " DIRCLRP0_14 ,Clear direction pin PIO0_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " DIRCLRP0_13 ,Clear direction pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " DIRCLRP0_12 ,Clear direction pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " DIRCLRP0_11 ,Clear direction pin PIO0_11" "No effect,Clear" bitfld.long 0x00 10. " DIRCLRP0_10 ,Clear direction pin PIO0_10" "No effect,Clear" textline " " bitfld.long 0x00 9. " DIRCLRP0_9 ,Clear direction pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " DIRCLRP0_8 ,Clear direction pin PIO0_8" "No effect,Clear" bitfld.long 0x00 5. " DIRCLRP0_5 ,Clear direction pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " DIRCLRP0_4 ,Clear direction pin PIO0_4" "No effect,Clear" textline " " bitfld.long 0x00 3. " DIRCLRP0_3 ,Clear direction pin PIO0_3" "No effect,Clear" bitfld.long 0x00 2. " DIRCLRP0_2 ,Clear direction pin PIO0_2" "No effect,Clear" bitfld.long 0x00 1. " DIRCLRP0_1 ,Clear direction pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " DIRCLRP0_0 ,Clear direction pin PIO0_0" "No effect,Clear" wgroup.long 0x2480++0x03 line.long 0x00 "DIRNOT0,GPIO Port 0 Direction Toggle Register" bitfld.long 0x00 23. " DIRNOTP0_23 ,Toggle direction pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 17. " DIRNOTP0_17 ,Toggle direction pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 15. " DIRNOTP0_15 ,Toggle direction pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " DIRNOTP0_14 ,Toggle direction pin PIO0_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " DIRNOTP0_13 ,Toggle direction pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " DIRNOTP0_12 ,Toggle direction pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " DIRNOTP0_11 ,Toggle direction pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " DIRNOTP0_10 ,Toggle direction pin PIO0_10" "No effect,Toggle" textline " " bitfld.long 0x00 9. " DIRNOTP0_9 ,Toggle direction pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " DIRNOTP0_8 ,Toggle direction pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 5. " DIRNOTP0_5 ,Toggle direction pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " DIRNOTP0_4 ,Toggle direction pin PIO0_4" "No effect,Toggle" textline " " bitfld.long 0x00 3. " DIRNOTP0_3 ,Toggle direction pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " DIRNOTP0_2 ,Toggle direction pin PIO0_2" "No effect,Toggle" bitfld.long 0x00 1. " DIRNOTP0_1 ,Toggle direction pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " DIRNOTP0_0 ,Toggle direction pin PIO0_0" "No effect,Toggle" width 0x0B elif cpuis("LPC80*") base ad:0xA0000000 width 9. tree "Byte Pin Registers Port 0" sif cpuis("LPC804M101JDH20")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" elif cpuis("LPC804M101JDH24") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" elif cpuis("LPC804M111JDH24") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" elif cpuis("LPC804M101JHI33") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin PIO0_22" bitfld.byte 0x00 0. " PBYTE ,PIO0_22 pin state" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin PIO0_23" bitfld.byte 0x00 0. " PBYTE ,PIO0_23 pin state" "Low,High" group.byte 0x18++0x00 line.byte 0x00 "B24,Byte Pin Register Port 0 Pin PIO0_24" bitfld.byte 0x00 0. " PBYTE ,PIO0_24 pin state" "Low,High" group.byte 0x19++0x00 line.byte 0x00 "B25,Byte Pin Register Port 0 Pin PIO0_25" bitfld.byte 0x00 0. " PBYTE ,PIO0_25 pin state" "Low,High" group.byte 0x1A++0x00 line.byte 0x00 "B26,Byte Pin Register Port 0 Pin PIO0_26" bitfld.byte 0x00 0. " PBYTE ,PIO0_26 pin state" "Low,High" group.byte 0x1B++0x00 line.byte 0x00 "B27,Byte Pin Register Port 0 Pin PIO0_27" bitfld.byte 0x00 0. " PBYTE ,PIO0_27 pin state" "Low,High" group.byte 0x1C++0x00 line.byte 0x00 "B28,Byte Pin Register Port 0 Pin PIO0_28" bitfld.byte 0x00 0. " PBYTE ,PIO0_28 pin state" "Low,High" group.byte 0x1D++0x00 line.byte 0x00 "B29,Byte Pin Register Port 0 Pin PIO0_29" bitfld.byte 0x00 0. " PBYTE ,PIO0_29 pin state" "Low,High" group.byte 0x1E++0x00 line.byte 0x00 "B30,Byte Pin Register Port 0 Pin PIO0_30" bitfld.byte 0x00 0. " PBYTE ,PIO0_30 pin state" "Low,High" elif cpuis("LPC802M011JDH20") group.byte 0x1000++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1001++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x1002++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x1003++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x1004++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x1005++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x1007++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x1008++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x1009++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0x100A++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0x100B++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0x100C++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0x100D++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0x100E++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0x100F++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x1010++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" elif cpuis("LPC802M001JDH16") group.byte 0x1000++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1001++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x1002++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x1003++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x1004++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x1005++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x1007++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x1008++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x1009++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0x100B++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0x100C++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0x100D++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0x1011++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" endif tree.end tree "Word Pin Registers Port 0" sif cpuis("LPC804M101JDH20")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1001++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1002++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x1003++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1004++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1005++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1007++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1008++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1009++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x100A++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x100B++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x100C++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x100D++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x100E++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x100F++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1010++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1011++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" elif cpuis("LPC804M101JDH24") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1001++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1002++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x1003++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1004++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1005++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1007++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1008++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1009++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x100A++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x100B++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x100C++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x100D++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x100E++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x100F++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1010++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1011++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" group.long 0x1012++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin PIO0_18" group.long 0x1013++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin PIO0_19" group.long 0x1014++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin PIO0_20" group.long 0x1015++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin PIO0_21" elif cpuis("LPC804M111JDH24") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1001++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1002++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x1003++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1004++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1005++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1007++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1008++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1009++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x100A++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x100B++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x100C++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x100D++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x100E++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x100F++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1010++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1012++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin PIO0_18" group.long 0x1013++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin PIO0_19" group.long 0x1014++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin PIO0_20" group.long 0x1015++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin PIO0_21" elif cpuis("LPC804M101JHI33") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1001++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1002++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x1003++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1004++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1005++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1007++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1008++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1009++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x100A++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x100B++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x100C++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x100D++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x100E++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x100F++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1010++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1011++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" group.long 0x1012++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin PIO0_18" group.long 0x1013++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin PIO0_19" group.long 0x1014++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin PIO0_20" group.long 0x1015++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin PIO0_21" group.long 0x1016++0x03 line.long 0x00 "W22,Word Pin Register Port 0 Pin PIO0_22" group.long 0x1017++0x03 line.long 0x00 "W23,Word Pin Register Port 0 Pin PIO0_23" group.long 0x1018++0x03 line.long 0x00 "W24,Word Pin Register Port 0 Pin PIO0_24" group.long 0x1019++0x03 line.long 0x00 "W25,Word Pin Register Port 0 Pin PIO0_25" group.long 0x101A++0x03 line.long 0x00 "W26,Word Pin Register Port 0 Pin PIO0_26" group.long 0x101B++0x03 line.long 0x00 "W27,Word Pin Register Port 0 Pin PIO0_27" group.long 0x101C++0x03 line.long 0x00 "W28,Word Pin Register Port 0 Pin PIO0_28" group.long 0x101D++0x03 line.long 0x00 "W29,Word Pin Register Port 0 Pin PIO0_29" group.long 0x101E++0x03 line.long 0x00 "W30,Word Pin Register Port 0 Pin PIO0_30" elif cpuis("LPC802M011JDH20") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1001++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1002++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x1003++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1004++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1005++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1007++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1008++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1009++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x100A++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x100B++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x100C++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x100D++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x100E++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x100F++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1010++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" elif cpuis("LPC802M001JDH16") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1001++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1002++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x1003++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1004++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1005++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1007++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1008++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1009++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x100B++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x100C++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x100D++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x1011++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" endif tree.end textline " " group.long 0x2000++0x3 line.long 0x00 "DIR0,Direction Register Port 0" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " DIRP0_30 ,Pin direction for pin PIO0_30" "Input,Output" bitfld.long 0x00 29. " DIRP0_29 ,Pin direction for pin PIO0_29" "Input,Output" bitfld.long 0x00 28. " DIRP0_28 ,Pin direction for pin PIO0_28" "Input,Output" bitfld.long 0x00 27. " DIRP0_27 ,Pin direction for pin PIO0_27" "Input,Output" textline " " bitfld.long 0x00 26. " DIRP0_26 ,Pin direction for pin PIO0_26" "Input,Output" bitfld.long 0x00 25. " DIRP0_25 ,Pin direction for pin PIO0_25" "Input,Output" bitfld.long 0x00 24. " DIRP0_24 ,Pin direction for pin PIO0_24" "Input,Output" textline " " bitfld.long 0x00 23. " DIRP0_23 ,Pin direction for pin PIO0_23" "Input,Output" bitfld.long 0x00 22. " DIRP0_22 ,Pin direction for pin PIO0_22" "Input,Output" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " DIRP0_21 ,Pin direction for pin PIO0_21" "Input,Output" bitfld.long 0x00 20. " DIRP0_20 ,Pin direction for pin PIO0_20" "Input,Output" bitfld.long 0x00 19. " DIRP0_19 ,Pin direction for pin PIO0_19" "Input,Output" bitfld.long 0x00 18. " DIRP0_18 ,Pin direction for pin PIO0_18" "Input,Output" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " DIRP0_17 ,Pin direction for pin PIO0_17" "Input,Output" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " DIRP0_16 ,Pin direction for pin PIO0_16" "Input,Output" bitfld.long 0x00 15. " DIRP0_15 ,Pin direction for pin PIO0_15" "Input,Output" bitfld.long 0x00 14. " DIRP0_14 ,Pin direction for pin PIO0_14" "Input,Output" textline " " endif bitfld.long 0x00 13. " DIRP0_13 ,Pin direction for pin PIO0_13" "Input,Output" bitfld.long 0x00 12. " DIRP0_12 ,Pin direction for pin PIO0_12" "Input,Output" bitfld.long 0x00 11. " DIRP0_11 ,Pin direction for pin PIO0_11" "Input,Output" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " DIRP0_10 ,Pin direction for pin PIO0_10" "Input,Output" endif textline " " bitfld.long 0x00 9. " DIRP0_9 ,Pin direction for pin PIO0_9" "Input,Output" bitfld.long 0x00 8. " DIRP0_8 ,Pin direction for pin PIO0_8" "Input,Output" bitfld.long 0x00 7. " DIRP0_7 ,Pin direction for pin PIO0_7" "Input,Output" textline " " bitfld.long 0x00 5. " DIRP0_5 ,Pin direction for pin PIO0_5" "Input,Output" bitfld.long 0x00 4. " DIRP0_4 ,Pin direction for pin PIO0_4" "Input,Output" bitfld.long 0x00 3. " DIRP0_3 ,Pin direction for pin PIO0_3" "Input,Output" textline " " bitfld.long 0x00 2. " DIRP0_2 ,Pin direction for pin PIO0_2" "Input,Output" bitfld.long 0x00 1. " DIRP0_1 ,Pin direction for pin PIO0_1" "Input,Output" bitfld.long 0x00 0. " DIRP0_0 ,Pin direction for pin PIO0_0" "Input,Output" group.long 0x2080++0x03 line.long 0x00 "MASK0,GPIO Mask Port 0 Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " MASKP0_30 ,Write via MPORT enable for pin PIO0_30" "Not masked,Masked" bitfld.long 0x00 29. " MASKP0_29 ,Write via MPORT enable for pin PIO0_29" "Not masked,Masked" bitfld.long 0x00 28. " MASKP0_28 ,Write via MPORT enable for pin PIO0_28" "Not masked,Masked" bitfld.long 0x00 27. " MASKP0_27 ,Write via MPORT enable for pin PIO0_27" "Not masked,Masked" textline " " bitfld.long 0x00 26. " MASKP0_26 ,Write via MPORT enable for pin PIO0_26" "Not masked,Masked" bitfld.long 0x00 25. " MASKP0_25 ,Write via MPORT enable for pin PIO0_25" "Not masked,Masked" bitfld.long 0x00 24. " MASKP0_24 ,Write via MPORT enable for pin PIO0_24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MASKP0_23 ,Write via MPORT enable for pin PIO0_23" "Not masked,Masked" bitfld.long 0x00 22. " MASKP0_22 ,Write via MPORT enable for pin PIO0_22" "Not masked,Masked" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " MASKP0_21 ,Write via MPORT enable for pin PIO0_21" "Not masked,Masked" textline " " bitfld.long 0x00 20. " MASKP0_20 ,Write via MPORT enable for pin PIO0_20" "Not masked,Masked" bitfld.long 0x00 19. " MASKP0_19 ,Write via MPORT enable for pin PIO0_19" "Not masked,Masked" bitfld.long 0x00 18. " MASKP0_18 ,Write via MPORT enable for pin PIO0_18" "Not masked,Masked" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " MASKP0_17 ,Write via MPORT enable for pin PIO0_17" "Not masked,Masked" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " MASKP0_16 ,Write via MPORT enable for pin PIO0_16" "Not masked,Masked" bitfld.long 0x00 15. " MASKP0_15 ,Write via MPORT enable for pin PIO0_15" "Not masked,Masked" bitfld.long 0x00 14. " MASKP0_14 ,Write via MPORT enable for pin PIO0_14" "Not masked,Masked" textline " " endif bitfld.long 0x00 13. " MASKP0_13 ,Write via MPORT enable for pin PIO0_13" "Not masked,Masked" bitfld.long 0x00 12. " MASKP0_12 ,Write via MPORT enable for pin PIO0_12" "Not masked,Masked" bitfld.long 0x00 11. " MASKP0_11 ,Write via MPORT enable for pin PIO0_11" "Not masked,Masked" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " MASKP0_10 ,Write via MPORT enable for pin PIO0_10" "Not masked,Masked" endif textline " " bitfld.long 0x00 9. " MASKP0_9 ,Write via MPORT enable for pin PIO0_9" "Not masked,Masked" bitfld.long 0x00 8. " MASKP0_8 ,Write via MPORT enable for pin PIO0_8" "Not masked,Masked" bitfld.long 0x00 7. " MASKP0_7 ,Write via MPORT enable for pin PIO0_7" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MASKP0_5 ,Write via MPORT enable for pin PIO0_5" "Not masked,Masked" bitfld.long 0x00 4. " MASKP0_4 ,Write via MPORT enable for pin PIO0_4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MASKP0_3 ,Write via MPORT enable for pin PIO0_3" "Not masked,Masked" bitfld.long 0x00 2. " MASKP0_2 ,Write via MPORT enable for pin PIO0_2" "Not masked,Masked" bitfld.long 0x00 1. " MASKP0_1 ,Write via MPORT enable for pin PIO0_1" "Not masked,Masked" bitfld.long 0x00 0. " MASKP0_0 ,Write via MPORT enable for pin PIO0_0" "Not masked,Masked" group.long 0x2100++0x03 line.long 0x00 "PIN0,GPIO Port 0 Pin Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " PORT0_30 ,Pin state for pin PIO0_30" "Low,High" bitfld.long 0x00 29. " PORT0_29 ,Pin state for pin PIO0_29" "Low,High" bitfld.long 0x00 28. " PORT0_28 ,Pin state for pin PIO0_28" "Low,High" bitfld.long 0x00 27. " PORT0_27 ,Pin state for pin PIO0_27" "Low,High" textline " " bitfld.long 0x00 26. " PORT0_26 ,Pin state for pin PIO0_26" "Low,High" bitfld.long 0x00 25. " PORT0_25 ,Pin state for pin PIO0_25" "Low,High" bitfld.long 0x00 24. " PORT0_24 ,Pin state for pin PIO0_24" "Low,High" textline " " bitfld.long 0x00 23. " PORT0_23 ,Pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 22. " PORT0_22 ,Pin state for pin PIO0_22" "Low,High" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " PORT0_21 ,Pin state for pin PIO0_21" "Low,High" bitfld.long 0x00 20. " PORT0_20 ,Pin state for pin PIO0_20" "Low,High" bitfld.long 0x00 19. " PORT0_19 ,Pin state for pin PIO0_19" "Low,High" bitfld.long 0x00 18. " PORT0_18 ,Pin state for pin PIO0_18" "Low,High" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " PORT0_17 ,Pin state for pin PIO0_17" "Low,High" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " PORT0_16 ,Pin state for pin PIO0_16" "Low,High" bitfld.long 0x00 15. " PORT0_15 ,Pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " PORT0_14 ,Pin state for pin PIO0_14" "Low,High" textline " " endif bitfld.long 0x00 13. " PORT0_13 ,Pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " PORT0_12 ,Pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " PORT0_11 ,Pin state for pin PIO0_11" "Low,High" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " PORT0_10 ,Pin state for pin PIO0_10" "Low,High" endif textline " " bitfld.long 0x00 9. " PORT0_9 ,Pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " PORT0_8 ,Pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 7. " PORT0_7 ,Pin state for pin PIO0_7" "Low,High" textline " " bitfld.long 0x00 5. " PORT0_5 ,Pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " PORT0_4 ,Pin state for pin PIO0_4" "Low,High" bitfld.long 0x00 3. " PORT0_3 ,Pin state for pin PIO0_3" "Low,High" textline " " bitfld.long 0x00 2. " PORT0_2 ,Pin state for pin PIO0_2" "Low,High" bitfld.long 0x00 1. " PORT0_1 ,Pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " PORT0_0 ,Pin state for pin PIO0_0" "Low,High" group.long 0x2180++0x03 line.long 0x00 "MPIN0,GPIO Masked Port 0 Pin Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " MPORTP0_30 ,Masked pin state for pin PIO0_30" "Low,High" bitfld.long 0x00 29. " MPORTP0_29 ,Masked pin state for pin PIO0_29" "Low,High" bitfld.long 0x00 28. " MPORTP0_28 ,Masked pin state for pin PIO0_28" "Low,High" bitfld.long 0x00 27. " MPORTP0_27 ,Masked pin state for pin PIO0_27" "Low,High" textline " " bitfld.long 0x00 26. " MPORTP0_26 ,Masked pin state for pin PIO0_26" "Low,High" bitfld.long 0x00 25. " MPORTP0_25 ,Masked pin state for pin PIO0_25" "Low,High" bitfld.long 0x00 24. " MPORTP0_24 ,Masked pin state for pin PIO0_24" "Low,High" textline " " bitfld.long 0x00 23. " MPORTP0_23 ,Masked pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 22. " MPORTP0_22 ,Masked pin state for pin PIO0_22" "Low,High" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " MPORTP0_21 ,Masked pin state for pin PIO0_21" "Low,High" bitfld.long 0x00 20. " MPORTP0_20 ,Masked pin state for pin PIO0_20" "Low,High" bitfld.long 0x00 19. " MPORTP0_19 ,Masked pin state for pin PIO0_19" "Low,High" bitfld.long 0x00 18. " MPORTP0_18 ,Masked pin state for pin PIO0_18" "Low,High" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " MPORTP0_17 ,Masked pin state for pin PIO0_17" "Low,High" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " MPORTP0_16 ,Masked pin state for pin PIO0_16" "Low,High" bitfld.long 0x00 15. " MPORTP0_15 ,Masked pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " MPORTP0_14 ,Masked pin state for pin PIO0_14" "Low,High" textline " " endif bitfld.long 0x00 13. " MPORTP0_13 ,Masked pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " MPORTP0_12 ,Masked pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " MPORTP0_11 ,Masked pin state for pin PIO0_11" "Low,High" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " MPORTP0_10 ,Masked pin state for pin PIO0_10" "Low,High" endif textline " " bitfld.long 0x00 9. " MPORTP0_9 ,Masked pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " MPORTP0_8 ,Masked pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 7. " MPORTP0_7 ,Masked pin state for pin PIO0_7" "Low,High" textline " " bitfld.long 0x00 5. " MPORTP0_5 ,Masked pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " MPORTP0_4 ,Masked pin state for pin PIO0_4" "Low,High" bitfld.long 0x00 3. " MPORTP0_3 ,Masked pin state for pin PIO0_3" "Low,High" textline " " bitfld.long 0x00 2. " MPORTP0_2 ,Masked pin state for pin PIO0_2" "Low,High" bitfld.long 0x00 1. " MPORTP0_1 ,Masked pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " MPORTP0_0 ,Masked pin state for pin PIO0_0" "Low,High" group.long 0x2200++0x03 line.long 0x00 "SET0,GPIO Set Port 0 Pin Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " SETP0_30 ,Set pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " SETP0_29 ,Set pin PIO0_29" "No effect,Set" bitfld.long 0x00 28. " SETP0_28 ,Set pin PIO0_28" "No effect,Set" bitfld.long 0x00 27. " SETP0_27 ,Set pin PIO0_27" "No effect,Set" textline " " bitfld.long 0x00 26. " SETP0_26 ,Set pin PIO0_26" "No effect,Set" bitfld.long 0x00 25. " SETP0_25 ,Set pin PIO0_25" "No effect,Set" bitfld.long 0x00 24. " SETP0_24 ,Set pin PIO0_24" "No effect,Set" textline " " bitfld.long 0x00 23. " SETP0_23 ,Set pin PIO0_23" "No effect,Set" bitfld.long 0x00 22. " SETP0_22 ,Set pin PIO0_22" "No effect,Set" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " SETP0_21 ,Set pin PIO0_21" "No effect,Set" bitfld.long 0x00 20. " SETP0_20 ,Set pin PIO0_20" "No effect,Set" bitfld.long 0x00 19. " SETP0_19 ,Set pin PIO0_19" "No effect,Set" bitfld.long 0x00 18. " SETP0_18 ,Set pin PIO0_18" "No effect,Set" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " SETP0_17 ,Set pin PIO0_17" "No effect,Set" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " SETP0_16 ,Set pin PIO0_16" "No effect,Set" bitfld.long 0x00 15. " SETP0_15 ,Set pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " SETP0_14 ,Set pin PIO0_14" "No effect,Set" textline " " endif bitfld.long 0x00 13. " SETP0_13 ,Set pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " SETP0_12 ,Set pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " SETP0_11 ,Set pin PIO0_11" "No effect,Set" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " SETP0_10 ,Set pin PIO0_10" "No effect,Set" endif textline " " bitfld.long 0x00 9. " SETP0_9 ,Set pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " SETP0_8 ,Set pin PIO0_8" "No effect,Set" bitfld.long 0x00 7. " SETP0_7 ,Set pin PIO0_7" "No effect,Set" textline " " bitfld.long 0x00 5. " SETP0_5 ,Set pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " SETP0_4 ,Set pin PIO0_4" "No effect,Set" bitfld.long 0x00 3. " SETP0_3 ,Set pin PIO0_3" "No effect,Set" textline " " bitfld.long 0x00 2. " SETP0_2 ,Set pin PIO0_2" "No effect,Set" bitfld.long 0x00 1. " SETP0_1 ,Set pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " SETP0_0 ,Set pin PIO0_0" "No effect,Set" wgroup.long 0x2280++0x03 line.long 0x00 "CLR0,GPIO Clear Port 0 Pin Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " CLRP0_30 ,Clear pin PIO0_30" "No effect,Clear" bitfld.long 0x00 29. " CLRP0_29 ,Clear pin PIO0_29" "No effect,Clear" bitfld.long 0x00 28. " CLRP0_28 ,Clear pin PIO0_28" "No effect,Clear" bitfld.long 0x00 27. " CLRP0_27 ,Clear pin PIO0_27" "No effect,Clear" textline " " bitfld.long 0x00 26. " CLRP0_26 ,Clear pin PIO0_26" "No effect,Clear" bitfld.long 0x00 25. " CLRP0_25 ,Clear pin PIO0_25" "No effect,Clear" bitfld.long 0x00 24. " CLRP0_24 ,Clear pin PIO0_24" "No effect,Clear" textline " " bitfld.long 0x00 23. " CLRP0_23 ,Clear pin PIO0_23" "No effect,Clear" bitfld.long 0x00 22. " CLRP0_22 ,Clear pin PIO0_22" "No effect,Clear" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " CLRP0_21 ,Clear pin PIO0_21" "No effect,Clear" bitfld.long 0x00 20. " CLRP0_20 ,Clear pin PIO0_20" "No effect,Clear" bitfld.long 0x00 19. " CLRP0_19 ,Clear pin PIO0_19" "No effect,Clear" bitfld.long 0x00 18. " CLRP0_18 ,Clear pin PIO0_18" "No effect,Clear" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " CLRP0_17 ,Clear pin PIO0_17" "No effect,Clear" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " CLRP0_16 ,Clear pin PIO0_16" "No effect,Clear" bitfld.long 0x00 15. " CLRP0_15 ,Clear pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " CLRP0_14 ,Clear pin PIO0_14" "No effect,Clear" textline " " endif bitfld.long 0x00 13. " CLRP0_13 ,Clear pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " CLRP0_12 ,Clear pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " CLRP0_11 ,Clear pin PIO0_11" "No effect,Clear" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " CLRP0_10 ,Clear pin PIO0_10" "No effect,Clear" endif textline " " bitfld.long 0x00 9. " CLRP0_9 ,Clear pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " CLRP0_8 ,Clear pin PIO0_8" "No effect,Clear" bitfld.long 0x00 7. " CLRP0_7 ,Clear pin PIO0_7" "No effect,Clear" textline " " bitfld.long 0x00 5. " CLRP0_5 ,Clear pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " CLRP0_4 ,Clear pin PIO0_4" "No effect,Clear" bitfld.long 0x00 3. " CLRP0_3 ,Clear pin PIO0_3" "No effect,Clear" textline " " bitfld.long 0x00 2. " CLRP0_2 ,Clear pin PIO0_2" "No effect,Clear" bitfld.long 0x00 1. " CLRP0_1 ,Clear pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " CLRP0_0 ,Clear pin PIO0_0" "No effect,Clear" wgroup.long 0x2300++0x03 line.long 0x00 "NOT0,GPIO Toggle Port 0 Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " NOTP0_30 ,Toggle pin PIO0_30" "No effect,Toggle" bitfld.long 0x00 29. " NOTP0_29 ,Toggle pin PIO0_29" "No effect,Toggle" bitfld.long 0x00 28. " NOTP0_28 ,Toggle pin PIO0_28" "No effect,Toggle" bitfld.long 0x00 27. " NOTP0_27 ,Toggle pin PIO0_27" "No effect,Toggle" textline " " bitfld.long 0x00 26. " NOTP0_26 ,Toggle pin PIO0_26" "No effect,Toggle" bitfld.long 0x00 25. " NOTP0_25 ,Toggle pin PIO0_25" "No effect,Toggle" bitfld.long 0x00 24. " NOTP0_24 ,Toggle pin PIO0_24" "No effect,Toggle" textline " " bitfld.long 0x00 23. " NOTP0_23 ,Toggle pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 22. " NOTP0_22 ,Toggle pin PIO0_22" "No effect,Toggle" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " NOTP0_21 ,Toggle pin PIO0_21" "No effect,Toggle" bitfld.long 0x00 20. " NOTP0_20 ,Toggle pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " NOTP0_19 ,Toggle pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " NOTP0_18 ,Toggle pin PIO0_18" "No effect,Toggle" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " NOTP0_17 ,Toggle pin PIO0_17" "No effect,Toggle" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " NOTP0_16 ,Toggle pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " NOTP0_15 ,Toggle pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " NOTP0_14 ,Toggle pin PIO0_14" "No effect,Toggle" textline " " endif bitfld.long 0x00 13. " NOTP0_13 ,Toggle pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " NOTP0_12 ,Toggle pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " NOTP0_11 ,Toggle pin PIO0_11" "No effect,Toggle" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " NOTP0_10 ,Toggle pin PIO0_10" "No effect,Toggle" endif textline " " bitfld.long 0x00 9. " NOTP0_9 ,Toggle pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " NOTP0_8 ,Toggle pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " NOTP0_7 ,Toggle pin PIO0_7" "No effect,Toggle" textline " " bitfld.long 0x00 5. " NOTP0_5 ,Toggle pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " NOTP0_4 ,Toggle pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " NOTP0_3 ,Toggle pin PIO0_3" "No effect,Toggle" textline " " bitfld.long 0x00 2. " NOTP0_2 ,Toggle pin PIO0_2" "No effect,Toggle" bitfld.long 0x00 1. " NOTP0_1 ,Toggle pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " NOTP0_0 ,Toggle pin PIO0_0" "No effect,Toggle" wgroup.long 0x2380++0x03 line.long 0x00 "DIRSET0,GPIO Port 0 Direction Set Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " DIRSETP0_30 ,Set direction pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " DIRSETP0_29 ,Set direction pin PIO0_29" "No effect,Set" bitfld.long 0x00 28. " DIRSETP0_28 ,Set direction pin PIO0_28" "No effect,Set" bitfld.long 0x00 27. " DIRSETP0_27 ,Set direction pin PIO0_27" "No effect,Set" textline " " bitfld.long 0x00 26. " DIRSETP0_26 ,Set direction pin PIO0_26" "No effect,Set" bitfld.long 0x00 25. " DIRSETP0_25 ,Set direction pin PIO0_25" "No effect,Set" bitfld.long 0x00 24. " DIRSETP0_24 ,Set direction pin PIO0_24" "No effect,Set" textline " " bitfld.long 0x00 23. " DIRSETP0_23 ,Set direction pin PIO0_23" "No effect,Set" bitfld.long 0x00 22. " DIRSETP0_22 ,Set direction pin PIO0_22" "No effect,Set" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " DIRSETP0_21 ,Set direction pin PIO0_21" "No effect,Set" bitfld.long 0x00 20. " DIRSETP0_20 ,Set direction pin PIO0_20" "No effect,Set" bitfld.long 0x00 19. " DIRSETP0_19 ,Set direction pin PIO0_19" "No effect,Set" bitfld.long 0x00 18. " DIRSETP0_18 ,Set direction pin PIO0_18" "No effect,Set" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " DIRSETP0_17 ,Set direction pin PIO0_17" "No effect,Set" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " DIRSETP0_16 ,Set direction pin PIO0_16" "No effect,Set" bitfld.long 0x00 15. " DIRSETP0_15 ,Set direction pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " DIRSETP0_14 ,Set direction pin PIO0_14" "No effect,Set" textline " " endif bitfld.long 0x00 13. " DIRSETP0_13 ,Set direction pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " DIRSETP0_12 ,Set direction pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " DIRSETP0_11 ,Set direction pin PIO0_11" "No effect,Set" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " DIRSETP0_10 ,Set direction pin PIO0_10" "No effect,Set" endif textline " " bitfld.long 0x00 9. " DIRSETP0_9 ,Set direction pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " DIRSETP0_8 ,Set direction pin PIO0_8" "No effect,Set" bitfld.long 0x00 7. " DIRSETP0_7 ,Set direction pin PIO0_7" "No effect,Set" textline " " bitfld.long 0x00 5. " DIRSETP0_5 ,Set direction pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " DIRSETP0_4 ,Set direction pin PIO0_4" "No effect,Set" bitfld.long 0x00 3. " DIRSETP0_3 ,Set direction pin PIO0_3" "No effect,Set" textline " " bitfld.long 0x00 2. " DIRSETP0_2 ,Set direction pin PIO0_2" "No effect,Set" bitfld.long 0x00 1. " DIRSETP0_1 ,Set direction pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " DIRSETP0_0 ,Set direction pin PIO0_0" "No effect,Set" wgroup.long 0x2400++0x03 line.long 0x00 "DIRCLR0,GPIO Port 0 Direction Clear Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " DIRCLRP0_30 ,Clear direction pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " DIRCLRP0_29 ,Clear direction pin PIO0_29" "No effect,Set" bitfld.long 0x00 28. " DIRCLRP0_28 ,Clear direction pin PIO0_28" "No effect,Clear" bitfld.long 0x00 27. " DIRCLRP0_27 ,Clear direction pin PIO0_27" "No effect,Clear" textline " " bitfld.long 0x00 26. " DIRCLRP0_26 ,Clear direction pin PIO0_26" "No effect,Clear" bitfld.long 0x00 25. " DIRCLRP0_25 ,Clear direction pin PIO0_25" "No effect,Clear" bitfld.long 0x00 24. " DIRCLRP0_24 ,Clear direction pin PIO0_24" "No effect,Clear" textline " " bitfld.long 0x00 23. " DIRCLRP0_23 ,Clear direction pin PIO0_23" "No effect,Clear" bitfld.long 0x00 22. " DIRCLRP0_22 ,Clear direction pin PIO0_22" "No effect,Clear" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " DIRCLRP0_21 ,Clear direction pin PIO0_21" "No effect,Clear" bitfld.long 0x00 20. " DIRCLRP0_20 ,Clear direction pin PIO0_20" "No effect,Clear" bitfld.long 0x00 19. " DIRCLRP0_19 ,Clear direction pin PIO0_19" "No effect,Clear" bitfld.long 0x00 18. " DIRCLRP0_18 ,Clear direction pin PIO0_18" "No effect,Clear" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " DIRCLRP0_17 ,Clear direction pin PIO0_17" "No effect,Clear" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " DIRCLRP0_16 ,Clear direction pin PIO0_16" "No effect,Clear" bitfld.long 0x00 15. " DIRCLRP0_15 ,Clear direction pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " DIRCLRP0_14 ,Clear direction pin PIO0_14" "No effect,Clear" textline " " endif bitfld.long 0x00 13. " DIRCLRP0_13 ,Clear direction pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " DIRCLRP0_12 ,Clear direction pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " DIRCLRP0_11 ,Clear direction pin PIO0_11" "No effect,Clear" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " DIRCLRP0_10 ,Clear direction pin PIO0_10" "No effect,Clear" endif textline " " bitfld.long 0x00 9. " DIRCLRP0_9 ,Clear direction pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " DIRCLRP0_8 ,Clear direction pin PIO0_8" "No effect,Clear" bitfld.long 0x00 7. " DIRCLRP0_7 ,Clear direction pin PIO0_7" "No effect,Clear" textline " " bitfld.long 0x00 5. " DIRCLRP0_5 ,Clear direction pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " DIRCLRP0_4 ,Clear direction pin PIO0_4" "No effect,Clear" bitfld.long 0x00 3. " DIRCLRP0_3 ,Clear direction pin PIO0_3" "No effect,Clear" textline " " bitfld.long 0x00 2. " DIRCLRP0_2 ,Clear direction pin PIO0_2" "No effect,Clear" bitfld.long 0x00 1. " DIRCLRP0_1 ,Clear direction pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " DIRCLRP0_0 ,Clear direction pin PIO0_0" "No effect,Clear" wgroup.long 0x2480++0x03 line.long 0x00 "DIRNOT0,GPIO Port 0 Direction Toggle Register" sif cpuis("LPC804M101JHI33") bitfld.long 0x00 30. " DIRNOTP0_30 ,Toggle direction pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " DIRNOTP0_29 ,Toggle direction pin PIO0_29" "No effect,Set" bitfld.long 0x00 28. " DIRNOTP0_28 ,Toggle direction pin PIO0_28" "No effect,Toggle" bitfld.long 0x00 27. " DIRNOTP0_27 ,Toggle direction pin PIO0_27" "No effect,Toggle" textline " " bitfld.long 0x00 26. " DIRNOTP0_26 ,Toggle direction pin PIO0_26" "No effect,Toggle" bitfld.long 0x00 25. " DIRNOTP0_25 ,Toggle direction pin PIO0_25" "No effect,Toggle" bitfld.long 0x00 24. " DIRNOTP0_24 ,Toggle direction pin PIO0_24" "No effect,Toggle" textline " " bitfld.long 0x00 23. " DIRNOTP0_23 ,Toggle direction pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 22. " DIRNOTP0_22 ,Toggle direction pin PIO0_22" "No effect,Toggle" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") bitfld.long 0x00 21. " DIRNOTP0_21 ,Toggle direction pin PIO0_21" "No effect,Toggle" bitfld.long 0x00 20. " DIRNOTP0_20 ,Toggle direction pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " DIRNOTP0_19 ,Toggle direction pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " DIRNOTP0_18 ,Toggle direction pin PIO0_18" "No effect,Toggle" textline " " endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JHI33")||cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33") bitfld.long 0x00 17. " DIRNOTP0_17 ,Toggle direction pin PIO0_17" "No effect,Toggle" textline " " endif sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 16. " DIRNOTP0_16 ,Toggle direction pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " DIRNOTP0_15 ,Toggle direction pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " DIRNOTP0_14 ,Toggle direction pin PIO0_14" "No effect,Toggle" textline " " endif bitfld.long 0x00 13. " DIRNOTP0_13 ,Toggle direction pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " DIRNOTP0_12 ,Toggle direction pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " DIRNOTP0_11 ,Toggle direction pin PIO0_11" "No effect,Toggle" sif !cpuis("LPC802M001JDH16") bitfld.long 0x00 10. " DIRNOTP0_10 ,Toggle direction pin PIO0_10" "No effect,Toggle" endif textline " " bitfld.long 0x00 9. " DIRNOTP0_9 ,Toggle direction pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " DIRNOTP0_8 ,Toggle direction pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " DIRNOTP0_7 ,Toggle direction pin PIO0_7" "No effect,Toggle" textline " " bitfld.long 0x00 5. " DIRNOTP0_5 ,Toggle direction pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " DIRNOTP0_4 ,Toggle direction pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " DIRNOTP0_3 ,Toggle direction pin PIO0_3" "No effect,Toggle" textline " " bitfld.long 0x00 2. " DIRNOTP0_2 ,Toggle direction pin PIO0_2" "No effect,Toggle" bitfld.long 0x00 1. " DIRNOTP0_1 ,Toggle direction pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " DIRNOTP0_0 ,Toggle direction pin PIO0_0" "No effect,Toggle" width 0x0B elif (cpuis("LPC84*")) base ad:0xA0000000 width 9. tree "Byte Pin Registers Port 0" sif (cpu()=="LPC844M201JHI33"||cpu()=="LPC845M301JHI33") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin PIO0_6" bitfld.byte 0x00 0. " PBYTE ,PIO0_6 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin PIO0_22" bitfld.byte 0x00 0. " PBYTE ,PIO0_22 pin state" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin PIO0_23" bitfld.byte 0x00 0. " PBYTE ,PIO0_23 pin state" "Low,High" group.byte 0x18++0x00 line.byte 0x00 "B24,Byte Pin Register Port 0 Pin PIO0_24" bitfld.byte 0x00 0. " PBYTE ,PIO0_24 pin state" "Low,High" group.byte 0x19++0x00 line.byte 0x00 "B25,Byte Pin Register Port 0 Pin PIO0_25" bitfld.byte 0x00 0. " PBYTE ,PIO0_25 pin state" "Low,High" group.byte 0x1A++0x00 line.byte 0x00 "B26,Byte Pin Register Port 0 Pin PIO0_26" bitfld.byte 0x00 0. " PBYTE ,PIO0_26 pin state" "Low,High" group.byte 0x1B++0x00 line.byte 0x00 "B27,Byte Pin Register Port 0 Pin PIO0_27" bitfld.byte 0x00 0. " PBYTE ,PIO0_27 pin state" "Low,High" group.byte 0x1C++0x00 line.byte 0x00 "B28,Byte Pin Register Port 0 Pin PIO0_28" bitfld.byte 0x00 0. " PBYTE ,PIO0_28 pin state" "Low,High" elif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin PIO0_6" bitfld.byte 0x00 0. " PBYTE ,PIO0_6 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin PIO0_22" bitfld.byte 0x00 0. " PBYTE ,PIO0_22 pin state" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin PIO0_23" bitfld.byte 0x00 0. " PBYTE ,PIO0_23 pin state" "Low,High" group.byte 0x18++0x00 line.byte 0x00 "B24,Byte Pin Register Port 0 Pin PIO0_24" bitfld.byte 0x00 0. " PBYTE ,PIO0_24 pin state" "Low,High" group.byte 0x19++0x00 line.byte 0x00 "B25,Byte Pin Register Port 0 Pin PIO0_25" bitfld.byte 0x00 0. " PBYTE ,PIO0_25 pin state" "Low,High" group.byte 0x1A++0x00 line.byte 0x00 "B26,Byte Pin Register Port 0 Pin PIO0_26" bitfld.byte 0x00 0. " PBYTE ,PIO0_26 pin state" "Low,High" group.byte 0x1B++0x00 line.byte 0x00 "B27,Byte Pin Register Port 0 Pin PIO0_27" bitfld.byte 0x00 0. " PBYTE ,PIO0_27 pin state" "Low,High" group.byte 0x1C++0x00 line.byte 0x00 "B28,Byte Pin Register Port 0 Pin PIO0_28" bitfld.byte 0x00 0. " PBYTE ,PIO0_28 pin state" "Low,High" group.byte 0x1D++0x00 line.byte 0x00 "B29,Byte Pin Register Port 0 Pin PIO0_29" bitfld.byte 0x00 0. " PBYTE ,PIO0_29 pin state" "Low,High" group.byte 0x1E++0x00 line.byte 0x00 "B30,Byte Pin Register Port 0 Pin PIO0_30" bitfld.byte 0x00 0. " PBYTE ,PIO0_30 pin state" "Low,High" group.byte 0x1F++0x00 line.byte 0x00 "B31,Byte Pin Register Port 0 Pin PIO0_31" bitfld.byte 0x00 0. " PBYTE ,PIO0_31 pin state" "Low,High" group.byte 0x20++0x00 line.byte 0x00 "B32,Byte Pin Register Port 0 Pin PIO0_32" bitfld.byte 0x00 0. " PBYTE ,PIO0_32 pin state" "Low,High" group.byte 0x21++0x00 line.byte 0x00 "B33,Byte Pin Register Port 0 Pin PIO0_33" bitfld.byte 0x00 0. " PBYTE ,PIO0_33 pin state" "Low,High" group.byte 0x22++0x00 line.byte 0x00 "B34,Byte Pin Register Port 0 Pin PIO0_34" bitfld.byte 0x00 0. " PBYTE ,PIO0_34 pin state" "Low,High" group.byte 0x23++0x00 line.byte 0x00 "B35,Byte Pin Register Port 0 Pin PIO0_35" bitfld.byte 0x00 0. " PBYTE ,PIO0_35 pin state" "Low,High" group.byte 0x24++0x00 line.byte 0x00 "B36,Byte Pin Register Port 0 Pin PIO0_36" bitfld.byte 0x00 0. " PBYTE ,PIO0_36 pin state" "Low,High" group.byte 0x25++0x00 line.byte 0x00 "B37,Byte Pin Register Port 0 Pin PIO0_37" bitfld.byte 0x00 0. " PBYTE ,PIO0_37 pin state" "Low,High" group.byte 0x26++0x00 line.byte 0x00 "B38,Byte Pin Register Port 0 Pin PIO0_38" bitfld.byte 0x00 0. " PBYTE ,PIO0_38 pin state" "Low,High" group.byte 0x27++0x00 line.byte 0x00 "B39,Byte Pin Register Port 0 Pin PIO0_39" bitfld.byte 0x00 0. " PBYTE ,PIO0_39 pin state" "Low,High" group.byte 0x28++0x00 line.byte 0x00 "B40,Byte Pin Register Port 0 Pin PIO0_40" bitfld.byte 0x00 0. " PBYTE ,PIO0_40 pin state" "Low,High" group.byte 0x29++0x00 line.byte 0x00 "B41,Byte Pin Register Port 0 Pin PIO0_41" bitfld.byte 0x00 0. " PBYTE ,PIO0_41 pin state" "Low,High" elif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin PIO0_6" bitfld.byte 0x00 0. " PBYTE ,PIO0_6 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin PIO0_22" bitfld.byte 0x00 0. " PBYTE ,PIO0_22 pin state" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin PIO0_23" bitfld.byte 0x00 0. " PBYTE ,PIO0_23 pin state" "Low,High" group.byte 0x18++0x00 line.byte 0x00 "B24,Byte Pin Register Port 0 Pin PIO0_24" bitfld.byte 0x00 0. " PBYTE ,PIO0_24 pin state" "Low,High" group.byte 0x19++0x00 line.byte 0x00 "B25,Byte Pin Register Port 0 Pin PIO0_25" bitfld.byte 0x00 0. " PBYTE ,PIO0_25 pin state" "Low,High" group.byte 0x1A++0x00 line.byte 0x00 "B26,Byte Pin Register Port 0 Pin PIO0_26" bitfld.byte 0x00 0. " PBYTE ,PIO0_26 pin state" "Low,High" group.byte 0x1B++0x00 line.byte 0x00 "B27,Byte Pin Register Port 0 Pin PIO0_27" bitfld.byte 0x00 0. " PBYTE ,PIO0_27 pin state" "Low,High" group.byte 0x1C++0x00 line.byte 0x00 "B28,Byte Pin Register Port 0 Pin PIO0_28" bitfld.byte 0x00 0. " PBYTE ,PIO0_28 pin state" "Low,High" group.byte 0x1D++0x00 line.byte 0x00 "B29,Byte Pin Register Port 0 Pin PIO0_29" bitfld.byte 0x00 0. " PBYTE ,PIO0_29 pin state" "Low,High" group.byte 0x1E++0x00 line.byte 0x00 "B30,Byte Pin Register Port 0 Pin PIO0_30" bitfld.byte 0x00 0. " PBYTE ,PIO0_30 pin state" "Low,High" group.byte 0x1F++0x00 line.byte 0x00 "B31,Byte Pin Register Port 0 Pin PIO0_31" bitfld.byte 0x00 0. " PBYTE ,PIO0_31 pin state" "Low,High" group.byte 0x20++0x00 line.byte 0x00 "B32,Byte Pin Register Port 0 Pin PIO0_32" bitfld.byte 0x00 0. " PBYTE ,PIO0_32 pin state" "Low,High" group.byte 0x21++0x00 line.byte 0x00 "B33,Byte Pin Register Port 0 Pin PIO0_33" bitfld.byte 0x00 0. " PBYTE ,PIO0_33 pin state" "Low,High" group.byte 0x22++0x00 line.byte 0x00 "B34,Byte Pin Register Port 0 Pin PIO0_34" bitfld.byte 0x00 0. " PBYTE ,PIO0_34 pin state" "Low,High" group.byte 0x23++0x00 line.byte 0x00 "B35,Byte Pin Register Port 0 Pin PIO0_35" bitfld.byte 0x00 0. " PBYTE ,PIO0_35 pin state" "Low,High" group.byte 0x24++0x00 line.byte 0x00 "B36,Byte Pin Register Port 0 Pin PIO0_36" bitfld.byte 0x00 0. " PBYTE ,PIO0_36 pin state" "Low,High" group.byte 0x25++0x00 line.byte 0x00 "B37,Byte Pin Register Port 0 Pin PIO0_37" bitfld.byte 0x00 0. " PBYTE ,PIO0_37 pin state" "Low,High" group.byte 0x26++0x00 line.byte 0x00 "B38,Byte Pin Register Port 0 Pin PIO0_38" bitfld.byte 0x00 0. " PBYTE ,PIO0_38 pin state" "Low,High" group.byte 0x27++0x00 line.byte 0x00 "B39,Byte Pin Register Port 0 Pin PIO0_39" bitfld.byte 0x00 0. " PBYTE ,PIO0_39 pin state" "Low,High" group.byte 0x28++0x00 line.byte 0x00 "B40,Byte Pin Register Port 0 Pin PIO0_40" bitfld.byte 0x00 0. " PBYTE ,PIO0_40 pin state" "Low,High" group.byte 0x29++0x00 line.byte 0x00 "B41,Byte Pin Register Port 0 Pin PIO0_41" bitfld.byte 0x00 0. " PBYTE ,PIO0_41 pin state" "Low,High" group.byte 0x2A++0x00 line.byte 0x00 "B42,Byte Pin Register Port 0 Pin PIO0_42" bitfld.byte 0x00 0. " PBYTE ,PIO0_42 pin state" "Low,High" group.byte 0x2B++0x00 line.byte 0x00 "B43,Byte Pin Register Port 0 Pin PIO0_43" bitfld.byte 0x00 0. " PBYTE ,PIO0_43 pin state" "Low,High" group.byte 0x2C++0x00 line.byte 0x00 "B44,Byte Pin Register Port 0 Pin PIO0_44" bitfld.byte 0x00 0. " PBYTE ,PIO0_44 pin state" "Low,High" group.byte 0x2D++0x00 line.byte 0x00 "B45,Byte Pin Register Port 0 Pin PIO0_45" bitfld.byte 0x00 0. " PBYTE ,PIO0_45 pin state" "Low,High" group.byte 0x2E++0x00 line.byte 0x00 "B46,Byte Pin Register Port 0 Pin PIO0_46" bitfld.byte 0x00 0. " PBYTE ,PIO0_46 pin state" "Low,High" group.byte 0x2F++0x00 line.byte 0x00 "B47,Byte Pin Register Port 0 Pin PIO0_47" bitfld.byte 0x00 0. " PBYTE ,PIO0_47 pin state" "Low,High" group.byte 0x30++0x00 line.byte 0x00 "B48,Byte Pin Register Port 0 Pin PIO0_48" bitfld.byte 0x00 0. " PBYTE ,PIO0_48 pin state" "Low,High" group.byte 0x31++0x00 line.byte 0x00 "B49,Byte Pin Register Port 0 Pin PIO0_49" bitfld.byte 0x00 0. " PBYTE ,PIO0_49 pin state" "Low,High" group.byte 0x32++0x00 line.byte 0x00 "B50,Byte Pin Register Port 0 Pin PIO0_50" bitfld.byte 0x00 0. " PBYTE ,PIO0_50 pin state" "Low,High" group.byte 0x33++0x00 line.byte 0x00 "B51,Byte Pin Register Port 0 Pin PIO0_51" bitfld.byte 0x00 0. " PBYTE ,PIO0_51 pin state" "Low,High" group.byte 0x34++0x00 line.byte 0x00 "B52,Byte Pin Register Port 0 Pin PIO0_52" bitfld.byte 0x00 0. " PBYTE ,PIO0_52 pin state" "Low,High" group.byte 0x35++0x00 line.byte 0x00 "B53,Byte Pin Register Port 0 Pin PIO0_53" bitfld.byte 0x00 0. " PBYTE ,PIO0_53 pin state" "Low,High" endif tree.end tree "Word Pin Registers Port 0" sif (cpu()=="LPC844M201JHI33"||cpu()=="LPC845M301JHI33") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Register Port 0 Pin PIO0_6" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" group.long 0x1048++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin PIO0_18" group.long 0x104C++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin PIO0_19" group.long 0x1050++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin PIO0_20" group.long 0x1054++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin PIO0_21" group.long 0x1058++0x03 line.long 0x00 "W22,Word Pin Register Port 0 Pin PIO0_22" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Register Port 0 Pin PIO0_23" group.long 0x1060++0x03 line.long 0x00 "W24,Word Pin Register Port 0 Pin PIO0_24" group.long 0x1064++0x03 line.long 0x00 "W25,Word Pin Register Port 0 Pin PIO0_25" group.long 0x1068++0x03 line.long 0x00 "W26,Word Pin Register Port 0 Pin PIO0_26" group.long 0x106C++0x03 line.long 0x00 "W27,Word Pin Register Port 0 Pin PIO0_27" group.long 0x1070++0x03 line.long 0x00 "W28,Word Pin Register Port 0 Pin PIO0_28" elif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Register Port 0 Pin PIO0_6" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" group.long 0x1048++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin PIO0_18" group.long 0x104C++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin PIO0_19" group.long 0x1050++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin PIO0_20" group.long 0x1054++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin PIO0_21" group.long 0x1058++0x03 line.long 0x00 "W22,Word Pin Register Port 0 Pin PIO0_22" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Register Port 0 Pin PIO0_23" group.long 0x1060++0x03 line.long 0x00 "W24,Word Pin Register Port 0 Pin PIO0_24" group.long 0x1064++0x03 line.long 0x00 "W25,Word Pin Register Port 0 Pin PIO0_25" group.long 0x1068++0x03 line.long 0x00 "W26,Word Pin Register Port 0 Pin PIO0_26" group.long 0x106C++0x03 line.long 0x00 "W27,Word Pin Register Port 0 Pin PIO0_27" group.long 0x1070++0x03 line.long 0x00 "W28,Word Pin Register Port 0 Pin PIO0_28" group.long 0x1074++0x03 line.long 0x00 "W29,Word Pin Register Port 0 Pin PIO0_29" group.long 0x1078++0x03 line.long 0x00 "W30,Word Pin Register Port 0 Pin PIO0_30" group.long 0x107C++0x03 line.long 0x00 "W31,Word Pin Register Port 0 Pin PIO0_31" group.long 0x1080++0x03 line.long 0x00 "W32,Word Pin Register Port 0 Pin PIO0_32" group.long 0x1084++0x03 line.long 0x00 "W33,Word Pin Register Port 0 Pin PIO0_33" group.long 0x1088++0x03 line.long 0x00 "W34,Word Pin Register Port 0 Pin PIO0_34" group.long 0x108C++0x03 line.long 0x00 "W35,Word Pin Register Port 0 Pin PIO0_35" group.long 0x1090++0x03 line.long 0x00 "W36,Word Pin Register Port 0 Pin PIO0_36" group.long 0x1094++0x03 line.long 0x00 "W37,Word Pin Register Port 0 Pin PIO0_37" group.long 0x1098++0x03 line.long 0x00 "W38,Word Pin Register Port 0 Pin PIO0_38" group.long 0x109C++0x03 line.long 0x00 "W39,Word Pin Register Port 0 Pin PIO0_39" group.long 0x10A0++0x03 line.long 0x00 "W40,Word Pin Register Port 0 Pin PIO0_40" group.long 0x10A4++0x03 line.long 0x00 "W41,Word Pin Register Port 0 Pin PIO0_41" elif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin PIO0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin PIO0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin PIO0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin PIO0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin PIO0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin PIO0_5" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Register Port 0 Pin PIO0_6" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin PIO0_7" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin PIO0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin PIO0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin PIO0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin PIO0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin PIO0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin PIO0_13" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin PIO0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin PIO0_15" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin PIO0_16" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin PIO0_17" group.long 0x1048++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin PIO0_18" group.long 0x104C++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin PIO0_19" group.long 0x1050++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin PIO0_20" group.long 0x1054++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin PIO0_21" group.long 0x1058++0x03 line.long 0x00 "W22,Word Pin Register Port 0 Pin PIO0_22" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Register Port 0 Pin PIO0_23" group.long 0x1060++0x03 line.long 0x00 "W24,Word Pin Register Port 0 Pin PIO0_24" group.long 0x1064++0x03 line.long 0x00 "W25,Word Pin Register Port 0 Pin PIO0_25" group.long 0x1068++0x03 line.long 0x00 "W26,Word Pin Register Port 0 Pin PIO0_26" group.long 0x106C++0x03 line.long 0x00 "W27,Word Pin Register Port 0 Pin PIO0_27" group.long 0x1070++0x03 line.long 0x00 "W28,Word Pin Register Port 0 Pin PIO0_28" group.long 0x1074++0x03 line.long 0x00 "W29,Word Pin Register Port 0 Pin PIO0_29" group.long 0x1078++0x03 line.long 0x00 "W30,Word Pin Register Port 0 Pin PIO0_30" group.long 0x107C++0x03 line.long 0x00 "W31,Word Pin Register Port 0 Pin PIO0_31" group.long 0x1080++0x03 line.long 0x00 "W32,Word Pin Register Port 0 Pin PIO0_32" group.long 0x1084++0x03 line.long 0x00 "W33,Word Pin Register Port 0 Pin PIO0_33" group.long 0x1088++0x03 line.long 0x00 "W34,Word Pin Register Port 0 Pin PIO0_34" group.long 0x108C++0x03 line.long 0x00 "W35,Word Pin Register Port 0 Pin PIO0_35" group.long 0x1090++0x03 line.long 0x00 "W36,Word Pin Register Port 0 Pin PIO0_36" group.long 0x1094++0x03 line.long 0x00 "W37,Word Pin Register Port 0 Pin PIO0_37" group.long 0x1098++0x03 line.long 0x00 "W38,Word Pin Register Port 0 Pin PIO0_38" group.long 0x109C++0x03 line.long 0x00 "W39,Word Pin Register Port 0 Pin PIO0_39" group.long 0x10A0++0x03 line.long 0x00 "W40,Word Pin Register Port 0 Pin PIO0_40" group.long 0x10A4++0x03 line.long 0x00 "W41,Word Pin Register Port 0 Pin PIO0_41" group.long 0x10A8++0x03 line.long 0x00 "W42,Word Pin Register Port 0 Pin PIO0_42" group.long 0x10AC++0x03 line.long 0x00 "W43,Word Pin Register Port 0 Pin PIO0_43" group.long 0x10B0++0x03 line.long 0x00 "W44,Word Pin Register Port 0 Pin PIO0_44" group.long 0x10B4++0x03 line.long 0x00 "W45,Word Pin Register Port 0 Pin PIO0_45" group.long 0x10B8++0x03 line.long 0x00 "W46,Word Pin Register Port 0 Pin PIO0_46" group.long 0x10BC++0x03 line.long 0x00 "W47,Word Pin Register Port 0 Pin PIO0_47" group.long 0x10C0++0x03 line.long 0x00 "W48,Word Pin Register Port 0 Pin PIO0_48" group.long 0x10C4++0x03 line.long 0x00 "W49,Word Pin Register Port 0 Pin PIO0_49" group.long 0x10C8++0x03 line.long 0x00 "W50,Word Pin Register Port 0 Pin PIO0_50" group.long 0x10CC++0x03 line.long 0x00 "W51,Word Pin Register Port 0 Pin PIO0_51" group.long 0x10D0++0x03 line.long 0x00 "W52,Word Pin Register Port 0 Pin PIO0_52" group.long 0x10D4++0x03 line.long 0x00 "W53,Word Pin Register Port 0 Pin PIO0_53" endif tree.end textline " " group.long 0x2000++0x3 line.long 0x00 "DIR0,Direction Register Port 0" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " DIRP0_31 ,Pin direction for pin PIO0_31" "Input,Output" bitfld.long 0x00 30. " DIRP0_30 ,Pin direction for pin PIO0_30" "Input,Output" bitfld.long 0x00 29. " DIRP0_29 ,Pin direction for pin PIO0_29" "Input,Output" textline " " endif bitfld.long 0x00 28. " DIRP0_28 ,Pin direction for pin PIO0_28" "Input,Output" bitfld.long 0x00 27. " DIRP0_27 ,Pin direction for pin PIO0_27" "Input,Output" bitfld.long 0x00 26. " DIRP0_26 ,Pin direction for pin PIO0_26" "Input,Output" bitfld.long 0x00 25. " DIRP0_25 ,Pin direction for pin PIO0_25" "Input,Output" textline " " bitfld.long 0x00 24. " DIRP0_24 ,Pin direction for pin PIO0_24" "Input,Output" bitfld.long 0x00 23. " DIRP0_23 ,Pin direction for pin PIO0_23" "Input,Output" bitfld.long 0x00 22. " DIRP0_22 ,Pin direction for pin PIO0_22" "Input,Output" bitfld.long 0x00 21. " DIRP0_21 ,Pin direction for pin PIO0_21" "Input,Output" textline " " bitfld.long 0x00 20. " DIRP0_20 ,Pin direction for pin PIO0_20" "Input,Output" bitfld.long 0x00 19. " DIRP0_19 ,Pin direction for pin PIO0_19" "Input,Output" bitfld.long 0x00 18. " DIRP0_18 ,Pin direction for pin PIO0_18" "Input,Output" textline " " bitfld.long 0x00 17. " DIRP0_17 ,Pin direction for pin PIO0_17" "Input,Output" bitfld.long 0x00 16. " DIRP0_16 ,Pin direction for pin PIO0_16" "Input,Output" bitfld.long 0x00 15. " DIRP0_15 ,Pin direction for pin PIO0_15" "Input,Output" bitfld.long 0x00 14. " DIRP0_14 ,Pin direction for pin PIO0_14" "Input,Output" textline " " bitfld.long 0x00 13. " DIRP0_13 ,Pin direction for pin PIO0_13" "Input,Output" bitfld.long 0x00 12. " DIRP0_12 ,Pin direction for pin PIO0_12" "Input,Output" bitfld.long 0x00 11. " DIRP0_11 ,Pin direction for pin PIO0_11" "Input,Output" bitfld.long 0x00 10. " DIRP0_10 ,Pin direction for pin PIO0_10" "Input,Output" textline " " bitfld.long 0x00 9. " DIRP0_9 ,Pin direction for pin PIO0_9" "Input,Output" bitfld.long 0x00 8. " DIRP0_8 ,Pin direction for pin PIO0_8" "Input,Output" bitfld.long 0x00 7. " DIRP0_7 ,Pin direction for pin PIO0_7" "Input,Output" bitfld.long 0x00 6. " DIRP0_6 ,Pin direction for pin PIO0_6" "Input,Output" textline " " bitfld.long 0x00 5. " DIRP0_5 ,Pin direction for pin PIO0_5" "Input,Output" bitfld.long 0x00 4. " DIRP0_4 ,Pin direction for pin PIO0_4" "Input,Output" bitfld.long 0x00 3. " DIRP0_3 ,Pin direction for pin PIO0_3" "Input,Output" bitfld.long 0x00 2. " DIRP0_2 ,Pin direction for pin PIO0_2" "Input,Output" textline " " bitfld.long 0x00 1. " DIRP0_1 ,Pin direction for pin PIO0_1" "Input,Output" bitfld.long 0x00 0. " DIRP0_0 ,Pin direction for pin PIO0_0" "Input,Output" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.long 0x2004++0x3 line.long 0x00 "DIR1,Direction Register Port 0" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " DIRP1_21 ,Pin direction for pin PIO0_21" "Input,Output" textline " " bitfld.long 0x00 20. " DIRP1_20 ,Pin direction for pin PIO0_20" "Input,Output" bitfld.long 0x00 19. " DIRP1_19 ,Pin direction for pin PIO0_19" "Input,Output" bitfld.long 0x00 18. " DIRP1_18 ,Pin direction for pin PIO0_18" "Input,Output" textline " " bitfld.long 0x00 17. " DIRP1_17 ,Pin direction for pin PIO0_17" "Input,Output" bitfld.long 0x00 16. " DIRP1_16 ,Pin direction for pin PIO0_16" "Input,Output" bitfld.long 0x00 15. " DIRP1_15 ,Pin direction for pin PIO0_15" "Input,Output" bitfld.long 0x00 14. " DIRP1_14 ,Pin direction for pin PIO0_14" "Input,Output" textline " " bitfld.long 0x00 13. " DIRP1_13 ,Pin direction for pin PIO0_13" "Input,Output" bitfld.long 0x00 12. " DIRP1_12 ,Pin direction for pin PIO0_12" "Input,Output" bitfld.long 0x00 11. " DIRP1_11 ,Pin direction for pin PIO0_11" "Input,Output" bitfld.long 0x00 10. " DIRP1_10 ,Pin direction for pin PIO0_10" "Input,Output" textline " " endif bitfld.long 0x00 9. " DIRP1_9 ,Pin direction for pin PIO0_9" "Input,Output" bitfld.long 0x00 8. " DIRP1_8 ,Pin direction for pin PIO0_8" "Input,Output" bitfld.long 0x00 7. " DIRP1_7 ,Pin direction for pin PIO0_7" "Input,Output" bitfld.long 0x00 6. " DIRP1_6 ,Pin direction for pin PIO0_6" "Input,Output" textline " " bitfld.long 0x00 5. " DIRP1_5 ,Pin direction for pin PIO0_5" "Input,Output" bitfld.long 0x00 4. " DIRP1_4 ,Pin direction for pin PIO0_4" "Input,Output" bitfld.long 0x00 3. " DIRP1_3 ,Pin direction for pin PIO0_3" "Input,Output" bitfld.long 0x00 2. " DIRP1_2 ,Pin direction for pin PIO0_2" "Input,Output" textline " " bitfld.long 0x00 1. " DIRP1_1 ,Pin direction for pin PIO0_1" "Input,Output" bitfld.long 0x00 0. " DIRP1_0 ,Pin direction for pin PIO0_0" "Input,Output" endif group.long 0x2080++0x03 line.long 0x00 "MASK0,GPIO Mask Port 0 Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " MASKP0_31 ,Write via MPORT enable for pin PIO0_31" "Not masked,Masked" bitfld.long 0x00 30. " MASKP0_30 ,Write via MPORT enable for pin PIO0_30" "Not masked,Masked" bitfld.long 0x00 29. " MASKP0_29 ,Write via MPORT enable for pin PIO0_29" "Not masked,Masked" textline " " endif bitfld.long 0x00 28. " MASKP0_28 ,Write via MPORT enable for pin PIO0_28" "Not masked,Masked" bitfld.long 0x00 27. " MASKP0_27 ,Write via MPORT enable for pin PIO0_27" "Not masked,Masked" bitfld.long 0x00 26. " MASKP0_26 ,Write via MPORT enable for pin PIO0_26" "Not masked,Masked" bitfld.long 0x00 25. " MASKP0_25 ,Write via MPORT enable for pin PIO0_25" "Not masked,Masked" textline " " bitfld.long 0x00 24. " MASKP0_24 ,Write via MPORT enable for pin PIO0_24" "Not masked,Masked" bitfld.long 0x00 23. " MASKP0_23 ,Write via MPORT enable for pin PIO0_23" "Not masked,Masked" bitfld.long 0x00 22. " MASKP0_22 ,Write via MPORT enable for pin PIO0_22" "Not masked,Masked" bitfld.long 0x00 21. " MASKP0_21 ,Write via MPORT enable for pin PIO0_21" "Not masked,Masked" textline " " bitfld.long 0x00 20. " MASKP0_20 ,Write via MPORT enable for pin PIO0_20" "Not masked,Masked" bitfld.long 0x00 19. " MASKP0_19 ,Write via MPORT enable for pin PIO0_19" "Not masked,Masked" bitfld.long 0x00 18. " MASKP0_18 ,Write via MPORT enable for pin PIO0_18" "Not masked,Masked" textline " " bitfld.long 0x00 17. " MASKP0_17 ,Write via MPORT enable for pin PIO0_17" "Not masked,Masked" bitfld.long 0x00 16. " MASKP0_16 ,Write via MPORT enable for pin PIO0_16" "Not masked,Masked" bitfld.long 0x00 15. " MASKP0_15 ,Write via MPORT enable for pin PIO0_15" "Not masked,Masked" bitfld.long 0x00 14. " MASKP0_14 ,Write via MPORT enable for pin PIO0_14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MASKP0_13 ,Write via MPORT enable for pin PIO0_13" "Not masked,Masked" bitfld.long 0x00 12. " MASKP0_12 ,Write via MPORT enable for pin PIO0_12" "Not masked,Masked" bitfld.long 0x00 11. " MASKP0_11 ,Write via MPORT enable for pin PIO0_11" "Not masked,Masked" bitfld.long 0x00 10. " MASKP0_10 ,Write via MPORT enable for pin PIO0_10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MASKP0_9 ,Write via MPORT enable for pin PIO0_9" "Not masked,Masked" bitfld.long 0x00 8. " MASKP0_8 ,Write via MPORT enable for pin PIO0_8" "Not masked,Masked" bitfld.long 0x00 7. " MASKP0_7 ,Write via MPORT enable for pin PIO0_7" "Not masked,Masked" bitfld.long 0x00 6. " MASKP0_6 ,Write via MPORT enable for pin PIO0_6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MASKP0_5 ,Write via MPORT enable for pin PIO0_5" "Not masked,Masked" bitfld.long 0x00 4. " MASKP0_4 ,Write via MPORT enable for pin PIO0_4" "Not masked,Masked" bitfld.long 0x00 3. " MASKP0_3 ,Write via MPORT enable for pin PIO0_3" "Not masked,Masked" bitfld.long 0x00 2. " MASKP0_2 ,Write via MPORT enable for pin PIO0_2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MASKP0_1 ,Write via MPORT enable for pin PIO0_1" "Not masked,Masked" bitfld.long 0x00 0. " MASKP0_0 ,Write via MPORT enable for pin PIO0_0" "Not masked,Masked" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.long 0x2084++0x03 line.long 0x00 "MASK1,GPIO Mask Port 1 Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " MASKP1_21 ,Write via MPORT enable for pin PIO1_21" "Not masked,Masked" textline " " bitfld.long 0x00 20. " MASKP1_20 ,Write via MPORT enable for pin PIO1_20" "Not masked,Masked" bitfld.long 0x00 19. " MASKP1_19 ,Write via MPORT enable for pin PIO1_19" "Not masked,Masked" bitfld.long 0x00 18. " MASKP1_18 ,Write via MPORT enable for pin PIO1_18" "Not masked,Masked" textline " " bitfld.long 0x00 17. " MASKP1_17 ,Write via MPORT enable for pin PIO1_17" "Not masked,Masked" bitfld.long 0x00 16. " MASKP1_16 ,Write via MPORT enable for pin PIO1_16" "Not masked,Masked" bitfld.long 0x00 15. " MASKP1_15 ,Write via MPORT enable for pin PIO1_15" "Not masked,Masked" bitfld.long 0x00 14. " MASKP1_14 ,Write via MPORT enable for pin PIO1_14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MASKP1_13 ,Write via MPORT enable for pin PIO1_13" "Not masked,Masked" bitfld.long 0x00 12. " MASKP1_12 ,Write via MPORT enable for pin PIO1_12" "Not masked,Masked" bitfld.long 0x00 11. " MASKP1_11 ,Write via MPORT enable for pin PIO1_11" "Not masked,Masked" bitfld.long 0x00 10. " MASKP1_10 ,Write via MPORT enable for pin PIO1_10" "Not masked,Masked" textline " " endif bitfld.long 0x00 9. " MASKP1_9 ,Write via MPORT enable for pin PIO1_9" "Not masked,Masked" bitfld.long 0x00 8. " MASKP1_8 ,Write via MPORT enable for pin PIO1_8" "Not masked,Masked" bitfld.long 0x00 7. " MASKP1_7 ,Write via MPORT enable for pin PIO1_7" "Not masked,Masked" bitfld.long 0x00 6. " MASKP1_6 ,Write via MPORT enable for pin PIO1_6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MASKP1_5 ,Write via MPORT enable for pin PIO1_5" "Not masked,Masked" bitfld.long 0x00 4. " MASKP1_4 ,Write via MPORT enable for pin PIO1_4" "Not masked,Masked" bitfld.long 0x00 3. " MASKP1_3 ,Write via MPORT enable for pin PIO1_3" "Not masked,Masked" bitfld.long 0x00 2. " MASKP1_2 ,Write via MPORT enable for pin PIO1_2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MASKP1_1 ,Write via MPORT enable for pin PIO1_1" "Not masked,Masked" bitfld.long 0x00 0. " MASKP1_0 ,Write via MPORT enable for pin PIO1_0" "Not masked,Masked" endif group.long 0x2100++0x03 line.long 0x00 "PIN0,GPIO Port 0 Pin Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " PORT0_31 ,Pin state for pin PIO0_31" "Low,High" bitfld.long 0x00 30. " PORT0_30 ,Pin state for pin PIO0_30" "Low,High" bitfld.long 0x00 29. " PORT0_29 ,Pin state for pin PIO0_29" "Low,High" textline " " endif bitfld.long 0x00 28. " PORT0_28 ,Pin state for pin PIO0_28" "Low,High" bitfld.long 0x00 27. " PORT0_27 ,Pin state for pin PIO0_27" "Low,High" bitfld.long 0x00 26. " PORT0_26 ,Pin state for pin PIO0_26" "Low,High" bitfld.long 0x00 25. " PORT0_25 ,Pin state for pin PIO0_25" "Low,High" textline " " bitfld.long 0x00 24. " PORT0_24 ,Pin state for pin PIO0_24" "Low,High" bitfld.long 0x00 23. " PORT0_23 ,Pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 22. " PORT0_22 ,Pin state for pin PIO0_22" "Low,High" bitfld.long 0x00 21. " PORT0_21 ,Pin state for pin PIO0_21" "Low,High" textline " " bitfld.long 0x00 20. " PORT0_20 ,Pin state for pin PIO0_20" "Low,High" bitfld.long 0x00 19. " PORT0_19 ,Pin state for pin PIO0_19" "Low,High" bitfld.long 0x00 18. " PORT0_18 ,Pin state for pin PIO0_18" "Low,High" textline " " bitfld.long 0x00 17. " PORT0_17 ,Pin state for pin PIO0_17" "Low,High" bitfld.long 0x00 16. " PORT0_16 ,Pin state for pin PIO0_16" "Low,High" bitfld.long 0x00 15. " PORT0_15 ,Pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " PORT0_14 ,Pin state for pin PIO0_14" "Low,High" textline " " bitfld.long 0x00 13. " PORT0_13 ,Pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " PORT0_12 ,Pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " PORT0_11 ,Pin state for pin PIO0_11" "Low,High" bitfld.long 0x00 10. " PORT0_10 ,Pin state for pin PIO0_10" "Low,High" textline " " bitfld.long 0x00 9. " PORT0_9 ,Pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " PORT0_8 ,Pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 7. " PORT0_7 ,Pin state for pin PIO0_7" "Low,High" bitfld.long 0x00 6. " PORT0_6 ,Pin state for pin PIO0_6" "Low,High" textline " " bitfld.long 0x00 5. " PORT0_5 ,Pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " PORT0_4 ,Pin state for pin PIO0_4" "Low,High" bitfld.long 0x00 3. " PORT0_3 ,Pin state for pin PIO0_3" "Low,High" bitfld.long 0x00 2. " PORT0_2 ,Pin state for pin PIO0_2" "Low,High" textline " " bitfld.long 0x00 1. " PORT0_1 ,Pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " PORT0_0 ,Pin state for pin PIO0_0" "Low,High" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.long 0x2104++0x03 line.long 0x00 "PIN1,GPIO Port 1 Pin Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " POTR1_21 ,Pin state for pin PIO1_21" "Low,High" textline " " bitfld.long 0x00 20. " POTR1_20 ,Pin state for pin PIO1_20" "Low,High" bitfld.long 0x00 19. " POTR1_19 ,Pin state for pin PIO1_19" "Low,High" bitfld.long 0x00 18. " POTR1_18 ,Pin state for pin PIO1_18" "Low,High" textline " " bitfld.long 0x00 17. " POTR1_17 ,Pin state for pin PIO1_17" "Low,High" bitfld.long 0x00 16. " POTR1_16 ,Pin state for pin PIO1_16" "Low,High" bitfld.long 0x00 15. " POTR1_15 ,Pin state for pin PIO1_15" "Low,High" bitfld.long 0x00 14. " POTR1_14 ,Pin state for pin PIO1_14" "Low,High" textline " " bitfld.long 0x00 13. " POTR1_13 ,Pin state for pin PIO1_13" "Low,High" bitfld.long 0x00 12. " POTR1_12 ,Pin state for pin PIO1_12" "Low,High" bitfld.long 0x00 11. " POTR1_11 ,Pin state for pin PIO1_11" "Low,High" bitfld.long 0x00 10. " POTR1_10 ,Pin state for pin PIO1_10" "Low,High" textline " " endif bitfld.long 0x00 9. " POTR1_9 ,Pin state for pin PIO1_9" "Low,High" bitfld.long 0x00 8. " POTR1_8 ,Pin state for pin PIO1_8" "Low,High" bitfld.long 0x00 7. " POTR1_7 ,Pin state for pin PIO1_7" "Low,High" bitfld.long 0x00 6. " POTR1_6 ,Pin state for pin PIO1_6" "Low,High" textline " " bitfld.long 0x00 5. " POTR1_5 ,Pin state for pin PIO1_5" "Low,High" bitfld.long 0x00 4. " POTR1_4 ,Pin state for pin PIO1_4" "Low,High" bitfld.long 0x00 3. " POTR1_3 ,Pin state for pin PIO1_3" "Low,High" bitfld.long 0x00 2. " POTR1_2 ,Pin state for pin PIO1_2" "Low,High" textline " " bitfld.long 0x00 1. " POTR1_1 ,Pin state for pin PIO1_1" "Low,High" bitfld.long 0x00 0. " POTR1_0 ,Pin state for pin PIO1_0" "Low,High" endif group.long 0x2180++0x03 line.long 0x00 "MPIN0,GPIO Masked Port 0 Pin Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " MPORTP0_31 ,Masked pin state for pin PIO0_31" "Low,High" bitfld.long 0x00 30. " MPORTP0_30 ,Masked pin state for pin PIO0_30" "Low,High" bitfld.long 0x00 29. " MPORTP0_29 ,Masked pin state for pin PIO0_29" "Low,High" textline " " endif bitfld.long 0x00 28. " MPORTP0_28 ,Masked pin state for pin PIO0_28" "Low,High" bitfld.long 0x00 27. " MPORTP0_27 ,Masked pin state for pin PIO0_27" "Low,High" bitfld.long 0x00 26. " MPORTP0_26 ,Masked pin state for pin PIO0_26" "Low,High" bitfld.long 0x00 25. " MPORTP0_25 ,Masked pin state for pin PIO0_25" "Low,High" textline " " bitfld.long 0x00 24. " MPORTP0_24 ,Masked pin state for pin PIO0_24" "Low,High" bitfld.long 0x00 23. " MPORTP0_23 ,Masked pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 22. " MPORTP0_22 ,Masked pin state for pin PIO0_22" "Low,High" bitfld.long 0x00 21. " MPORTP0_21 ,Masked pin state for pin PIO0_21" "Low,High" textline " " bitfld.long 0x00 20. " MPORTP0_20 ,Masked pin state for pin PIO0_20" "Low,High" bitfld.long 0x00 19. " MPORTP0_19 ,Masked pin state for pin PIO0_19" "Low,High" bitfld.long 0x00 18. " MPORTP0_18 ,Masked pin state for pin PIO0_18" "Low,High" textline " " bitfld.long 0x00 17. " MPORTP0_17 ,Masked pin state for pin PIO0_17" "Low,High" bitfld.long 0x00 16. " MPORTP0_16 ,Masked pin state for pin PIO0_16" "Low,High" bitfld.long 0x00 15. " MPORTP0_15 ,Masked pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " MPORTP0_14 ,Masked pin state for pin PIO0_14" "Low,High" textline " " bitfld.long 0x00 13. " MPORTP0_13 ,Masked pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " MPORTP0_12 ,Masked pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " MPORTP0_11 ,Masked pin state for pin PIO0_11" "Low,High" bitfld.long 0x00 10. " MPORTP0_10 ,Masked pin state for pin PIO0_10" "Low,High" textline " " bitfld.long 0x00 9. " MPORTP0_9 ,Masked pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " MPORTP0_8 ,Masked pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 7. " MPORTP0_7 ,Masked pin state for pin PIO0_7" "Low,High" bitfld.long 0x00 6. " MPORTP0_6 ,Masked pin state for pin PIO0_6" "Low,High" textline " " bitfld.long 0x00 5. " MPORTP0_5 ,Masked pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " MPORTP0_4 ,Masked pin state for pin PIO0_4" "Low,High" bitfld.long 0x00 3. " MPORTP0_3 ,Masked pin state for pin PIO0_3" "Low,High" bitfld.long 0x00 2. " MPORTP0_2 ,Masked pin state for pin PIO0_2" "Low,High" textline " " bitfld.long 0x00 1. " MPORTP0_1 ,Masked pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " MPORTP0_0 ,Masked pin state for pin PIO0_0" "Low,High" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.long 0x2184++0x03 line.long 0x00 "MPIN1,GPIO Masked Port 1 Pin Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " MPORTP1_21 ,Masked pin state for pin PIO1_21" "Low,High" textline " " bitfld.long 0x00 20. " MPORTP1_20 ,Masked pin state for pin PIO1_20" "Low,High" bitfld.long 0x00 19. " MPORTP1_19 ,Masked pin state for pin PIO1_19" "Low,High" bitfld.long 0x00 18. " MPORTP1_18 ,Masked pin state for pin PIO1_18" "Low,High" textline " " bitfld.long 0x00 17. " MPORTP1_17 ,Masked pin state for pin PIO1_17" "Low,High" bitfld.long 0x00 16. " MPORTP1_16 ,Masked pin state for pin PIO1_16" "Low,High" bitfld.long 0x00 15. " MPORTP1_15 ,Masked pin state for pin PIO1_15" "Low,High" bitfld.long 0x00 14. " MPORTP1_14 ,Masked pin state for pin PIO1_14" "Low,High" textline " " bitfld.long 0x00 13. " MPORTP1_13 ,Masked pin state for pin PIO1_13" "Low,High" bitfld.long 0x00 12. " MPORTP1_12 ,Masked pin state for pin PIO1_12" "Low,High" bitfld.long 0x00 11. " MPORTP1_11 ,Masked pin state for pin PIO1_11" "Low,High" bitfld.long 0x00 10. " MPORTP1_10 ,Masked pin state for pin PIO1_10" "Low,High" textline " " endif bitfld.long 0x00 9. " MPORTP1_9 ,Masked pin state for pin PIO1_9" "Low,High" bitfld.long 0x00 8. " MPORTP1_8 ,Masked pin state for pin PIO1_8" "Low,High" bitfld.long 0x00 7. " MPORTP1_7 ,Masked pin state for pin PIO1_7" "Low,High" bitfld.long 0x00 6. " MPORTP1_6 ,Masked pin state for pin PIO1_6" "Low,High" textline " " bitfld.long 0x00 5. " MPORTP1_5 ,Masked pin state for pin PIO1_5" "Low,High" bitfld.long 0x00 4. " MPORTP1_4 ,Masked pin state for pin PIO1_4" "Low,High" bitfld.long 0x00 3. " MPORTP1_3 ,Masked pin state for pin PIO1_3" "Low,High" bitfld.long 0x00 2. " MPORTP1_2 ,Masked pin state for pin PIO1_2" "Low,High" textline " " bitfld.long 0x00 1. " MPORTP1_1 ,Masked pin state for pin PIO1_1" "Low,High" bitfld.long 0x00 0. " MPORTP1_0 ,Masked pin state for pin PIO1_0" "Low,High" endif group.long 0x2200++0x03 line.long 0x00 "SET0,GPIO Set Port 0 Pin Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " SETP0_31 ,Set pin PIO0_31" "No effect,Set" bitfld.long 0x00 30. " SETP0_30 ,Set pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " SETP0_29 ,Set pin PIO0_29" "No effect,Set" textline " " endif bitfld.long 0x00 28. " SETP0_28 ,Set pin PIO0_28" "No effect,Set" bitfld.long 0x00 27. " SETP0_27 ,Set pin PIO0_27" "No effect,Set" bitfld.long 0x00 26. " SETP0_26 ,Set pin PIO0_26" "No effect,Set" bitfld.long 0x00 25. " SETP0_25 ,Set pin PIO0_25" "No effect,Set" textline " " bitfld.long 0x00 24. " SETP0_24 ,Set pin PIO0_24" "No effect,Set" bitfld.long 0x00 23. " SETP0_23 ,Set pin PIO0_23" "No effect,Set" bitfld.long 0x00 22. " SETP0_22 ,Set pin PIO0_22" "No effect,Set" bitfld.long 0x00 21. " SETP0_21 ,Set pin PIO0_21" "No effect,Set" textline " " bitfld.long 0x00 20. " SETP0_20 ,Set pin PIO0_20" "No effect,Set" bitfld.long 0x00 19. " SETP0_19 ,Set pin PIO0_19" "No effect,Set" bitfld.long 0x00 18. " SETP0_18 ,Set pin PIO0_18" "No effect,Set" textline " " bitfld.long 0x00 17. " SETP0_17 ,Set pin PIO0_17" "No effect,Set" bitfld.long 0x00 16. " SETP0_16 ,Set pin PIO0_16" "No effect,Set" bitfld.long 0x00 15. " SETP0_15 ,Set pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " SETP0_14 ,Set pin PIO0_14" "No effect,Set" textline " " bitfld.long 0x00 13. " SETP0_13 ,Set pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " SETP0_12 ,Set pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " SETP0_11 ,Set pin PIO0_11" "No effect,Set" bitfld.long 0x00 10. " SETP0_10 ,Set pin PIO0_10" "No effect,Set" textline " " bitfld.long 0x00 9. " SETP0_9 ,Set pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " SETP0_8 ,Set pin PIO0_8" "No effect,Set" bitfld.long 0x00 7. " SETP0_7 ,Set pin PIO0_7" "No effect,Set" bitfld.long 0x00 6. " SETP0_6 ,Set pin PIO0_6" "No effect,Set" textline " " bitfld.long 0x00 5. " SETP0_5 ,Set pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " SETP0_4 ,Set pin PIO0_4" "No effect,Set" bitfld.long 0x00 3. " SETP0_3 ,Set pin PIO0_3" "No effect,Set" bitfld.long 0x00 2. " SETP0_2 ,Set pin PIO0_2" "No effect,Set" textline " " bitfld.long 0x00 1. " SETP0_1 ,Set pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " SETP0_0 ,Set pin PIO0_0" "No effect,Set" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") group.long 0x2204++0x03 line.long 0x00 "SET1,GPIO Set Port 1 Pin Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " SETP1_21 ,Set pin PIO1_21" "No effect,Set" textline " " bitfld.long 0x00 20. " SETP1_20 ,Set pin PIO1_20" "No effect,Set" bitfld.long 0x00 19. " SETP1_19 ,Set pin PIO1_19" "No effect,Set" bitfld.long 0x00 18. " SETP1_18 ,Set pin PIO1_18" "No effect,Set" textline " " bitfld.long 0x00 17. " SETP1_17 ,Set pin PIO1_17" "No effect,Set" bitfld.long 0x00 16. " SETP1_16 ,Set pin PIO1_16" "No effect,Set" bitfld.long 0x00 15. " SETP1_15 ,Set pin PIO1_15" "No effect,Set" bitfld.long 0x00 14. " SETP1_14 ,Set pin PIO1_14" "No effect,Set" textline " " bitfld.long 0x00 13. " SETP1_13 ,Set pin PIO1_13" "No effect,Set" bitfld.long 0x00 12. " SETP1_12 ,Set pin PIO1_12" "No effect,Set" bitfld.long 0x00 11. " SETP1_11 ,Set pin PIO1_11" "No effect,Set" bitfld.long 0x00 10. " SETP1_10 ,Set pin PIO1_10" "No effect,Set" textline " " endif bitfld.long 0x00 9. " SETP1_9 ,Set pin PIO1_9" "No effect,Set" bitfld.long 0x00 8. " SETP1_8 ,Set pin PIO1_8" "No effect,Set" bitfld.long 0x00 7. " SETP1_7 ,Set pin PIO1_7" "No effect,Set" bitfld.long 0x00 6. " SETP1_6 ,Set pin PIO1_6" "No effect,Set" textline " " bitfld.long 0x00 5. " SETP1_5 ,Set pin PIO1_5" "No effect,Set" bitfld.long 0x00 4. " SETP1_4 ,Set pin PIO1_4" "No effect,Set" bitfld.long 0x00 3. " SETP1_3 ,Set pin PIO1_3" "No effect,Set" bitfld.long 0x00 2. " SETP1_2 ,Set pin PIO1_2" "No effect,Set" textline " " bitfld.long 0x00 1. " SETP1_1 ,Set pin PIO1_1" "No effect,Set" bitfld.long 0x00 0. " SETP1_0 ,Set pin PIO1_0" "No effect,Set" endif wgroup.long 0x2280++0x03 line.long 0x00 "CLR0,GPIO Clear Port 0 Pin Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " CLRP0_31 ,Clear pin PIO0_31" "No effect,Clear" bitfld.long 0x00 30. " CLRP0_30 ,Clear pin PIO0_30" "No effect,Clear" bitfld.long 0x00 29. " CLRP0_29 ,Clear pin PIO0_29" "No effect,Clear" textline " " endif bitfld.long 0x00 28. " CLRP0_28 ,Clear pin PIO0_28" "No effect,Clear" bitfld.long 0x00 27. " CLRP0_27 ,Clear pin PIO0_27" "No effect,Clear" bitfld.long 0x00 26. " CLRP0_26 ,Clear pin PIO0_26" "No effect,Clear" bitfld.long 0x00 25. " CLRP0_25 ,Clear pin PIO0_25" "No effect,Clear" textline " " bitfld.long 0x00 24. " CLRP0_24 ,Clear pin PIO0_24" "No effect,Clear" bitfld.long 0x00 23. " CLRP0_23 ,Clear pin PIO0_23" "No effect,Clear" bitfld.long 0x00 22. " CLRP0_22 ,Clear pin PIO0_22" "No effect,Clear" bitfld.long 0x00 21. " CLRP0_21 ,Clear pin PIO0_21" "No effect,Clear" textline " " bitfld.long 0x00 20. " CLRP0_20 ,Clear pin PIO0_20" "No effect,Clear" bitfld.long 0x00 19. " CLRP0_19 ,Clear pin PIO0_19" "No effect,Clear" bitfld.long 0x00 18. " CLRP0_18 ,Clear pin PIO0_18" "No effect,Clear" textline " " bitfld.long 0x00 17. " CLRP0_17 ,Clear pin PIO0_17" "No effect,Clear" bitfld.long 0x00 16. " CLRP0_16 ,Clear pin PIO0_16" "No effect,Clear" bitfld.long 0x00 15. " CLRP0_15 ,Clear pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " CLRP0_14 ,Clear pin PIO0_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " CLRP0_13 ,Clear pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " CLRP0_12 ,Clear pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " CLRP0_11 ,Clear pin PIO0_11" "No effect,Clear" bitfld.long 0x00 10. " CLRP0_10 ,Clear pin PIO0_10" "No effect,Clear" textline " " bitfld.long 0x00 9. " CLRP0_9 ,Clear pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " CLRP0_8 ,Clear pin PIO0_8" "No effect,Clear" bitfld.long 0x00 7. " CLRP0_7 ,Clear pin PIO0_7" "No effect,Clear" bitfld.long 0x00 6. " CLRP0_6 ,Clear pin PIO0_6" "No effect,Clear" textline " " bitfld.long 0x00 5. " CLRP0_5 ,Clear pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " CLRP0_4 ,Clear pin PIO0_4" "No effect,Clear" bitfld.long 0x00 3. " CLRP0_3 ,Clear pin PIO0_3" "No effect,Clear" bitfld.long 0x00 2. " CLRP0_2 ,Clear pin PIO0_2" "No effect,Clear" textline " " bitfld.long 0x00 1. " CLRP0_1 ,Clear pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " CLRP0_0 ,Clear pin PIO0_0" "No effect,Clear" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") wgroup.long 0x2284++0x03 line.long 0x00 "CLR1,GPIO Clear Port 1 Pin Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " CLRP1_21 ,Clear pin PIO1_21" "No effect,Clear" textline " " bitfld.long 0x00 20. " CLRP1_20 ,Clear pin PIO1_20" "No effect,Clear" bitfld.long 0x00 19. " CLRP1_19 ,Clear pin PIO1_19" "No effect,Clear" bitfld.long 0x00 18. " CLRP1_18 ,Clear pin PIO1_18" "No effect,Clear" textline " " bitfld.long 0x00 17. " CLRP1_17 ,Clear pin PIO1_17" "No effect,Clear" bitfld.long 0x00 16. " CLRP1_16 ,Clear pin PIO1_16" "No effect,Clear" bitfld.long 0x00 15. " CLRP1_15 ,Clear pin PIO1_15" "No effect,Clear" bitfld.long 0x00 14. " CLRP1_14 ,Clear pin PIO1_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " CLRP1_13 ,Clear pin PIO1_13" "No effect,Clear" bitfld.long 0x00 12. " CLRP1_12 ,Clear pin PIO1_12" "No effect,Clear" bitfld.long 0x00 11. " CLRP1_11 ,Clear pin PIO1_11" "No effect,Clear" bitfld.long 0x00 10. " CLRP1_10 ,Clear pin PIO1_10" "No effect,Clear" textline " " endif bitfld.long 0x00 9. " CLRP1_9 ,Clear pin PIO1_9" "No effect,Clear" bitfld.long 0x00 8. " CLRP1_8 ,Clear pin PIO1_8" "No effect,Clear" bitfld.long 0x00 7. " CLRP1_7 ,Clear pin PIO1_7" "No effect,Clear" bitfld.long 0x00 6. " CLRP1_6 ,Clear pin PIO1_6" "No effect,Clear" textline " " bitfld.long 0x00 5. " CLRP1_5 ,Clear pin PIO1_5" "No effect,Clear" bitfld.long 0x00 4. " CLRP1_4 ,Clear pin PIO1_4" "No effect,Clear" bitfld.long 0x00 3. " CLRP1_3 ,Clear pin PIO1_3" "No effect,Clear" bitfld.long 0x00 2. " CLRP1_2 ,Clear pin PIO1_2" "No effect,Clear" textline " " bitfld.long 0x00 1. " CLRP1_1 ,Clear pin PIO1_1" "No effect,Clear" bitfld.long 0x00 0. " CLRP1_0 ,Clear pin PIO1_0" "No effect,Clear" endif wgroup.long 0x2300++0x03 line.long 0x00 "NOT0,GPIO Toggle Port 0 Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " NOTP0_31 ,Toggle pin PIO0_31" "No effect,Toggle" bitfld.long 0x00 30. " NOTP0_30 ,Toggle pin PIO0_30" "No effect,Toggle" bitfld.long 0x00 29. " NOTP0_29 ,Toggle pin PIO0_29" "No effect,Toggle" textline " " endif bitfld.long 0x00 28. " NOTP0_28 ,Toggle pin PIO0_28" "No effect,Toggle" bitfld.long 0x00 27. " NOTP0_27 ,Toggle pin PIO0_27" "No effect,Toggle" bitfld.long 0x00 26. " NOTP0_26 ,Toggle pin PIO0_26" "No effect,Toggle" bitfld.long 0x00 25. " NOTP0_25 ,Toggle pin PIO0_25" "No effect,Toggle" textline " " bitfld.long 0x00 24. " NOTP0_24 ,Toggle pin PIO0_24" "No effect,Toggle" bitfld.long 0x00 23. " NOTP0_23 ,Toggle pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 22. " NOTP0_22 ,Toggle pin PIO0_22" "No effect,Toggle" bitfld.long 0x00 21. " NOTP0_21 ,Toggle pin PIO0_21" "No effect,Toggle" textline " " bitfld.long 0x00 20. " NOTP0_20 ,Toggle pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " NOTP0_19 ,Toggle pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " NOTP0_18 ,Toggle pin PIO0_18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " NOTP0_17 ,Toggle pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 16. " NOTP0_16 ,Toggle pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " NOTP0_15 ,Toggle pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " NOTP0_14 ,Toggle pin PIO0_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " NOTP0_13 ,Toggle pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " NOTP0_12 ,Toggle pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " NOTP0_11 ,Toggle pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " NOTP0_10 ,Toggle pin PIO0_10" "No effect,Toggle" textline " " bitfld.long 0x00 9. " NOTP0_9 ,Toggle pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " NOTP0_8 ,Toggle pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " NOTP0_7 ,Toggle pin PIO0_7" "No effect,Toggle" bitfld.long 0x00 6. " NOTP0_6 ,Toggle pin PIO0_6" "No effect,Toggle" textline " " bitfld.long 0x00 5. " NOTP0_5 ,Toggle pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " NOTP0_4 ,Toggle pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " NOTP0_3 ,Toggle pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " NOTP0_2 ,Toggle pin PIO0_2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " NOTP0_1 ,Toggle pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " NOTP0_0 ,Toggle pin PIO0_0" "No effect,Toggle" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") wgroup.long 0x2304++0x03 line.long 0x00 "NOT1,GPIO Toggle Port 1 Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " NOTP1_21 ,Toggle pin PIO1_21" "No effect,Toggle" textline " " bitfld.long 0x00 20. " NOTP1_20 ,Toggle pin PIO1_20" "No effect,Toggle" bitfld.long 0x00 19. " NOTP1_19 ,Toggle pin PIO1_19" "No effect,Toggle" bitfld.long 0x00 18. " NOTP1_18 ,Toggle pin PIO1_18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " NOTP1_17 ,Toggle pin PIO1_17" "No effect,Toggle" bitfld.long 0x00 16. " NOTP1_16 ,Toggle pin PIO1_16" "No effect,Toggle" bitfld.long 0x00 15. " NOTP1_15 ,Toggle pin PIO1_15" "No effect,Toggle" bitfld.long 0x00 14. " NOTP1_14 ,Toggle pin PIO1_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " NOTP1_13 ,Toggle pin PIO1_13" "No effect,Toggle" bitfld.long 0x00 12. " NOTP1_12 ,Toggle pin PIO1_12" "No effect,Toggle" bitfld.long 0x00 11. " NOTP1_11 ,Toggle pin PIO1_11" "No effect,Toggle" bitfld.long 0x00 10. " NOTP1_10 ,Toggle pin PIO1_10" "No effect,Toggle" textline " " endif bitfld.long 0x00 9. " NOTP1_9 ,Toggle pin PIO1_9" "No effect,Toggle" bitfld.long 0x00 8. " NOTP1_8 ,Toggle pin PIO1_8" "No effect,Toggle" bitfld.long 0x00 7. " NOTP1_7 ,Toggle pin PIO1_7" "No effect,Toggle" bitfld.long 0x00 6. " NOTP1_6 ,Toggle pin PIO1_6" "No effect,Toggle" textline " " bitfld.long 0x00 5. " NOTP1_5 ,Toggle pin PIO1_5" "No effect,Toggle" bitfld.long 0x00 4. " NOTP1_4 ,Toggle pin PIO1_4" "No effect,Toggle" bitfld.long 0x00 3. " NOTP1_3 ,Toggle pin PIO1_3" "No effect,Toggle" bitfld.long 0x00 2. " NOTP1_2 ,Toggle pin PIO1_2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " NOTP1_1 ,Toggle pin PIO1_1" "No effect,Toggle" bitfld.long 0x00 0. " NOTP1_0 ,Toggle pin PIO1_0" "No effect,Toggle" endif wgroup.long 0x2380++0x03 line.long 0x00 "DIRSET0,GPIO Port 0 Direction Set Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " DIRSETP0_31 ,Set direction pin PIO0_31" "No effect,Set" bitfld.long 0x00 30. " DIRSETP0_30 ,Set direction pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " DIRSETP0_29 ,Set direction pin PIO0_29" "No effect,Set" textline " " endif bitfld.long 0x00 28. " DIRSETP0_28 ,Set direction pin PIO0_28" "No effect,Set" bitfld.long 0x00 27. " DIRSETP0_27 ,Set direction pin PIO0_27" "No effect,Set" bitfld.long 0x00 26. " DIRSETP0_26 ,Set direction pin PIO0_26" "No effect,Set" bitfld.long 0x00 25. " DIRSETP0_25 ,Set direction pin PIO0_25" "No effect,Set" textline " " bitfld.long 0x00 24. " DIRSETP0_24 ,Set direction pin PIO0_24" "No effect,Set" bitfld.long 0x00 23. " DIRSETP0_23 ,Set direction pin PIO0_23" "No effect,Set" bitfld.long 0x00 22. " DIRSETP0_22 ,Set direction pin PIO0_22" "No effect,Set" bitfld.long 0x00 21. " DIRSETP0_21 ,Set direction pin PIO0_21" "No effect,Set" textline " " bitfld.long 0x00 20. " DIRSETP0_20 ,Set direction pin PIO0_20" "No effect,Set" bitfld.long 0x00 19. " DIRSETP0_19 ,Set direction pin PIO0_19" "No effect,Set" bitfld.long 0x00 18. " DIRSETP0_18 ,Set direction pin PIO0_18" "No effect,Set" textline " " bitfld.long 0x00 17. " DIRSETP0_17 ,Set direction pin PIO0_17" "No effect,Set" bitfld.long 0x00 16. " DIRSETP0_16 ,Set direction pin PIO0_16" "No effect,Set" bitfld.long 0x00 15. " DIRSETP0_15 ,Set direction pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " DIRSETP0_14 ,Set direction pin PIO0_14" "No effect,Set" textline " " bitfld.long 0x00 13. " DIRSETP0_13 ,Set direction pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " DIRSETP0_12 ,Set direction pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " DIRSETP0_11 ,Set direction pin PIO0_11" "No effect,Set" bitfld.long 0x00 10. " DIRSETP0_10 ,Set direction pin PIO0_10" "No effect,Set" textline " " bitfld.long 0x00 9. " DIRSETP0_9 ,Set direction pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " DIRSETP0_8 ,Set direction pin PIO0_8" "No effect,Set" bitfld.long 0x00 7. " DIRSETP0_7 ,Set direction pin PIO0_7" "No effect,Set" bitfld.long 0x00 6. " DIRSETP0_6 ,Set direction pin PIO0_6" "No effect,Set" textline " " bitfld.long 0x00 5. " DIRSETP0_5 ,Set direction pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " DIRSETP0_4 ,Set direction pin PIO0_4" "No effect,Set" bitfld.long 0x00 3. " DIRSETP0_3 ,Set direction pin PIO0_3" "No effect,Set" bitfld.long 0x00 2. " DIRSETP0_2 ,Set direction pin PIO0_2" "No effect,Set" textline " " bitfld.long 0x00 1. " DIRSETP0_1 ,Set direction pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " DIRSETP0_0 ,Set direction pin PIO0_0" "No effect,Set" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") wgroup.long 0x2384++0x03 line.long 0x00 "DIRSET1,GPIO Port 1 Direction Set Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " DIRSETP1_21 ,Set direction pin PIO1_21" "No effect,Set" textline " " bitfld.long 0x00 20. " DIRSETP1_20 ,Set direction pin PIO1_20" "No effect,Set" bitfld.long 0x00 19. " DIRSETP1_19 ,Set direction pin PIO1_19" "No effect,Set" bitfld.long 0x00 18. " DIRSETP1_18 ,Set direction pin PIO1_18" "No effect,Set" textline " " bitfld.long 0x00 17. " DIRSETP1_17 ,Set direction pin PIO1_17" "No effect,Set" bitfld.long 0x00 16. " DIRSETP1_16 ,Set direction pin PIO1_16" "No effect,Set" bitfld.long 0x00 15. " DIRSETP1_15 ,Set direction pin PIO1_15" "No effect,Set" bitfld.long 0x00 14. " DIRSETP1_14 ,Set direction pin PIO1_14" "No effect,Set" textline " " bitfld.long 0x00 13. " DIRSETP1_13 ,Set direction pin PIO1_13" "No effect,Set" bitfld.long 0x00 12. " DIRSETP1_12 ,Set direction pin PIO1_12" "No effect,Set" bitfld.long 0x00 11. " DIRSETP1_11 ,Set direction pin PIO1_11" "No effect,Set" bitfld.long 0x00 10. " DIRSETP1_10 ,Set direction pin PIO1_10" "No effect,Set" textline " " endif bitfld.long 0x00 9. " DIRSETP1_9 ,Set direction pin PIO1_9" "No effect,Set" bitfld.long 0x00 8. " DIRSETP1_8 ,Set direction pin PIO1_8" "No effect,Set" bitfld.long 0x00 7. " DIRSETP1_7 ,Set direction pin PIO1_7" "No effect,Set" bitfld.long 0x00 6. " DIRSETP1_6 ,Set direction pin PIO1_6" "No effect,Set" textline " " bitfld.long 0x00 5. " DIRSETP1_5 ,Set direction pin PIO1_5" "No effect,Set" bitfld.long 0x00 4. " DIRSETP1_4 ,Set direction pin PIO1_4" "No effect,Set" bitfld.long 0x00 3. " DIRSETP1_3 ,Set direction pin PIO1_3" "No effect,Set" bitfld.long 0x00 2. " DIRSETP1_2 ,Set direction pin PIO1_2" "No effect,Set" textline " " bitfld.long 0x00 1. " DIRSETP1_1 ,Set direction pin PIO1_1" "No effect,Set" bitfld.long 0x00 0. " DIRSETP1_0 ,Set direction pin PIO1_0" "No effect,Set" endif wgroup.long 0x2400++0x03 line.long 0x00 "DIRCLR0,GPIO Port 0 Direction Clear Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " DIRCLRP0_31 ,Clear direction pin PIO0_31" "No effect,Set" bitfld.long 0x00 30. " DIRCLRP0_30 ,Clear direction pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " DIRCLRP0_29 ,Clear direction pin PIO0_29" "No effect,Set" textline " " endif bitfld.long 0x00 28. " DIRCLRP0_28 ,Clear direction pin PIO0_28" "No effect,Clear" bitfld.long 0x00 27. " DIRCLRP0_27 ,Clear direction pin PIO0_27" "No effect,Clear" bitfld.long 0x00 26. " DIRCLRP0_26 ,Clear direction pin PIO0_26" "No effect,Clear" bitfld.long 0x00 25. " DIRCLRP0_25 ,Clear direction pin PIO0_25" "No effect,Clear" textline " " bitfld.long 0x00 24. " DIRCLRP0_24 ,Clear direction pin PIO0_24" "No effect,Clear" bitfld.long 0x00 23. " DIRCLRP0_23 ,Clear direction pin PIO0_23" "No effect,Clear" bitfld.long 0x00 22. " DIRCLRP0_22 ,Clear direction pin PIO0_22" "No effect,Clear" bitfld.long 0x00 21. " DIRCLRP0_21 ,Clear direction pin PIO0_21" "No effect,Clear" textline " " bitfld.long 0x00 20. " DIRCLRP0_20 ,Clear direction pin PIO0_20" "No effect,Clear" bitfld.long 0x00 19. " DIRCLRP0_19 ,Clear direction pin PIO0_19" "No effect,Clear" bitfld.long 0x00 18. " DIRCLRP0_18 ,Clear direction pin PIO0_18" "No effect,Clear" textline " " bitfld.long 0x00 17. " DIRCLRP0_17 ,Clear direction pin PIO0_17" "No effect,Clear" bitfld.long 0x00 16. " DIRCLRP0_16 ,Clear direction pin PIO0_16" "No effect,Clear" bitfld.long 0x00 15. " DIRCLRP0_15 ,Clear direction pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " DIRCLRP0_14 ,Clear direction pin PIO0_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " DIRCLRP0_13 ,Clear direction pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " DIRCLRP0_12 ,Clear direction pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " DIRCLRP0_11 ,Clear direction pin PIO0_11" "No effect,Clear" bitfld.long 0x00 10. " DIRCLRP0_10 ,Clear direction pin PIO0_10" "No effect,Clear" textline " " bitfld.long 0x00 9. " DIRCLRP0_9 ,Clear direction pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " DIRCLRP0_8 ,Clear direction pin PIO0_8" "No effect,Clear" bitfld.long 0x00 7. " DIRCLRP0_7 ,Clear direction pin PIO0_7" "No effect,Clear" bitfld.long 0x00 6. " DIRCLRP0_6 ,Clear direction pin PIO0_6" "No effect,Clear" textline " " bitfld.long 0x00 5. " DIRCLRP0_5 ,Clear direction pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " DIRCLRP0_4 ,Clear direction pin PIO0_4" "No effect,Clear" bitfld.long 0x00 3. " DIRCLRP0_3 ,Clear direction pin PIO0_3" "No effect,Clear" bitfld.long 0x00 2. " DIRCLRP0_2 ,Clear direction pin PIO0_2" "No effect,Clear" textline " " bitfld.long 0x00 1. " DIRCLRP0_1 ,Clear direction pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " DIRCLRP0_0 ,Clear direction pin PIO0_0" "No effect,Clear" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") wgroup.long 0x2404++0x03 line.long 0x00 "DIRCLR1,GPIO Port 1 Direction Clear Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " DIRCLRP1_21 ,Clear direction pin PIO1_21" "No effect,Clear" textline " " bitfld.long 0x00 20. " DIRCLRP1_20 ,Clear direction pin PIO1_20" "No effect,Clear" bitfld.long 0x00 19. " DIRCLRP1_19 ,Clear direction pin PIO1_19" "No effect,Clear" bitfld.long 0x00 18. " DIRCLRP1_18 ,Clear direction pin PIO1_18" "No effect,Clear" textline " " bitfld.long 0x00 17. " DIRCLRP1_17 ,Clear direction pin PIO1_17" "No effect,Clear" bitfld.long 0x00 16. " DIRCLRP1_16 ,Clear direction pin PIO1_16" "No effect,Clear" bitfld.long 0x00 15. " DIRCLRP1_15 ,Clear direction pin PIO1_15" "No effect,Clear" bitfld.long 0x00 14. " DIRCLRP1_14 ,Clear direction pin PIO1_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " DIRCLRP1_13 ,Clear direction pin PIO1_13" "No effect,Clear" bitfld.long 0x00 12. " DIRCLRP1_12 ,Clear direction pin PIO1_12" "No effect,Clear" bitfld.long 0x00 11. " DIRCLRP1_11 ,Clear direction pin PIO1_11" "No effect,Clear" bitfld.long 0x00 10. " DIRCLRP1_10 ,Clear direction pin PIO1_10" "No effect,Clear" textline " " endif bitfld.long 0x00 9. " DIRCLRP1_9 ,Clear direction pin PIO1_9" "No effect,Clear" bitfld.long 0x00 8. " DIRCLRP1_8 ,Clear direction pin PIO1_8" "No effect,Clear" bitfld.long 0x00 7. " DIRCLRP1_7 ,Clear direction pin PIO1_7" "No effect,Clear" bitfld.long 0x00 6. " DIRCLRP1_6 ,Clear direction pin PIO1_6" "No effect,Clear" textline " " bitfld.long 0x00 5. " DIRCLRP1_5 ,Clear direction pin PIO1_5" "No effect,Clear" bitfld.long 0x00 4. " DIRCLRP1_4 ,Clear direction pin PIO1_4" "No effect,Clear" bitfld.long 0x00 3. " DIRCLRP1_3 ,Clear direction pin PIO1_3" "No effect,Clear" bitfld.long 0x00 2. " DIRCLRP1_2 ,Clear direction pin PIO1_2" "No effect,Clear" textline " " bitfld.long 0x00 1. " DIRCLRP1_1 ,Clear direction pin PIO1_1" "No effect,Clear" bitfld.long 0x00 0. " DIRCLRP1_0 ,Clear direction pin PIO1_0" "No effect,Clear" endif wgroup.long 0x2480++0x03 line.long 0x00 "DIRNOT0,GPIO Port 0 Direction Toggle Register" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 31. " DIRNOTP0_31 ,Toggle direction pin PIO0_31" "No effect,Set" bitfld.long 0x00 30. " DIRNOTP0_30 ,Toggle direction pin PIO0_30" "No effect,Set" bitfld.long 0x00 29. " DIRNOTP0_29 ,Toggle direction pin PIO0_29" "No effect,Set" textline " " endif bitfld.long 0x00 28. " DIRNOTP0_28 ,Toggle direction pin PIO0_28" "No effect,Toggle" bitfld.long 0x00 27. " DIRNOTP0_27 ,Toggle direction pin PIO0_27" "No effect,Toggle" bitfld.long 0x00 26. " DIRNOTP0_26 ,Toggle direction pin PIO0_26" "No effect,Toggle" bitfld.long 0x00 25. " DIRNOTP0_25 ,Toggle direction pin PIO0_25" "No effect,Toggle" textline " " bitfld.long 0x00 24. " DIRNOTP0_24 ,Toggle direction pin PIO0_24" "No effect,Toggle" bitfld.long 0x00 23. " DIRNOTP0_23 ,Toggle direction pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 22. " DIRNOTP0_22 ,Toggle direction pin PIO0_22" "No effect,Toggle" bitfld.long 0x00 21. " DIRNOTP0_21 ,Toggle direction pin PIO0_21" "No effect,Toggle" textline " " bitfld.long 0x00 20. " DIRNOTP0_20 ,Toggle direction pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " DIRNOTP0_19 ,Toggle direction pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " DIRNOTP0_18 ,Toggle direction pin PIO0_18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " DIRNOTP0_17 ,Toggle direction pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 16. " DIRNOTP0_16 ,Toggle direction pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " DIRNOTP0_15 ,Toggle direction pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " DIRNOTP0_14 ,Toggle direction pin PIO0_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " DIRNOTP0_13 ,Toggle direction pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " DIRNOTP0_12 ,Toggle direction pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " DIRNOTP0_11 ,Toggle direction pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " DIRNOTP0_10 ,Toggle direction pin PIO0_10" "No effect,Toggle" textline " " bitfld.long 0x00 9. " DIRNOTP0_9 ,Toggle direction pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " DIRNOTP0_8 ,Toggle direction pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " DIRNOTP0_7 ,Toggle direction pin PIO0_7" "No effect,Toggle" bitfld.long 0x00 6. " DIRNOTP0_6 ,Toggle direction pin PIO0_6" "No effect,Toggle" textline " " bitfld.long 0x00 5. " DIRNOTP0_5 ,Toggle direction pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " DIRNOTP0_4 ,Toggle direction pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " DIRNOTP0_3 ,Toggle direction pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " DIRNOTP0_2 ,Toggle direction pin PIO0_2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " DIRNOTP0_1 ,Toggle direction pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " DIRNOTP0_0 ,Toggle direction pin PIO0_0" "No effect,Toggle" sif (cpu()=="LPC844M201JHI48"||cpu()=="LPC845M301JHI48"||cpu()=="LPC844M201JBD48"||cpu()=="LPC845M301JBD48"||cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") wgroup.long 0x2484++0x03 line.long 0x00 "DIRNOT1,GPIO Port 1 Direction Toggle Register" sif (cpu()=="LPC844M201JBD64"||cpu()=="LPC845M301JBD64") bitfld.long 0x00 21. " DIRNOTP0_21 ,Toggle direction pin PIO0_21" "No effect,Toggle" textline " " bitfld.long 0x00 20. " DIRNOTP0_20 ,Toggle direction pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " DIRNOTP0_19 ,Toggle direction pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " DIRNOTP0_18 ,Toggle direction pin PIO0_18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " DIRNOTP0_17 ,Toggle direction pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 16. " DIRNOTP0_16 ,Toggle direction pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " DIRNOTP0_15 ,Toggle direction pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " DIRNOTP0_14 ,Toggle direction pin PIO0_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " DIRNOTP0_13 ,Toggle direction pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " DIRNOTP0_12 ,Toggle direction pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " DIRNOTP0_11 ,Toggle direction pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " DIRNOTP0_10 ,Toggle direction pin PIO0_10" "No effect,Toggle" textline " " endif bitfld.long 0x00 9. " DIRNOTP0_9 ,Toggle direction pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " DIRNOTP0_8 ,Toggle direction pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " DIRNOTP0_7 ,Toggle direction pin PIO0_7" "No effect,Toggle" bitfld.long 0x00 6. " DIRNOTP0_6 ,Toggle direction pin PIO0_6" "No effect,Toggle" textline " " bitfld.long 0x00 5. " DIRNOTP0_5 ,Toggle direction pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " DIRNOTP0_4 ,Toggle direction pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " DIRNOTP0_3 ,Toggle direction pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " DIRNOTP0_2 ,Toggle direction pin PIO0_2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " DIRNOTP0_1 ,Toggle direction pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " DIRNOTP0_0 ,Toggle direction pin PIO0_0" "No effect,Toggle" endif width 0x0B elif cpuis("LPC8N04") base ad:0x50000000 width 10. group.long 0x00++0x03 line.long 0x00 "GPIODATA,GPIO Data Register" BUTTON "Data" "Data.dump ad:0x50000000--(ad:0x50000000+0x3FF8) /LONG" hgroup.long 0x3FFC++0x03 hide.long 0x00 "GPIODATA,GPIO Data Register" in newline group.long 0x8000++0x13 line.long 0x00 "DIR,Data Direction Register" bitfld.long 0x00 11. " IO[11] ,Selects PIO0_11 as input or output" "Input,Output" bitfld.long 0x00 10. " [10] ,Selects PIO0_10 as input or output" "Input,Output" bitfld.long 0x00 9. " [9] ,Selects PIO0_9 as input or output" "Input,Output" bitfld.long 0x00 8. " [8] ,Selects PIO0_8 as input or output" "Input,Output" textline " " bitfld.long 0x00 7. " [7] ,Selects PIO0_7 as input or output" "Input,Output" bitfld.long 0x00 6. " [6] ,Selects PIO0_6 as input or output" "Input,Output" bitfld.long 0x00 5. " [5] ,Selects PIO0_5 as input or output" "Input,Output" bitfld.long 0x00 4. " [4] ,Selects PIO0_4 as input or output" "Input,Output" textline " " bitfld.long 0x00 3. " [3] ,Selects PIO0_3 as input or output" "Input,Output" bitfld.long 0x00 2. " [2] ,Selects PIO0_2 as input or output" "Input,Output" bitfld.long 0x00 1. " [1] ,Selects PIO0_1 as input or output" "Input,Output" bitfld.long 0x00 0. " [0] ,Selects PIO0_0 as input or output" "Input,Output" line.long 0x04 "IS,Interrupt Sense Register" bitfld.long 0x04 11. " ISENSE[11] ,Selects interrupt on pin PIO0_11 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 10. " [10] ,Selects interrupt on pin PIO0_10 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 9. " [9] ,Selects interrupt on pin PIO0_9 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 8. " [8] ,Selects interrupt on pin PIO0_8 as level or edge sensitive" "Edge,Level" textline " " bitfld.long 0x04 7. " [7] ,Selects interrupt on pin PIO0_7 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 6. " [6] ,Selects interrupt on pin PIO0_6 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 5. " [5] ,Selects interrupt on pin PIO0_5 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 4. " [4] ,Selects interrupt on pin PIO0_4 as level or edge sensitive" "Edge,Level" textline " " bitfld.long 0x04 3. " [3] ,Selects interrupt on pin PIO0_3 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 2. " [2] ,Selects interrupt on pin PIO0_2 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 1. " [1] ,Selects interrupt on pin PIO0_1 as level or edge sensitive" "Edge,Level" bitfld.long 0x04 0. " [0] ,Selects interrupt on pin PIO0_0 as level or edge sensitive" "Edge,Level" line.long 0x08 "IBE,Interrupt Both Edges Sense Register" bitfld.long 0x08 11. " IBE[11] ,Selects interrupt on pin PIO0_11" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 10. " [10] ,Selects interrupt on pin PIO0_10" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 9. " [9] ,Selects interrupt on pin PIO0_9" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 8. " [8] ,Selects interrupt on pin PIO0_8" "Controlled through GPIOIEV,On both edges" textline " " bitfld.long 0x08 7. " [7] ,Selects interrupt on pin PIO0_7" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 6. " [6] ,Selects interrupt on pin PIO0_6" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 5. " [5] ,Selects interrupt on pin PIO0_5" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 4. " [4] ,Selects interrupt on pin PIO0_4" "Controlled through GPIOIEV,On both edges" textline " " bitfld.long 0x08 3. " [3] ,Selects interrupt on pin PIO0_3" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 2. " [2] ,Selects interrupt on pin PIO0_2" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 1. " [1] ,Selects interrupt on pin PIO0_1" "Controlled through GPIOIEV,On both edges" bitfld.long 0x08 0. " [0] ,Selects interrupt on pin PIO0_0" "Controlled through GPIOIEV,On both edges" line.long 0x0C "IEV,Interrupt Event Register" bitfld.long 0x0C 11. " IEV[11] ,Selects interrupt on pin PIO0_11 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 10. " [10] ,Selects interrupt on pin PIO0_10 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 9. " [9] ,Selects interrupt on pin PIO0_9 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 8. " [8] ,Selects interrupt on pin PIO0_8 to be triggered rising or falling edges" "Falling,Rising" textline " " bitfld.long 0x0C 7. " [7] ,Selects interrupt on pin PIO0_7 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 6. " [6] ,Selects interrupt on pin PIO0_6 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 5. " [5] ,Selects interrupt on pin PIO0_5 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 4. " [4] ,Selects interrupt on pin PIO0_4 to be triggered rising or falling edges" "Falling,Rising" textline " " bitfld.long 0x0C 3. " [3] ,Selects interrupt on pin PIO0_3 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 2. " [2] ,Selects interrupt on pin PIO0_2 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 1. " [1] ,Selects interrupt on pin PIO0_1 to be triggered rising or falling edges" "Falling,Rising" bitfld.long 0x0C 0. " [0] ,Selects interrupt on pin PIO0_0 to be triggered rising or falling edges" "Falling,Rising" line.long 0x10 "IMSC,Interrupt Mask Register" bitfld.long 0x10 11. " MASK[11] ,Selects interrupt on pin PIO0_11 to be masked" "Masked,Not masked" bitfld.long 0x10 10. " [10] ,Selects interrupt on pin PIO0_10 to be masked" "Masked,Not masked" bitfld.long 0x10 9. " [9] ,Selects interrupt on pin PIO0_9 to be masked" "Masked,Not masked" bitfld.long 0x10 8. " [8] ,Selects interrupt on pin PIO0_8 to be masked" "Masked,Not masked" textline " " bitfld.long 0x10 7. " [7] ,Selects interrupt on pin PIO0_7 to be masked" "Masked,Not masked" bitfld.long 0x10 6. " [6] ,Selects interrupt on pin PIO0_6 to be masked" "Masked,Not masked" bitfld.long 0x10 5. " [5] ,Selects interrupt on pin PIO0_5 to be masked" "Masked,Not masked" bitfld.long 0x10 4. " [4] ,Selects interrupt on pin PIO0_4 to be masked" "Masked,Not masked" textline " " bitfld.long 0x10 3. " [3] ,Selects interrupt on pin PIO0_3 to be masked" "Masked,Not masked" bitfld.long 0x10 2. " [2] ,Selects interrupt on pin PIO0_2 to be masked" "Masked,Not masked" bitfld.long 0x10 1. " [1] ,Selects interrupt on pin PIO0_1 to be masked" "Masked,Not masked" bitfld.long 0x10 0. " [0] ,Selects interrupt on pin PIO0_0 to be masked" "Masked,Not masked" rgroup.long 0x8010++0x07 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt status on PIO0_11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Raw interrupt status on PIO0_10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Raw interrupt status on PIO0_9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Raw interrupt status on PIO0_8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " [7] ,Raw interrupt status on PIO0_7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Raw interrupt status on PIO0_6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Raw interrupt status on PIO0_5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Raw interrupt status on PIO0_4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " [3] ,Raw interrupt status on PIO0_3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Raw interrupt status on PIO0_2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Raw interrupt status on PIO0_1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Raw interrupt status on PIO0_0" "No interrupt,Interrupt" line.long 0x04 "MIS,Masked Interrupt Status Register" bitfld.long 0x04 11. " MASK[11] ,Selects interrupt on pin PIO0_11 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 10. " [10] ,Selects interrupt on pin PIO0_10 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 9. " [9] ,Selects interrupt on pin PIO0_9 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 8. " [8] ,Selects interrupt on pin PIO0_8 to be masked" "No interrupt/Interrupt masked,Interrupt" textline " " bitfld.long 0x04 7. " [7] ,Selects interrupt on pin PIO0_7 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 6. " [6] ,Selects interrupt on pin PIO0_6 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 5. " [5] ,Selects interrupt on pin PIO0_5 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 4. " [4] ,Selects interrupt on pin PIO0_4 to be masked" "No interrupt/Interrupt masked,Interrupt" textline " " bitfld.long 0x04 3. " [3] ,Selects interrupt on pin PIO0_3 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 2. " [2] ,Selects interrupt on pin PIO0_2 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 1. " [1] ,Selects interrupt on pin PIO0_1 to be masked" "No interrupt/Interrupt masked,Interrupt" bitfld.long 0x04 0. " [0] ,Selects interrupt on pin PIO0_0 to be masked" "No interrupt/Interrupt masked,Interrupt" wgroup.long 0x801C++0x03 line.long 0x00 "IC,Interrupt Clear Register" bitfld.long 0x00 11. " CLR[11] ,Selects interrupt on pin PIO0_11 to be cleared" "No effect,Cleared" bitfld.long 0x00 10. " [10] ,Selects interrupt on pin PIO0_10 to be cleared" "No effect,Cleared" bitfld.long 0x00 9. " [9] ,Selects interrupt on pin PIO0_9 to be cleared" "No effect,Cleared" bitfld.long 0x00 8. " [8] ,Selects interrupt on pin PIO0_8 to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 7. " [7] ,Selects interrupt on pin PIO0_7 to be cleared" "No effect,Cleared" bitfld.long 0x00 6. " [6] ,Selects interrupt on pin PIO0_6 to be cleared" "No effect,Cleared" bitfld.long 0x00 5. " [5] ,Selects interrupt on pin PIO0_5 to be cleared" "No effect,Cleared" bitfld.long 0x00 4. " [4] ,Selects interrupt on pin PIO0_4 to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 3. " [3] ,Selects interrupt on pin PIO0_3 to be cleared" "No effect,Cleared" bitfld.long 0x00 2. " [2] ,Selects interrupt on pin PIO0_2 to be cleared" "No effect,Cleared" bitfld.long 0x00 1. " [1] ,Selects interrupt on pin PIO0_1 to be cleared" "No effect,Cleared" bitfld.long 0x00 0. " [0] ,Selects interrupt on pin PIO0_0 to be cleared" "No effect,Cleared" width 0x0B else base ad:0xA0000000 width 7. tree "Byte Pin Registers Port 0" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin PIO0_6" bitfld.byte 0x00 0. " PBYTE ,PIO0_6 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin PIO0_18" bitfld.byte 0x00 0. " PBYTE ,PIO0_18 pin state" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin PIO0_19" bitfld.byte 0x00 0. " PBYTE ,PIO0_19 pin state" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin PIO0_20" bitfld.byte 0x00 0. " PBYTE ,PIO0_20 pin state" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin PIO0_21" bitfld.byte 0x00 0. " PBYTE ,PIO0_21 pin state" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin PIO0_22" bitfld.byte 0x00 0. " PBYTE ,PIO0_22 pin state" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin PIO0_23" bitfld.byte 0x00 0. " PBYTE ,PIO0_23 pin state" "Low,High" group.byte 0x18++0x00 line.byte 0x00 "B24,Byte Pin Register Port 0 Pin PIO0_24" bitfld.byte 0x00 0. " PBYTE ,PIO0_24 pin state" "Low,High" group.byte 0x19++0x00 line.byte 0x00 "B25,Byte Pin Register Port 0 Pin PIO0_25" bitfld.byte 0x00 0. " PBYTE ,PIO0_25 pin state" "Low,High" group.byte 0x1A++0x00 line.byte 0x00 "B26,Byte Pin Register Port 0 Pin PIO0_26" bitfld.byte 0x00 0. " PBYTE ,PIO0_26 pin state" "Low,High" group.byte 0x1B++0x00 line.byte 0x00 "B27,Byte Pin Register Port 0 Pin PIO0_27" bitfld.byte 0x00 0. " PBYTE ,PIO0_27 pin state" "Low,High" group.byte 0x1C++0x00 line.byte 0x00 "B28,Byte Pin Register Port 0 Pin PIO0_28" bitfld.byte 0x00 0. " PBYTE ,PIO0_28 pin state" "Low,High" else group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin PIO0_0" bitfld.byte 0x00 0. " PBYTE ,PIO0_0 pin state" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin PIO0_1" bitfld.byte 0x00 0. " PBYTE ,PIO0_1 pin state" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin PIO0_2" bitfld.byte 0x00 0. " PBYTE ,PIO0_2 pin state" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin PIO0_3" bitfld.byte 0x00 0. " PBYTE ,PIO0_3 pin state" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin PIO0_4" bitfld.byte 0x00 0. " PBYTE ,PIO0_4 pin state" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin PIO0_5" bitfld.byte 0x00 0. " PBYTE ,PIO0_5 pin state" "Low,High" sif cpu()!="LPC810M021FN8" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin PIO0_6" bitfld.byte 0x00 0. " PBYTE ,PIO0_6 pin state" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin PIO0_7" bitfld.byte 0x00 0. " PBYTE ,PIO0_7 pin state" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin PIO0_8" bitfld.byte 0x00 0. " PBYTE ,PIO0_8 pin state" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin PIO0_9" bitfld.byte 0x00 0. " PBYTE ,PIO0_9 pin state" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin PIO0_10" bitfld.byte 0x00 0. " PBYTE ,PIO0_10 pin state" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin PIO0_11" bitfld.byte 0x00 0. " PBYTE ,PIO0_11 pin state" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin PIO0_12" bitfld.byte 0x00 0. " PBYTE ,PIO0_12 pin state" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin PIO0_13" bitfld.byte 0x00 0. " PBYTE ,PIO0_13 pin state" "Low,High" endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")) group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin PIO0_14" bitfld.byte 0x00 0. " PBYTE ,PIO0_14 pin state" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin PIO0_15" bitfld.byte 0x00 0. " PBYTE ,PIO0_15 pin state" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin PIO0_16" bitfld.byte 0x00 0. " PBYTE ,PIO0_16 pin state" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin PIO0_17" bitfld.byte 0x00 0. " PBYTE ,PIO0_17 pin state" "Low,High" endif endif tree.end tree "Word Pin Registers Port 0" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Registers Port 0 Pin PIO0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Registers Port 0 Pin PIO0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Registers Port 0 Pin PIO0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Registers Port 0 Pin PIO0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Registers Port 0 Pin PIO0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Registers Port 0 Pin PIO0_5" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Registers Port 0 Pin PIO0_6" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Registers Port 0 Pin PIO0_7" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Registers Port 0 Pin PIO0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Registers Port 0 Pin PIO0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Registers Port 0 Pin PIO0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Registers Port 0 Pin PIO0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Registers Port 0 Pin PIO0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Registers Port 0 Pin PIO0_13" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Registers Port 0 Pin PIO0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Registers Port 0 Pin PIO0_15" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Registers Port 0 Pin PIO0_16" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Registers Port 0 Pin PIO0_17" group.long 0x1048++0x03 line.long 0x00 "W18,Word Pin Registers Port 0 Pin PIO0_18" group.long 0x104C++0x03 line.long 0x00 "W19,Word Pin Registers Port 0 Pin PIO0_19" group.long 0x1050++0x03 line.long 0x00 "W20,Word Pin Registers Port 0 Pin PIO0_20" group.long 0x1054++0x03 line.long 0x00 "W21,Word Pin Registers Port 0 Pin PIO0_21" group.long 0x1058++0x03 line.long 0x00 "W22,Word Pin Registers Port 0 Pin PIO0_22" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Registers Port 0 Pin PIO0_23" group.long 0x1060++0x03 line.long 0x00 "W24,Word Pin Registers Port 0 Pin PIO0_24" group.long 0x1064++0x03 line.long 0x00 "W25,Word Pin Registers Port 0 Pin PIO0_25" group.long 0x1068++0x03 line.long 0x00 "W26,Word Pin Registers Port 0 Pin PIO0_26" group.long 0x106C++0x03 line.long 0x00 "W27,Word Pin Registers Port 0 Pin PIO0_27" group.long 0x1070++0x03 line.long 0x00 "W28,Word Pin Registers Port 0 Pin PIO0_28" else group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Registers Port 0 Pin PIO0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Registers Port 0 Pin PIO0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Registers Port 0 Pin PIO0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Registers Port 0 Pin PIO0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Registers Port 0 Pin PIO0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Registers Port 0 Pin PIO0_5" sif cpu()!="LPC810M021FN8" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Registers Port 0 Pin PIO0_6" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Registers Port 0 Pin PIO0_7" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Registers Port 0 Pin PIO0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Registers Port 0 Pin PIO0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Registers Port 0 Pin PIO0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Registers Port 0 Pin PIO0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Registers Port 0 Pin PIO0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Registers Port 0 Pin PIO0_13" endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")) group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Registers Port 0 Pin PIO0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Registers Port 0 Pin PIO0_15" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Registers Port 0 Pin PIO0_16" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Registers Port 0 Pin PIO0_17" endif endif tree.end textline " " group.long 0x2000++0x3 line.long 0x00 "DIR0,Direction Registers Port 0" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " DIRP0_28 ,Pin direction for pin PIO0_28" "Input,Output" bitfld.long 0x00 27. " DIRP0_27 ,Pin direction for pin PIO0_27" "Input,Output" bitfld.long 0x00 26. " DIRP0_26 ,Pin direction for pin PIO0_26" "Input,Output" bitfld.long 0x00 25. " DIRP0_25 ,Pin direction for pin PIO0_25" "Input,Output" textline " " bitfld.long 0x00 24. " DIRP0_24 ,Pin direction for pin PIO0_24" "Input,Output" bitfld.long 0x00 23. " DIRP0_23 ,Pin direction for pin PIO0_23" "Input,Output" bitfld.long 0x00 22. " DIRP0_22 ,Pin direction for pin PIO0_22" "Input,Output" bitfld.long 0x00 21. " DIRP0_21 ,Pin direction for pin PIO0_21" "Input,Output" textline " " bitfld.long 0x00 20. " DIRP0_20 ,Pin direction for pin PIO0_20" "Input,Output" bitfld.long 0x00 19. " DIRP0_19 ,Pin direction for pin PIO0_19" "Input,Output" bitfld.long 0x00 18. " DIRP0_18 ,Pin direction for pin PIO0_18" "Input,Output" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " DIRP0_17 ,Pin direction for pin PIO0_17" "Input,Output" bitfld.long 0x00 16. " DIRP0_16 ,Pin direction for pin PIO0_16" "Input,Output" bitfld.long 0x00 15. " DIRP0_15 ,Pin direction for pin PIO0_15" "Input,Output" bitfld.long 0x00 14. " DIRP0_14 ,Pin direction for pin PIO0_14" "Input,Output" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " DIRP0_13 ,Pin direction for pin PIO0_13" "Input,Output" bitfld.long 0x00 12. " DIRP0_12 ,Pin direction for pin PIO0_12" "Input,Output" bitfld.long 0x00 11. " DIRP0_11 ,Pin direction for pin PIO0_11" "Input,Output" bitfld.long 0x00 10. " DIRP0_10 ,Pin direction for pin PIO0_10" "Input,Output" textline " " bitfld.long 0x00 9. " DIRP0_9 ,Pin direction for pin PIO0_9" "Input,Output" bitfld.long 0x00 8. " DIRP0_8 ,Pin direction for pin PIO0_8" "Input,Output" bitfld.long 0x00 7. " DIRP0_7 ,Pin direction for pin PIO0_7" "Input,Output" bitfld.long 0x00 6. " DIRP0_6 ,Pin direction for pin PIO0_6" "Input,Output" textline " " endif bitfld.long 0x00 5. " DIRP0_5 ,Pin direction for pin PIO0_5" "Input,Output" bitfld.long 0x00 4. " DIRP0_4 ,Pin direction for pin PIO0_4" "Input,Output" bitfld.long 0x00 3. " DIRP0_3 ,Pin direction for pin PIO0_3" "Input,Output" bitfld.long 0x00 2. " DIRP0_2 ,Pin direction for pin PIO0_2" "Input,Output" textline " " bitfld.long 0x00 1. " DIRP0_1 ,Pin direction for pin PIO0_1" "Input,Output" bitfld.long 0x00 0. " DIRP0_0 ,Pin direction for pin PIO0_0" "Input,Output" group.long 0x2080++0x03 line.long 0x00 "MASK0,GPIO Mask Port 0 Register" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " MASKP0_28 ,Write via MPORT enable for pin PIO0_28" "Not masked,Masked" bitfld.long 0x00 27. " MASKP0_27 ,Write via MPORT enable for pin PIO0_27" "Not masked,Masked" bitfld.long 0x00 26. " MASKP0_26 ,Write via MPORT enable for pin PIO0_26" "Not masked,Masked" bitfld.long 0x00 25. " MASKP0_25 ,Write via MPORT enable for pin PIO0_25" "Not masked,Masked" textline " " bitfld.long 0x00 24. " MASKP0_24 ,Write via MPORT enable for pin PIO0_24" "Not masked,Masked" bitfld.long 0x00 23. " MASKP0_23 ,Write via MPORT enable for pin PIO0_23" "Not masked,Masked" bitfld.long 0x00 22. " MASKP0_22 ,Write via MPORT enable for pin PIO0_22" "Not masked,Masked" bitfld.long 0x00 21. " MASKP0_21 ,Write via MPORT enable for pin PIO0_21" "Not masked,Masked" textline " " bitfld.long 0x00 20. " MASKP0_20 ,Write via MPORT enable for pin PIO0_20" "Not masked,Masked" bitfld.long 0x00 19. " MASKP0_19 ,Write via MPORT enable for pin PIO0_19" "Not masked,Masked" bitfld.long 0x00 18. " MASKP0_18 ,Write via MPORT enable for pin PIO0_18" "Not masked,Masked" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " MASKP0_17 ,Write via MPORT enable for pin PIO0_17" "Not masked,Masked" bitfld.long 0x00 16. " MASKP0_16 ,Write via MPORT enable for pin PIO0_16" "Not masked,Masked" bitfld.long 0x00 15. " MASKP0_15 ,Write via MPORT enable for pin PIO0_15" "Not masked,Masked" bitfld.long 0x00 14. " MASKP0_14 ,Write via MPORT enable for pin PIO0_14" "Not masked,Masked" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " MASKP0_13 ,Write via MPORT enable for pin PIO0_13" "Not masked,Masked" bitfld.long 0x00 12. " MASKP0_12 ,Write via MPORT enable for pin PIO0_12" "Not masked,Masked" bitfld.long 0x00 11. " MASKP0_11 ,Write via MPORT enable for pin PIO0_11" "Not masked,Masked" bitfld.long 0x00 10. " MASKP0_10 ,Write via MPORT enable for pin PIO0_10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MASKP0_9 ,Write via MPORT enable for pin PIO0_9" "Not masked,Masked" bitfld.long 0x00 8. " MASKP0_8 ,Write via MPORT enable for pin PIO0_8" "Not masked,Masked" bitfld.long 0x00 7. " MASKP0_7 ,Write via MPORT enable for pin PIO0_7" "Not masked,Masked" bitfld.long 0x00 6. " MASKP0_6 ,Write via MPORT enable for pin PIO0_6" "Not masked,Masked" textline " " endif bitfld.long 0x00 5. " MASKP0_5 ,Write via MPORT enable for pin PIO0_5" "Not masked,Masked" bitfld.long 0x00 4. " MASKP0_4 ,Write via MPORT enable for pin PIO0_4" "Not masked,Masked" bitfld.long 0x00 3. " MASKP0_3 ,Write via MPORT enable for pin PIO0_3" "Not masked,Masked" bitfld.long 0x00 2. " MASKP0_2 ,Write via MPORT enable for pin PIO0_2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MASKP0_1 ,Write via MPORT enable for pin PIO0_1" "Not masked,Masked" bitfld.long 0x00 0. " MASKP0_0 ,Write via MPORT enable for pin PIO0_0" "Not masked,Masked" group.long 0x2100++0x03 line.long 0x00 "PIN0,GPIO Port 0 Pin Register" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " PORT0_28 ,Pin state for pin PIO0_28" "Low,High" bitfld.long 0x00 27. " PORT0_27 ,Pin state for pin PIO0_27" "Low,High" bitfld.long 0x00 26. " PORT0_26 ,Pin state for pin PIO0_26" "Low,High" bitfld.long 0x00 25. " PORT0_25 ,Pin state for pin PIO0_25" "Low,High" textline " " bitfld.long 0x00 24. " PORT0_24 ,Pin state for pin PIO0_24" "Low,High" bitfld.long 0x00 23. " PORT0_23 ,Pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 22. " PORT0_22 ,Pin state for pin PIO0_22" "Low,High" bitfld.long 0x00 21. " PORT0_21 ,Pin state for pin PIO0_21" "Low,High" textline " " bitfld.long 0x00 20. " PORT0_20 ,Pin state for pin PIO0_20" "Low,High" bitfld.long 0x00 19. " PORT0_19 ,Pin state for pin PIO0_19" "Low,High" bitfld.long 0x00 18. " PORT0_18 ,Pin state for pin PIO0_18" "Low,High" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " PORT0_17 ,Pin state for pin PIO0_17" "Low,High" bitfld.long 0x00 16. " PORT0_16 ,Pin state for pin PIO0_16" "Low,High" bitfld.long 0x00 15. " PORT0_15 ,Pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " PORT0_14 ,Pin state for pin PIO0_14" "Low,High" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " PORT0_13 ,Pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " PORT0_12 ,Pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " PORT0_11 ,Pin state for pin PIO0_11" "Low,High" bitfld.long 0x00 10. " PORT0_10 ,Pin state for pin PIO0_10" "Low,High" textline " " bitfld.long 0x00 9. " PORT0_9 ,Pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " PORT0_8 ,Pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 7. " PORT0_7 ,Pin state for pin PIO0_7" "Low,High" bitfld.long 0x00 6. " PORT0_6 ,Pin state for pin PIO0_6" "Low,High" textline " " endif bitfld.long 0x00 5. " PORT0_5 ,Pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " PORT0_4 ,Pin state for pin PIO0_4" "Low,High" bitfld.long 0x00 3. " PORT0_3 ,Pin state for pin PIO0_3" "Low,High" bitfld.long 0x00 2. " PORT0_2 ,Pin state for pin PIO0_2" "Low,High" textline " " bitfld.long 0x00 1. " PORT0_1 ,Pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " PORT0_0 ,Pin state for pin PIO0_0" "Low,High" group.long 0x2180++0x03 line.long 0x00 "MPIN0,GPIO Masked Port 0 Pin Register" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " MPORTP0_28 ,Masked pin state for pin PIO0_28" "Low,High" bitfld.long 0x00 27. " MPORTP0_27 ,Masked pin state for pin PIO0_27" "Low,High" bitfld.long 0x00 26. " MPORTP0_26 ,Masked pin state for pin PIO0_26" "Low,High" bitfld.long 0x00 25. " MPORTP0_25 ,Masked pin state for pin PIO0_25" "Low,High" textline " " bitfld.long 0x00 24. " MPORTP0_24 ,Masked pin state for pin PIO0_24" "Low,High" bitfld.long 0x00 23. " MPORTP0_23 ,Masked pin state for pin PIO0_23" "Low,High" bitfld.long 0x00 22. " MPORTP0_22 ,Masked pin state for pin PIO0_22" "Low,High" bitfld.long 0x00 21. " MPORTP0_21 ,Masked pin state for pin PIO0_21" "Low,High" textline " " bitfld.long 0x00 20. " MPORTP0_20 ,Masked pin state for pin PIO0_20" "Low,High" bitfld.long 0x00 19. " MPORTP0_19 ,Masked pin state for pin PIO0_19" "Low,High" bitfld.long 0x00 18. " MPORTP0_18 ,Masked pin state for pin PIO0_18" "Low,High" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " MPORTP0_17 ,Masked pin state for pin PIO0_17" "Low,High" bitfld.long 0x00 16. " MPORTP0_16 ,Masked pin state for pin PIO0_16" "Low,High" bitfld.long 0x00 15. " MPORTP0_15 ,Masked pin state for pin PIO0_15" "Low,High" bitfld.long 0x00 14. " MPORTP0_14 ,Masked pin state for pin PIO0_14" "Low,High" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " MPORTP0_13 ,Masked pin state for pin PIO0_13" "Low,High" bitfld.long 0x00 12. " MPORTP0_12 ,Masked pin state for pin PIO0_12" "Low,High" bitfld.long 0x00 11. " MPORTP0_11 ,Masked pin state for pin PIO0_11" "Low,High" bitfld.long 0x00 10. " MPORTP0_10 ,Masked pin state for pin PIO0_10" "Low,High" textline " " bitfld.long 0x00 9. " MPORTP0_9 ,Masked pin state for pin PIO0_9" "Low,High" bitfld.long 0x00 8. " MPORTP0_8 ,Masked pin state for pin PIO0_8" "Low,High" bitfld.long 0x00 7. " MPORTP0_7 ,Masked pin state for pin PIO0_7" "Low,High" bitfld.long 0x00 6. " MPORTP0_6 ,Masked pin state for pin PIO0_6" "Low,High" textline " " endif bitfld.long 0x00 5. " MPORTP0_5 ,Masked pin state for pin PIO0_5" "Low,High" bitfld.long 0x00 4. " MPORTP0_4 ,Masked pin state for pin PIO0_4" "Low,High" bitfld.long 0x00 3. " MPORTP0_3 ,Masked pin state for pin PIO0_3" "Low,High" bitfld.long 0x00 2. " MPORTP0_2 ,Masked pin state for pin PIO0_2" "Low,High" textline " " bitfld.long 0x00 1. " MPORTP0_1 ,Masked pin state for pin PIO0_1" "Low,High" bitfld.long 0x00 0. " MPORTP0_0 ,Masked pin state for pin PIO0_0" "Low,High" group.long 0x2200++0x03 line.long 0x00 "SET0,GPIO Set Port 0 Pin Register" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " SETP0_28 ,Set pin PIO0_28" "No effect,Set" bitfld.long 0x00 27. " SETP0_27 ,Set pin PIO0_27" "No effect,Set" bitfld.long 0x00 26. " SETP0_26 ,Set pin PIO0_26" "No effect,Set" bitfld.long 0x00 25. " SETP0_25 ,Set pin PIO0_25" "No effect,Set" textline " " bitfld.long 0x00 24. " SETP0_24 ,Set pin PIO0_24" "No effect,Set" bitfld.long 0x00 23. " SETP0_23 ,Set pin PIO0_23" "No effect,Set" bitfld.long 0x00 22. " SETP0_22 ,Set pin PIO0_22" "No effect,Set" bitfld.long 0x00 21. " SETP0_21 ,Set pin PIO0_21" "No effect,Set" textline " " bitfld.long 0x00 20. " SETP0_20 ,Set pin PIO0_20" "No effect,Set" bitfld.long 0x00 19. " SETP0_19 ,Set pin PIO0_19" "No effect,Set" bitfld.long 0x00 18. " SETP0_18 ,Set pin PIO0_18" "No effect,Set" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " SETP0_17 ,Set pin PIO0_17" "No effect,Set" bitfld.long 0x00 16. " SETP0_16 ,Set pin PIO0_16" "No effect,Set" bitfld.long 0x00 15. " SETP0_15 ,Set pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " SETP0_14 ,Set pin PIO0_14" "No effect,Set" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " SETP0_13 ,Set pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " SETP0_12 ,Set pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " SETP0_11 ,Set pin PIO0_11" "No effect,Set" bitfld.long 0x00 10. " SETP0_10 ,Set pin PIO0_10" "No effect,Set" textline " " bitfld.long 0x00 9. " SETP0_9 ,Set pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " SETP0_8 ,Set pin PIO0_8" "No effect,Set" bitfld.long 0x00 7. " SETP0_7 ,Set pin PIO0_7" "No effect,Set" bitfld.long 0x00 6. " SETP0_6 ,Set pin PIO0_6" "No effect,Set" textline " " endif bitfld.long 0x00 5. " SETP0_5 ,Set pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " SETP0_4 ,Set pin PIO0_4" "No effect,Set" bitfld.long 0x00 3. " SETP0_3 ,Set pin PIO0_3" "No effect,Set" bitfld.long 0x00 2. " SETP0_2 ,Set pin PIO0_2" "No effect,Set" textline " " bitfld.long 0x00 1. " SETP0_1 ,Set pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " SETP0_0 ,Set pin PIO0_0" "No effect,Set" wgroup.long 0x2280++0x03 line.long 0x00 "CLR0,GPIO Clear Port 0 Pin Register" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " CLRP0_28 ,Clear pin PIO0_28" "No effect,Clear" bitfld.long 0x00 27. " CLRP0_27 ,Clear pin PIO0_27" "No effect,Clear" bitfld.long 0x00 26. " CLRP0_26 ,Clear pin PIO0_26" "No effect,Clear" bitfld.long 0x00 25. " CLRP0_25 ,Clear pin PIO0_25" "No effect,Clear" textline " " bitfld.long 0x00 24. " CLRP0_24 ,Clear pin PIO0_24" "No effect,Clear" bitfld.long 0x00 23. " CLRP0_23 ,Clear pin PIO0_23" "No effect,Clear" bitfld.long 0x00 22. " CLRP0_22 ,Clear pin PIO0_22" "No effect,Clear" bitfld.long 0x00 21. " CLRP0_21 ,Clear pin PIO0_21" "No effect,Clear" textline " " bitfld.long 0x00 20. " CLRP0_20 ,Clear pin PIO0_20" "No effect,Clear" bitfld.long 0x00 19. " CLRP0_19 ,Clear pin PIO0_19" "No effect,Clear" bitfld.long 0x00 18. " CLRP0_18 ,Clear pin PIO0_18" "No effect,Clear" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " CLRP0_17 ,Clear pin PIO0_17" "No effect,Clear" bitfld.long 0x00 16. " CLRP0_16 ,Clear pin PIO0_16" "No effect,Clear" bitfld.long 0x00 15. " CLRP0_15 ,Clear pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " CLRP0_14 ,Clear pin PIO0_14" "No effect,Clear" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " CLRP0_13 ,Clear pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " CLRP0_12 ,Clear pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " CLRP0_11 ,Clear pin PIO0_11" "No effect,Clear" bitfld.long 0x00 10. " CLRP0_10 ,Clear pin PIO0_10" "No effect,Clear" textline " " bitfld.long 0x00 9. " CLRP0_9 ,Clear pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " CLRP0_8 ,Clear pin PIO0_8" "No effect,Clear" bitfld.long 0x00 7. " CLRP0_7 ,Clear pin PIO0_7" "No effect,Clear" bitfld.long 0x00 6. " CLRP0_6 ,Clear pin PIO0_6" "No effect,Clear" textline " " endif bitfld.long 0x00 5. " CLRP0_5 ,Clear pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " CLRP0_4 ,Clear pin PIO0_4" "No effect,Clear" bitfld.long 0x00 3. " CLRP0_3 ,Clear pin PIO0_3" "No effect,Clear" bitfld.long 0x00 2. " CLRP0_2 ,Clear pin PIO0_2" "No effect,Clear" textline " " bitfld.long 0x00 1. " CLRP0_1 ,Clear pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " CLRP0_0 ,Clear pin PIO0_0" "No effect,Clear" wgroup.long 0x2300++0x03 line.long 0x00 "NOT0,GPIO Toggle Port 0 Register" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 28. " NOTP0_28 ,Toggle pin PIO0_28" "No effect,Toggle" bitfld.long 0x00 27. " NOTP0_27 ,Toggle pin PIO0_27" "No effect,Toggle" bitfld.long 0x00 26. " NOTP0_26 ,Toggle pin PIO0_26" "No effect,Toggle" bitfld.long 0x00 25. " NOTP0_25 ,Toggle pin PIO0_25" "No effect,Toggle" textline " " bitfld.long 0x00 24. " NOTP0_24 ,Toggle pin PIO0_24" "No effect,Toggle" bitfld.long 0x00 23. " NOTP0_23 ,Toggle pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 22. " NOTP0_22 ,Toggle pin PIO0_22" "No effect,Toggle" bitfld.long 0x00 21. " NOTP0_21 ,Toggle pin PIO0_21" "No effect,Toggle" textline " " bitfld.long 0x00 20. " NOTP0_20 ,Toggle pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " NOTP0_19 ,Toggle pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " NOTP0_18 ,Toggle pin PIO0_18" "No effect,Toggle" textline " " endif sif (cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH20"||cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpuis("LPC812M101JD20")||cpuis("LPC812M101JDH20")||cpu()=="LPC834M101FHI33") bitfld.long 0x00 17. " NOTP0_17 ,Toggle pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 16. " NOTP0_16 ,Toggle pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " NOTP0_15 ,Toggle pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " NOTP0_14 ,Toggle pin PIO0_14" "No effect,Toggle" textline " " endif sif cpu()!="LPC810M021FN8" bitfld.long 0x00 13. " NOTP0_13 ,Toggle pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " NOTP0_12 ,Toggle pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " NOTP0_11 ,Toggle pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " NOTP0_10 ,Toggle pin PIO0_10" "No effect,Toggle" textline " " bitfld.long 0x00 9. " NOTP0_9 ,Toggle pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " NOTP0_8 ,Toggle pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " NOTP0_7 ,Toggle pin PIO0_7" "No effect,Toggle" bitfld.long 0x00 6. " NOTP0_6 ,Toggle pin PIO0_6" "No effect,Toggle" textline " " endif bitfld.long 0x00 5. " NOTP0_5 ,Toggle pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " NOTP0_4 ,Toggle pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " NOTP0_3 ,Toggle pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " NOTP0_2 ,Toggle pin PIO0_2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " NOTP0_1 ,Toggle pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " NOTP0_0 ,Toggle pin PIO0_0" "No effect,Toggle" sif (cpuis("LPC822M101JHI33")||cpuis("LPC824M201JHI33")||cpu()=="LPC834M101FHI33") width 9. textline " " wgroup.long 0x2380++0x03 line.long 0x00 "DIRSET0,GPIO Port 0 Direction Set Register" bitfld.long 0x00 28. " DIRSETP0_28 ,Set direction pin PIO0_28" "No effect,Set" bitfld.long 0x00 27. " DIRSETP0_27 ,Set direction pin PIO0_27" "No effect,Set" bitfld.long 0x00 26. " DIRSETP0_26 ,Set direction pin PIO0_26" "No effect,Set" bitfld.long 0x00 25. " DIRSETP0_25 ,Set direction pin PIO0_25" "No effect,Set" textline " " bitfld.long 0x00 24. " DIRSETP0_24 ,Set direction pin PIO0_24" "No effect,Set" bitfld.long 0x00 23. " DIRSETP0_23 ,Set direction pin PIO0_23" "No effect,Set" bitfld.long 0x00 22. " DIRSETP0_22 ,Set direction pin PIO0_22" "No effect,Set" bitfld.long 0x00 21. " DIRSETP0_21 ,Set direction pin PIO0_21" "No effect,Set" textline " " bitfld.long 0x00 20. " DIRSETP0_20 ,Set direction pin PIO0_20" "No effect,Set" bitfld.long 0x00 19. " DIRSETP0_19 ,Set direction pin PIO0_19" "No effect,Set" bitfld.long 0x00 18. " DIRSETP0_18 ,Set direction pin PIO0_18" "No effect,Set" textline " " bitfld.long 0x00 17. " DIRSETP0_17 ,Set direction pin PIO0_17" "No effect,Set" bitfld.long 0x00 16. " DIRSETP0_16 ,Set direction pin PIO0_16" "No effect,Set" bitfld.long 0x00 15. " DIRSETP0_15 ,Set direction pin PIO0_15" "No effect,Set" bitfld.long 0x00 14. " DIRSETP0_14 ,Set direction pin PIO0_14" "No effect,Set" textline " " bitfld.long 0x00 13. " DIRSETP0_13 ,Set direction pin PIO0_13" "No effect,Set" bitfld.long 0x00 12. " DIRSETP0_12 ,Set direction pin PIO0_12" "No effect,Set" bitfld.long 0x00 11. " DIRSETP0_11 ,Set direction pin PIO0_11" "No effect,Set" bitfld.long 0x00 10. " DIRSETP0_10 ,Set direction pin PIO0_10" "No effect,Set" textline " " bitfld.long 0x00 9. " DIRSETP0_9 ,Set direction pin PIO0_9" "No effect,Set" bitfld.long 0x00 8. " DIRSETP0_8 ,Set direction pin PIO0_8" "No effect,Set" bitfld.long 0x00 7. " DIRSETP0_7 ,Set direction pin PIO0_7" "No effect,Set" bitfld.long 0x00 6. " DIRSETP0_6 ,Set direction pin PIO0_6" "No effect,Set" textline " " bitfld.long 0x00 5. " DIRSETP0_5 ,Set direction pin PIO0_5" "No effect,Set" bitfld.long 0x00 4. " DIRSETP0_4 ,Set direction pin PIO0_4" "No effect,Set" bitfld.long 0x00 3. " DIRSETP0_3 ,Set direction pin PIO0_3" "No effect,Set" bitfld.long 0x00 2. " DIRSETP0_2 ,Set direction pin PIO0_2" "No effect,Set" textline " " bitfld.long 0x00 1. " DIRSETP0_1 ,Set direction pin PIO0_1" "No effect,Set" bitfld.long 0x00 0. " DIRSETP0_0 ,Set direction pin PIO0_0" "No effect,Set" wgroup.long 0x2400++0x03 line.long 0x00 "DIRCLR0,GPIO Port 0 Direction Clear Register" bitfld.long 0x00 28. " DIRCLRP0_28 ,Clear direction pin PIO0_28" "No effect,Clear" bitfld.long 0x00 27. " DIRCLRP0_27 ,Clear direction pin PIO0_27" "No effect,Clear" bitfld.long 0x00 26. " DIRCLRP0_26 ,Clear direction pin PIO0_26" "No effect,Clear" bitfld.long 0x00 25. " DIRCLRP0_25 ,Clear direction pin PIO0_25" "No effect,Clear" textline " " bitfld.long 0x00 24. " DIRCLRP0_24 ,Clear direction pin PIO0_24" "No effect,Clear" bitfld.long 0x00 23. " DIRCLRP0_23 ,Clear direction pin PIO0_23" "No effect,Clear" bitfld.long 0x00 22. " DIRCLRP0_22 ,Clear direction pin PIO0_22" "No effect,Clear" bitfld.long 0x00 21. " DIRCLRP0_21 ,Clear direction pin PIO0_21" "No effect,Clear" textline " " bitfld.long 0x00 20. " DIRCLRP0_20 ,Clear direction pin PIO0_20" "No effect,Clear" bitfld.long 0x00 19. " DIRCLRP0_19 ,Clear direction pin PIO0_19" "No effect,Clear" bitfld.long 0x00 18. " DIRCLRP0_18 ,Clear direction pin PIO0_18" "No effect,Clear" textline " " bitfld.long 0x00 17. " DIRCLRP0_17 ,Clear direction pin PIO0_17" "No effect,Clear" bitfld.long 0x00 16. " DIRCLRP0_16 ,Clear direction pin PIO0_16" "No effect,Clear" bitfld.long 0x00 15. " DIRCLRP0_15 ,Clear direction pin PIO0_15" "No effect,Clear" bitfld.long 0x00 14. " DIRCLRP0_14 ,Clear direction pin PIO0_14" "No effect,Clear" textline " " bitfld.long 0x00 13. " DIRCLRP0_13 ,Clear direction pin PIO0_13" "No effect,Clear" bitfld.long 0x00 12. " DIRCLRP0_12 ,Clear direction pin PIO0_12" "No effect,Clear" bitfld.long 0x00 11. " DIRCLRP0_11 ,Clear direction pin PIO0_11" "No effect,Clear" bitfld.long 0x00 10. " DIRCLRP0_10 ,Clear direction pin PIO0_10" "No effect,Clear" textline " " bitfld.long 0x00 9. " DIRCLRP0_9 ,Clear direction pin PIO0_9" "No effect,Clear" bitfld.long 0x00 8. " DIRCLRP0_8 ,Clear direction pin PIO0_8" "No effect,Clear" bitfld.long 0x00 7. " DIRCLRP0_7 ,Clear direction pin PIO0_7" "No effect,Clear" bitfld.long 0x00 6. " DIRCLRP0_6 ,Clear direction pin PIO0_6" "No effect,Clear" textline " " bitfld.long 0x00 5. " DIRCLRP0_5 ,Clear direction pin PIO0_5" "No effect,Clear" bitfld.long 0x00 4. " DIRCLRP0_4 ,Clear direction pin PIO0_4" "No effect,Clear" bitfld.long 0x00 3. " DIRCLRP0_3 ,Clear direction pin PIO0_3" "No effect,Clear" bitfld.long 0x00 2. " DIRCLRP0_2 ,Clear direction pin PIO0_2" "No effect,Clear" textline " " bitfld.long 0x00 1. " DIRCLRP0_1 ,Clear direction pin PIO0_1" "No effect,Clear" bitfld.long 0x00 0. " DIRCLRP0_0 ,Clear direction pin PIO0_0" "No effect,Clear" wgroup.long 0x2480++0x03 line.long 0x00 "DIRNOT0,GPIO Port 0 Direction Toggle Register" bitfld.long 0x00 28. " DIRNOTP0_28 ,Toggle direction pin PIO0_28" "No effect,Toggle" bitfld.long 0x00 27. " DIRNOTP0_27 ,Toggle direction pin PIO0_27" "No effect,Toggle" bitfld.long 0x00 26. " DIRNOTP0_26 ,Toggle direction pin PIO0_26" "No effect,Toggle" bitfld.long 0x00 25. " DIRNOTP0_25 ,Toggle direction pin PIO0_25" "No effect,Toggle" textline " " bitfld.long 0x00 24. " DIRNOTP0_24 ,Toggle direction pin PIO0_24" "No effect,Toggle" bitfld.long 0x00 23. " DIRNOTP0_23 ,Toggle direction pin PIO0_23" "No effect,Toggle" bitfld.long 0x00 22. " DIRNOTP0_22 ,Toggle direction pin PIO0_22" "No effect,Toggle" bitfld.long 0x00 21. " DIRNOTP0_21 ,Toggle direction pin PIO0_21" "No effect,Toggle" textline " " bitfld.long 0x00 20. " DIRNOTP0_20 ,Toggle direction pin PIO0_20" "No effect,Toggle" bitfld.long 0x00 19. " DIRNOTP0_19 ,Toggle direction pin PIO0_19" "No effect,Toggle" bitfld.long 0x00 18. " DIRNOTP0_18 ,Toggle direction pin PIO0_18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " DIRNOTP0_17 ,Toggle direction pin PIO0_17" "No effect,Toggle" bitfld.long 0x00 16. " DIRNOTP0_16 ,Toggle direction pin PIO0_16" "No effect,Toggle" bitfld.long 0x00 15. " DIRNOTP0_15 ,Toggle direction pin PIO0_15" "No effect,Toggle" bitfld.long 0x00 14. " DIRNOTP0_14 ,Toggle direction pin PIO0_14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " DIRNOTP0_13 ,Toggle direction pin PIO0_13" "No effect,Toggle" bitfld.long 0x00 12. " DIRNOTP0_12 ,Toggle direction pin PIO0_12" "No effect,Toggle" bitfld.long 0x00 11. " DIRNOTP0_11 ,Toggle direction pin PIO0_11" "No effect,Toggle" bitfld.long 0x00 10. " DIRNOTP0_10 ,Toggle direction pin PIO0_10" "No effect,Toggle" textline " " bitfld.long 0x00 9. " DIRNOTP0_9 ,Toggle direction pin PIO0_9" "No effect,Toggle" bitfld.long 0x00 8. " DIRNOTP0_8 ,Toggle direction pin PIO0_8" "No effect,Toggle" bitfld.long 0x00 7. " DIRNOTP0_7 ,Toggle direction pin PIO0_7" "No effect,Toggle" bitfld.long 0x00 6. " DIRNOTP0_6 ,Toggle direction pin PIO0_6" "No effect,Toggle" textline " " bitfld.long 0x00 5. " DIRNOTP0_5 ,Toggle direction pin PIO0_5" "No effect,Toggle" bitfld.long 0x00 4. " DIRNOTP0_4 ,Toggle direction pin PIO0_4" "No effect,Toggle" bitfld.long 0x00 3. " DIRNOTP0_3 ,Toggle direction pin PIO0_3" "No effect,Toggle" bitfld.long 0x00 2. " DIRNOTP0_2 ,Toggle direction pin PIO0_2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " DIRNOTP0_1 ,Toggle direction pin PIO0_1" "No effect,Toggle" bitfld.long 0x00 0. " DIRNOTP0_0 ,Toggle direction pin PIO0_0" "No effect,Toggle" endif width 0x0B endif tree.end sif !cpuis("LPC8N04") tree.open "Pin Interrupts/Pattern Match Engine" base ad:0xA0004000 width 7. tree "Pin interrupts" sif (cpuis("LPC81*")||cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x00++0x03 line.long 0x00 "ISEL,Pin Interrupt Mode Register" bitfld.long 0x00 7. " PMODE[7] ,Pin interrupt sensing mode select for PINTSEL[7]" "Edge,Level" bitfld.long 0x00 6. " [6] ,Pin interrupt sensing mode select for PINTSEL[6]" "Edge,Level" bitfld.long 0x00 5. " [5] ,Pin interrupt sensing mode select for PINTSEL[5]" "Edge,Level" bitfld.long 0x00 4. " [4] ,Pin interrupt sensing mode select for PINTSEL[4]" "Edge,Level" textline " " bitfld.long 0x00 3. " [3] ,Pin interrupt sensing mode select for PINTSEL[3]" "Edge,Level" bitfld.long 0x00 2. " [2] ,Pin interrupt sensing mode select for PINTSEL[2]" "Edge,Level" bitfld.long 0x00 1. " [1] ,Pin interrupt sensing mode select for PINTSEL[1]" "Edge,Level" bitfld.long 0x00 0. " [0] ,Pin interrupt sensing mode select for PINTSEL[0]" "Edge,Level" else group.long 0x00++0x03 line.long 0x00 "PMODE,Pin Interrupt Sensing Mode Select" bitfld.long 0x00 7. " PMODE[7] ,Pin interrupt sensing mode select for PINTSEL[7]" "Edge,Level" bitfld.long 0x00 6. " PMODE[6] ,Pin interrupt sensing mode select for PINTSEL[6]" "Edge,Level" bitfld.long 0x00 5. " PMODE[5] ,Pin interrupt sensing mode select for PINTSEL[5]" "Edge,Level" bitfld.long 0x00 4. " PMODE[4] ,Pin interrupt sensing mode select for PINTSEL[4]" "Edge,Level" textline " " bitfld.long 0x00 3. " PMODE[3] ,Pin interrupt sensing mode select for PINTSEL[3]" "Edge,Level" bitfld.long 0x00 2. " PMODE[2] ,Pin interrupt sensing mode select for PINTSEL[2]" "Edge,Level" bitfld.long 0x00 1. " PMODE[1] ,Pin interrupt sensing mode select for PINTSEL[1]" "Edge,Level" bitfld.long 0x00 0. " PMODE[0] ,Pin interrupt sensing mode select for PINTSEL[0]" "Edge,Level" endif group.long 0x04++0x03 line.long 0x00 "IENR,Pin Level Or Rising Edge Interrupt Enable Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENRL[7]_set/clr ,PINTSEL[7] pin level or rising edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6]_set/clr ,PINTSEL[6] pin level or rising edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5]_set/clr ,PINTSEL[5] pin level or rising edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4]_set/clr ,PINTSEL[4] pin level or rising edge interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3]_set/clr ,PINTSEL[3] pin level or rising edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2]_set/clr ,PINTSEL[2] pin level or rising edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1]_set/clr ,PINTSEL[1] pin level or rising edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0]_set/clr ,PINTSEL[0] pin level or rising edge interrupt enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "IENF,Pin Level Or Falling Edge Interrupt Enable Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENAF[7]_set/clr ,PINTSEL[7] pin level or falling edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6]_set/clr ,PINTSEL[6] pin level or falling edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5]_set/clr ,PINTSEL[5] pin level or falling edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4]_set/clr ,PINTSEL[4] pin level or falling edge interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3]_set/clr ,PINTSEL[3] pin level or falling edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2]_set/clr ,PINTSEL[2] pin level or falling edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1]_set/clr ,PINTSEL[1] pin level or falling edge interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0]_set/clr ,PINTSEL[0] pin level or falling edge interrupt enable" "Disabled,Enabled" group.long 0x1C++0x0B line.long 0x00 "RISE,Pin Interrupt Rising Edge Register" eventfld.long 0x00 7. " RDET[7] ,PINTSEL[7] pin rising edge detected" "Not detected,Detected" eventfld.long 0x00 6. " [6] ,PINTSEL[6] pin rising edge detected" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,PINTSEL[5] pin rising edge detected" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,PINTSEL[4] pin rising edge detected" "Not detected,Detected" textline " " eventfld.long 0x00 3. " [3] ,PINTSEL[3] pin rising edge detected" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,PINTSEL[2] pin rising edge detected" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,PINTSEL[1] pin rising edge detected" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,PINTSEL[0] pin rising edge detected" "Not detected,Detected" line.long 0x04 "FALL,Pin Interrupt Falling Edge Register" eventfld.long 0x04 7. " FDET[7] ,PINTSEL[7] pin falling edge detected" "Not detected,Detected" eventfld.long 0x04 6. " [6] ,PINTSEL[6] pin falling edge detected" "Not detected,Detected" eventfld.long 0x04 5. " [5] ,PINTSEL[5] pin falling edge detected" "Not detected,Detected" eventfld.long 0x04 4. " [4] ,PINTSEL[4] pin falling edge detected" "Not detected,Detected" textline " " eventfld.long 0x04 3. " [3] ,PINTSEL[3] pin falling edge detected" "Not detected,Detected" eventfld.long 0x04 2. " [2] ,PINTSEL[2] pin falling edge detected" "Not detected,Detected" eventfld.long 0x04 1. " [1] ,PINTSEL[1] pin falling edge detected" "Not detected,Detected" eventfld.long 0x04 0. " [0] ,PINTSEL[0] pin falling edge detected" "Not detected,Detected" line.long 0x08 "IST,Pin Interrupt Status Register" eventfld.long 0x08 7. " PSTAT[7] ,PINTSEL[7] pin interrupt status" "Not requested,Requested" eventfld.long 0x08 6. " [6] ,PINTSEL[6] pin interrupt status" "Not requested,Requested" eventfld.long 0x08 5. " [5] ,PINTSEL[5] pin interrupt status" "Not requested,Requested" eventfld.long 0x08 4. " [4] ,PINTSEL[4] pin interrupt status" "Not requested,Requested" textline " " eventfld.long 0x08 3. " [3] ,PINTSEL[3] pin interrupt status" "Not requested,Requested" eventfld.long 0x08 2. " [2] ,PINTSEL[2] pin interrupt status" "Not requested,Requested" eventfld.long 0x08 1. " [1] ,PINTSEL[1] pin interrupt status" "Not requested,Requested" eventfld.long 0x08 0. " [0] ,PINTSEL[0] pin interrupt status" "Not requested,Requested" tree.end tree "Pattern matching" group.long 0x28++0x0B line.long 0x00 "PMCTRL,Pattern Match Interrupt Control Register" hexmask.long.byte 0x00 24.--31. 1. " PMAT ,Pattern matching current state" bitfld.long 0x00 1. " ENA_RXEV ,RXEV output to CPU/GPIO enable" "Disabled,Enabled" bitfld.long 0x00 0. " SEL_PMATCH ,Pin interrupt/Pattern match interrupt select" "Pin interrupt,Pattern match" line.long 0x04 "PMSRC,Pattern Match Bit-slice Source Register" bitfld.long 0x04 29.--31. " SRC7 ,Input source for bit slice 7" "0,1,2,3,4,5,6,7" bitfld.long 0x04 26.--28. " SRC6 ,Input source for bit slice 6" "0,1,2,3,4,5,6,7" bitfld.long 0x04 23.--25. " SRC5 ,Input source for bit slice 5" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " SRC4 ,Input source for bit slice 4" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 17.--19. " SRC3 ,Input source for bit slice 3" "0,1,2,3,4,5,6,7" bitfld.long 0x04 14.--16. " SRC2 ,Input source for bit slice 2" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11.--13. " SRC1 ,Input source for bit slice 1" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " SRC0 ,Input source for bit slice 0" "0,1,2,3,4,5,6,7" line.long 0x08 "PMCFG,Pattern Match Bit-slice Configuration Register" bitfld.long 0x08 29.--31. " CFG7 ,Match contribution condition for bit slice 7" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" bitfld.long 0x08 26.--28. " CFG6 ,Match contribution condition for bit slice 6" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" bitfld.long 0x08 23.--25. " CFG5 ,Match contribution condition for bit slice 5" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" textline " " bitfld.long 0x08 20.--22. " CFG4 ,Match contribution condition for bit slice 4" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" bitfld.long 0x08 17.--19. " CFG3 ,Match contribution condition for bit slice 3" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" bitfld.long 0x08 14.--16. " CFG2 ,Match contribution condition for bit slice 2" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" textline " " bitfld.long 0x08 11.--13. " CFG1 ,Match contribution condition for bit slice 1" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" bitfld.long 0x08 8.--10. " CFG0 ,Match contribution condition for bit slice 0" "Constant HIGH,Sticky rising edge,Sticky falling edge,Sticky rising/falling edge,High level,Low level,Constant 0,Non-sticky rising/falling edge" bitfld.long 0x08 6. " PROD_ENDPTS6 ,Determines whether slice 6 is an endpoint" "No effect,Endpoint" textline " " bitfld.long 0x08 5. " PROD_ENDPTS5 ,Determines whether slice 5 is an endpoint" "No effect,Endpoint" bitfld.long 0x08 4. " PROD_ENDPTS4 ,Determines whether slice 4 is an endpoint" "No effect,Endpoint" bitfld.long 0x08 3. " PROD_ENDPTS3 ,Determines whether slice 3 is an endpoint" "No effect,Endpoint" textline " " bitfld.long 0x08 2. " PROD_ENDPTS2 ,Determines whether slice 2 is an endpoint" "No effect,Endpoint" bitfld.long 0x08 1. " PROD_ENDPTS1 ,Determines whether slice 1 is an endpoint" "No effect,Endpoint" bitfld.long 0x08 0. " PROD_ENDPTS0 ,Determines whether slice 0 is an endpoint" "No effect,Endpoint" tree.end width 0x0B tree.end endif sif (cpuis("LPC82*")) tree "INPUT MUX/DMA TRIGMUX (Input Multiplexing and DMA Trigger Multiplexing)" base ad:0x40028000 width 20. tree "DMA Input Trigger Registers 0 - 17" group.long 0x0++0x03 line.long 0x00 "DMA_ITRIG_INMUX_0,DMA Input Trigger Input Mux Register 0" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 0" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x4++0x03 line.long 0x00 "DMA_ITRIG_INMUX_1,DMA Input Trigger Input Mux Register 1" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 1" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x8++0x03 line.long 0x00 "DMA_ITRIG_INMUX_2,DMA Input Trigger Input Mux Register 2" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 2" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0xC++0x03 line.long 0x00 "DMA_ITRIG_INMUX_3,DMA Input Trigger Input Mux Register 3" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 3" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x10++0x03 line.long 0x00 "DMA_ITRIG_INMUX_4,DMA Input Trigger Input Mux Register 4" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 4" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x14++0x03 line.long 0x00 "DMA_ITRIG_INMUX_5,DMA Input Trigger Input Mux Register 5" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 5" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x18++0x03 line.long 0x00 "DMA_ITRIG_INMUX_6,DMA Input Trigger Input Mux Register 6" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 6" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x1C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_7,DMA Input Trigger Input Mux Register 7" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 7" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x20++0x03 line.long 0x00 "DMA_ITRIG_INMUX_8,DMA Input Trigger Input Mux Register 8" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 8" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x24++0x03 line.long 0x00 "DMA_ITRIG_INMUX_9,DMA Input Trigger Input Mux Register 9" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 9" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x28++0x03 line.long 0x00 "DMA_ITRIG_INMUX_10,DMA Input Trigger Input Mux Register 10" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 10" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x2C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_11,DMA Input Trigger Input Mux Register 11" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 11" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x30++0x03 line.long 0x00 "DMA_ITRIG_INMUX_12,DMA Input Trigger Input Mux Register 12" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 12" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x34++0x03 line.long 0x00 "DMA_ITRIG_INMUX_13,DMA Input Trigger Input Mux Register 13" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 13" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x38++0x03 line.long 0x00 "DMA_ITRIG_INMUX_14,DMA Input Trigger Input Mux Register 14" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 14" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x3C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_15,DMA Input Trigger Input Mux Register 15" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 15" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x40++0x03 line.long 0x00 "DMA_ITRIG_INMUX_16,DMA Input Trigger Input Mux Register 16" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 16" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x44++0x03 line.long 0x00 "DMA_ITRIG_INMUX_17,DMA Input Trigger Input Mux Register 17" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 17" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." tree.end textline "" group.long 0x4000++0x07 line.long 0x00 "DMA_INMUX_INMUX_0,Input Mux Register For DMA Trigger Input 20" bitfld.long 0x00 0.--4. " INP ,DMA trigger output number for DMA channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_INMUX_INMUX_1,Input Mux Register For DMA Trigger Input 21" bitfld.long 0x04 0.--4. " INP ,DMA trigger output number for DMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4020++0x0F line.long 0x00 "SCT0_INMUX_0,Input Mux Register For SCT Input 0" bitfld.long 0x00 0.--3. " INP_N ,Input number to SCT0 input 0" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x04 "SCT0_INMUX_1,Input Mux Register For SCT Input 1" bitfld.long 0x04 0.--3. " INP_N ,Input number to SCT0 input 1" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x08 "SCT0_INMUX_2,Input Mux Register For SCT Input 2" bitfld.long 0x08 0.--3. " INP_N ,Input number to SCT0 input 2" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x0C "SCT0_INMUX_3,Input Mux Register For SCT Input 3" bitfld.long 0x0C 0.--3. " INP_N ,Input number to SCT0 input 3" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,ARM_TXEV,DEBUG_HALTED,?..." width 0x0B tree.end elif (cpuis("LPC84*")) tree "INPUT MUX/DMA TRIGMUX (Input Multiplexing and DMA Trigger Multiplexing)" base ad:0x4002C000 width 20. group.long 0x00++0x07 line.long 0x00 "DMA_INMUX_INMUX_0,Input Mux Register For DMA Trigger Input 20" bitfld.long 0x00 0.--4. " INP ,DMA trigger output number for DMA channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." line.long 0x04 "DMA_INMUX_INMUX_1,Input Mux Register For DMA Trigger Input 21" bitfld.long 0x04 0.--4. " INP ,DMA trigger output number for DMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." group.long 0x20++0x0F line.long 0x00 "SCT0_INMUX_0,Input Mux Register For SCT Input 0" bitfld.long 0x00 0.--3. " INP_N ,Input number to SCT0 input 0" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,T0_MAT2,GPIOINT_BMATCH,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x04 "SCT0_INMUX_1,Input Mux Register For SCT Input 1" bitfld.long 0x04 0.--3. " INP_N ,Input number to SCT0 input 1" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,T0_MAT2,GPIOINT_BMATCH,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x08 "SCT0_INMUX_2,Input Mux Register For SCT Input 2" bitfld.long 0x08 0.--3. " INP_N ,Input number to SCT0 input 2" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,T0_MAT2,GPIOINT_BMATCH,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x0C "SCT0_INMUX_3,Input Mux Register For SCT Input 3" bitfld.long 0x0C 0.--3. " INP_N ,Input number to SCT0 input 3" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,ACMP_O,T0_MAT2,GPIOINT_BMATCH,ARM_TXEV,DEBUG_HALTED,?..." textline "" tree "DMA Input Trigger Registers 0 - 17" group.long 0x40++0x03 line.long 0x00 "DMA_ITRIG_INMUX_0,DMA Input Trigger Input Mux Register 0" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 0" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x44++0x03 line.long 0x00 "DMA_ITRIG_INMUX_1,DMA Input Trigger Input Mux Register 1" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 1" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x48++0x03 line.long 0x00 "DMA_ITRIG_INMUX_2,DMA Input Trigger Input Mux Register 2" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 2" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x4C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_3,DMA Input Trigger Input Mux Register 3" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 3" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x50++0x03 line.long 0x00 "DMA_ITRIG_INMUX_4,DMA Input Trigger Input Mux Register 4" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 4" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x54++0x03 line.long 0x00 "DMA_ITRIG_INMUX_5,DMA Input Trigger Input Mux Register 5" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 5" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x58++0x03 line.long 0x00 "DMA_ITRIG_INMUX_6,DMA Input Trigger Input Mux Register 6" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 6" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x5C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_7,DMA Input Trigger Input Mux Register 7" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 7" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x60++0x03 line.long 0x00 "DMA_ITRIG_INMUX_8,DMA Input Trigger Input Mux Register 8" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 8" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x64++0x03 line.long 0x00 "DMA_ITRIG_INMUX_9,DMA Input Trigger Input Mux Register 9" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 9" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x68++0x03 line.long 0x00 "DMA_ITRIG_INMUX_10,DMA Input Trigger Input Mux Register 10" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 10" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x6C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_11,DMA Input Trigger Input Mux Register 11" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 11" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x70++0x03 line.long 0x00 "DMA_ITRIG_INMUX_12,DMA Input Trigger Input Mux Register 12" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 12" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x74++0x03 line.long 0x00 "DMA_ITRIG_INMUX_13,DMA Input Trigger Input Mux Register 13" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 13" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x78++0x03 line.long 0x00 "DMA_ITRIG_INMUX_14,DMA Input Trigger Input Mux Register 14" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 14" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x7C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_15,DMA Input Trigger Input Mux Register 15" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 15" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x80++0x03 line.long 0x00 "DMA_ITRIG_INMUX_16,DMA Input Trigger Input Mux Register 16" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 16" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x84++0x03 line.long 0x00 "DMA_ITRIG_INMUX_17,DMA Input Trigger Input Mux Register 17" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 17" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x88++0x03 line.long 0x00 "DMA_ITRIG_INMUX_18,DMA Input Trigger Input Mux Register 18" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 18" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x8C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_19,DMA Input Trigger Input Mux Register 19" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 19" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x90++0x03 line.long 0x00 "DMA_ITRIG_INMUX_20,DMA Input Trigger Input Mux Register 20" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 20" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x94++0x03 line.long 0x00 "DMA_ITRIG_INMUX_21,DMA Input Trigger Input Mux Register 21" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 21" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x98++0x03 line.long 0x00 "DMA_ITRIG_INMUX_22,DMA Input Trigger Input Mux Register 22" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 22" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x9C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_23,DMA Input Trigger Input Mux Register 23" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 23" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0xA0++0x03 line.long 0x00 "DMA_ITRIG_INMUX_24,DMA Input Trigger Input Mux Register 24" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 24" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,ACMP_O,PININT4,PININT5,PININT6,PININT7,T0_DMAREQ_M0,T0_DMAREQ_M1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." tree.end width 0x0B tree.end elif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") tree "INPUT MUX/DMA TRIGMUX (Input Multiplexing and DMA Trigger Multiplexing)" base ad:0x40028000 width 20. tree "DMA Input Trigger Registers 0 - 17" group.long 0x0++0x03 line.long 0x00 "DMA_ITRIG_INMUX_0,DMA Input Trigger Input Mux Register 0" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 0" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x4++0x03 line.long 0x00 "DMA_ITRIG_INMUX_1,DMA Input Trigger Input Mux Register 1" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 1" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x8++0x03 line.long 0x00 "DMA_ITRIG_INMUX_2,DMA Input Trigger Input Mux Register 2" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 2" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0xC++0x03 line.long 0x00 "DMA_ITRIG_INMUX_3,DMA Input Trigger Input Mux Register 3" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 3" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x10++0x03 line.long 0x00 "DMA_ITRIG_INMUX_4,DMA Input Trigger Input Mux Register 4" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 4" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x14++0x03 line.long 0x00 "DMA_ITRIG_INMUX_5,DMA Input Trigger Input Mux Register 5" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 5" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x18++0x03 line.long 0x00 "DMA_ITRIG_INMUX_6,DMA Input Trigger Input Mux Register 6" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 6" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x1C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_7,DMA Input Trigger Input Mux Register 7" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 7" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x20++0x03 line.long 0x00 "DMA_ITRIG_INMUX_8,DMA Input Trigger Input Mux Register 8" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 8" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x24++0x03 line.long 0x00 "DMA_ITRIG_INMUX_9,DMA Input Trigger Input Mux Register 9" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 9" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x28++0x03 line.long 0x00 "DMA_ITRIG_INMUX_10,DMA Input Trigger Input Mux Register 10" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 10" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x2C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_11,DMA Input Trigger Input Mux Register 11" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 11" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x30++0x03 line.long 0x00 "DMA_ITRIG_INMUX_12,DMA Input Trigger Input Mux Register 12" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 12" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x34++0x03 line.long 0x00 "DMA_ITRIG_INMUX_13,DMA Input Trigger Input Mux Register 13" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 13" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x38++0x03 line.long 0x00 "DMA_ITRIG_INMUX_14,DMA Input Trigger Input Mux Register 14" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 14" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x3C++0x03 line.long 0x00 "DMA_ITRIG_INMUX_15,DMA Input Trigger Input Mux Register 15" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 15" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x40++0x03 line.long 0x00 "DMA_ITRIG_INMUX_16,DMA Input Trigger Input Mux Register 16" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 16" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." group.long 0x44++0x03 line.long 0x00 "DMA_ITRIG_INMUX_17,DMA Input Trigger Input Mux Register 17" bitfld.long 0x00 0.--3. " INP ,Trigger input number for DMA channel 17" "ADC_SEQA_IRQ,ADC_SEQB_IRQ,SCT_DMA0,SCT_DMA1,,PININT0,PININT1,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,?..." tree.end textline "" group.long 0x4000++0x07 line.long 0x00 "DMA_INMUX_INMUX_0,Input Mux Register For DMA Trigger Input 20" bitfld.long 0x00 0.--4. " INP ,DMA trigger output number for DMA channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..." line.long 0x04 "DMA_INMUX_INMUX_1,Input Mux Register For DMA Trigger Input 21" bitfld.long 0x04 0.--4. " INP ,DMA trigger output number for DMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..." group.long 0x4020++0x0F line.long 0x00 "SCT0_INMUX_0,Input Mux Register For SCT Input 0" bitfld.long 0x00 0.--3. " INP_N ,Input number to SCT0 input 0" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x04 "SCT0_INMUX_1,Input Mux Register For SCT Input 1" bitfld.long 0x04 0.--3. " INP_N ,Input number to SCT0 input 1" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x08 "SCT0_INMUX_2,Input Mux Register For SCT Input 2" bitfld.long 0x08 0.--3. " INP_N ,Input number to SCT0 input 2" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,,ARM_TXEV,DEBUG_HALTED,?..." line.long 0x0C "SCT0_INMUX_3,Input Mux Register For SCT Input 3" bitfld.long 0x0C 0.--3. " INP_N ,Input number to SCT0 input 3" "SCT_PIN0,SCT_PIN1,SCT_PIN2,SCT_PIN3,ADC_THCMP_IRQ,,ARM_TXEV,DEBUG_HALTED,?..." width 0x0B tree.end endif sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) tree "DMA (DMA Controller)" base ad:0x50008000 width 17. tree "Global Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 0. " ENABLE ,DMA controller master enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. " ACTIVEINT ,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "Not pending,Pending" bitfld.long 0x00 2. " ACTIVEERRINT ,Summarizes whether any error interrupts are pending" "Not pending,Pending" group.long 0x08++0x03 line.long 0x00 "SRAMBASE,SRAM Base Address Register" hexmask.long.tbyte 0x00 9.--31. 0x2 " OFFSET ,Address bits 31:9 of the beginning of the DMA descriptor table" tree.end tree "Shared registers" group.long 0x30++0x03 line.long 0x00 "ENABLE0_set/clr,Channel Enable Read And Set For All DMA Channel" sif (cpuis("LPC84*")) setclrfld.long 0x00 24. -0x10 24. -0x08 24. " ENA[24]_set/clr ,DMA channel 24 enable" "Disabled,Enabled" setclrfld.long 0x00 23. -0x10 23. -0x08 23. " ENA[23]_set/clr ,DMA channel 23 enable" "Disabled,Enabled" setclrfld.long 0x00 22. -0x10 22. -0x08 22. " ENA[22]_set/clr ,DMA channel 22 enable" "Disabled,Enabled" setclrfld.long 0x00 21. -0x10 21. -0x08 21. " ENA[21]_set/clr ,DMA channel 21 enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. -0x10 20. -0x08 20. " ENA[20]_set/clr ,DMA channel 20 enable" "Disabled,Enabled" setclrfld.long 0x00 19. -0x10 19. -0x08 19. " ENA[19]_set/clr ,DMA channel 19 enable" "Disabled,Enabled" setclrfld.long 0x00 18. -0x10 18. -0x08 18. " ENA[18]_set/clr ,DMA channel 18 enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 17. -0x10 17. -0x08 17. " ENA[17]_set/clr ,DMA channel 17 enable" "Disabled,Enabled" setclrfld.long 0x00 16. -0x10 16. -0x08 16. " ENA[16]_set/clr ,DMA channel 16 enable" "Disabled,Enabled" setclrfld.long 0x00 15. -0x10 15. -0x08 15. " ENA[15]_set/clr ,DMA channel 15 enable" "Disabled,Enabled" setclrfld.long 0x00 14. -0x10 14. -0x08 14. " ENA[14]_set/clr ,DMA channel 14 enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x10 13. -0x08 13. " ENA[13]_set/clr ,DMA channel 13 enable" "Disabled,Enabled" setclrfld.long 0x00 12. -0x10 12. -0x08 12. " ENA[12]_set/clr ,DMA channel 12 enable" "Disabled,Enabled" setclrfld.long 0x00 11. -0x10 11. -0x08 11. " ENA[11]_set/clr ,DMA channel 11 enable" "Disabled,Enabled" setclrfld.long 0x00 10. -0x10 10. -0x08 10. " ENA[10]_set/clr ,DMA channel 10 enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x10 9. -0x08 9. " ENA[9]_set/clr ,DMA channel 9 enable" "Disabled,Enabled" setclrfld.long 0x00 8. -0x10 8. -0x08 8. " ENA[8]_set/clr ,DMA channel 8 enable" "Disabled,Enabled" setclrfld.long 0x00 7. -0x10 7. -0x08 7. " ENA[7]_set/clr ,DMA channel 7 enable" "Disabled,Enabled" setclrfld.long 0x00 6. -0x10 6. -0x08 6. " ENA[6]_set/clr ,DMA channel 6 enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x10 5. -0x08 5. " ENA[5]_set/clr ,DMA channel 5 enable" "Disabled,Enabled" setclrfld.long 0x00 4. -0x10 4. -0x08 4. " ENA[4]_set/clr ,DMA channel 4 enable" "Disabled,Enabled" setclrfld.long 0x00 3. -0x10 3. -0x08 3. " ENA[3]_set/clr ,DMA channel 3 enable" "Disabled,Enabled" setclrfld.long 0x00 2. -0x10 2. -0x08 2. " ENA[2]_set/clr ,DMA channel 2 enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x10 1. -0x08 1. " ENA[1]_set/clr ,DMA channel 1 enable" "Disabled,Enabled" setclrfld.long 0x00 0. -0x10 0. -0x08 0. " ENA[0]_set/clr ,DMA channel 0 enable" "Disabled,Enabled" rgroup.long 0x38++0x03 line.long 0x00 "BUSY_0,Busy Status Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " BSY[24] ,DMA channel 24 busy flag" "Not busy,Busy" bitfld.long 0x00 23. " BSY[23] ,DMA channel 23 busy flag" "Not busy,Busy" bitfld.long 0x00 22. " BSY[22] ,DMA channel 22 busy flag" "Not busy,Busy" bitfld.long 0x00 21. " BSY[21] ,DMA channel 21 busy flag" "Not busy,Busy" textline " " bitfld.long 0x00 20. " BSY[20] ,DMA channel 20 busy flag" "Not busy,Busy" bitfld.long 0x00 19. " BSY[19] ,DMA channel 19 busy flag" "Not busy,Busy" bitfld.long 0x00 18. " BSY[18] ,DMA channel 18 busy flag" "Not busy,Busy" textline " " endif bitfld.long 0x00 17. " BSY[17] ,DMA channel 17 busy flag" "Not busy,Busy" bitfld.long 0x00 16. " BSY[16] ,DMA channel 16 busy flag" "Not busy,Busy" bitfld.long 0x00 15. " BSY[15] ,DMA channel 15 busy flag" "Not busy,Busy" bitfld.long 0x00 14. " BSY[14] ,DMA channel 14 busy flag" "Not busy,Busy" textline " " bitfld.long 0x00 13. " BSY[13] ,DMA channel 13 busy flag" "Not busy,Busy" bitfld.long 0x00 12. " BSY[12] ,DMA channel 12 busy flag" "Not busy,Busy" bitfld.long 0x00 11. " BSY[11] ,DMA channel 11 busy flag" "Not busy,Busy" bitfld.long 0x00 10. " BSY[10] ,DMA channel 10 busy flag" "Not busy,Busy" textline " " bitfld.long 0x00 9. " BSY[9] ,DMA channel 9 busy flag" "Not busy,Busy" bitfld.long 0x00 8. " BSY[8] ,DMA channel 8 busy flag" "Not busy,Busy" bitfld.long 0x00 7. " BSY[7] ,DMA channel 7 busy flag" "Not busy,Busy" bitfld.long 0x00 6. " BSY[6] ,DMA channel 6 busy flag" "Not busy,Busy" textline " " bitfld.long 0x00 5. " BSY[5] ,DMA channel 5 busy flag" "Not busy,Busy" bitfld.long 0x00 4. " BSY[4] ,DMA channel 4 busy flag" "Not busy,Busy" bitfld.long 0x00 3. " BSY[3] ,DMA channel 3 busy flag" "Not busy,Busy" bitfld.long 0x00 2. " BSY[2] ,DMA channel 2 busy flag" "Not busy,Busy" textline " " bitfld.long 0x00 1. " BSY[1] ,DMA channel 1 busy flag" "Not busy,Busy" bitfld.long 0x00 0. " BSY[0] ,DMA channel 0 busy flag" "Not busy,Busy" group.long 0x40++0x03 line.long 0x00 "ERRINT_0,Error Interrupt Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " ERR[24] ,DMA channel 24 error flag" "No effect,Error" bitfld.long 0x00 23. " ERR[23] ,DMA channel 23 error flag" "No effect,Error" bitfld.long 0x00 22. " ERR[22] ,DMA channel 22 error flag" "No effect,Error" bitfld.long 0x00 21. " ERR[21] ,DMA channel 21 error flag" "No effect,Error" textline " " bitfld.long 0x00 20. " ERR[20] ,DMA channel 20 error flag" "No effect,Error" bitfld.long 0x00 19. " ERR[19] ,DMA channel 19 error flag" "No effect,Error" bitfld.long 0x00 18. " ERR[18] ,DMA channel 18 error flag" "No effect,Error" textline " " endif bitfld.long 0x00 17. " ERR[17] ,DMA channel 17 error flag" "No effect,Error" bitfld.long 0x00 16. " ERR[16] ,DMA channel 16 error flag" "No effect,Error" bitfld.long 0x00 15. " ERR[15] ,DMA channel 15 error flag" "No effect,Error" bitfld.long 0x00 14. " ERR[14] ,DMA channel 14 error flag" "No effect,Error" textline " " bitfld.long 0x00 13. " ERR[13] ,DMA channel 13 error flag" "No effect,Error" bitfld.long 0x00 12. " ERR[12] ,DMA channel 12 error flag" "No effect,Error" bitfld.long 0x00 11. " ERR[11] ,DMA channel 11 error flag" "No effect,Error" bitfld.long 0x00 10. " ERR[10] ,DMA channel 10 error flag" "No effect,Error" textline " " bitfld.long 0x00 9. " ERR[9] ,DMA channel 9 error flag" "No effect,Error" bitfld.long 0x00 8. " ERR[8] ,DMA channel 8 error flag" "No effect,Error" bitfld.long 0x00 7. " ERR[7] ,DMA channel 7 error flag" "No effect,Error" bitfld.long 0x00 6. " ERR[6] ,DMA channel 6 error flag" "No effect,Error" textline " " bitfld.long 0x00 5. " ERR[5] ,DMA channel 5 error flag" "No effect,Error" bitfld.long 0x00 4. " ERR[4] ,DMA channel 4 error flag" "No effect,Error" bitfld.long 0x00 3. " ERR[3] ,DMA channel 3 error flag" "No effect,Error" bitfld.long 0x00 2. " ERR[2] ,DMA channel 2 error flag" "No effect,Error" textline " " bitfld.long 0x00 1. " ERR[1] ,DMA channel 1 error flag" "No effect,Error" bitfld.long 0x00 0. " ERR[0] ,DMA channel 0 error flag" "No effect,Error" group.long 0x48++0x03 line.long 0x00 "INTENSET_0,Interrupt Enable Read And Set Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " INTEN[24] ,Interrupt Enable read and set for DMA channel 24" "Disabled,Enabled" bitfld.long 0x00 23. " INTEN[23] ,Interrupt Enable read and set for DMA channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTEN[22] ,Interrupt Enable read and set for DMA channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTEN[21] ,Interrupt Enable read and set for DMA channel 21" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " INTEN[20] ,Interrupt Enable read and set for DMA channel 20" "Disabled,Enabled" bitfld.long 0x00 19. " INTEN[19] ,Interrupt Enable read and set for DMA channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTEN[18] ,Interrupt Enable read and set for DMA channel 18" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " INTEN[17] ,Interrupt Enable read and set for DMA channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTEN[16] ,Interrupt Enable read and set for DMA channel 16" "Disabled,Enabled" bitfld.long 0x00 15. " INTEN[15] ,Interrupt Enable read and set for DMA channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTEN[14] ,Interrupt Enable read and set for DMA channel 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " INTEN[13] ,Interrupt Enable read and set for DMA channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTEN[12] ,Interrupt Enable read and set for DMA channel 12" "Disabled,Enabled" bitfld.long 0x00 11. " INTEN[11] ,Interrupt Enable read and set for DMA channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTEN[10] ,Interrupt Enable read and set for DMA channel 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " INTEN[9] ,Interrupt Enable read and set for DMA channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTEN[8] ,Interrupt Enable read and set for DMA channel 8" "Disabled,Enabled" bitfld.long 0x00 7. " INTEN[7] ,Interrupt Enable read and set for DMA channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTEN[6] ,Interrupt Enable read and set for DMA channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " INTEN[5] ,Interrupt Enable read and set for DMA channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTEN[4] ,Interrupt Enable read and set for DMA channel 4" "Disabled,Enabled" bitfld.long 0x00 3. " INTEN[3] ,Interrupt Enable read and set for DMA channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTEN[2] ,Interrupt Enable read and set for DMA channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " INTEN[1] ,Interrupt Enable read and set for DMA channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN[0] ,Interrupt Enable read and set for DMA channel 0" "Disabled,Enabled" wgroup.long 0x50++0x03 line.long 0x00 "INTENCLR_0,Interrupt Enable Clear Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " CLR[24] ,Clear INTEN[24]" "No effect,Clear" bitfld.long 0x00 23. " CLR[23] ,Clear INTEN[23]" "No effect,Clear" bitfld.long 0x00 22. " CLR[22] ,Clear INTEN[22]" "No effect,Clear" bitfld.long 0x00 21. " CLR[21] ,Clear INTEN[21]" "No effect,Clear" textline " " bitfld.long 0x00 20. " CLR[20] ,Clear INTEN[20]" "No effect,Clear" bitfld.long 0x00 19. " CLR[19] ,Clear INTEN[19]" "No effect,Clear" bitfld.long 0x00 18. " CLR[18] ,Clear INTEN[18]" "No effect,Clear" textline " " endif bitfld.long 0x00 17. " CLR[17] ,Clear INTEN[17]" "No effect,Clear" bitfld.long 0x00 16. " CLR[16] ,Clear INTEN[16]" "No effect,Clear" bitfld.long 0x00 15. " CLR[15] ,Clear INTEN[15]" "No effect,Clear" bitfld.long 0x00 14. " CLR[14] ,Clear INTEN[14]" "No effect,Clear" textline " " bitfld.long 0x00 13. " CLR[13] ,Clear INTEN[13]" "No effect,Clear" bitfld.long 0x00 12. " CLR[12] ,Clear INTEN[12]" "No effect,Clear" bitfld.long 0x00 11. " CLR[11] ,Clear INTEN[11]" "No effect,Clear" bitfld.long 0x00 10. " CLR[10] ,Clear INTEN[10]" "No effect,Clear" textline " " bitfld.long 0x00 9. " CLR[9] ,Clear INTEN[9]" "No effect,Clear" bitfld.long 0x00 8. " CLR[8] ,Clear INTEN[8]" "No effect,Clear" bitfld.long 0x00 7. " CLR[7] ,Clear INTEN[7]" "No effect,Clear" bitfld.long 0x00 6. " CLR[6] ,Clear INTEN[6]" "No effect,Clear" textline " " bitfld.long 0x00 5. " CLR[5] ,Clear INTEN[5]" "No effect,Clear" bitfld.long 0x00 4. " CLR[4] ,Clear INTEN[4]" "No effect,Clear" bitfld.long 0x00 3. " CLR[3] ,Clear INTEN[3]" "No effect,Clear" bitfld.long 0x00 2. " CLR[2] ,Clear INTEN[2]" "No effect,Clear" textline " " bitfld.long 0x00 1. " CLR[1] ,Clear INTEN[1]" "No effect,Clear" bitfld.long 0x00 0. " CLR[0] ,Clear INTEN[0]" "No effect,Clear" group.long 0x58++0x03 line.long 0x00 "INTA_0,Interrupt A Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " IA[24] ,Interrupt A status for DMA channel 24" "Not activeted,Activeted" bitfld.long 0x00 23. " IA[23] ,Interrupt A status for DMA channel 23" "Not activeted,Activeted" bitfld.long 0x00 22. " IA[22] ,Interrupt A status for DMA channel 22" "Not activeted,Activeted" bitfld.long 0x00 21. " IA[21] ,Interrupt A status for DMA channel 21" "Not activeted,Activeted" textline " " bitfld.long 0x00 20. " IA[20] ,Interrupt A status for DMA channel 20" "Not activeted,Activeted" bitfld.long 0x00 19. " IA[19] ,Interrupt A status for DMA channel 19" "Not activeted,Activeted" bitfld.long 0x00 18. " IA[18] ,Interrupt A status for DMA channel 18" "Not activeted,Activeted" textline " " endif bitfld.long 0x00 17. " IA[17] ,Interrupt A status for DMA channel 17" "Not activeted,Activeted" bitfld.long 0x00 16. " IA[16] ,Interrupt A status for DMA channel 16" "Not activeted,Activeted" bitfld.long 0x00 15. " IA[15] ,Interrupt A status for DMA channel 15" "Not activeted,Activeted" bitfld.long 0x00 14. " IA[14] ,Interrupt A status for DMA channel 14" "Not activeted,Activeted" textline " " bitfld.long 0x00 13. " IA[13] ,Interrupt A status for DMA channel 13" "Not activeted,Activeted" bitfld.long 0x00 12. " IA[12] ,Interrupt A status for DMA channel 12" "Not activeted,Activeted" bitfld.long 0x00 11. " IA[11] ,Interrupt A status for DMA channel 11" "Not activeted,Activeted" bitfld.long 0x00 10. " IA[10] ,Interrupt A status for DMA channel 10" "Not activeted,Activeted" textline " " bitfld.long 0x00 9. " IA[9] ,Interrupt A status for DMA channel 9" "Not activeted,Activeted" bitfld.long 0x00 8. " IA[8] ,Interrupt A status for DMA channel 8" "Not activeted,Activeted" bitfld.long 0x00 7. " IA[7] ,Interrupt A status for DMA channel 7" "Not activeted,Activeted" bitfld.long 0x00 6. " IA[6] ,Interrupt A status for DMA channel 6" "Not activeted,Activeted" textline " " bitfld.long 0x00 5. " IA[5] ,Interrupt A status for DMA channel 5" "Not activeted,Activeted" bitfld.long 0x00 4. " IA[4] ,Interrupt A status for DMA channel 4" "Not activeted,Activeted" bitfld.long 0x00 3. " IA[3] ,Interrupt A status for DMA channel 3" "Not activeted,Activeted" bitfld.long 0x00 2. " IA[2] ,Interrupt A status for DMA channel 2" "Not activeted,Activeted" textline " " bitfld.long 0x00 1. " IA[1] ,Interrupt A status for DMA channel 1" "Not activeted,Activeted" bitfld.long 0x00 0. " IA[0] ,Interrupt A status for DMA channel 0" "Not activeted,Activeted" group.long 0x60++0x03 line.long 0x00 "INTB_0,Interrupt B Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " IB[24] ,Interrupt B status for DMA channel 24" "Not activeted,Activeted" bitfld.long 0x00 23. " IB[23] ,Interrupt B status for DMA channel 23" "Not activeted,Activeted" bitfld.long 0x00 22. " IB[22] ,Interrupt B status for DMA channel 22" "Not activeted,Activeted" bitfld.long 0x00 21. " IB[21] ,Interrupt B status for DMA channel 21" "Not activeted,Activeted" textline " " bitfld.long 0x00 20. " IB[20] ,Interrupt B status for DMA channel 20" "Not activeted,Activeted" bitfld.long 0x00 19. " IB[19] ,Interrupt B status for DMA channel 19" "Not activeted,Activeted" bitfld.long 0x00 18. " IB[18] ,Interrupt B status for DMA channel 18" "Not activeted,Activeted" textline " " endif bitfld.long 0x00 17. " IB[17] ,Interrupt B status for DMA channel 17" "Not activeted,Activeted" bitfld.long 0x00 16. " IB[16] ,Interrupt B status for DMA channel 16" "Not activeted,Activeted" bitfld.long 0x00 15. " IB[15] ,Interrupt B status for DMA channel 15" "Not activeted,Activeted" bitfld.long 0x00 14. " IB[14] ,Interrupt B status for DMA channel 14" "Not activeted,Activeted" textline " " bitfld.long 0x00 13. " IB[13] ,Interrupt B status for DMA channel 13" "Not activeted,Activeted" bitfld.long 0x00 12. " IB[12] ,Interrupt B status for DMA channel 12" "Not activeted,Activeted" bitfld.long 0x00 11. " IB[11] ,Interrupt B status for DMA channel 11" "Not activeted,Activeted" bitfld.long 0x00 10. " IB[10] ,Interrupt B status for DMA channel 10" "Not activeted,Activeted" textline " " bitfld.long 0x00 9. " IB[9] ,Interrupt B status for DMA channel 9" "Not activeted,Activeted" bitfld.long 0x00 8. " IB[8] ,Interrupt B status for DMA channel 8" "Not activeted,Activeted" bitfld.long 0x00 7. " IB[7] ,Interrupt B status for DMA channel 7" "Not activeted,Activeted" bitfld.long 0x00 6. " IB[6] ,Interrupt B status for DMA channel 6" "Not activeted,Activeted" textline " " bitfld.long 0x00 5. " IB[5] ,Interrupt B status for DMA channel 5" "Not activeted,Activeted" bitfld.long 0x00 4. " IB[4] ,Interrupt B status for DMA channel 4" "Not activeted,Activeted" bitfld.long 0x00 3. " IB[3] ,Interrupt B status for DMA channel 3" "Not activeted,Activeted" bitfld.long 0x00 2. " IB[2] ,Interrupt B status for DMA channel 2" "Not activeted,Activeted" textline " " bitfld.long 0x00 1. " IB[1] ,Interrupt B status for DMA channel 1" "Not activeted,Activeted" bitfld.long 0x00 0. " IB[0] ,Interrupt B status for DMA channel 0" "Not activeted,Activeted" wgroup.long 0x68++0x03 line.long 0x00 "SETVALID_0,Set Valid Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " SV[24] ,SETVALID control for DMA channel 24" "No effect,Set" bitfld.long 0x00 23. " SV[23] ,SETVALID control for DMA channel 23" "No effect,Set" bitfld.long 0x00 22. " SV[22] ,SETVALID control for DMA channel 22" "No effect,Set" bitfld.long 0x00 21. " SV[21] ,SETVALID control for DMA channel 21" "No effect,Set" textline " " bitfld.long 0x00 20. " SV[20] ,SETVALID control for DMA channel 20" "No effect,Set" bitfld.long 0x00 19. " SV[19] ,SETVALID control for DMA channel 19" "No effect,Set" bitfld.long 0x00 18. " SV[18] ,SETVALID control for DMA channel 18" "No effect,Set" textline " " endif bitfld.long 0x00 17. " SV[17] ,SETVALID control for DMA channel 17" "No effect,Set" bitfld.long 0x00 16. " SV[16] ,SETVALID control for DMA channel 16" "No effect,Set" bitfld.long 0x00 15. " SV[15] ,SETVALID control for DMA channel 15" "No effect,Set" bitfld.long 0x00 14. " SV[14] ,SETVALID control for DMA channel 14" "No effect,Set" textline " " bitfld.long 0x00 13. " SV[13] ,SETVALID control for DMA channel 13" "No effect,Set" bitfld.long 0x00 12. " SV[12] ,SETVALID control for DMA channel 12" "No effect,Set" bitfld.long 0x00 11. " SV[11] ,SETVALID control for DMA channel 11" "No effect,Set" bitfld.long 0x00 10. " SV[10] ,SETVALID control for DMA channel 10" "No effect,Set" textline " " bitfld.long 0x00 9. " SV[9] ,SETVALID control for DMA channel 9" "No effect,Set" bitfld.long 0x00 8. " SV[8] ,SETVALID control for DMA channel 8" "No effect,Set" bitfld.long 0x00 7. " SV[7] ,SETVALID control for DMA channel 7" "No effect,Set" bitfld.long 0x00 6. " SV[6] ,SETVALID control for DMA channel 6" "No effect,Set" textline " " bitfld.long 0x00 5. " SV[5] ,SETVALID control for DMA channel 5" "No effect,Set" bitfld.long 0x00 4. " SV[4] ,SETVALID control for DMA channel 4" "No effect,Set" bitfld.long 0x00 3. " SV[3] ,SETVALID control for DMA channel 3" "No effect,Set" bitfld.long 0x00 2. " SV[2] ,SETVALID control for DMA channel 2" "No effect,Set" textline " " bitfld.long 0x00 1. " SV[1] ,SETVALID control for DMA channel 1" "No effect,Set" bitfld.long 0x00 0. " SV[0] ,SETVALID control for DMA channel 0" "No effect,Set" wgroup.long 0x70++0x03 line.long 0x00 "SETTRIG_0,Set Trigger Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " TRIG[24] ,Set Trigger control bit for DMA channel 24" "No effect,Set" bitfld.long 0x00 23. " TRIG[23] ,Set Trigger control bit for DMA channel 23" "No effect,Set" bitfld.long 0x00 22. " TRIG[22] ,Set Trigger control bit for DMA channel 22" "No effect,Set" bitfld.long 0x00 21. " TRIG[21] ,Set Trigger control bit for DMA channel 21" "No effect,Set" textline " " bitfld.long 0x00 20. " TRIG[20] ,Set Trigger control bit for DMA channel 20" "No effect,Set" bitfld.long 0x00 19. " TRIG[19] ,Set Trigger control bit for DMA channel 19" "No effect,Set" bitfld.long 0x00 18. " TRIG[18] ,Set Trigger control bit for DMA channel 18" "No effect,Set" textline " " endif bitfld.long 0x00 17. " TRIG[17] ,Set Trigger control bit for DMA channel 17" "No effect,Set" bitfld.long 0x00 16. " TRIG[16] ,Set Trigger control bit for DMA channel 16" "No effect,Set" bitfld.long 0x00 15. " TRIG[15] ,Set Trigger control bit for DMA channel 15" "No effect,Set" bitfld.long 0x00 14. " TRIG[14] ,Set Trigger control bit for DMA channel 14" "No effect,Set" textline " " bitfld.long 0x00 13. " TRIG[13] ,Set Trigger control bit for DMA channel 13" "No effect,Set" bitfld.long 0x00 12. " TRIG[12] ,Set Trigger control bit for DMA channel 12" "No effect,Set" bitfld.long 0x00 11. " TRIG[11] ,Set Trigger control bit for DMA channel 11" "No effect,Set" bitfld.long 0x00 10. " TRIG[10] ,Set Trigger control bit for DMA channel 10" "No effect,Set" textline " " bitfld.long 0x00 9. " TRIG[9] ,Set Trigger control bit for DMA channel 9" "No effect,Set" bitfld.long 0x00 8. " TRIG[8] ,Set Trigger control bit for DMA channel 8" "No effect,Set" bitfld.long 0x00 7. " TRIG[7] ,Set Trigger control bit for DMA channel 7" "No effect,Set" bitfld.long 0x00 6. " TRIG[6] ,Set Trigger control bit for DMA channel 6" "No effect,Set" textline " " bitfld.long 0x00 5. " TRIG[5] ,Set Trigger control bit for DMA channel 5" "No effect,Set" bitfld.long 0x00 4. " TRIG[4] ,Set Trigger control bit for DMA channel 4" "No effect,Set" bitfld.long 0x00 3. " TRIG[3] ,Set Trigger control bit for DMA channel 3" "No effect,Set" bitfld.long 0x00 2. " TRIG[2] ,Set Trigger control bit for DMA channel 2" "No effect,Set" textline " " bitfld.long 0x00 1. " TRIG[1] ,Set Trigger control bit for DMA channel 1" "No effect,Set" bitfld.long 0x00 0. " TRIG[0] ,Set Trigger control bit for DMA channel 0" "No effect,Set" wgroup.long 0x78++0x03 line.long 0x00 "ABORT_0,Abort 0 Register" sif (cpuis("LPC84*")) bitfld.long 0x00 24. " ABORTCTRL[24] ,Abort control for DMA channel 24" "No effect,Abort" bitfld.long 0x00 23. " ABORTCTRL[23] ,Abort control for DMA channel 23" "No effect,Abort" bitfld.long 0x00 22. " ABORTCTRL[22] ,Abort control for DMA channel 22" "No effect,Abort" bitfld.long 0x00 21. " ABORTCTRL[21] ,Abort control for DMA channel 21" "No effect,Abort" textline " " bitfld.long 0x00 20. " ABORTCTRL[20] ,Abort control for DMA channel 20" "No effect,Abort" bitfld.long 0x00 19. " ABORTCTRL[19] ,Abort control for DMA channel 19" "No effect,Abort" bitfld.long 0x00 18. " ABORTCTRL[18] ,Abort control for DMA channel 18" "No effect,Abort" textline " " endif bitfld.long 0x00 17. " ABORTCTRL[17] ,Abort control for DMA channel 17" "No effect,Abort" bitfld.long 0x00 16. " ABORTCTRL[16] ,Abort control for DMA channel 16" "No effect,Abort" bitfld.long 0x00 15. " ABORTCTRL[15] ,Abort control for DMA channel 15" "No effect,Abort" bitfld.long 0x00 14. " ABORTCTRL[14] ,Abort control for DMA channel 14" "No effect,Abort" textline " " bitfld.long 0x00 13. " ABORTCTRL[13] ,Abort control for DMA channel 13" "No effect,Abort" bitfld.long 0x00 12. " ABORTCTRL[12] ,Abort control for DMA channel 12" "No effect,Abort" bitfld.long 0x00 11. " ABORTCTRL[11] ,Abort control for DMA channel 11" "No effect,Abort" bitfld.long 0x00 10. " ABORTCTRL[10] ,Abort control for DMA channel 10" "No effect,Abort" textline " " bitfld.long 0x00 9. " ABORTCTRL[9] ,Abort control for DMA channel 9" "No effect,Abort" bitfld.long 0x00 8. " ABORTCTRL[8] ,Abort control for DMA channel 8" "No effect,Abort" bitfld.long 0x00 7. " ABORTCTRL[7] ,Abort control for DMA channel 7" "No effect,Abort" bitfld.long 0x00 6. " ABORTCTRL[6] ,Abort control for DMA channel 6" "No effect,Abort" textline " " bitfld.long 0x00 5. " ABORTCTRL[5] ,Abort control for DMA channel 5" "No effect,Abort" bitfld.long 0x00 4. " ABORTCTRL[4] ,Abort control for DMA channel 4" "No effect,Abort" bitfld.long 0x00 3. " ABORTCTRL[3] ,Abort control for DMA channel 3" "No effect,Abort" bitfld.long 0x00 2. " ABORTCTRL[2] ,Abort control for DMA channel 2" "No effect,Abort" textline " " bitfld.long 0x00 1. " ABORTCTRL[1] ,Abort control for DMA channel 1" "No effect,Abort" bitfld.long 0x00 0. " ABORTCTRL[0] ,Abort control for DMA channel 0" "No effect,Abort" tree.end tree.open "Channel registers" sif (cpuis("LPC84*")) tree "Channel 0" group.long 0x400++0x03 line.long 0x00 "CFG_0,Configuration Register For Channel 0" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x400+0x04)++0x03 line.long 0x00 "CTLSTAT_0,Control And Status Register For Channel 0" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x400+0x08)++0x03 line.long 0x00 "XFERCFG_0,Transfer Configuration Register For Channel 0" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 1" group.long 0x410++0x03 line.long 0x00 "CFG_1,Configuration Register For Channel 1" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x410+0x04)++0x03 line.long 0x00 "CTLSTAT_1,Control And Status Register For Channel 1" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x410+0x08)++0x03 line.long 0x00 "XFERCFG_1,Transfer Configuration Register For Channel 1" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 2" group.long 0x420++0x03 line.long 0x00 "CFG_2,Configuration Register For Channel 2" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x420+0x04)++0x03 line.long 0x00 "CTLSTAT_2,Control And Status Register For Channel 2" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x420+0x08)++0x03 line.long 0x00 "XFERCFG_2,Transfer Configuration Register For Channel 2" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 3" group.long 0x430++0x03 line.long 0x00 "CFG_3,Configuration Register For Channel 3" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x430+0x04)++0x03 line.long 0x00 "CTLSTAT_3,Control And Status Register For Channel 3" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x430+0x08)++0x03 line.long 0x00 "XFERCFG_3,Transfer Configuration Register For Channel 3" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 4" group.long 0x440++0x03 line.long 0x00 "CFG_4,Configuration Register For Channel 4" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x440+0x04)++0x03 line.long 0x00 "CTLSTAT_4,Control And Status Register For Channel 4" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x440+0x08)++0x03 line.long 0x00 "XFERCFG_4,Transfer Configuration Register For Channel 4" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 5" group.long 0x450++0x03 line.long 0x00 "CFG_5,Configuration Register For Channel 5" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x450+0x04)++0x03 line.long 0x00 "CTLSTAT_5,Control And Status Register For Channel 5" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x450+0x08)++0x03 line.long 0x00 "XFERCFG_5,Transfer Configuration Register For Channel 5" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 6" group.long 0x460++0x03 line.long 0x00 "CFG_6,Configuration Register For Channel 6" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x460+0x04)++0x03 line.long 0x00 "CTLSTAT_6,Control And Status Register For Channel 6" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x460+0x08)++0x03 line.long 0x00 "XFERCFG_6,Transfer Configuration Register For Channel 6" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 7" group.long 0x470++0x03 line.long 0x00 "CFG_7,Configuration Register For Channel 7" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x470+0x04)++0x03 line.long 0x00 "CTLSTAT_7,Control And Status Register For Channel 7" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x470+0x08)++0x03 line.long 0x00 "XFERCFG_7,Transfer Configuration Register For Channel 7" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 8" group.long 0x480++0x03 line.long 0x00 "CFG_8,Configuration Register For Channel 8" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x480+0x04)++0x03 line.long 0x00 "CTLSTAT_8,Control And Status Register For Channel 8" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x480+0x08)++0x03 line.long 0x00 "XFERCFG_8,Transfer Configuration Register For Channel 8" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 9" group.long 0x490++0x03 line.long 0x00 "CFG_9,Configuration Register For Channel 9" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x490+0x04)++0x03 line.long 0x00 "CTLSTAT_9,Control And Status Register For Channel 9" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x490+0x08)++0x03 line.long 0x00 "XFERCFG_9,Transfer Configuration Register For Channel 9" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 10" group.long 0x4A0++0x03 line.long 0x00 "CFG_10,Configuration Register For Channel 10" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4A0+0x04)++0x03 line.long 0x00 "CTLSTAT_10,Control And Status Register For Channel 10" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4A0+0x08)++0x03 line.long 0x00 "XFERCFG_10,Transfer Configuration Register For Channel 10" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 11" group.long 0x4B0++0x03 line.long 0x00 "CFG_11,Configuration Register For Channel 11" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4B0+0x04)++0x03 line.long 0x00 "CTLSTAT_11,Control And Status Register For Channel 11" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4B0+0x08)++0x03 line.long 0x00 "XFERCFG_11,Transfer Configuration Register For Channel 11" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 12" group.long 0x4C0++0x03 line.long 0x00 "CFG_12,Configuration Register For Channel 12" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4C0+0x04)++0x03 line.long 0x00 "CTLSTAT_12,Control And Status Register For Channel 12" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4C0+0x08)++0x03 line.long 0x00 "XFERCFG_12,Transfer Configuration Register For Channel 12" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 13" group.long 0x4D0++0x03 line.long 0x00 "CFG_13,Configuration Register For Channel 13" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4D0+0x04)++0x03 line.long 0x00 "CTLSTAT_13,Control And Status Register For Channel 13" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4D0+0x08)++0x03 line.long 0x00 "XFERCFG_13,Transfer Configuration Register For Channel 13" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 14" group.long 0x4E0++0x03 line.long 0x00 "CFG_14,Configuration Register For Channel 14" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4E0+0x04)++0x03 line.long 0x00 "CTLSTAT_14,Control And Status Register For Channel 14" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4E0+0x08)++0x03 line.long 0x00 "XFERCFG_14,Transfer Configuration Register For Channel 14" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 15" group.long 0x4F0++0x03 line.long 0x00 "CFG_15,Configuration Register For Channel 15" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4F0+0x04)++0x03 line.long 0x00 "CTLSTAT_15,Control And Status Register For Channel 15" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4F0+0x08)++0x03 line.long 0x00 "XFERCFG_15,Transfer Configuration Register For Channel 15" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 16" group.long 0x500++0x03 line.long 0x00 "CFG_16,Configuration Register For Channel 16" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x500+0x04)++0x03 line.long 0x00 "CTLSTAT_16,Control And Status Register For Channel 16" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x500+0x08)++0x03 line.long 0x00 "XFERCFG_16,Transfer Configuration Register For Channel 16" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 17" group.long 0x510++0x03 line.long 0x00 "CFG_17,Configuration Register For Channel 17" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x510+0x04)++0x03 line.long 0x00 "CTLSTAT_17,Control And Status Register For Channel 17" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x510+0x08)++0x03 line.long 0x00 "XFERCFG_17,Transfer Configuration Register For Channel 17" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 18" group.long 0x520++0x03 line.long 0x00 "CFG_18,Configuration Register For Channel 18" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x520+0x04)++0x03 line.long 0x00 "CTLSTAT_18,Control And Status Register For Channel 18" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x520+0x08)++0x03 line.long 0x00 "XFERCFG_18,Transfer Configuration Register For Channel 18" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 19" group.long 0x530++0x03 line.long 0x00 "CFG_19,Configuration Register For Channel 19" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x530+0x04)++0x03 line.long 0x00 "CTLSTAT_19,Control And Status Register For Channel 19" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x530+0x08)++0x03 line.long 0x00 "XFERCFG_19,Transfer Configuration Register For Channel 19" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 20" group.long 0x540++0x03 line.long 0x00 "CFG_20,Configuration Register For Channel 20" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x540+0x04)++0x03 line.long 0x00 "CTLSTAT_20,Control And Status Register For Channel 20" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x540+0x08)++0x03 line.long 0x00 "XFERCFG_20,Transfer Configuration Register For Channel 20" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 21" group.long 0x550++0x03 line.long 0x00 "CFG_21,Configuration Register For Channel 21" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x550+0x04)++0x03 line.long 0x00 "CTLSTAT_21,Control And Status Register For Channel 21" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x550+0x08)++0x03 line.long 0x00 "XFERCFG_21,Transfer Configuration Register For Channel 21" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 22" group.long 0x560++0x03 line.long 0x00 "CFG_22,Configuration Register For Channel 22" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x560+0x04)++0x03 line.long 0x00 "CTLSTAT_22,Control And Status Register For Channel 22" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x560+0x08)++0x03 line.long 0x00 "XFERCFG_22,Transfer Configuration Register For Channel 22" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 23" group.long 0x570++0x03 line.long 0x00 "CFG_23,Configuration Register For Channel 23" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x570+0x04)++0x03 line.long 0x00 "CTLSTAT_23,Control And Status Register For Channel 23" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x570+0x08)++0x03 line.long 0x00 "XFERCFG_23,Transfer Configuration Register For Channel 23" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 24" group.long 0x580++0x03 line.long 0x00 "CFG_24,Configuration Register For Channel 24" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x580+0x04)++0x03 line.long 0x00 "CTLSTAT_24,Control And Status Register For Channel 24" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x580+0x08)++0x03 line.long 0x00 "XFERCFG_24,Transfer Configuration Register For Channel 24" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end else tree "Channel 0" group.long 0x400++0x03 line.long 0x00 "CFG_0,Configuration Register For Channel 0" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x400+0x04)++0x03 line.long 0x00 "CTLSTAT_0,Control And Status Register For Channel 0" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x400+0x08)++0x03 line.long 0x00 "XFERCFG_0,Transfer Configuration Register For Channel 0" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 1" group.long 0x410++0x03 line.long 0x00 "CFG_1,Configuration Register For Channel 1" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x410+0x04)++0x03 line.long 0x00 "CTLSTAT_1,Control And Status Register For Channel 1" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x410+0x08)++0x03 line.long 0x00 "XFERCFG_1,Transfer Configuration Register For Channel 1" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 2" group.long 0x420++0x03 line.long 0x00 "CFG_2,Configuration Register For Channel 2" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x420+0x04)++0x03 line.long 0x00 "CTLSTAT_2,Control And Status Register For Channel 2" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x420+0x08)++0x03 line.long 0x00 "XFERCFG_2,Transfer Configuration Register For Channel 2" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 3" group.long 0x430++0x03 line.long 0x00 "CFG_3,Configuration Register For Channel 3" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x430+0x04)++0x03 line.long 0x00 "CTLSTAT_3,Control And Status Register For Channel 3" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x430+0x08)++0x03 line.long 0x00 "XFERCFG_3,Transfer Configuration Register For Channel 3" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 4" group.long 0x440++0x03 line.long 0x00 "CFG_4,Configuration Register For Channel 4" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x440+0x04)++0x03 line.long 0x00 "CTLSTAT_4,Control And Status Register For Channel 4" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x440+0x08)++0x03 line.long 0x00 "XFERCFG_4,Transfer Configuration Register For Channel 4" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 5" group.long 0x450++0x03 line.long 0x00 "CFG_5,Configuration Register For Channel 5" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x450+0x04)++0x03 line.long 0x00 "CTLSTAT_5,Control And Status Register For Channel 5" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x450+0x08)++0x03 line.long 0x00 "XFERCFG_5,Transfer Configuration Register For Channel 5" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 6" group.long 0x460++0x03 line.long 0x00 "CFG_6,Configuration Register For Channel 6" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x460+0x04)++0x03 line.long 0x00 "CTLSTAT_6,Control And Status Register For Channel 6" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x460+0x08)++0x03 line.long 0x00 "XFERCFG_6,Transfer Configuration Register For Channel 6" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 7" group.long 0x470++0x03 line.long 0x00 "CFG_7,Configuration Register For Channel 7" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x470+0x04)++0x03 line.long 0x00 "CTLSTAT_7,Control And Status Register For Channel 7" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x470+0x08)++0x03 line.long 0x00 "XFERCFG_7,Transfer Configuration Register For Channel 7" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 8" group.long 0x480++0x03 line.long 0x00 "CFG_8,Configuration Register For Channel 8" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x480+0x04)++0x03 line.long 0x00 "CTLSTAT_8,Control And Status Register For Channel 8" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x480+0x08)++0x03 line.long 0x00 "XFERCFG_8,Transfer Configuration Register For Channel 8" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 9" group.long 0x490++0x03 line.long 0x00 "CFG_9,Configuration Register For Channel 9" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x490+0x04)++0x03 line.long 0x00 "CTLSTAT_9,Control And Status Register For Channel 9" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x490+0x08)++0x03 line.long 0x00 "XFERCFG_9,Transfer Configuration Register For Channel 9" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 10" group.long 0x4A0++0x03 line.long 0x00 "CFG_10,Configuration Register For Channel 10" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4A0+0x04)++0x03 line.long 0x00 "CTLSTAT_10,Control And Status Register For Channel 10" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4A0+0x08)++0x03 line.long 0x00 "XFERCFG_10,Transfer Configuration Register For Channel 10" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 11" group.long 0x4B0++0x03 line.long 0x00 "CFG_11,Configuration Register For Channel 11" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4B0+0x04)++0x03 line.long 0x00 "CTLSTAT_11,Control And Status Register For Channel 11" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4B0+0x08)++0x03 line.long 0x00 "XFERCFG_11,Transfer Configuration Register For Channel 11" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 12" group.long 0x4C0++0x03 line.long 0x00 "CFG_12,Configuration Register For Channel 12" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4C0+0x04)++0x03 line.long 0x00 "CTLSTAT_12,Control And Status Register For Channel 12" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4C0+0x08)++0x03 line.long 0x00 "XFERCFG_12,Transfer Configuration Register For Channel 12" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 13" group.long 0x4D0++0x03 line.long 0x00 "CFG_13,Configuration Register For Channel 13" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4D0+0x04)++0x03 line.long 0x00 "CTLSTAT_13,Control And Status Register For Channel 13" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4D0+0x08)++0x03 line.long 0x00 "XFERCFG_13,Transfer Configuration Register For Channel 13" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 14" group.long 0x4E0++0x03 line.long 0x00 "CFG_14,Configuration Register For Channel 14" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4E0+0x04)++0x03 line.long 0x00 "CTLSTAT_14,Control And Status Register For Channel 14" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4E0+0x08)++0x03 line.long 0x00 "XFERCFG_14,Transfer Configuration Register For Channel 14" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 15" group.long 0x4F0++0x03 line.long 0x00 "CFG_15,Configuration Register For Channel 15" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x4F0+0x04)++0x03 line.long 0x00 "CTLSTAT_15,Control And Status Register For Channel 15" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4F0+0x08)++0x03 line.long 0x00 "XFERCFG_15,Transfer Configuration Register For Channel 15" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 16" group.long 0x500++0x03 line.long 0x00 "CFG_16,Configuration Register For Channel 16" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x500+0x04)++0x03 line.long 0x00 "CTLSTAT_16,Control And Status Register For Channel 16" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x500+0x08)++0x03 line.long 0x00 "XFERCFG_16,Transfer Configuration Register For Channel 16" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end tree "Channel 17" group.long 0x510++0x03 line.long 0x00 "CFG_17,Configuration Register For Channel 17" bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Selects how many transfers are performed for each DMA trigger" "1,2,4,8,16,32,64,128,256,512,1024,?..." textline " " bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Active low,Active high" bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled" rgroup.long (0x510+0x04)++0x03 line.long 0x00 "CTLSTAT_17,Control And Status Register For Channel 17" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x510+0x08)++0x03 line.long 0x00 "XFERCFG_17,Transfer Configuration Register For Channel 17" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed, minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software Trigger" "Not set,Set" textline " " bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Not valid,Valid" tree.end endif tree.end width 0x0B tree.end endif sif !cpuis("LPC8N04") sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) tree "SWM (Switch Matrix)" base ad:0x4000C000 width 13. group.long 0x00++0x07 line.long 0x00 "PINASSIGN0,Pin Assign Register 0" hexmask.long.byte 0x00 24.--31. 1. " U0_CTS_I ,U0_CTS_I function assignment" hexmask.long.byte 0x00 16.--23. 1. " U0_RTS_O ,U0_RTS_O function assignment" hexmask.long.byte 0x00 8.--15. 1. " U0_RXD_I ,U0_RXD_I function assignment" hexmask.long.byte 0x00 0.--7. 1. " U0_TXD_O ,U0_TXD_O function assignment" line.long 0x04 "PINASSIGN1,Pin Assign Register 1" sif (cpu()!="LPC832M101FDH20"||cpu()!="LPC834M101FHI33") hexmask.long.byte 0x04 24.--31. 1. " U1_RTS_O ,U1_RTS_O function assignment" hexmask.long.byte 0x04 16.--23. 1. " U1_RXD_I ,U1_RXD_I function assignment" hexmask.long.byte 0x04 8.--15. 1. " U1_TXD_O ,U1_TXD_O function assignment" textline " " endif hexmask.long.byte 0x04 0.--7. 1. " U0_SCLK_IO ,U0_SCLK_IO function assignment" sif (cpu()!="LPC832M101FDH20"||cpu()!="LPC834M101FHI33") group.long 0x08++0x03 line.long 0x00 "PINASSIGN2,Pin Assign Register 2" hexmask.long.byte 0x00 24.--31. 1. " U2_RXD_I ,U2_RXD_I function assignment" hexmask.long.byte 0x00 16.--23. 1. " U2_TXD_O ,U2_TXD_O function assignment" hexmask.long.byte 0x00 8.--15. 1. " U1_SCLK_IO ,U1_SCLK_IO function assignment" hexmask.long.byte 0x00 0.--7. 1. " U1_CTS_I ,U1_CTS_I function assignment" endif group.long 0x0C++0x1B line.long 0x00 "PINASSIGN3,Pin Assign Register 3" hexmask.long.byte 0x00 24.--31. 1. " SPI0_SCK_IO ,SPI0_SCK_IO function assignment" textline " " sif (cpu()!="LPC832M101FDH20"||cpu()!="LPC834M101FHI33") hexmask.long.byte 0x00 16.--23. 1. " U2_SCLK_IO ,U2_SCLK_IO function assignment" hexmask.long.byte 0x00 8.--15. 1. " U2_CTS_I ,U2_CTS_I function assignment" hexmask.long.byte 0x00 0.--7. 1. " U2_RTS_O ,U2_RTS_O function assignment" endif line.long 0x04 "PINASSIGN4,Pin Assign Register 4" hexmask.long.byte 0x04 24.--31. 1. " SPI0_SSEL1_IO ,SPI0_SSEL1_IO function assignment" hexmask.long.byte 0x04 16.--23. 1. " SPI0_SSEL0_IO ,SPI0_SSEL0_IO function assignment" hexmask.long.byte 0x04 8.--15. 1. " SPI0_MISO_IO ,SPI0_MISO_IO function assignment" hexmask.long.byte 0x04 0.--7. 1. " SPI0_MOSI_IO ,SPI0_MOSI_IO function assignment" line.long 0x08 "PINASSIGN5,Pin Assign Register 5" hexmask.long.byte 0x08 24.--31. 1. " SPI1_MOSI_IO ,SPI1_MOSI_IO function assignment" hexmask.long.byte 0x08 16.--23. 1. " SPI1_SCK_IO ,SPI1_SCK_IO function assignment" hexmask.long.byte 0x08 8.--15. 1. " SPI0_SSEL3_IO ,SPI0_SSEL3_IO function assignment" hexmask.long.byte 0x08 0.--7. 1. " SPI0_SSEL2_IO ,SPI0_SSEL2_IO function assignment" line.long 0x0C "PINASSIGN6,Pin Assign Register 6" sif (cpu()!="LPC832M101FDH20"||cpu()!="LPC834M101FHI33") hexmask.long.byte 0x0C 24.--31. 1. " SCT0_GPIO_IN_A_I ,SCT0_GPIO_IN_A_I function assignment" else hexmask.long.byte 0x0C 24.--31. 1. " SCT_PIN0_I ,SCT_PIN0_I function assignment" endif hexmask.long.byte 0x0C 16.--23. 1. " SPI1_SSEL1_IO ,SPI1_SSEL1_IO function assignment" hexmask.long.byte 0x0C 8.--15. 1. " SPI1_SSEL0_IO ,SPI1_SSEL0_IO function assignment" hexmask.long.byte 0x0C 0.--7. 1. " SPI1_MISO_IO ,SPI1_MISO_IO function assignment" line.long 0x10 "PINASSIGN7,Pin Assign Register 7" hexmask.long.byte 0x10 24.--31. 1. " SCT_OUT0_O ,SCT_OUT0_O function assignment" sif (cpu()!="LPC832M101FDH20"||cpu()!="LPC834M101FHI33") hexmask.long.byte 0x10 16.--23. 1. " SCT0_GPIO_IN_D_I ,SCT0_GPIO_IN_D_I function assignment" hexmask.long.byte 0x10 8.--15. 1. " SCT0_GPIO_IN_C_I ,SCT0_GPIO_IN_C_I function assignment" hexmask.long.byte 0x10 0.--7. 1. " SCT0_GPIO_IN_B_I ,SCT0_GPIO_IN_B_I function assignment" else hexmask.long.byte 0x10 16.--23. 1. " SCT_PIN3_I ,SCT_PIN3_I function assignment" hexmask.long.byte 0x10 8.--15. 1. " SCT_PIN2_I ,SCT_PIN2_I function assignment" hexmask.long.byte 0x10 0.--7. 1. " SCT_PIN1_I ,SCT_PIN1_I function assignment" endif line.long 0x14 "PINASSIGN8,Pin Assign Register 8" hexmask.long.byte 0x14 24.--31. 1. " SCT_OUT4_O ,SCT_OUT4_O function assignment" hexmask.long.byte 0x14 16.--23. 1. " SCT_OUT3_O ,SCT_OUT3_O function assignment" hexmask.long.byte 0x14 8.--15. 1. " SCT_OUT2_O ,SCT_OUT2_O function assignment" hexmask.long.byte 0x14 0.--7. 1. " SCT_OUT1_O ,SCT_OUT1_O function assignment" line.long 0x18 "PINASSIGN9,Pin Assign Register 9" sif (cpu()!="LPC832M101FDH20"||cpu()!="LPC834M101FHI33") hexmask.long.byte 0x18 24.--31. 1. " I2C1_SCL_IO ,I2C1_SCL_IO function assignment" hexmask.long.byte 0x18 16.--23. 1. " I2C1_SDA_IO ,I2C1_SDA_IO function assignment" hexmask.long.byte 0x18 8.--15. 1. " SCT_OUT6_O ,SCT_OUT6_O function assignment" textline " " endif hexmask.long.byte 0x18 0.--7. 1. " SCT_OUT5_O ,SCT_OUT5_O function assignment" sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") group.long 0x28++0x07 line.long 0x00 "PINASSIGN10,Pin Assign Register 10" hexmask.long.byte 0x00 24.--31. 1. " ADC_PINTRIG0_I ,ADC_PINTRIG0_I function assignment" line.long 0x04 "PINASSIGN11,Pin Assign Register 11" hexmask.long.byte 0x04 24.--31. 1. " GPIO_INT_BMAT_O ,GPIO_INT_BMAT_O function assignment" hexmask.long.byte 0x04 16.--23. 1. " CLKOUT_O ,CLKOUT_O function assignment" hexmask.long.byte 0x04 0.--7. 1. " ADC_PINTRIG1_I ,ADC_PINTRIG1_I function assignment" else group.long 0x28++0x13 line.long 0x00 "PINASSIGN10,Pin Assign Register 10" hexmask.long.byte 0x00 24.--31. 1. " I2C3_SCL_IO ,I2C3_SCL_IO function assignment" hexmask.long.byte 0x00 16.--23. 1. " I2C3_SDA_IO ,I2C3_SDA_IO function assignment" hexmask.long.byte 0x00 8.--15. 1. " I2C2_SCL_IO ,I2C2_SCL_IO function assignment" hexmask.long.byte 0x00 0.--7. 1. " I2C2_SDA_IO ,I2C2_SDA_IO function assignment" line.long 0x04 "PINASSIGN11,Pin Assign Register 11" hexmask.long.byte 0x04 24.--31. 1. " UART3_TXD ,UART3_TXD function assignment" hexmask.long.byte 0x04 16.--23. 1. " GPIO_INT_BMAT_O ,GPIO_INT_BMAT_O function assignment" hexmask.long.byte 0x04 8.--15. 1. " CLKOUT_O ,CLKOUT_O function assignment" hexmask.long.byte 0x04 0.--7. 1. " COMP0_OUT_O ,COMP0_OUT_O function assignment" line.long 0x08 "PINASSIGN12,Pin Assign Register 12" hexmask.long.byte 0x08 24.--31. 1. " UART4_RXD ,UART4_RXD function assignment" hexmask.long.byte 0x08 16.--23. 1. " UART4_TXD ,UART4_TXD function assignment" hexmask.long.byte 0x08 8.--15. 1. " UART3_SCLK ,UART3_SCLK function assignment" hexmask.long.byte 0x08 0.--7. 1. " UART3_RXD ,UART3_RXD function assignment" line.long 0x0C "PINASSIGN13,Pin Assign Register 13" hexmask.long.byte 0x0C 24.--31. 1. " T0_MAT2 ,T0_MAT2 function assignment" hexmask.long.byte 0x0C 16.--23. 1. " T0_MAT1 ,T0_MAT1 function assignment" hexmask.long.byte 0x0C 8.--15. 1. " T0_MAT0 ,T0_MAT0 function assignment" hexmask.long.byte 0x0C 0.--7. 1. " UART4_SCLK ,UART4_SCLK function assignment" line.long 0x10 "PINASSIGN14,Pin Assign Register 14" hexmask.long.byte 0x10 24.--31. 1. " T0_CAP2 ,T0_CAP2 function assignment" hexmask.long.byte 0x10 16.--23. 1. " T0_CAP1 ,T0_CAP1 function assignment" hexmask.long.byte 0x10 8.--15. 1. " T0_CAP0 ,T0_CAP0 function assignment" hexmask.long.byte 0x10 0.--7. 1. " T0_MAT3 ,T0_MAT3 function assignment" endif sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") group.long 0x1C0++0x03 line.long 0x00 "PINENABLE0,Pin Enable Register 0" bitfld.long 0x00 24. " ADC_11 ,ADC_11 function select (PIO0_4)" "Enabled,Disabled" bitfld.long 0x00 23. " ADC_10 ,ADC_10 function select (PIO0_13)" "Enabled,Disabled" bitfld.long 0x00 22. " ADC_9 ,ADC_9 function select (PIO0_17)" "Enabled,Disabled" bitfld.long 0x00 21. " ADC_8 ,ADC_8 function select (PIO0_18)" "Enabled,Disabled" textline " " bitfld.long 0x00 20. " ADC_7 ,ADC_7 function select (PIO0_19)" "Enabled,Disabled" bitfld.long 0x00 19. " ADC_6 ,ADC_6 function select (PIO0_20)" "Enabled,Disabled" bitfld.long 0x00 18. " ADC_5 ,ADC_5 function select (PIO0_21)" "Enabled,Disabled" bitfld.long 0x00 17. " ADC_4 ,ADC_4 function select (PIO0_22)" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " ADC_3 ,ADC_3 function select (PIO0_23)" "Enabled,Disabled" bitfld.long 0x00 15. " ADC_2 ,ADC_2 function select (PIO0_14)" "Enabled,Disabled" bitfld.long 0x00 14. " ADC_1 ,ADC_1 function select (PIO0_6)" "Enabled,Disabled" bitfld.long 0x00 13. " ADC_0 ,ADC_0 function select (PIO0_7)" "Enabled,Disabled" textline " " bitfld.long 0x00 12. " I2C0_SCL ,I2C0_SCL function select (PIO0_10)" "Enabled,Disabled" bitfld.long 0x00 11. " I2C0_SDA ,I2C0_SDA function select (PIO0_11)" "Enabled,Disabled" bitfld.long 0x00 9. " CLKIN ,CLKIN function select (PIO0_1)" "Enabled,Disabled" bitfld.long 0x00 8. " RESETN ,RESETN function select (PIO0_5)" "Enabled,Disabled" textline " " bitfld.long 0x00 7. " XTALOUT ,XTALOUT function select (PIO0_9)" "Enabled,Disabled" bitfld.long 0x00 6. " XTALIN ,XTALIN function select (PIO0_8)" "Enabled,Disabled" bitfld.long 0x00 5. " SWDIO ,SWDIO function select (PIO0_2)" "Enabled,Disabled" bitfld.long 0x00 4. " SWCLK ,SWCLK function select (PIO0_3)" "Enabled,Disabled" else group.long 0x1C0++0x07 line.long 0x00 "PINENABLE0,Pin Enable Register 0" bitfld.long 0x00 31. " CAPT_X3 ,CAPT_X3 function select (PIO1_2)" "Enabled,Disabled" bitfld.long 0x00 30. " CAPT_X2 ,CAPT_X2 function select (PIO1_1)" "Enabled,Disabled" bitfld.long 0x00 29. " CAPT_X1 ,CAPT_X1 function select (PIO1_0)" "Enabled,Disabled" bitfld.long 0x00 28. " CAPT_X0 ,CAPT_X0 function select (PIO0_31)" "Enabled,Disabled" textline " " bitfld.long 0x00 27. " DACOUT1 ,DACOUT1 function select (PIO0_29)" "Enabled,Disabled" bitfld.long 0x00 26. " DACOUT0 ,DACOUT0 function select (PIO0_17)" "Enabled,Disabled" bitfld.long 0x00 25. " ADC_11 ,ADC_11 function select (PIO0_4)" "Enabled,Disabled" bitfld.long 0x00 24. " ADC_10 ,ADC_10 function select (PIO0_13)" "Enabled,Disabled" textline " " bitfld.long 0x00 23. " ADC_9 ,ADC_9 function select (PIO0_17)" "Enabled,Disabled" bitfld.long 0x00 22. " ADC_8 ,ADC_8 function select (PIO0_18)" "Enabled,Disabled" bitfld.long 0x00 21. " ADC_7 ,ADC_7 function select (PIO0_19)" "Enabled,Disabled" bitfld.long 0x00 20. " ADC_6 ,ADC_6 function select (PIO0_20)" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " ADC_5 ,ADC_5 function select (PIO0_21)" "Enabled,Disabled" bitfld.long 0x00 18. " ADC_4 ,ADC_4 function select (PIO0_22)" "Enabled,Disabled" bitfld.long 0x00 17. " ADC_3 ,ADC_3 function select (PIO0_23)" "Enabled,Disabled" bitfld.long 0x00 16. " ADC_2 ,ADC_2 function select (PIO0_14)" "Enabled,Disabled" textline " " bitfld.long 0x00 15. " ADC_1 ,ADC_1 function select (PIO0_6)" "Enabled,Disabled" bitfld.long 0x00 14. " ADC_0 ,ADC_0 function select (PIO0_7)" "Enabled,Disabled" bitfld.long 0x00 13. " I2C0_SCL ,I2C0_SCL function select (PIO0_10)" "Enabled,Disabled" bitfld.long 0x00 12. " I2C0_SDA ,I2C0_SDA function select (PIO0_11)" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " VDDCMP ,VDDCMP function select (PIO0_6)" "Enabled,Disabled" bitfld.long 0x00 10. " CLKIN ,CLKIN function select (PIO0_1)" "Enabled,Disabled" bitfld.long 0x00 9. " RESETN ,RESETN function select (PIO0_5)" "Enabled,Disabled" bitfld.long 0x00 8. " XTALOUT ,XTALOUT function select (PIO0_9)" "Enabled,Disabled" textline " " bitfld.long 0x00 7. " XTALIN ,XTALIN function select (PIO0_8)" "Enabled,Disabled" bitfld.long 0x00 6. " SWDIO ,SWDIO function select (PIO0_2)" "Enabled,Disabled" bitfld.long 0x00 5. " SWCLK ,SWCLK function select (PIO0_3)" "Enabled,Disabled" bitfld.long 0x00 4. " ACMP_I5 ,ACMP_I5 function select (PIO0_30)" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " ACMP_I4 ,ACMP_I4 function select (PIO0_23)" "Enabled,Disabled" bitfld.long 0x00 2. " ACMP_I3 ,ACMP_I3 function select (PIO0_14)" "Enabled,Disabled" bitfld.long 0x00 1. " ACMP_I2 ,ACMP_I2 function select (PIO0_1)" "Enabled,Disabled" bitfld.long 0x00 0. " ACMP_I1 ,ACMP_I1 function select (PIO0_00)" "Enabled,Disabled" line.long 0x04 "PINENABLE1,Pin Enable Register 1" bitfld.long 0x04 6. " CAPT_YH ,CAPT_YH function select (PIO1_9)" "Enabled,Disabled" bitfld.long 0x04 5. " CAPT_YL ,CAPT_YL function select (PIO1_8)" "Enabled,Disabled" bitfld.long 0x04 4. " CAPT_X8 ,CAPT_X8 function select (PIO1_7)" "Enabled,Disabled" bitfld.long 0x04 3. " CAPT_X7 ,CAPT_X7 function select (PIO1_6)" "Enabled,Disabled" textline " " bitfld.long 0x04 2. " CAPT_X6 ,CAPT_X6 function select (PIO1_5)" "Enabled,Disabled" bitfld.long 0x04 1. " CAPT_X5 ,CAPT_X5 function select (PIO1_4)" "Enabled,Disabled" bitfld.long 0x04 0. " CAPT_X4 ,CAPT_X4 function select (PIO1_3)" "Enabled,Disabled" endif width 0x0b tree.end elif cpuis("LPC802*")||cpuis("LPC804*") tree "SWM (Switch Matrix)" base ad:0x4000C000 width 17. group.long 0x00++0x1C line.long 0x00 "PINASSIGN0,Pin Assign Register 0" hexmask.long.byte 0x00 24.--31. 1. " U0_CTS_I ,U0_CTS_I function assignment" hexmask.long.byte 0x00 16.--23. 1. " U0_RTS_O ,U0_RTS_O function assignment" hexmask.long.byte 0x00 8.--15. 1. " U0_RXD_I ,U0_RXD_I function assignment" hexmask.long.byte 0x00 0.--7. 1. " U0_TXD_O ,U0_TXD_O function assignment" line.long 0x04 "PINASSIGN1,Pin Assign Register 1" hexmask.long.byte 0x04 24.--31. 1. " U1_SCLK_IO ,U1_SCLK_IO function assignment" hexmask.long.byte 0x04 16.--23. 1. " U1_RXD_I ,U1_RXD_I function assignment" hexmask.long.byte 0x04 8.--15. 1. " U1_TXD_O ,U1_TXD_O function assignment" hexmask.long.byte 0x04 0.--7. 1. " U0_SCLK_IO ,U0_SCLK_IO function assignment" line.long 0x08 "PINASSIGN2,Pin Assign Register 2" hexmask.long.byte 0x08 24.--31. 1. " SPI0_SSEL0_IO ,SPI0_SSEL0_IO function assignment" hexmask.long.byte 0x08 16.--23. 1. " SPI0_MISO_IO ,SPI0_MISO_IO function assignment" hexmask.long.byte 0x08 8.--15. 1. " SPI0_MOSI_IO ,SPI0_MOSI_IO function assignment" hexmask.long.byte 0x08 0.--7. 1. " SPI0_SCK_IO ,U0_SCLK_IO function assignment" line.long 0x0C "PINASSIGN3,Pin Assign Register 3" hexmask.long.byte 0x0C 24.--31. 1. " T0_CAP2 ,T0_CAP2 function assignment" hexmask.long.byte 0x0C 16.--23. 1. " T0_CAP1 ,T0_CAP1 function assignment" hexmask.long.byte 0x0C 8.--15. 1. " T0_CAP0 ,T0_CAP0 function assignment" hexmask.long.byte 0x0C 0.--7. 1. " SPI0_SSEL1_IO ,U0_SCLK_IO function assignment" line.long 0x10 "PINASSIGN4,Pin Assign Register 4" hexmask.long.byte 0x10 24.--31. 1. " T0_MAT3 ,T0_MAT3 function assignment" hexmask.long.byte 0x10 16.--23. 1. " T0_MAT2 ,T0_MAT2 function assignment" hexmask.long.byte 0x10 8.--15. 1. " T0_MAT1 ,T0_MAT1 function assignment" hexmask.long.byte 0x10 0.--7. 1. " T0_MAT0 ,T0_MAT0 function assignment" line.long 0x14 "PINASSIGN5,Pin Assign Register 5" hexmask.long.byte 0x14 24.--31. 1. " CLKOUT_O ,CLKOUT_O function assignment" hexmask.long.byte 0x14 16.--23. 1. " COMP0_OUT_O ,COMP0_OUT_O function assignment" newline hexmask.long.byte 0x14 8.--15. 1. " I2C0_SCL_IO ,I2C0_SCL_IO function assignment" hexmask.long.byte 0x14 0.--7. 1. " I2C0_SDA_IO ,CLKOUT_O function assignment" line.long 0x18 "PINASSIGN6,Pin Assign Register 6" hexmask.long.byte 0x18 24.--31. 1. " LVLSHFT_OUT0 ,LVLSHFT_OUT0 function assignment" hexmask.long.byte 0x18 16.--23. 1. " LVLSHFT_IN1 ,LVLSHFT_IN1 function assignment" hexmask.long.byte 0x18 8.--15. 1. " LVLSHFT_IN0 ,LVLSHFT_IN0 function assignment" hexmask.long.byte 0x18 0.--7. 1. " GPIO_INT_BMAT_O ,GPIO_INT_BMAT_O function assignment" sif cpuis("LPC804*") group.long 0x1C++0x0B line.long 0x00 "PINASSIGN7,Pin Assign Register 7" hexmask.long.byte 0x00 24.--31. 1. " PLU_CLKIN_IN ,PLU_CLKIN_IN function assignment" hexmask.long.byte 0x00 16.--23. 1. " I2C1_SCL_IO ,I2C1_SCL_IO function assignment" hexmask.long.byte 0x00 8.--15. 1. " I2C1_SDA_IO ,I2C1_SDA_IO function assignment" hexmask.long.byte 0x00 0.--7. 1. " LVLSHFT_OUT1 ,LVLSHFT_OUT1 function assignment" line.long 0x04 "PINASSIGN8,Pin Assign Register 8" hexmask.long.byte 0x04 24.--31. 1. " CAPT_X3_O ,CAPT_X3_O function assignment" hexmask.long.byte 0x04 16.--23. 1. " CAPT_X2_O ,CAPT_X2_O function assignment" hexmask.long.byte 0x04 8.--15. 1. " CAPT_X1_O ,CAPT_X1_O function assignment" hexmask.long.byte 0x04 0.--7. 1. " CAPT_X1_O ,CAPT_X1_O function assignment" line.long 0x08 "PINASSIGN9,Pin Assign Register 9" hexmask.long.byte 0x08 16.--23. 1. " CAPT_YH_O ,CAPT_YH_O function assignment" hexmask.long.byte 0x08 8.--15. 1. " CAPT_YL_O ,CAPT_YL_O function assignment" hexmask.long.byte 0x08 0.--7. 1. " CAPT_X4_O ,CAPT_X4_O function assignment" newline else group.long 0x1C++0x3 line.long 0x00 "PINASSIGN7,Pin Assign Register 7" hexmask.long.byte 0x00 0.--7. 1. " LVLSHFT_OUT1 ,LVLSHFT_OUT1 function assignment" newline endif sif cpuis("LPC804*") group.long 0x180++0x03 line.long 0x00 "PINASSIGNFIXED0,Pin fixed assign register 0" bitfld.long 0x00 26.--27. " PLU_OUT7 ,PLU_OUT7 function assignment" "PIO0_14,PIO0_21,PIO0_30,None" bitfld.long 0x00 24.--25. " PLU_OUT6 ,PLU_OUT6 function assignment" "PIO0_13,PIO0_20,PIO0_29,None" bitfld.long 0x00 22.--23. " PLU_OUT5 ,PLU_OUT5 function assignment" "PIO0_12,PIO0_19,PIO0_28,None" bitfld.long 0x00 20.--21. " PLU_OUT4 ,PLU_OUT4 function assignment" "PIO0_11,PIO0_18,PIO0_27,None" newline bitfld.long 0x00 18.--19. " PLU_OUT3 ,PLU_OUT3 function assignment" "PIO0_10,PIO0_17,PIO0_26,None" bitfld.long 0x00 16.--17. " PLU_OUT2 ,PLU_OUT2 function assignment" "PIO0_09,PIO0_16,PIO0_25,None" bitfld.long 0x00 14.--15. " PLU_OUT1 ,PLU_OUT1 function assignment" "PIO0_08,PIO0_15,PIO0_24,None" bitfld.long 0x00 12.--13. " PLU_OUT0 ,PLU_OUT0 function assignment" "PIO0_07,PIO0_14,PIO0_23,None" newline bitfld.long 0x00 10.--11. " PLU_INPUT5 ,PLU_INPUT5 function assignment" "PIO0_05,PIO0_13,PIO0_22,None" bitfld.long 0x00 8.--9. " PLU_INPUT4 ,PLU_INPUT4 function assignment" "PIO0_04,PIO0_12,PIO0_21,None" bitfld.long 0x00 6.--7. " PLU_INPUT3 ,PLU_INPUT3 function assignment" "PIO0_03,PIO0_11,PIO0_20,None" bitfld.long 0x00 4.--5. " PLU_INPUT2 ,PLU_INPUT2 function assignment" "PIO0_02,PIO0_10,PIO0_19,None" newline bitfld.long 0x00 2.--3. " PLU_INPUT1 ,PLU_INPUT1 function assignment" "PIO0_01,PIO0_09,PIO0_18,None" bitfld.long 0x00 0.--1. " PLU_INPUT0 ,PLU_INPUT0 function assignment" "PIO0_00,PIO0_08,PIO0_17,None" endif group.long 0x1C0++0x03 line.long 0x00 "PINENABLE0,Pin Enable Register 0" sif cpuis("LPC804*") bitfld.long 0x00 23. " DACOUT0 ,DACOUT0 enable on PIO0_19" "Enabled,Disabled" bitfld.long 0x00 22. " ACMP_15 ,ACMP_15 enable on PIO0_21" "Enabled,Disabled" newline endif bitfld.long 0x00 21. " ADC_11 ,ADC_11 enable on PIO0_4" "Enabled,Disabled" bitfld.long 0x00 20. " ADC_10 ,ADC_10 enable on PIO0_13" "Enabled,Disabled" bitfld.long 0x00 19. " ADC_9 ,ADC_9 enable on PIO0_17" "Enabled,Disabled" bitfld.long 0x00 18. " ADC_8 ,ADC_8 enable on PIO0_15" "Enabled,Disabled" newline bitfld.long 0x00 17. " ADC_7 ,ADC_7 enable on PIO0_10" "Enabled,Disabled" bitfld.long 0x00 16. " ADC_6 ,ADC_6 enable on PIO0_11" "Enabled,Disabled" bitfld.long 0x00 15. " ADC_5 ,ADC_5 enable on PIO0_8" "Enabled,Disabled" bitfld.long 0x00 14. " ADC_4 ,ADC_4 enable on PIO0_9" "Enabled,Disabled" newline bitfld.long 0x00 13. " ADC_3 ,ADC_3 enable on PIO0_16" "Enabled,Disabled" bitfld.long 0x00 12. " ADC_2 ,ADC_2 enable on PIO0_14" "Enabled,Disabled" bitfld.long 0x00 11. " ADC_1 ,ADC_1 enable on PIO0_7" "Enabled,Disabled" bitfld.long 0x00 10. " ADC_0 ,ADC_0 enable on PIO0_1" "Enabled,Disabled" newline bitfld.long 0x00 9. " VDDCMP ,VDDCMP enable on PIO0_7" "Enabled,Disabled" bitfld.long 0x00 8. " WKCLKIN ,WKCLKIN enable on PIO0_11" "Enabled,Disabled" bitfld.long 0x00 7. " CLKIN ,CLKIN enable on PIO0_1" "Enabled,Disabled" bitfld.long 0x00 6. " RESETN ,RESETN enable on PIO0_5" "Enabled,Disabled" newline bitfld.long 0x00 5. " SWDIO ,SWDIO enable on PIO0_2" "Enabled,Disabled" bitfld.long 0x00 4. " SWCLK ,SWCLK enable on PIO0_3" "Enabled,Disabled" bitfld.long 0x00 3. " ACMP_I4 ,ACMP_I4 enable on PIO0_16" "Enabled,Disabled" bitfld.long 0x00 2. " ACMP_I3 ,ACMP_I3 enable on PIO0_14" "Enabled,Disabled" newline bitfld.long 0x00 1. " ACMP_I2 ,ACMP_I2 enable on PIO0_1" "Enabled,Disabled" bitfld.long 0x00 0. " ACMP_I1 ,ACMP_I1 enable on PIO0_00" "Enabled,Disabled" width 0x0B tree.end else tree "SWM (Switch Matrix)" base ad:0x4000C000 width 14. group.long 0x00++0x13 line.long 0x00 "PINASSIGN_0,Pin Assign Register 0" hexmask.long.byte 0x00 24.--31. 1. " U0_CTS_I ,U0_CTS function assignment" hexmask.long.byte 0x00 16.--23. 1. " U0_RTS_O ,U0_RTS function assignment" hexmask.long.byte 0x00 8.--15. 1. " U0_RXD_I ,U0_RXD function assignment" hexmask.long.byte 0x00 0.--7. 1. " U0_TXD_O ,U0_TXD function assignment" line.long 0x04 "PINASSIGN_1,Pin Assign Register 1" hexmask.long.byte 0x04 24.--31. 1. " U1_RTS_O ,U1_RTS function assignment" hexmask.long.byte 0x04 16.--23. 1. " U1_RXD_I ,U1_RXD function assignment" hexmask.long.byte 0x04 8.--15. 1. " U1_TXD_O ,U1_TXD function assignment" hexmask.long.byte 0x04 0.--7. 1. " U0_SCLK_IO ,U0_SCLK function assignment" line.long 0x08 "PINASSIGN_2,Pin Assign Register 2" sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") hexmask.long.byte 0x08 24.--31. 1. " U2_RXD_I ,U2_RXD function assignment" hexmask.long.byte 0x08 16.--23. 1. " U2_TXD_O ,U2_TXD function assignment" textline " " endif hexmask.long.byte 0x08 8.--15. 1. " U1_SCLK_IO ,U1_SCLK function assignment" hexmask.long.byte 0x08 0.--7. 1. " U1_CTS_I ,U1_CTS function assignment" line.long 0x0C "PINASSIGN_3,Pin Assign Register 3" hexmask.long.byte 0x0C 24.--31. 1. " SPI0_SCK_IO ,SPI0_SCK function assignment" sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") textline " " hexmask.long.byte 0x0C 16.--23. 1. " U2_SCLK_IO ,U2_SCLK function assignment" hexmask.long.byte 0x0C 8.--15. 1. " U2_CTS_I ,U2_CTS function assignment" hexmask.long.byte 0x0C 0.--7. 1. " U2_RTS_O ,U2_RTS function assignment" endif line.long 0x10 "PINASSIGN_4,Pin Assign Register 4" sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") hexmask.long.byte 0x10 24.--31. 1. " SPI1_SCK_IO ,SPI1_SCK function assignment" textline " " elif (cpuis("LPC82*")) hexmask.long.byte 0x10 24.--31. 1. " SPI0_SSEL1_IO ,SPI0_SSEL1 function assignment" textline " " endif hexmask.long.byte 0x10 16.--23. 1. " SPI0_SSEL_IO ,SPI0_SSEL function assignment" hexmask.long.byte 0x10 8.--15. 1. " SPI0_MISO_IO ,SPI0_MISO function assignment" hexmask.long.byte 0x10 0.--7. 1. " SPI0_MOSI_IO ,SPI0_MOSI function assignment" sif (cpuis("LPC82*")) group.long 0x14++0x1B line.long 0x00 "PINASSIGN_5,Pin Assign Register 5" hexmask.long.byte 0x00 24.--31. 1. " SPI1_MOSI_IO ,SPI1_MOSI function assignment" hexmask.long.byte 0x00 16.--23. 1. " SPI1_SCK_IO ,SPI1_SCK function assignment" hexmask.long.byte 0x00 8.--15. 1. " SPI0_SSEL3_IO ,SPI0_SSEL3 function assignment" hexmask.long.byte 0x00 0.--7. 1. " SPI0_SSEL2_IO ,SPI0_SSEL2 function assignment" line.long 0x04 "PINASSIGN_6,Pin Assign Register 6" hexmask.long.byte 0x04 24.--31. 1. " SCT_PIN0_I ,SCT_PIN0 function assignment" hexmask.long.byte 0x04 16.--23. 1. " SPI1_SSEL1_IO ,SPI1_SSEL1 function assignment" hexmask.long.byte 0x04 8.--15. 1. " SPI1_SSEL0_IO ,SPI1_SSEL0 function assignment" hexmask.long.byte 0x04 0.--7. 1. " SPI1_MISO_IO ,SPI1_MISO function assignment" line.long 0x08 "PINASSIGN_7,Pin Assign Register 7" hexmask.long.byte 0x08 24.--31. 1. " SCT_OUT0_O ,SCT_OUT0 function assignment" hexmask.long.byte 0x08 16.--23. 1. " SCT_PIN3_I ,SCT_PIN3 function assignment" hexmask.long.byte 0x08 8.--15. 1. " SCT_PIN2_I ,SCT_PIN2 function assignment" hexmask.long.byte 0x08 0.--7. 1. " SCT_PIN1_I ,SCT_PIN1 function assignment" line.long 0x0C "PINASSIGN_8,Pin Assign Register 8" hexmask.long.byte 0x0C 24.--31. 1. " SCT_OUT4_O ,SCT_OUT4 function assignment" hexmask.long.byte 0x0C 16.--23. 1. " SCT_OUT3_O ,SCT_OUT3 function assignment" hexmask.long.byte 0x0C 8.--15. 1. " SCT_OUT2_O ,SCT_OUT2 function assignment" hexmask.long.byte 0x0C 0.--7. 1. " SCT_OUT1_O ,SCT_OUT1 function assignment" line.long 0x10 "PINASSIGN_9,Pin Assign Register 9" hexmask.long.byte 0x10 24.--31. 1. " I2C2_SDA_IO ,I2C2_SDA function assignment" hexmask.long.byte 0x10 16.--23. 1. " I2C1_SCL_IO ,I2C1_SCL function assignment" hexmask.long.byte 0x10 8.--15. 1. " I2C1_SDA_IO ,I2C1_SDA function assignment" hexmask.long.byte 0x10 0.--7. 1. " SCT_OUT5_O ,SCT_OUT5 function assignment" line.long 0x14 "PINASSIGN_10,Pin Assign Register 10" hexmask.long.byte 0x14 24.--31. 1. " ADC_PINTRIG0 ,ADC_PINTRIG0 function assignment" hexmask.long.byte 0x14 16.--23. 1. " I2C3_SCL_IO ,I2C3_SCL function assignment" hexmask.long.byte 0x14 8.--15. 1. " I2C3_SDA_IO ,I2C3_SDA function assignment" hexmask.long.byte 0x14 0.--7. 1. " I2C2_SCL_IO ,I2C2_SCL function assignment" line.long 0x18 "PINASSIGN_11,Pin Assign Register 11" hexmask.long.byte 0x18 24.--31. 1. " GPIO_INT_BMAT_O ,GPIO_INT_BMAT function assignment" hexmask.long.byte 0x18 16.--23. 1. " CLKOUT_O ,CLKOUT function assignment" hexmask.long.byte 0x18 8.--15. 1. " ACMP_O_O ,ACMP_O function assignment" hexmask.long.byte 0x18 0.--7. 1. " ADC_PINTRIG1_I ,ADC_PINTRIG1 function assignment" group.long 0x1C0++0x03 line.long 0x00 "PINENABLE_0,Pin Enable Register 0" bitfld.long 0x00 24. " ADC_11 ,ADC_11 function select" "PIO0_4,Disabled" bitfld.long 0x00 23. " ADC_10 ,ADC_10 function select" "PIO0_13,Disabled" bitfld.long 0x00 22. " ADC_9 ,ADC_9 function select" "PIO0_17,Disabled" bitfld.long 0x00 21. " ADC_8 ,ADC_8 function select" "PIO0_18,Disabled" textline " " bitfld.long 0x00 20. " ADC_7 ,ADC_7 function select" "PIO0_19,Disabled" bitfld.long 0x00 19. " ADC_6 ,ADC_6 function select" "PIO0_20,Disabled" bitfld.long 0x00 18. " ADC_5 ,ADC_5 function select" "PIO0_21,Disabled" bitfld.long 0x00 17. " ADC_4 ,ADC_4 function select" "PIO0_22,Disabled" textline " " bitfld.long 0x00 16. " ADC_3 ,ADC_3 function select" "PIO0_23,Disabled" bitfld.long 0x00 15. " ADC_2 ,ADC_2 function select" "PIO0_14,Disabled" bitfld.long 0x00 14. " ADC_1 ,ADC_1 function select" "PIO0_6,Disabled" bitfld.long 0x00 13. " ADC_0 ,ADC_0 function select" "PIO0_7,Disabled" textline " " bitfld.long 0x00 12. " I2C0_SCL ,I2C0_SCL function select" "PIO0_10,Disabled" bitfld.long 0x00 11. " I2C0_SDA ,I2C0_SDA function select" "PIO0_11,Disabled" bitfld.long 0x00 10. " VDDCMP ,VDDCMP function select" "PIO0_6,Disabled" bitfld.long 0x00 9. " CLKIN ,CLKIN function select" "PIO0_1,Disabled" textline " " bitfld.long 0x00 8. " RESETN ,RESETN function select" "PIO0_5,Disabled" bitfld.long 0x00 7. " XTALOUT ,XTALOUT function select" "PIO0_9,Disabled" bitfld.long 0x00 6. " XTALIN ,XTALIN function select" "PIO0_8,Disabled" bitfld.long 0x00 5. " SWDIO ,SWDIO function select" "PIO0_2,Disabled" textline " " bitfld.long 0x00 4. " SWCLK ,SWCLK function select" "PIO0_3,Disabled" bitfld.long 0x00 3. " ACMP_I4 ,ACMP_I4 function select" "PIO0_23,Disabled" bitfld.long 0x00 2. " ACMP_I3 ,ACMP_I3 function select" "PIO0_14,Disabled" bitfld.long 0x00 1. " ACMP_I2 ,ACMP_I2 function select" "PIO0_1,Disabled" textline " " bitfld.long 0x00 0. " ACMP_I1 ,ACMP_I1 function select" "PIO0_0,Disabled" else group.long 0x14++0x13 line.long 0x00 "PINASSIGN_5,Pin Assign Register 5" hexmask.long.byte 0x00 24.--31. 1. " CTIN_0_I ,CTIN_0 function assignment" sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") textline " " hexmask.long.byte 0x00 16.--23. 1. " SPI1_SSEL_IO ,SPI1_SSEL function assignment" hexmask.long.byte 0x00 8.--15. 1. " SPI1_MISO_IO ,SPI1_MISO function assignment" hexmask.long.byte 0x00 0.--7. 1. " SPI1_MOSI_IO ,SPI1_MOSI function assignment" endif line.long 0x04 "PINASSIGN_6,Pin Assign Register 6" hexmask.long.byte 0x04 24.--31. 1. " CTOUT_0_O ,CTOUT_0 function assignment" hexmask.long.byte 0x04 16.--23. 1. " CTIN_3_I ,CTIN_3 function assignment" hexmask.long.byte 0x04 8.--15. 1. " CTIN_2_I ,CTIN_2 function assignment" hexmask.long.byte 0x04 0.--7. 1. " CTIN_1_I ,CTIN_1 function assignment" line.long 0x08 "PINASSIGN_7,Pin Assign Register 7" hexmask.long.byte 0x08 24.--31. 1. " I2C_SDA_IO ,I2C_SDA function assignment" hexmask.long.byte 0x08 16.--23. 1. " CTOUT_3_O ,CTOUT_3 function assignment" hexmask.long.byte 0x08 8.--15. 1. " CTOUT_2_O ,CTOUT_2 function assignment" hexmask.long.byte 0x08 0.--7. 1. " CTOUT_1_O ,CTOUT_1 function assignment" line.long 0x0C "PINASSIGN_8,Pin Assign Register 8" hexmask.long.byte 0x0C 24.--31. 1. " GPIO_INT_BMAT_O ,GPIO_INT_BMAT function assignment" hexmask.long.byte 0x0C 16.--23. 1. " CLKOUT_O ,CLKOUT function assignment" hexmask.long.byte 0x0C 8.--15. 1. " ACMP_O_O ,ACMP_O function assignment" hexmask.long.byte 0x0C 0.--7. 1. " I2C_SCL_IO ,I2C_SCL_IO function assignment" group.long 0x1C0++0x03 line.long 0x00 "PINENABLE_0,Pin Enable Register 0" sif cpu()!="LPC810M021FN8" bitfld.long 0x00 8. " VDDCMP ,Enables fixed-pin function VDDCMP on PIO0_6" "Enabled,Disabled" textline " " endif bitfld.long 0x00 7. " CLKIN ,Enables fixed-pin function CLKIN on PIO0_1" "Enabled,Disabled" bitfld.long 0x00 6. " RESET_EN ,Enables fixed-pin function RESET on PIO0_5" "Enabled,Disabled" sif cpu()!="LPC810M021FN8" bitfld.long 0x00 5. " XTALOUT_EN ,Enables fixed-pin function XTALOUT on PIO0_9" "Enabled,Disabled" bitfld.long 0x00 4. " XTALIN_EN ,Enables fixed-pin function XTALIN on PIO0_8" "Enabled,Disabled" endif textline " " bitfld.long 0x00 3. " SWDIO_EN ,Enables fixed-pin function SWDIO on PIO0_2" "Enabled,Disabled" bitfld.long 0x00 2. " SWCLK_EN ,Enables fixed-pin function SWCLK on PIO0_3" "Enabled,Disabled" bitfld.long 0x00 1. " ACMP_I2_EN ,Enables fixed-pin function ACMP_I2 on PIO0_1" "Enabled,Disabled" bitfld.long 0x00 0. " ACMP_I1_EN ,Enables fixed-pin function ACMP_I1 on PIO0_0" "Enabled,Disabled" endif width 0x0B tree.end endif endif sif !cpuis("LPC80*")&&!cpuis("LPC8N04") tree "SCT (State Configurable Timer)" base ad:0x50004000 sif (cpuis("LPC82*")) width 15. if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT configuration register" bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on Match Register 0 as a limit condition" "Disabled,Enabled" textline " " sif (!cpuis("LPC82*")) bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled" bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled" bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled" textline " " endif bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled" bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled" bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " NORELAOD ,Prevents the lower and higher match registers from being reloaded" "Disabled,Enabled" textline " " bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),?..." sif (cpuis("LPC82*")) textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System Clock,Sampled System Clock,SCT Input Clock,Asynchronous" else textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field" endif textline " " bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit" group.long 0x04++0x03 line.long 0x00 "CTRL_L,SCT control register" hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock" bitfld.long 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit condition,Limit" textline " " bitfld.long 0x00 3. " CLRCTR_L ,Writing a 1 to this bit clears the L or unified counter" "No action,Clear" bitfld.long 0x00 2. " HALT_L ,When this bit is 1, the L or unified counter does not run and no events can occur" "Run,Not run" textline " " bitfld.long 0x00 1. " STOP_L ,When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur" "Run,Not run" bitfld.long 0x00 0. " DOWN_L ,This bit is 1 when the L or unified counter is counting down" "No action,Counting down" group.long 0x08++0x03 line.long 0x00 "LIMIT_L,SCT limit register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " LIMMSK_L7 ,Counter limit L event 7" "Not occurred,Occurred" bitfld.long 0x00 6. " LIMMSK_L6 ,Counter limit L event 6" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 5. " LIMMSK_L5 ,Counter limit L event 5" "Not occurred,Occurred" bitfld.long 0x00 4. " LIMMSK_L4 ,Counter limit L event 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " LIMMSK_L3 ,Counter limit L event 3" "Not occurred,Occurred" bitfld.long 0x00 2. " LIMMSK_L2 ,Counter limit L event 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " LIMMSK_L1 ,Counter limit L event 1" "Not occurred,Occurred" bitfld.long 0x00 0. " LIMMSK_L0 ,Counter limit L event 0" "Not occurred,Occurred" group.long 0x0C++0x03 line.long 0x00 "HALT_L,SCT halt condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted" bitfld.long 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted" textline " " endif bitfld.long 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.long 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" textline " " bitfld.long 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted" bitfld.long 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted" textline " " bitfld.long 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted" bitfld.long 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted" group.long 0x10++0x03 line.long 0x00 "STOP_L,SCT stop condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STOPMSK_L7 ,Event 7 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 6. " STOPMSK_L6 ,Event 6 counter Stopped" "Not stopped,Stopped" textline " " endif bitfld.long 0x00 5. " STOPMSK_L5 ,Event 6 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 4. " STOPMSK_L4 ,Event 4 counter Stopped" "Not stopped,Stopped" textline " " bitfld.long 0x00 3. " STOPMSK_L3 ,Event 3 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 2. " STOPMSK_L2 ,Event 2 counter Stopped" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " STOPMSK_L1 ,Event 1 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 0. " STOPMSK_L0 ,Event 0 counter Stopped" "Not stopped,Stopped" group.long 0x14++0x03 line.long 0x00 "START_L,SCT start condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STARTMSK_L7 ,Event 7 counter Started" "Not started,Started" bitfld.long 0x00 6. " STARTMSK_L6 ,Event 6 counter Started" "Not started,Started" textline " " endif bitfld.long 0x00 5. " STARTMSK_L5 ,Event 5 counter Started" "Not started,Started" bitfld.long 0x00 4. " STARTMSK_L4 ,Event 4 counter Started" "Not started,Started" textline " " bitfld.long 0x00 3. " STARTMSK_L3 ,Event 3 counter Started" "Not started,Started" bitfld.long 0x00 2. " STARTMSK_L2 ,Event 2 counter Started" "Not started,Started" textline " " bitfld.long 0x00 1. " STARTMSK_L1 ,Event 1 counter Started" "Not started,Started" bitfld.long 0x00 0. " STARTMSK_L0 ,Event 0 counter Started" "Not started,Started" group.long 0x40++0x03 line.long 0x00 "COUNT_L,SCT counter register" hexmask.long.word 0x00 0.--15. 1. " CTR_L ,L counter value" group.long 0x44++0x03 line.long 0x00 "STATE_L,SCT state register" bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT configuration register" bitfld.long 0x00 18. " AUTOLIMIT_H ,Treat match on Match Register 0 as a limit condition" "Disabled,Enabled" bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on Match Register 0 as a limit condition" "Disabled,Enabled" textline " " sif (!cpuis("LPC82*")) bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled" bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled" bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled" textline " " endif bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled" bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled" bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " NORELOADH , Prevents the higher match registers from being reloaded" "Disabled,Enabled" bitfld.long 0x00 7. " NORELAODL ,Prevents the lower match registers from being reloaded " "Disabled,Enabled" textline " " bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),?..." sif (cpuis("LPC82*")) textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System Clock,Sampled System Clock,SCT Input Clock,Asynchronous" else textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field" endif textline " " bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit" group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT control register" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock" bitfld.word 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit condition,Limit" textline " " bitfld.word 0x00 3. " CLRCTR_L ,Writing a 1 to this bit clears the L or unified counter" "No action,Clear" bitfld.word 0x00 2. " HALT_L ,When this bit is 1, the L or unified counter does not run and no events can occur" "Run,Not run" textline " " bitfld.word 0x00 1. " STOP_L ,When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur" "Run,Not run" bitfld.word 0x00 0. " DOWN_L ,This bit is 1 when the L or unified counter is counting down" "No action,Counting down" line.word 0x02 "CTRL_H,SCT control register" hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter lock" bitfld.word 0x02 4. " BIDIR_H ,Direction select" "Limit condition,Limit" textline " " bitfld.word 0x02 3. " CLRCTR_H ,Writing a 1 to this bit clears the H counter" "No action,Clear" bitfld.word 0x02 2. " HALT_H ,When this bit is 1, the H counter does not run and no events can occur" "Run,Not run" textline " " bitfld.word 0x02 1. " STOP_H ,When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur" "Run,Not run" bitfld.word 0x02 0. " DOWN_H ,This bit is 1 when the H counter is counting down" "No action,Counting down" group.word 0x08++0x03 line.word 0x00 "LIMIT_L,SCT limit register" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " LIMMSK_L7 ,Counter limit L event 7" "Not occurred,Occurred" bitfld.word 0x00 6. " LIMMSK_L6 ,Counter limit L event 6" "Not occurred,Occurred" textline " " bitfld.word 0x00 5. " LIMMSK_L5 ,Counter limit L event 5" "Not occurred,Occurred" bitfld.word 0x00 4. " LIMMSK_L4 ,Counter limit L event 4" "Not occurred,Occurred" textline " " else bitfld.word 0x00 5. " LIMMSK_L5 ,Counter limit L event 5" "Not occurred,Occurred" bitfld.word 0x00 4. " LIMMSK_L4 ,Counter limit L event 4" "Not occurred,Occurred" textline " " endif bitfld.word 0x00 3. " LIMMSK_L3 ,Counter limit L event 3" "Not occurred,Occurred" bitfld.word 0x00 2. " LIMMSK_L2 ,Counter limit L event 2" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " LIMMSK_L1 ,Counter limit L event 1" "Not occurred,Occurred" bitfld.word 0x00 0. " LIMMSK_L0 ,Counter limit L event 0" "Not occurred,Occurred" line.word 0x02 "LIMIT_H,SCT limit register" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " LIMMSK_H23 ,Counter limit H event 23" "Not occurred,Occurred" bitfld.word 0x02 6. " LIMMSK_H22 ,Counter limit H event 22" "Not occurred,Occurred" textline " " bitfld.word 0x02 5. " LIMMSK_H21 ,Counter limit H event 21" "Not occurred,Occurred" bitfld.word 0x02 4. " LIMMSK_H20 ,Counter limit H event 20" "Not occurred,Occurred" textline " " else bitfld.word 0x02 5. " LIMMSK_H21 ,Counter limit H event 21" "Not occurred,Occurred" bitfld.word 0x02 4. " LIMMSK_H20 ,Counter limit H event 20" "Not occurred,Occurred" textline " " endif bitfld.word 0x02 3. " LIMMSK_H19 ,Counter limit H event 19" "Not occurred,Occurred" bitfld.word 0x02 2. " LIMMSK_H18 ,Counter limit H event 18" "Not occurred,Occurred" textline " " bitfld.word 0x02 1. " LIMMSK_H17 ,Counter limit H event 17" "Not occurred,Occurred" bitfld.word 0x02 0. " LIMMSK_H16 ,Counter limit H event 16" "Not occurred,Occurred" group.word 0x0C++0x03 line.word 0x00 "HALT_L,SCT halt condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted" bitfld.word 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted" textline " " bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" textline " " else bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" textline " " endif bitfld.word 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted" bitfld.word 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted" textline " " bitfld.word 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted" bitfld.word 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted" line.word 0x02 "HALT_H,SCT halt condition register high counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " HALTMSK_H23 ,Counter halted H event 23" "Not halted,Halted" bitfld.word 0x02 6. " HALTMSK_H22 ,Counter halted H event 22" "Not halted,Halted" textline " " bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted" bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted" textline " " else bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted" bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted" textline " " endif bitfld.word 0x02 3. " HALTMSK_H19 ,Counter halted H event 19" "Not halted,Halted" bitfld.word 0x02 2. " HALTMSK_H18 ,Counter halted H event 18" "Not halted,Halted" textline " " bitfld.word 0x02 1. " HALTMSK_H17 ,Counter halted H event 17" "Not halted,Halted" bitfld.word 0x02 0. " HALTMSK_H16 ,Counter halted H event 16" "Not halted,Halted" group.word 0x10++0x03 line.word 0x00 "STOP_L,SCT stop condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " STOPMSK_L7 ,Event 7 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 6. " STOPMSK_L6 ,Event 6 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter Stopped" "Not stopped,Stopped" textline " " else bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter Stopped" "Not stopped,Stopped" textline " " endif bitfld.word 0x00 3. " STOPMSK_L3 ,Event 3 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 2. " STOPMSK_L2 ,Event 2 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x00 1. " STOPMSK_L1 ,Event 1 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 0. " STOPMSK_L0 ,Event 0 counter Stopped" "Not stopped,Stopped" line.word 0x02 "STOP_H,SCT stop condition register high counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " STOPMSK_H23 ,Event 23 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 6. " STOPMSK_H22 ,Event 22 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter Stopped" "Not stopped,Stopped" textline " " else bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter Stopped" "Not stopped,Stopped" textline " " endif bitfld.word 0x02 3. " STOPMSK_H19 ,Event 19 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 2. " STOPMSK_H18 ,Event 18 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x02 1. " STOPMSK_H17 ,Event 17 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 0. " STOPMSK_H16 ,Event 16 counter Stopped" "Not stopped,Stopped" group.word 0x14++0x03 line.word 0x00 "START_L,SCT start condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " STARTMSK_L7 ,Event 7 counter Started" "Not started,Started" bitfld.word 0x00 6. " STARTMSK_L6 ,Event 6 counter Started" "Not started,Started" textline " " bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter Started" "Not started,Started" bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter Started" "Not started,Started" textline " " else bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter Started" "Not started,Started" bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter Started" "Not started,Started" textline " " endif bitfld.word 0x00 3. " STARTMSK_L3 ,Event 3 counter Started" "Not started,Started" bitfld.word 0x00 2. " STARTMSK_L2 ,Event 2 counter Started" "Not started,Started" textline " " bitfld.word 0x00 1. " STARTMSK_L1 ,Event 1 counter Started" "Not started,Started" bitfld.word 0x00 0. " STARTMSK_L0 ,Event 0 counter Started" "Not started,Started" line.word 0x02 "START_H,SCT start condition register high counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " STARTMSK_H23 ,Event 23 counter Started" "Not started,Started" bitfld.word 0x02 6. " STARTMSK_H22 ,Event 22 counter Started" "Not started,Started" textline " " bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter Started" "Not started,Started" bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter Started" "Not started,Started" textline " " else bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter Started" "Not started,Started" bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter Started" "Not started,Started" textline " " endif bitfld.word 0x02 3. " STARTMSK_H19 ,Event 19 counter Started" "Not started,Started" bitfld.word 0x02 2. " STARTMSK_H18 ,Event 18 counter Started" "Not started,Started" textline " " bitfld.word 0x02 1. " STARTMSK_H17 ,Event 17 counter Started" "Not started,Started" bitfld.word 0x02 0. " STARTMSK_H16 ,Event 16 counter Started" "Not started,Started" group.word 0x40++0x03 line.word 0x00 "COUNT_L,SCT counter register" line.word 0x02 "COUNT_H,SCT counter register" group.word 0x44++0x03 line.word 0x00 "STATE_L,SCT state register" bitfld.word 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "STATE_H,SCT state register" bitfld.word 0x02 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif textline " " rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT input register" bitfld.long 0x00 19. " SIN3 ,Input 3 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 18. " SIN2 ,Input 2 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 17. " SIN1 ,Input 1 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 16. " SIN0 ,Input 0 state synchronized to the SCT clock" "0,1" textline " " bitfld.long 0x00 3. " AIN3 ,Real-time status of input 3" "0,1" bitfld.long 0x00 2. " AIN2 ,Real-time status of input 2" "0,1" bitfld.long 0x00 1. " AIN1 ,Real-time status of input 1" "0,1" bitfld.long 0x00 0. " AIN0 ,Real-time status of input 0" "0,1" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x4C++0x03 line.long 0x00 "REGMODE_L,SCT match/capture registers mode register" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " REGMOD_L7 ,8th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 6. " REGMOD_L6 ,7th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 5. " REGMOD_L5 ,6th pair of match/capture registers" "Match,Capture" textline " " endif bitfld.long 0x00 4. " REGMOD_L4 ,5th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 3. " REGMOD_L3 ,4th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 2. " REGMOD_L2 ,3rd pair of match/capture registers" "Match,Capture" bitfld.long 0x00 1. " REGMOD_L1 ,2nd pair of match/capture registers" "Match,Capture" textline " " bitfld.long 0x00 0. " REGMOD_L0 ,1th pair of match/capture registers" "Match,Capture" else group.word 0x4C++0x03 line.word 0x00 "REGMODE_L,SCT match/capture registers mode register" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " REGMOD_L7 ,8th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 6. " REGMOD_L6 ,7th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 5. " REGMOD_L5 ,6th pair of match/capture registers" "Match,Capture" textline " " endif bitfld.word 0x00 4. " REGMOD_L4 ,5th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 3. " REGMOD_L3 ,4th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 2. " REGMOD_L2 ,3rd pair of match/capture registers" "Match,Capture" bitfld.word 0x00 1. " REGMOD_L1 ,2nd pair of match/capture registers" "Match,Capture" textline " " bitfld.word 0x00 0. " REGMOD_L0 ,1th pair of match/capture registers" "Match,Capture" line.word 0x02 "REGMODE_H,SCT match/capture registers mode register" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " REGMOD_H7 ,8th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 6. " REGMOD_H6 ,7th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 5. " REGMOD_H5 ,6th pair of match/capture registers" "Match,Capture" textline " " endif bitfld.word 0x02 4. " REGMOD_H4 ,5th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 3. " REGMOD_H3 ,4th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 2. " REGMOD_H2 ,3rd pair of match/capture registers" "Match,Capture" bitfld.word 0x02 1. " REGMOD_H1 ,2nd pair of match/capture registers" "Match,Capture" textline " " bitfld.word 0x02 0. " REGMOD_H0 ,1th pair of match/capture registers" "Match,Capture" endif group.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT output register" sif (cpuis("LPC82*")) bitfld.long 0x00 5. " OUT5 ,Output 5" "Low,High" bitfld.long 0x00 4. " OUT4 ,Output 4" "Low,High" textline " " endif bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High" bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High" bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High" bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High" textline " " if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT bidirectional output control register" sif (cpuis("LPC82*")) bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,?..." bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,?..." textline " " endif bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,?..." bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,?..." bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,?..." textline " " bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT bidirectional output control register" sif (cpuis("LPC82*")) bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,H is counting down,?..." textline " " endif bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,H is counting down,?..." textline " " bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,H is counting down,?..." endif group.long 0x58++0x03 line.long 0x00 "RES,SCT conflict resolution register" sif (cpuis("LPC82*")) bitfld.long 0x00 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set output,Clear output,Toggle output" textline " " endif bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set output,Clear output,Toggle output" textline " " bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set output,Clear output,Toggle output" sif (cpuis("LPC82*")) group.long 0x5C++0x07 line.long 0x00 "DMAREQ0,SCT DMA 0 request register" rbitfld.long 0x00 31. " DRQ0 ,This read-only bit indicates the state of DMA Request 0" "Not requested,Requested" bitfld.long 0x00 30. " DRL0 ,The SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Not requested,Requested" textline " " bitfld.long 0x00 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 4. " DEV_0[4] ,Event 4 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 3. " DEV_0[3] ,Event 3 sets DMA request 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " DEV_0[2] ,Event 2 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 1. " DEV_0[1] ,Event 1 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 0. " DEV_0[0] ,Event 0 sets DMA request 0" "Not requested,Requested" line.long 0x04 "DMAREQ1,SCT DMA 1 request register" rbitfld.long 0x04 31. " DRQ1 ,This read-only bit indicates the state of DMA request 1" "Not requested,Requested" bitfld.long 0x04 30. " DRL1 ,The SCT set DMA request 1 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Not requested,Requested" textline " " bitfld.long 0x04 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 4. " DEV_1[4] ,Event 4 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 3. " DEV_1[3] ,Event 3 sets DMA request 1" "Not requested,Requested" textline " " bitfld.long 0x04 2. " DEV_1[2] ,Event 2 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 1. " DEV_1[1] ,Event 1 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 0. " DEV_1[0] ,Event 0 sets DMA request 1" "Not requested,Requested" endif group.long 0xF0++0x0F line.long 0x00 "EVEN,SCT flag enable register" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " IEN7 ,Enables flag 7 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " IEN6 ,Enables flag 6 to request an interrupt" "Disabled,Enabled" textline " " endif bitfld.long 0x00 5. " IEN5 ,Enables flag 5 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " IEN4 ,Enables flag 4 to request an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IEN3 ,Enables flag 3 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " IEN2 ,Enables flag 2 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " IEN1 ,Enables flag 1 to request an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " IEN0 ,Enables flag 0 to request an interrupt" "Disabled,Enabled" line.long 0x04 "EVFLAG,SCT event flag register" sif (cpuis("LPC82*")) eventfld.long 0x04 7. " FLAG7 ,Event 7 occurred" "Not occurred,Occurred" eventfld.long 0x04 6. " FLAG6 ,Event 6 occurred" "Not occurred,Occurred" textline " " endif eventfld.long 0x04 5. " FLAG5 ,Event 5 occurred" "Not occurred,Occurred" eventfld.long 0x04 4. " FLAG4 ,Event 4 occurred" "Not occurred,Occurred" textline " " eventfld.long 0x04 3. " FLAG3 ,Event 3 occurred" "Not occurred,Occurred" eventfld.long 0x04 2. " FLAG2 ,Event 2 occurred" "Not occurred,Occurred" eventfld.long 0x04 1. " FLAG1 ,Event 1 occurred" "Not occurred,Occurred" textline " " eventfld.long 0x04 0. " FLAG0 ,Event 0 occurred" "Not occurred,Occurred" line.long 0x08 "CONEN,SCT conflict enable register" sif (cpuis("LPC82*")) bitfld.long 0x08 5. " NCEN5 ,No change conflict event 5 enable" "Disabled,Enabled" bitfld.long 0x08 4. " NCEN4 ,No change conflict event 4 enable" "Disabled,Enabled" textline " " endif bitfld.long 0x08 3. " NCEN3 ,No change conflict event 3 enable" "Disabled,Enabled" bitfld.long 0x08 2. " NCEN2 ,No change conflict event 2 enable" "Disabled,Enabled" bitfld.long 0x08 1. " NCEN1 ,No change conflict event 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " NCEN0 ,No change conflict event 0 enable" "Disabled,Enabled" line.long 0x0C "CONFLAG,SCT conflict flag register" bitfld.long 0x0C 31. " BUSERRH ,Bus error" "No error,Error" bitfld.long 0x0C 30. " BUSERRL ,Bus error" "No error,Error" textline " " sif (cpuis("LPC82*")) bitfld.long 0x0C 5. " NCFLAG5 ,No-change conflict event 5 occurred" "Not occurred,Occurred" bitfld.long 0x0C 4. " NCFLAG4 ,No-change conflict event 4 occurred" "Not occurred,Occurred" textline " " endif bitfld.long 0x0C 3. " NCFLAG3 ,No-change conflict event 3 occurred" "Not occurred,Occurred" textline " " bitfld.long 0x0C 2. " NCFLAG2 ,No-change conflict event 2 occurred" "Not occurred,Occurred" bitfld.long 0x0C 1. " NCFLAG1 ,No-change conflict event 1 occurred" "Not occurred,Occurred" bitfld.long 0x0C 0. " NCFLAG0 ,No-change conflict event 0 occurred" "Not occurred,Occurred" width 26. tree "Channel 0 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x100++0x03 line.long 0x00 "MATCH0/CAP0,SCT match/capture register 0" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 0" "Disabled,Enabled" group.long (0x100+0x100)++0x03 line.long 0x00 "MATCHREL0/CAPCTRL0,SCT match/capture reload register 0" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x100++0x03 line.word 0x00 "MATCH0_L/CAP0_L,SCT match/capture register 0" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 0" "Disabled,Enabled" line.word 0x02 "MATCH0_H/CAP0_H,SCT match/capture register 0" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 0" "Disabled,Enabled" group.word (0x100+0x100)++0x03 line.word 0x00 "MATCHREL0_L/CAPCTRL0_L,SCT match/capture reload register 0" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL0_H/CAPCTRL0_H,SCT match/capture reload register 0" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x100+0x200)++0x07 line.long 0x00 "EVSTATEMSK0,SCT event state mask 0" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL0,SCT event control register 0" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x100+0x400)++0x07 line.long 0x00 "OUTPUTSET0,SCT output set register 0" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 0" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 0" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 0" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 0" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 0" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 0" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 0" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 0" "Not set,Set" line.long 0x04 "OUTPUTCLR0,SCT output clear register 0" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 0" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 0" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 0" "Not cleared,Cleared" tree.end tree "Channel 1 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x104++0x03 line.long 0x00 "MATCH1/CAP1,SCT match/capture register 1" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 1" "Disabled,Enabled" group.long (0x104+0x100)++0x03 line.long 0x00 "MATCHREL1/CAPCTRL1,SCT match/capture reload register 1" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x104++0x03 line.word 0x00 "MATCH1_L/CAP1_L,SCT match/capture register 1" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 1" "Disabled,Enabled" line.word 0x02 "MATCH1_H/CAP1_H,SCT match/capture register 1" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 1" "Disabled,Enabled" group.word (0x104+0x100)++0x03 line.word 0x00 "MATCHREL1_L/CAPCTRL1_L,SCT match/capture reload register 1" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL1_H/CAPCTRL1_H,SCT match/capture reload register 1" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x108+0x200)++0x07 line.long 0x00 "EVSTATEMSK1,SCT event state mask 1" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL1,SCT event control register 1" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x108+0x400)++0x07 line.long 0x00 "OUTPUTSET1,SCT output set register 1" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 1" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 1" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 1" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 1" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 1" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 1" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 1" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 1" "Not set,Set" line.long 0x04 "OUTPUTCLR1,SCT output clear register 1" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 1" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 1" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 1" "Not cleared,Cleared" tree.end tree "Channel 2 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x108++0x03 line.long 0x00 "MATCH2/CAP2,SCT match/capture register 2" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 2" "Disabled,Enabled" group.long (0x108+0x100)++0x03 line.long 0x00 "MATCHREL2/CAPCTRL2,SCT match/capture reload register 2" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x108++0x03 line.word 0x00 "MATCH2_L/CAP2_L,SCT match/capture register 2" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 2" "Disabled,Enabled" line.word 0x02 "MATCH2_H/CAP2_H,SCT match/capture register 2" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 2" "Disabled,Enabled" group.word (0x108+0x100)++0x03 line.word 0x00 "MATCHREL2_L/CAPCTRL2_L,SCT match/capture reload register 2" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL2_H/CAPCTRL2_H,SCT match/capture reload register 2" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x110+0x200)++0x07 line.long 0x00 "EVSTATEMSK2,SCT event state mask 2" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL2,SCT event control register 2" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x110+0x400)++0x07 line.long 0x00 "OUTPUTSET2,SCT output set register 2" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 2" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 2" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 2" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 2" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 2" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 2" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 2" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 2" "Not set,Set" line.long 0x04 "OUTPUTCLR2,SCT output clear register 2" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 2" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 2" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 2" "Not cleared,Cleared" tree.end tree "Channel 3 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x10C++0x03 line.long 0x00 "MATCH3/CAP3,SCT match/capture register 3" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 3" "Disabled,Enabled" group.long (0x10C+0x100)++0x03 line.long 0x00 "MATCHREL3/CAPCTRL3,SCT match/capture reload register 3" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x10C++0x03 line.word 0x00 "MATCH3_L/CAP3_L,SCT match/capture register 3" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 3" "Disabled,Enabled" line.word 0x02 "MATCH3_H/CAP3_H,SCT match/capture register 3" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 3" "Disabled,Enabled" group.word (0x10C+0x100)++0x03 line.word 0x00 "MATCHREL3_L/CAPCTRL3_L,SCT match/capture reload register 3" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL3_H/CAPCTRL3_H,SCT match/capture reload register 3" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x118+0x200)++0x07 line.long 0x00 "EVSTATEMSK3,SCT event state mask 3" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL3,SCT event control register 3" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x118+0x400)++0x07 line.long 0x00 "OUTPUTSET3,SCT output set register 3" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 3" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 3" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 3" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 3" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 3" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 3" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 3" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 3" "Not set,Set" line.long 0x04 "OUTPUTCLR3,SCT output clear register 3" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 3" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 3" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 3" "Not cleared,Cleared" tree.end tree "Channel 4 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x110++0x03 line.long 0x00 "MATCH4/CAP4,SCT match/capture register 4" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 4" "Disabled,Enabled" group.long (0x110+0x100)++0x03 line.long 0x00 "MATCHREL4/CAPCTRL4,SCT match/capture reload register 4" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x110++0x03 line.word 0x00 "MATCH4_L/CAP4_L,SCT match/capture register 4" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 4" "Disabled,Enabled" line.word 0x02 "MATCH4_H/CAP4_H,SCT match/capture register 4" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 4" "Disabled,Enabled" group.word (0x110+0x100)++0x03 line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT match/capture reload register 4" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT match/capture reload register 4" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x120+0x200)++0x07 line.long 0x00 "EVSTATEMSK4,SCT event state mask 4" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL4,SCT event control register 4" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x120+0x400)++0x07 line.long 0x00 "OUTPUTSET4,SCT output set register 4" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 4" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 4" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 4" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 4" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 4" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 4" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 4" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 4" "Not set,Set" line.long 0x04 "OUTPUTCLR4,SCT output clear register 4" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 4" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 4" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 4" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 4" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 4" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 4" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 4" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 4" "Not cleared,Cleared" tree.end tree "Channel 5 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x114++0x03 line.long 0x00 "MATCH5/CAP5,SCT match/capture register 5" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 5" "Disabled,Enabled" group.long (0x114+0x100)++0x03 line.long 0x00 "MATCHREL5/CAPCTRL5,SCT match/capture reload register 5" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x114++0x03 line.word 0x00 "MATCH5_L/CAP5_L,SCT match/capture register 5" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 5" "Disabled,Enabled" line.word 0x02 "MATCH5_H/CAP5_H,SCT match/capture register 5" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 5" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 5" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 5" "Disabled,Enabled" group.word (0x114+0x100)++0x03 line.word 0x00 "MATCHREL5_L/CAPCTRL5_L,SCT match/capture reload register 5" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL5_H/CAPCTRL5_H,SCT match/capture reload register 5" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x128+0x200)++0x07 line.long 0x00 "EVSTATEMSK5,SCT event state mask 5" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL5,SCT event control register 5" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x128+0x400)++0x07 line.long 0x00 "OUTPUTSET5,SCT output set register 5" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 5" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 5" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 5" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 5" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 5" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 5" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 5" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 5" "Not set,Set" line.long 0x04 "OUTPUTCLR5,SCT output clear register 5" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 5" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 5" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 5" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 5" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 5" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 5" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 5" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 5" "Not cleared,Cleared" tree.end tree "Channel 6 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x118++0x03 line.long 0x00 "MATCH6/CAP6,SCT match/capture register 6" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 6" "Disabled,Enabled" group.long (0x118+0x100)++0x03 line.long 0x00 "MATCHREL6/CAPCTRL6,SCT match/capture reload register 6" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x118++0x03 line.word 0x00 "MATCH6_L/CAP6_L,SCT match/capture register 6" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 6" "Disabled,Enabled" line.word 0x02 "MATCH6_H/CAP6_H,SCT match/capture register 6" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 6" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 6" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 6" "Disabled,Enabled" group.word (0x118+0x100)++0x03 line.word 0x00 "MATCHREL6_L/CAPCTRL6_L,SCT match/capture reload register 6" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL6_H/CAPCTRL6_H,SCT match/capture reload register 6" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x130+0x200)++0x07 line.long 0x00 "EVSTATEMSK6,SCT event state mask 6" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL6,SCT event control register 6" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel 7 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x11C++0x03 line.long 0x00 "MATCH7/CAP7,SCT match/capture register 7" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 7" "Disabled,Enabled" group.long (0x11C+0x100)++0x03 line.long 0x00 "MATCHREL7/CAPCTRL7,SCT match/capture reload register 7" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x11C++0x03 line.word 0x00 "MATCH7_L/CAP7_L,SCT match/capture register 7" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 7" "Disabled,Enabled" line.word 0x02 "MATCH7_H/CAP7_H,SCT match/capture register 7" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 7" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 7" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 7" "Disabled,Enabled" group.word (0x11C+0x100)++0x03 line.word 0x00 "MATCHREL7_L/CAPCTRL7_L,SCT match/capture reload register 7" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL7_H/CAPCTRL7_H,SCT match/capture reload register 7" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x138+0x200)++0x07 line.long 0x00 "EVSTATEMSK7,SCT event state mask 7" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL7,SCT event control register 7" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 0x0B elif (cpuis("LPC812M101J*")) width 15. if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT configuration register" bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on Match Register 0 as a limit condition" "Disabled,Enabled" textline " " sif (!cpuis("LPC82*")) bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled" bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled" bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled" textline " " endif bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled" bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled" bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " NORELAOD ,Prevents the lower and higher match registers from being reloaded" "Disabled,Enabled" textline " " bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),?..." sif (cpuis("LPC82*")) textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System Clock,Sampled System Clock,SCT Input Clock,Asynchronous" else textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field" endif textline " " bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit" group.long 0x04++0x03 line.long 0x00 "CTRL_L,SCT control register" hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock" bitfld.long 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit condition,Limit" textline " " bitfld.long 0x00 3. " CLRCTR_L ,Writing a 1 to this bit clears the L or unified counter" "No action,Clear" bitfld.long 0x00 2. " HALT_L ,When this bit is 1, the L or unified counter does not run and no events can occur" "Run,Not run" textline " " bitfld.long 0x00 1. " STOP_L ,When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur" "Run,Not run" bitfld.long 0x00 0. " DOWN_L ,This bit is 1 when the L or unified counter is counting down" "No action,Counting down" group.long 0x08++0x03 line.long 0x00 "LIMIT_L,SCT limit register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " LIMMSK_L7 ,Counter limit L event 7" "Not occurred,Occurred" bitfld.long 0x00 6. " LIMMSK_L6 ,Counter limit L event 6" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 5. " LIMMSK_L5 ,Counter limit L event 5" "Not occurred,Occurred" bitfld.long 0x00 4. " LIMMSK_L4 ,Counter limit L event 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " LIMMSK_L3 ,Counter limit L event 3" "Not occurred,Occurred" bitfld.long 0x00 2. " LIMMSK_L2 ,Counter limit L event 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " LIMMSK_L1 ,Counter limit L event 1" "Not occurred,Occurred" bitfld.long 0x00 0. " LIMMSK_L0 ,Counter limit L event 0" "Not occurred,Occurred" group.long 0x0C++0x03 line.long 0x00 "HALT_L,SCT halt condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted" bitfld.long 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted" textline " " endif bitfld.long 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.long 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" textline " " bitfld.long 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted" bitfld.long 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted" textline " " bitfld.long 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted" bitfld.long 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted" group.long 0x10++0x03 line.long 0x00 "STOP_L,SCT stop condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STOPMSK_L7 ,Event 7 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 6. " STOPMSK_L6 ,Event 6 counter Stopped" "Not stopped,Stopped" textline " " endif bitfld.long 0x00 5. " STOPMSK_L5 ,Event 6 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 4. " STOPMSK_L4 ,Event 4 counter Stopped" "Not stopped,Stopped" textline " " bitfld.long 0x00 3. " STOPMSK_L3 ,Event 3 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 2. " STOPMSK_L2 ,Event 2 counter Stopped" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " STOPMSK_L1 ,Event 1 counter Stopped" "Not stopped,Stopped" bitfld.long 0x00 0. " STOPMSK_L0 ,Event 0 counter Stopped" "Not stopped,Stopped" group.long 0x14++0x03 line.long 0x00 "START_L,SCT start condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STARTMSK_L7 ,Event 7 counter Started" "Not started,Started" bitfld.long 0x00 6. " STARTMSK_L6 ,Event 6 counter Started" "Not started,Started" textline " " endif bitfld.long 0x00 5. " STARTMSK_L5 ,Event 5 counter Started" "Not started,Started" bitfld.long 0x00 4. " STARTMSK_L4 ,Event 4 counter Started" "Not started,Started" textline " " bitfld.long 0x00 3. " STARTMSK_L3 ,Event 3 counter Started" "Not started,Started" bitfld.long 0x00 2. " STARTMSK_L2 ,Event 2 counter Started" "Not started,Started" textline " " bitfld.long 0x00 1. " STARTMSK_L1 ,Event 1 counter Started" "Not started,Started" bitfld.long 0x00 0. " STARTMSK_L0 ,Event 0 counter Started" "Not started,Started" group.long 0x40++0x03 line.long 0x00 "COUNT_L,SCT counter register" hexmask.long.word 0x00 0.--15. 1. " CTR_L ,L counter value" group.long 0x44++0x03 line.long 0x00 "STATE_L,SCT state register" bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT configuration register" bitfld.long 0x00 18. " AUTOLIMIT_H ,Treat match on Match Register 0 as a limit condition" "Disabled,Enabled" bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on Match Register 0 as a limit condition" "Disabled,Enabled" textline " " sif (!cpuis("LPC82*")) bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled" bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled" bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled" textline " " endif bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled" bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled" bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " NORELOADH , Prevents the higher match registers from being reloaded" "Disabled,Enabled" bitfld.long 0x00 7. " NORELAODL ,Prevents the lower match registers from being reloaded " "Disabled,Enabled" textline " " bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),?..." sif (cpuis("LPC82*")) textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System Clock,Sampled System Clock,SCT Input Clock,Asynchronous" else textline " " bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field" endif textline " " bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit" group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT control register" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock" bitfld.word 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit condition,Limit" textline " " bitfld.word 0x00 3. " CLRCTR_L ,Writing a 1 to this bit clears the L or unified counter" "No action,Clear" bitfld.word 0x00 2. " HALT_L ,When this bit is 1, the L or unified counter does not run and no events can occur" "Run,Not run" textline " " bitfld.word 0x00 1. " STOP_L ,When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur" "Run,Not run" bitfld.word 0x00 0. " DOWN_L ,This bit is 1 when the L or unified counter is counting down" "No action,Counting down" line.word 0x02 "CTRL_H,SCT control register" hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter lock" bitfld.word 0x02 4. " BIDIR_H ,Direction select" "Limit condition,Limit" textline " " bitfld.word 0x02 3. " CLRCTR_H ,Writing a 1 to this bit clears the H counter" "No action,Clear" bitfld.word 0x02 2. " HALT_H ,When this bit is 1, the H counter does not run and no events can occur" "Run,Not run" textline " " bitfld.word 0x02 1. " STOP_H ,When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur" "Run,Not run" bitfld.word 0x02 0. " DOWN_H ,This bit is 1 when the H counter is counting down" "No action,Counting down" group.word 0x08++0x03 line.word 0x00 "LIMIT_L,SCT limit register" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " LIMMSK_L7 ,Counter limit L event 7" "Not occurred,Occurred" bitfld.word 0x00 6. " LIMMSK_L6 ,Counter limit L event 6" "Not occurred,Occurred" textline " " bitfld.word 0x00 5. " LIMMSK_L5 ,Counter limit L event 5" "Not occurred,Occurred" bitfld.word 0x00 4. " LIMMSK_L4 ,Counter limit L event 4" "Not occurred,Occurred" textline " " else bitfld.word 0x00 5. " LIMMSK_L5 ,Counter limit L event 5" "Not occurred,Occurred" bitfld.word 0x00 4. " LIMMSK_L4 ,Counter limit L event 4" "Not occurred,Occurred" textline " " endif bitfld.word 0x00 3. " LIMMSK_L3 ,Counter limit L event 3" "Not occurred,Occurred" bitfld.word 0x00 2. " LIMMSK_L2 ,Counter limit L event 2" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " LIMMSK_L1 ,Counter limit L event 1" "Not occurred,Occurred" bitfld.word 0x00 0. " LIMMSK_L0 ,Counter limit L event 0" "Not occurred,Occurred" line.word 0x02 "LIMIT_H,SCT limit register" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " LIMMSK_H23 ,Counter limit H event 23" "Not occurred,Occurred" bitfld.word 0x02 6. " LIMMSK_H22 ,Counter limit H event 22" "Not occurred,Occurred" textline " " bitfld.word 0x02 5. " LIMMSK_H21 ,Counter limit H event 21" "Not occurred,Occurred" bitfld.word 0x02 4. " LIMMSK_H20 ,Counter limit H event 20" "Not occurred,Occurred" textline " " else bitfld.word 0x02 5. " LIMMSK_H21 ,Counter limit H event 21" "Not occurred,Occurred" bitfld.word 0x02 4. " LIMMSK_H20 ,Counter limit H event 20" "Not occurred,Occurred" textline " " endif bitfld.word 0x02 3. " LIMMSK_H19 ,Counter limit H event 19" "Not occurred,Occurred" bitfld.word 0x02 2. " LIMMSK_H18 ,Counter limit H event 18" "Not occurred,Occurred" textline " " bitfld.word 0x02 1. " LIMMSK_H17 ,Counter limit H event 17" "Not occurred,Occurred" bitfld.word 0x02 0. " LIMMSK_H16 ,Counter limit H event 16" "Not occurred,Occurred" group.word 0x0C++0x03 line.word 0x00 "HALT_L,SCT halt condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted" bitfld.word 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted" textline " " bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" textline " " else bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" textline " " endif bitfld.word 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted" bitfld.word 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted" textline " " bitfld.word 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted" bitfld.word 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted" line.word 0x02 "HALT_H,SCT halt condition register high counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " HALTMSK_H23 ,Counter halted H event 23" "Not halted,Halted" bitfld.word 0x02 6. " HALTMSK_H22 ,Counter halted H event 22" "Not halted,Halted" textline " " bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted" bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted" textline " " else bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted" bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted" textline " " endif bitfld.word 0x02 3. " HALTMSK_H19 ,Counter halted H event 19" "Not halted,Halted" bitfld.word 0x02 2. " HALTMSK_H18 ,Counter halted H event 18" "Not halted,Halted" textline " " bitfld.word 0x02 1. " HALTMSK_H17 ,Counter halted H event 17" "Not halted,Halted" bitfld.word 0x02 0. " HALTMSK_H16 ,Counter halted H event 16" "Not halted,Halted" group.word 0x10++0x03 line.word 0x00 "STOP_L,SCT stop condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " STOPMSK_L7 ,Event 7 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 6. " STOPMSK_L6 ,Event 6 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter Stopped" "Not stopped,Stopped" textline " " else bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter Stopped" "Not stopped,Stopped" textline " " endif bitfld.word 0x00 3. " STOPMSK_L3 ,Event 3 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 2. " STOPMSK_L2 ,Event 2 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x00 1. " STOPMSK_L1 ,Event 1 counter Stopped" "Not stopped,Stopped" bitfld.word 0x00 0. " STOPMSK_L0 ,Event 0 counter Stopped" "Not stopped,Stopped" line.word 0x02 "STOP_H,SCT stop condition register high counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " STOPMSK_H23 ,Event 23 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 6. " STOPMSK_H22 ,Event 22 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter Stopped" "Not stopped,Stopped" textline " " else bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter Stopped" "Not stopped,Stopped" textline " " endif bitfld.word 0x02 3. " STOPMSK_H19 ,Event 19 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 2. " STOPMSK_H18 ,Event 18 counter Stopped" "Not stopped,Stopped" textline " " bitfld.word 0x02 1. " STOPMSK_H17 ,Event 17 counter Stopped" "Not stopped,Stopped" bitfld.word 0x02 0. " STOPMSK_H16 ,Event 16 counter Stopped" "Not stopped,Stopped" group.word 0x14++0x03 line.word 0x00 "START_L,SCT start condition register low counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " STARTMSK_L7 ,Event 7 counter Started" "Not started,Started" bitfld.word 0x00 6. " STARTMSK_L6 ,Event 6 counter Started" "Not started,Started" textline " " bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter Started" "Not started,Started" bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter Started" "Not started,Started" textline " " else bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter Started" "Not started,Started" bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter Started" "Not started,Started" textline " " endif bitfld.word 0x00 3. " STARTMSK_L3 ,Event 3 counter Started" "Not started,Started" bitfld.word 0x00 2. " STARTMSK_L2 ,Event 2 counter Started" "Not started,Started" textline " " bitfld.word 0x00 1. " STARTMSK_L1 ,Event 1 counter Started" "Not started,Started" bitfld.word 0x00 0. " STARTMSK_L0 ,Event 0 counter Started" "Not started,Started" line.word 0x02 "START_H,SCT start condition register high counter 16-bit" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " STARTMSK_H23 ,Event 23 counter Started" "Not started,Started" bitfld.word 0x02 6. " STARTMSK_H22 ,Event 22 counter Started" "Not started,Started" textline " " bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter Started" "Not started,Started" bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter Started" "Not started,Started" textline " " else bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter Started" "Not started,Started" bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter Started" "Not started,Started" textline " " endif bitfld.word 0x02 3. " STARTMSK_H19 ,Event 19 counter Started" "Not started,Started" bitfld.word 0x02 2. " STARTMSK_H18 ,Event 18 counter Started" "Not started,Started" textline " " bitfld.word 0x02 1. " STARTMSK_H17 ,Event 17 counter Started" "Not started,Started" bitfld.word 0x02 0. " STARTMSK_H16 ,Event 16 counter Started" "Not started,Started" group.word 0x40++0x03 line.word 0x00 "COUNT_L,SCT counter register" line.word 0x02 "COUNT_H,SCT counter register" group.word 0x44++0x03 line.word 0x00 "STATE_L,SCT state register" bitfld.word 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "STATE_H,SCT state register" bitfld.word 0x02 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif textline " " rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT input register" bitfld.long 0x00 19. " SIN3 ,Input 3 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 18. " SIN2 ,Input 2 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 17. " SIN1 ,Input 1 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 16. " SIN0 ,Input 0 state synchronized to the SCT clock" "0,1" textline " " bitfld.long 0x00 3. " AIN3 ,Real-time status of input 3" "0,1" bitfld.long 0x00 2. " AIN2 ,Real-time status of input 2" "0,1" bitfld.long 0x00 1. " AIN1 ,Real-time status of input 1" "0,1" bitfld.long 0x00 0. " AIN0 ,Real-time status of input 0" "0,1" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x4C++0x03 line.long 0x00 "REGMODE_L,SCT match/capture registers mode register" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " REGMOD_L7 ,8th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 6. " REGMOD_L6 ,7th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 5. " REGMOD_L5 ,6th pair of match/capture registers" "Match,Capture" textline " " endif bitfld.long 0x00 4. " REGMOD_L4 ,5th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 3. " REGMOD_L3 ,4th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 2. " REGMOD_L2 ,3rd pair of match/capture registers" "Match,Capture" bitfld.long 0x00 1. " REGMOD_L1 ,2nd pair of match/capture registers" "Match,Capture" textline " " bitfld.long 0x00 0. " REGMOD_L0 ,1th pair of match/capture registers" "Match,Capture" else group.word 0x4C++0x03 line.word 0x00 "REGMODE_L,SCT match/capture registers mode register" sif (cpuis("LPC82*")) bitfld.word 0x00 7. " REGMOD_L7 ,8th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 6. " REGMOD_L6 ,7th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 5. " REGMOD_L5 ,6th pair of match/capture registers" "Match,Capture" textline " " endif bitfld.word 0x00 4. " REGMOD_L4 ,5th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 3. " REGMOD_L3 ,4th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 2. " REGMOD_L2 ,3rd pair of match/capture registers" "Match,Capture" bitfld.word 0x00 1. " REGMOD_L1 ,2nd pair of match/capture registers" "Match,Capture" textline " " bitfld.word 0x00 0. " REGMOD_L0 ,1th pair of match/capture registers" "Match,Capture" line.word 0x02 "REGMODE_H,SCT match/capture registers mode register" sif (cpuis("LPC82*")) bitfld.word 0x02 7. " REGMOD_H7 ,8th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 6. " REGMOD_H6 ,7th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 5. " REGMOD_H5 ,6th pair of match/capture registers" "Match,Capture" textline " " endif bitfld.word 0x02 4. " REGMOD_H4 ,5th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 3. " REGMOD_H3 ,4th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 2. " REGMOD_H2 ,3rd pair of match/capture registers" "Match,Capture" bitfld.word 0x02 1. " REGMOD_H1 ,2nd pair of match/capture registers" "Match,Capture" textline " " bitfld.word 0x02 0. " REGMOD_H0 ,1th pair of match/capture registers" "Match,Capture" endif group.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT output register" sif (cpuis("LPC82*")) bitfld.long 0x00 5. " OUT5 ,Output 5" "Low,High" bitfld.long 0x00 4. " OUT4 ,Output 4" "Low,High" textline " " endif bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High" bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High" bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High" bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High" textline " " if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT bidirectional output control register" sif (cpuis("LPC82*")) bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,?..." bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,?..." textline " " endif bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,?..." bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,?..." bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,?..." textline " " bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT bidirectional output control register" sif (cpuis("LPC82*")) bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,H is counting down,?..." textline " " endif bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,H is counting down,?..." textline " " bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,H is counting down,?..." endif group.long 0x58++0x03 line.long 0x00 "RES,SCT conflict resolution register" sif (cpuis("LPC82*")) bitfld.long 0x00 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set output,Clear output,Toggle output" textline " " endif bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set output,Clear output,Toggle output" textline " " bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set output,Clear output,Toggle output" sif (cpuis("LPC82*")) group.long 0x5C++0x07 line.long 0x00 "DMAREQ0,SCT DMA 0 request register" rbitfld.long 0x00 31. " DRQ0 ,This read-only bit indicates the state of DMA Request 0" "Not requested,Requested" bitfld.long 0x00 30. " DRL0 ,The SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Not requested,Requested" textline " " bitfld.long 0x00 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 4. " DEV_0[4] ,Event 4 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 3. " DEV_0[3] ,Event 3 sets DMA request 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " DEV_0[2] ,Event 2 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 1. " DEV_0[1] ,Event 1 sets DMA request 0" "Not requested,Requested" bitfld.long 0x00 0. " DEV_0[0] ,Event 0 sets DMA request 0" "Not requested,Requested" line.long 0x04 "DMAREQ1,SCT DMA 1 request register" rbitfld.long 0x04 31. " DRQ1 ,This read-only bit indicates the state of DMA request 1" "Not requested,Requested" bitfld.long 0x04 30. " DRL1 ,The SCT set DMA request 1 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Not requested,Requested" textline " " bitfld.long 0x04 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 4. " DEV_1[4] ,Event 4 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 3. " DEV_1[3] ,Event 3 sets DMA request 1" "Not requested,Requested" textline " " bitfld.long 0x04 2. " DEV_1[2] ,Event 2 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 1. " DEV_1[1] ,Event 1 sets DMA request 1" "Not requested,Requested" bitfld.long 0x04 0. " DEV_1[0] ,Event 0 sets DMA request 1" "Not requested,Requested" endif group.long 0xF0++0x0F line.long 0x00 "EVEN,SCT flag enable register" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " IEN7 ,Enables flag 7 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " IEN6 ,Enables flag 6 to request an interrupt" "Disabled,Enabled" textline " " endif bitfld.long 0x00 5. " IEN5 ,Enables flag 5 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " IEN4 ,Enables flag 4 to request an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IEN3 ,Enables flag 3 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " IEN2 ,Enables flag 2 to request an interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " IEN1 ,Enables flag 1 to request an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " IEN0 ,Enables flag 0 to request an interrupt" "Disabled,Enabled" line.long 0x04 "EVFLAG,SCT event flag register" sif (cpuis("LPC82*")) eventfld.long 0x04 7. " FLAG7 ,Event 7 occurred" "Not occurred,Occurred" eventfld.long 0x04 6. " FLAG6 ,Event 6 occurred" "Not occurred,Occurred" textline " " endif eventfld.long 0x04 5. " FLAG5 ,Event 5 occurred" "Not occurred,Occurred" eventfld.long 0x04 4. " FLAG4 ,Event 4 occurred" "Not occurred,Occurred" textline " " eventfld.long 0x04 3. " FLAG3 ,Event 3 occurred" "Not occurred,Occurred" eventfld.long 0x04 2. " FLAG2 ,Event 2 occurred" "Not occurred,Occurred" eventfld.long 0x04 1. " FLAG1 ,Event 1 occurred" "Not occurred,Occurred" textline " " eventfld.long 0x04 0. " FLAG0 ,Event 0 occurred" "Not occurred,Occurred" line.long 0x08 "CONEN,SCT conflict enable register" sif (cpuis("LPC82*")) bitfld.long 0x08 5. " NCEN5 ,No change conflict event 5 enable" "Disabled,Enabled" bitfld.long 0x08 4. " NCEN4 ,No change conflict event 4 enable" "Disabled,Enabled" textline " " endif bitfld.long 0x08 3. " NCEN3 ,No change conflict event 3 enable" "Disabled,Enabled" bitfld.long 0x08 2. " NCEN2 ,No change conflict event 2 enable" "Disabled,Enabled" bitfld.long 0x08 1. " NCEN1 ,No change conflict event 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " NCEN0 ,No change conflict event 0 enable" "Disabled,Enabled" line.long 0x0C "CONFLAG,SCT conflict flag register" bitfld.long 0x0C 31. " BUSERRH ,Bus error" "No error,Error" bitfld.long 0x0C 30. " BUSERRL ,Bus error" "No error,Error" textline " " sif (cpuis("LPC82*")) bitfld.long 0x0C 5. " NCFLAG5 ,No-change conflict event 5 occurred" "Not occurred,Occurred" bitfld.long 0x0C 4. " NCFLAG4 ,No-change conflict event 4 occurred" "Not occurred,Occurred" textline " " endif bitfld.long 0x0C 3. " NCFLAG3 ,No-change conflict event 3 occurred" "Not occurred,Occurred" textline " " bitfld.long 0x0C 2. " NCFLAG2 ,No-change conflict event 2 occurred" "Not occurred,Occurred" bitfld.long 0x0C 1. " NCFLAG1 ,No-change conflict event 1 occurred" "Not occurred,Occurred" bitfld.long 0x0C 0. " NCFLAG0 ,No-change conflict event 0 occurred" "Not occurred,Occurred" width 26. tree "Channel 0 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x100++0x03 line.long 0x00 "MATCH0/CAP0,SCT match/capture register 0" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 0" "Disabled,Enabled" group.long (0x100+0x100)++0x03 line.long 0x00 "MATCHREL0/CAPCTRL0,SCT match/capture reload register 0" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x100++0x03 line.word 0x00 "MATCH0_L/CAP0_L,SCT match/capture register 0" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 0" "Disabled,Enabled" line.word 0x02 "MATCH0_H/CAP0_H,SCT match/capture register 0" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 0" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 0" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 0" "Disabled,Enabled" group.word (0x100+0x100)++0x03 line.word 0x00 "MATCHREL0_L/CAPCTRL0_L,SCT match/capture reload register 0" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL0_H/CAPCTRL0_H,SCT match/capture reload register 0" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x100+0x200)++0x07 line.long 0x00 "EVSTATEMSK0,SCT event state mask 0" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL0,SCT event control register 0" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x100+0x400)++0x07 line.long 0x00 "OUTPUTSET0,SCT output set register 0" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 0" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 0" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 0" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 0" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 0" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 0" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 0" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 0" "Not set,Set" line.long 0x04 "OUTPUTCLR0,SCT output clear register 0" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 0" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 0" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 0" "Not cleared,Cleared" tree.end tree "Channel 1 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x104++0x03 line.long 0x00 "MATCH1/CAP1,SCT match/capture register 1" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 1" "Disabled,Enabled" group.long (0x104+0x100)++0x03 line.long 0x00 "MATCHREL1/CAPCTRL1,SCT match/capture reload register 1" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x104++0x03 line.word 0x00 "MATCH1_L/CAP1_L,SCT match/capture register 1" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 1" "Disabled,Enabled" line.word 0x02 "MATCH1_H/CAP1_H,SCT match/capture register 1" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 1" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 1" "Disabled,Enabled" group.word (0x104+0x100)++0x03 line.word 0x00 "MATCHREL1_L/CAPCTRL1_L,SCT match/capture reload register 1" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL1_H/CAPCTRL1_H,SCT match/capture reload register 1" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x108+0x200)++0x07 line.long 0x00 "EVSTATEMSK1,SCT event state mask 1" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL1,SCT event control register 1" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x108+0x400)++0x07 line.long 0x00 "OUTPUTSET1,SCT output set register 1" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 1" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 1" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 1" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 1" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 1" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 1" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 1" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 1" "Not set,Set" line.long 0x04 "OUTPUTCLR1,SCT output clear register 1" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 1" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 1" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 1" "Not cleared,Cleared" tree.end tree "Channel 2 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x108++0x03 line.long 0x00 "MATCH2/CAP2,SCT match/capture register 2" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 2" "Disabled,Enabled" group.long (0x108+0x100)++0x03 line.long 0x00 "MATCHREL2/CAPCTRL2,SCT match/capture reload register 2" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x108++0x03 line.word 0x00 "MATCH2_L/CAP2_L,SCT match/capture register 2" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 2" "Disabled,Enabled" line.word 0x02 "MATCH2_H/CAP2_H,SCT match/capture register 2" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 2" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 2" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 2" "Disabled,Enabled" group.word (0x108+0x100)++0x03 line.word 0x00 "MATCHREL2_L/CAPCTRL2_L,SCT match/capture reload register 2" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL2_H/CAPCTRL2_H,SCT match/capture reload register 2" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x110+0x200)++0x07 line.long 0x00 "EVSTATEMSK2,SCT event state mask 2" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL2,SCT event control register 2" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x110+0x400)++0x07 line.long 0x00 "OUTPUTSET2,SCT output set register 2" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 2" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 2" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 2" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 2" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 2" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 2" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 2" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 2" "Not set,Set" line.long 0x04 "OUTPUTCLR2,SCT output clear register 2" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 2" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 2" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 2" "Not cleared,Cleared" tree.end tree "Channel 3 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x10C++0x03 line.long 0x00 "MATCH3/CAP3,SCT match/capture register 3" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 3" "Disabled,Enabled" group.long (0x10C+0x100)++0x03 line.long 0x00 "MATCHREL3/CAPCTRL3,SCT match/capture reload register 3" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x10C++0x03 line.word 0x00 "MATCH3_L/CAP3_L,SCT match/capture register 3" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 3" "Disabled,Enabled" line.word 0x02 "MATCH3_H/CAP3_H,SCT match/capture register 3" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 3" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 3" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 3" "Disabled,Enabled" group.word (0x10C+0x100)++0x03 line.word 0x00 "MATCHREL3_L/CAPCTRL3_L,SCT match/capture reload register 3" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL3_H/CAPCTRL3_H,SCT match/capture reload register 3" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x118+0x200)++0x07 line.long 0x00 "EVSTATEMSK3,SCT event state mask 3" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL3,SCT event control register 3" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x118+0x400)++0x07 line.long 0x00 "OUTPUTSET3,SCT output set register 3" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " SET7 ,Event 7 to set output 3" "Not set,Set" bitfld.long 0x00 6. " SET6 ,Event 6 to set output 3" "Not set,Set" textline " " endif bitfld.long 0x00 5. " SET5 ,Event 5 to set output 3" "Not set,Set" bitfld.long 0x00 4. " SET4 ,Event 4 to set output 3" "Not set,Set" textline " " bitfld.long 0x00 3. " SET3 ,Event 3 to set output 3" "Not set,Set" bitfld.long 0x00 2. " SET2 ,Event 2 to set output 3" "Not set,Set" bitfld.long 0x00 1. " SET1 ,Event 1 to set output 3" "Not set,Set" bitfld.long 0x00 0. " SET0 ,Event 0 to set output 3" "Not set,Set" line.long 0x04 "OUTPUTCLR3,SCT output clear register 3" sif (cpuis("LPC82*")) bitfld.long 0x04 7. " CLR7 ,Event 7 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 6. " CLR6 ,Event 6 to clear output 3" "Not cleared,Cleared" textline " " endif bitfld.long 0x04 5. " CLR5 ,Event 5 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 4. " CLR4 ,Event 4 to clear output 3" "Not cleared,Cleared" textline " " bitfld.long 0x04 3. " CLR3 ,Event 3 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " CLR2 ,Event 2 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 1. " CLR1 ,Event 1 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 0. " CLR0 ,Event 0 to clear output 3" "Not cleared,Cleared" tree.end tree "Channel 4 Registers" if (((per.l(ad:0x50004000))&0x1)==0x1) group.long 0x110++0x03 line.long 0x00 "MATCH4/CAP4,SCT match/capture register 4" bitfld.long 0x00 31. " MATCH31_H/CAP31_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 30. " MATCH30_H/CAP30_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 29. " MATCH29_H/CAP29_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MATCH28_H/CAP28_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 27. " MATCH27_H/CAP27_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 26. " MATCH26_H/CAP26_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MATCH25_H/CAP25_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 24. " MATCH24_H/CAP24_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 23. " MATCH23_H/CAP23_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MATCH22_H/CAP22_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 21. " MATCH21_H/CAP21_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 20. " MATCH20_H/CAP20_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MATCH19_H/CAP19_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 18. " MATCH18_H/CAP18_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 17. " MATCH17_H/CAP17_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MATCH16_H/CAP16_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.long 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 4" "Disabled,Enabled" group.long (0x110+0x100)++0x03 line.long 0x00 "MATCHREL4/CAPCTRL4,SCT match/capture reload register 4" bitfld.long 0x00 31. " RELOAD31_H ,SCT match reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H ,SCT match reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H ,SCT match reload register 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RELOAD28_H ,SCT match reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H ,SCT match reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H ,SCT match reload register 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " RELOAD25_H ,SCT match reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H ,SCT match reload register 24" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" else textline " " bitfld.long 0x00 23. " RELOAD23_H ,SCT match reload register 23" "Disabled,Enabled" bitfld.long 0x00 22. " RELOAD22_H ,SCT match reload register 22" "Disabled,Enabled" endif textline " " bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.long 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word 0x110++0x03 line.word 0x00 "MATCH4_L/CAP4_L,SCT match/capture register 4" bitfld.word 0x00 15. " MATCH15_L/CAP15_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 14. " MATCH14_L/CAP14_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 13. " MATCH13_L/CAP13_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " MATCH12_L/CAP12_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 11. " MATCH11_L/CAP11_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 10. " MATCH10_L/CAP10_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " MATCH9_L/CAP9_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 8. " MATCH8_L/CAP8_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 7. " MATCH7_L/CAP7_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " MATCH6_L/CAP6_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 5. " MATCH5_L/CAP5_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 4. " MATCH4_L/CAP4_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " MATCH3_L/CAP3_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 2. " MATCH2_L/CAP2_L ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x00 1. " MATCH1_L/CAP1_L ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " MATCH0_L/CAP0_L ,SCT match/capture register of channel 4" "Disabled,Enabled" line.word 0x02 "MATCH4_H/CAP4_H,SCT match/capture register 4" bitfld.word 0x02 15. " MATCH15_H/CAP15_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 14. " MATCH14_H/CAP14_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 13. " MATCH13_H/CAP13_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " MATCH12_H/CAP12_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 11. " MATCH11_H/CAP11_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 10. " MATCH10_H/CAP10_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " MATCH9_H/CAP9_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 8. " MATCH8_H/CAP8_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 7. " MATCH7_H/CAP7_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 6. " MATCH6_H/CAP6_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 5. " MATCH5_H/CAP5_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 4. " MATCH4_H/CAP4_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " MATCH3_H/CAP3_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 2. " MATCH2_H/CAP2_H ,SCT match/capture register of channel 4" "Disabled,Enabled" bitfld.word 0x02 1. " MATCH1_H/CAP1_H ,SCT match/capture register of channel 4" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " MATCH0_H/CAP0_H ,SCT match/capture register of channel 4" "Disabled,Enabled" group.word (0x110+0x100)++0x03 line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT match/capture reload register 4" bitfld.word 0x00 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x00 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x00 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT match/capture reload register 4" bitfld.word 0x02 15. " RELOAD15_L ,SCT match reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_L ,SCT match reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_L ,SCT match reload register 13" "Disabled,Enabled" textline " " bitfld.word 0x02 12. " RELOAD12_L ,SCT match reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_L ,SCT match reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_L ,SCT match reload register 10" "Disabled,Enabled" textline " " bitfld.word 0x02 9. " RELOAD9_L ,SCT match reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_L ,SCT match reload register 8" "Disabled,Enabled" sif cpuis("LPC82*") textline " " bitfld.word 0x02 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" else textline " " bitfld.word 0x02 7. " RELOAD7_L ,SCT match reload register 7" "Disabled,Enabled" bitfld.word 0x02 6. " RELOAD6_L ,SCT match reload register 6" "Disabled,Enabled" endif textline " " bitfld.word 0x02 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" textline " " bitfld.word 0x02 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" endif textline " " group.long (0x120+0x200)++0x07 line.long 0x00 "EVSTATEMSK4,SCT event state mask 4" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL4,SCT event control register 4" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel 5 Registers" textline " " group.long (0x128+0x200)++0x07 line.long 0x00 "EVSTATEMSK5,SCT event state mask 5" sif (cpuis("LPC82*")) bitfld.long 0x00 7. " STATEMSK7 ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " STATEMSK6 ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " STATEMSK5 ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " STATEMSK4 ,SCT event state mask 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " STATEMSK3 ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " STATEMSK2 ,SCT event state mask 2" "Masked,Not masked" textline " " endif bitfld.long 0x00 1. " STATEMSK1 ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " STATEMSK0 ,SCT event state mask 0" "Masked,Not masked" textline " " line.long 0x04 "EVCTRL5,SCT event control register 5" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when COMBMODE=Match" "Equal,Greater/Less or equal" textline " " bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" textline " " bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the Match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 0x0B else width 15. if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT Configuration Register" sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled" newline endif sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*") bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled" bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled" newline bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled" bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled" newline endif bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled" bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled" newline bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled" bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled" newline bitfld.long 0x00 7. " NORELAOD ,Prevents the lower and higher match registers from being reloaded" "Disabled,Enabled" newline sif cpuis("LPC11E*") bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..." bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT" else bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)" bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field" endif newline bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit" else group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT Configuration Register" sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 18. " AUTOLIMIT_H ,Treat match on match register 0 as a limit condition" "Disabled,Enabled" bitfld.long 0x00 17. " AUTOLIMIT_L ,Treat match on match register 0 as a limit condition" "Disabled,Enabled" newline endif sif !cpuis("LPC811M001JDH16")&&!cpuis("LPC832M101FDH20")&&!cpuis("LPC834M101FHI33")&&!cpuis("LPC84*")&&!cpuis("LPC11E*") bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Disabled,Enabled" bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Disabled,Enabled" newline bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Disabled,Enabled" bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Disabled,Enabled" newline endif bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Disabled,Enabled" bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Disabled,Enabled" newline bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Disabled,Enabled" bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Disabled,Enabled" newline bitfld.long 0x00 8. " NORELOADH ,Prevents the higher match registers from being reloaded" "Disabled,Enabled" bitfld.long 0x00 7. " NORELAODL ,Prevents the lower match registers from being reloaded" "Disabled,Enabled" newline sif cpuis("LPC11E*") bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..." bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT" else bitfld.long 0x00 3.--6. " CLKSEL ,SCT clock select" "Rising edges(input 0),Falling edges(input 0),Rising edges(input 1),Falling edges(input 1),Rising edges(input 2),Falling edges(input 2),Rising edges(input 3),Falling edges(input 3),Rising edges(input 4),Falling edges(input 4),Rising edges(input 5),Falling edges(input 5),Rising edges(input 6),Falling edges(input 6),Rising edges(input 7),Falling edges(input 7)" bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "BusClock clocks,BusClock,Sel.CKSEL,Sel.by CKSEL field" endif newline bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16 bit,Unified 32-bit" endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x04++0x03 line.long 0x00 "CTRL,SCT Control Register" hexmask.long.byte 0x00 5.--12. 1. " PRE ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock" bitfld.long 0x00 4. " BIDIR ,L or unified counter direction select" "Limit then zero,Limit then down" newline bitfld.long 0x00 3. " CLRCTR ,Unified clear counter" "Not cleared,Cleared" bitfld.long 0x00 2. " HALT ,Unified halt counter" "Not halted,Halted" newline bitfld.long 0x00 1. " STOP ,Unified stop counter" "Not stopped,Stopped" bitfld.long 0x00 0. " DOWN ,Unified counting down counter" "No action,Counting down" else group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock" bitfld.word 0x00 4. " BIDIR_L ,L or unified counter direction select" "Limit then zero,Limit then down" newline bitfld.word 0x00 3. " CLRCTR_L ,Unified clear counter" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_L ,Unified halt counter" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_L ,Unified stop counter" "Not stopped,Stopped" bitfld.word 0x00 0. " DOWN_L ,Unified counting down counter" "No action,Counting down" line.word 0x02 "CTRL_H,SCT Control Register High Counter 16-bit" hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter lock" bitfld.word 0x02 4. " BIDIR_H ,Direction select" "Limit then zero,Limit then down" newline bitfld.word 0x02 3. " CLRCTR_H ,Unified clear counter" "Not cleared,Cleared" bitfld.word 0x02 2. " HALT_H ,Unified halt counter" "Not halted,Halted" newline bitfld.word 0x02 1. " STOP_H ,Unified stop counter" "Not stopped,Stopped" bitfld.word 0x02 0. " DOWN_H ,Unified counting down counter" "No action,Counting down" endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "LIMIT,SCT Limit Register" sif !cpuis("LPC11E*") bitfld.long 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit" "Not used,Used" bitfld.long 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit" "Not used,Used" newline bitfld.long 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit" "Not used,Used" bitfld.long 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit" "Not used,Used" newline bitfld.long 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit" "Not used,Used" bitfld.long 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit" "Not used,Used" newline bitfld.long 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit" "Not used,Used" bitfld.long 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit" "Not used,Used" newline bitfld.long 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit" "Not used,Used" bitfld.long 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit" "Not used,Used" newline endif bitfld.long 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit" "Not used,Used" bitfld.long 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit" "Not used,Used" newline bitfld.long 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit" "Not used,Used" bitfld.long 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit" "Not used,Used" newline bitfld.long 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit" "Not used,Used" bitfld.long 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit" "Not used,Used" else group.word 0x08++0x03 line.word 0x00 "LIMIT_L,SCT Limit Register Low Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used" else newline bitfld.word 0x00 15. " LIMMSK_L15 ,Event 15 used as counter limit L" "Not used,Used" bitfld.word 0x00 14. " LIMMSK_L14 ,Event 14 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 13. " LIMMSK_L13 ,Event 13 used as counter limit L" "Not used,Used" bitfld.word 0x00 12. " LIMMSK_L12 ,Event 12 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 11. " LIMMSK_L11 ,Event 11 used as counter limit L" "Not used,Used" bitfld.word 0x00 10. " LIMMSK_L10 ,Event 10 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 9. " LIMMSK_L9 ,Event 9 used as counter limit L" "Not used,Used" bitfld.word 0x00 8. " LIMMSK_L8 ,Event 8 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 7. " LIMMSK_L7 ,Event 7 used as counter limit L" "Not used,Used" bitfld.word 0x00 6. " LIMMSK_L6 ,Event 6 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 5. " LIMMSK_L5 ,Event 5 used as counter limit L" "Not used,Used" endif bitfld.word 0x00 4. " LIMMSK_L4 ,Event 4 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 3. " LIMMSK_L3 ,Event 3 used as counter limit L" "Not used,Used" bitfld.word 0x00 2. " LIMMSK_L2 ,Event 2 used as counter limit L" "Not used,Used" newline bitfld.word 0x00 1. " LIMMSK_L1 ,Event 1 used as counter limit L" "Not used,Used" bitfld.word 0x00 0. " LIMMSK_L0 ,Event 0 used as counter limit L" "Not used,Used" line.word 0x02 "LIMIT_H,SCT Limit Register High Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used" else newline bitfld.word 0x02 15. " LIMMSK_H31 ,Event 31 used as counter limit H" "Not used,Used" bitfld.word 0x02 14. " LIMMSK_H30 ,Event 30 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 13. " LIMMSK_H29 ,Event 29 used as counter limit H" "Not used,Used" bitfld.word 0x02 12. " LIMMSK_H28 ,Event 28 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 11. " LIMMSK_H27 ,Event 27 used as counter limit H" "Not used,Used" bitfld.word 0x02 10. " LIMMSK_H26 ,Event 26 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 9. " LIMMSK_H25 ,Event 25 used as counter limit H" "Not used,Used" bitfld.word 0x02 8. " LIMMSK_H24 ,Event 24 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 7. " LIMMSK_H23 ,Event 23 used as counter limit H" "Not used,Used" bitfld.word 0x02 6. " LIMMSK_H22 ,Event 22 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 5. " LIMMSK_H21 ,Event 21 used as counter limit H" "Not used,Used" endif bitfld.word 0x02 4. " LIMMSK_H20 ,Event 20 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 3. " LIMMSK_H19 ,Event 19 used as counter limit H" "Not used,Used" bitfld.word 0x02 2. " LIMMSK_H18 ,Event 18 used as counter limit H" "Not used,Used" newline bitfld.word 0x02 1. " LIMMSK_H17 ,Event 17 used as counter limit H" "Not used,Used" bitfld.word 0x02 0. " LIMMSK_H16 ,Event 16 used as counter limit H" "Not used,Used" endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "HALT,SCT Halt Condition Register" sif !cpuis("LPC11E*") bitfld.long 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted" bitfld.long 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted" newline bitfld.long 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted" bitfld.long 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted" newline bitfld.long 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted" bitfld.long 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted" newline bitfld.long 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted" bitfld.long 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted" newline bitfld.long 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted" bitfld.long 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted" newline endif bitfld.long 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" bitfld.long 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" newline bitfld.long 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted" bitfld.long 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted" newline bitfld.long 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted" bitfld.long 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted" else group.word 0x0C++0x03 line.word 0x00 "HALT_L,SCT Halt Condition Register Low Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" else newline bitfld.word 0x00 15. " HALTMSK_L15 ,Counter halted L event 15" "Not halted,Halted" bitfld.word 0x00 14. " HALTMSK_L14 ,Counter halted L event 14" "Not halted,Halted" newline bitfld.word 0x00 13. " HALTMSK_L13 ,Counter halted L event 13" "Not halted,Halted" bitfld.word 0x00 12. " HALTMSK_L12 ,Counter halted L event 12" "Not halted,Halted" newline bitfld.word 0x00 11. " HALTMSK_L11 ,Counter halted L event 11" "Not halted,Halted" bitfld.word 0x00 10. " HALTMSK_L10 ,Counter halted L event 10" "Not halted,Halted" newline bitfld.word 0x00 9. " HALTMSK_L9 ,Counter halted L event 9" "Not halted,Halted" bitfld.word 0x00 8. " HALTMSK_L8 ,Counter halted L event 8" "Not halted,Halted" newline bitfld.word 0x00 7. " HALTMSK_L7 ,Counter halted L event 7" "Not halted,Halted" bitfld.word 0x00 6. " HALTMSK_L6 ,Counter halted L event 6" "Not halted,Halted" newline bitfld.word 0x00 5. " HALTMSK_L5 ,Counter halted L event 5" "Not halted,Halted" endif bitfld.word 0x00 4. " HALTMSK_L4 ,Counter halted L event 4" "Not halted,Halted" newline bitfld.word 0x00 3. " HALTMSK_L3 ,Counter halted L event 3" "Not halted,Halted" bitfld.word 0x00 2. " HALTMSK_L2 ,Counter halted L event 2" "Not halted,Halted" newline bitfld.word 0x00 1. " HALTMSK_L1 ,Counter halted L event 1" "Not halted,Halted" bitfld.word 0x00 0. " HALTMSK_L0 ,Counter halted L event 0" "Not halted,Halted" line.word 0x02 "HALT_H,SCT Halt Condition Register High Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted" else newline bitfld.word 0x02 15. " HALTMSK_H31 ,Counter halted H event 31" "Not halted,Halted" bitfld.word 0x02 14. " HALTMSK_H30 ,Counter halted H event 30" "Not halted,Halted" newline bitfld.word 0x02 13. " HALTMSK_H29 ,Counter halted H event 29" "Not halted,Halted" bitfld.word 0x02 12. " HALTMSK_H28 ,Counter halted H event 28" "Not halted,Halted" newline bitfld.word 0x02 11. " HALTMSK_H27 ,Counter halted H event 27" "Not halted,Halted" bitfld.word 0x02 10. " HALTMSK_H26 ,Counter halted H event 26" "Not halted,Halted" newline bitfld.word 0x02 9. " HALTMSK_H25 ,Counter halted H event 25" "Not halted,Halted" bitfld.word 0x02 8. " HALTMSK_H24 ,Counter halted H event 24" "Not halted,Halted" newline bitfld.word 0x02 7. " HALTMSK_H23 ,Counter halted H event 23" "Not halted,Halted" bitfld.word 0x02 6. " HALTMSK_H22 ,Counter halted H event 22" "Not halted,Halted" newline bitfld.word 0x02 5. " HALTMSK_H21 ,Counter halted H event 21" "Not halted,Halted" bitfld.word 0x02 4. " HALTMSK_H20 ,Counter halted H event 20" "Not halted,Halted" endif newline bitfld.word 0x02 3. " HALTMSK_H19 ,Counter halted H event 19" "Not halted,Halted" bitfld.word 0x02 2. " HALTMSK_H18 ,Counter halted H event 18" "Not halted,Halted" newline bitfld.word 0x02 1. " HALTMSK_H17 ,Counter halted H event 17" "Not halted,Halted" bitfld.word 0x02 0. " HALTMSK_H16 ,Counter halted H event 16" "Not halted,Halted" endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "STOP,SCT Stop Condition Register" sif !cpuis("LPC11E*") bitfld.long 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped" newline bitfld.long 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped" newline bitfld.long 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped" newline bitfld.long 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped" newline bitfld.long 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped" newline endif bitfld.long 0x00 5. " STOPMSK_L5 ,Event 6 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped" newline bitfld.long 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped" newline bitfld.long 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped" bitfld.long 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped" else group.word 0x10++0x03 line.word 0x00 "STOP_L,SCT Stop Condition Register Low Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped" else newline bitfld.word 0x00 15. " STOPMSK_L15 ,Event 15 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 14. " STOPMSK_L14 ,Event 14 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 13. " STOPMSK_L13 ,Event 13 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 12. " STOPMSK_L12 ,Event 12 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 11. " STOPMSK_L11 ,Event 11 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 10. " STOPMSK_L10 ,Event 10 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 9. " STOPMSK_L9 ,Event 9 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 8. " STOPMSK_L8 ,Event 8 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 7. " STOPMSK_L7 ,Event 7 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 6. " STOPMSK_L6 ,Event 6 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 5. " STOPMSK_L5 ,Event 5 counter stopped" "Not stopped,Stopped" endif bitfld.word 0x00 4. " STOPMSK_L4 ,Event 4 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 3. " STOPMSK_L3 ,Event 3 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 2. " STOPMSK_L2 ,Event 2 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x00 1. " STOPMSK_L1 ,Event 1 counter stopped" "Not stopped,Stopped" bitfld.word 0x00 0. " STOPMSK_L0 ,Event 0 counter stopped" "Not stopped,Stopped" line.word 0x02 "STOP_H,SCT Stop Condition Register High Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped" else newline bitfld.word 0x02 15. " STOPMSK_H31 ,Event 31 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 14. " STOPMSK_H30 ,Event 30 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 13. " STOPMSK_H29 ,Event 29 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 12. " STOPMSK_H28 ,Event 28 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 11. " STOPMSK_H27 ,Event 27 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 10. " STOPMSK_H26 ,Event 26 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 9. " STOPMSK_H25 ,Event 25 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 8. " STOPMSK_H24 ,Event 24 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 7. " STOPMSK_H23 ,Event 23 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 6. " STOPMSK_H22 ,Event 22 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 5. " STOPMSK_H21 ,Event 21 counter stopped" "Not stopped,Stopped" endif bitfld.word 0x02 4. " STOPMSK_H20 ,Event 20 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 3. " STOPMSK_H19 ,Event 19 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 2. " STOPMSK_H18 ,Event 18 counter stopped" "Not stopped,Stopped" newline bitfld.word 0x02 1. " STOPMSK_H17 ,Event 17 counter stopped" "Not stopped,Stopped" bitfld.word 0x02 0. " STOPMSK_H16 ,Event 16 counter stopped" "Not stopped,Stopped" endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "START,SCT Start Condition Register" sif !cpuis("LPC11E*") bitfld.long 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started" bitfld.long 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started" newline bitfld.long 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started" bitfld.long 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started" newline bitfld.long 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started" bitfld.long 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started" newline bitfld.long 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started" bitfld.long 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started" newline bitfld.long 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started" bitfld.long 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started" newline endif bitfld.long 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started" bitfld.long 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started" newline bitfld.long 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started" bitfld.long 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started" newline bitfld.long 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started" bitfld.long 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started" else group.word 0x14++0x03 line.word 0x00 "START_L,SCT Start Condition Register Low Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started" else newline bitfld.word 0x00 15. " STARTMSK_L15 ,Event 15 counter started" "Not started,Started" bitfld.word 0x00 14. " STARTMSK_L14 ,Event 14 counter started" "Not started,Started" newline bitfld.word 0x00 13. " STARTMSK_L13 ,Event 13 counter started" "Not started,Started" bitfld.word 0x00 12. " STARTMSK_L12 ,Event 12 counter started" "Not started,Started" newline bitfld.word 0x00 11. " STARTMSK_L11 ,Event 11 counter started" "Not started,Started" bitfld.word 0x00 10. " STARTMSK_L10 ,Event 10 counter started" "Not started,Started" newline bitfld.word 0x00 9. " STARTMSK_L9 ,Event 9 counter started" "Not started,Started" bitfld.word 0x00 8. " STARTMSK_L8 ,Event 8 counter started" "Not started,Started" newline bitfld.word 0x00 7. " STARTMSK_L7 ,Event 7 counter started" "Not started,Started" bitfld.word 0x00 6. " STARTMSK_L6 ,Event 6 counter started" "Not started,Started" newline bitfld.word 0x00 5. " STARTMSK_L5 ,Event 5 counter started" "Not started,Started" endif bitfld.word 0x00 4. " STARTMSK_L4 ,Event 4 counter started" "Not started,Started" newline bitfld.word 0x00 3. " STARTMSK_L3 ,Event 3 counter started" "Not started,Started" bitfld.word 0x00 2. " STARTMSK_L2 ,Event 2 counter started" "Not started,Started" newline bitfld.word 0x00 1. " STARTMSK_L1 ,Event 1 counter started" "Not started,Started" bitfld.word 0x00 0. " STARTMSK_L0 ,Event 0 counter started" "Not started,Started" line.word 0x02 "START_H,SCT Start Condition Register High Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started" else newline bitfld.word 0x02 15. " STARTMSK_H31 ,Event 31 counter started" "Not started,Started" bitfld.word 0x02 14. " STARTMSK_H30 ,Event 30 counter started" "Not started,Started" newline bitfld.word 0x02 13. " STARTMSK_H29 ,Event 29 counter started" "Not started,Started" bitfld.word 0x02 12. " STARTMSK_H28 ,Event 28 counter started" "Not started,Started" newline bitfld.word 0x02 11. " STARTMSK_H27 ,Event 27 counter started" "Not started,Started" bitfld.word 0x02 10. " STARTMSK_H26 ,Event 26 counter started" "Not started,Started" newline bitfld.word 0x02 9. " STARTMSK_H25 ,Event 25 counter started" "Not started,Started" bitfld.word 0x02 8. " STARTMSK_H24 ,Event 24 counter started" "Not started,Started" newline bitfld.word 0x02 7. " STARTMSK_H23 ,Event 23 counter started" "Not started,Started" bitfld.word 0x02 6. " STARTMSK_H22 ,Event 22 counter started" "Not started,Started" newline bitfld.word 0x02 5. " STARTMSK_H21 ,Event 21 counter started" "Not started,Started" endif bitfld.word 0x02 4. " STARTMSK_H20 ,Event 20 counter started" "Not started,Started" newline bitfld.word 0x02 3. " STARTMSK_H19 ,Event 19 counter started" "Not started,Started" bitfld.word 0x02 2. " STARTMSK_H18 ,Event 18 counter started" "Not started,Started" newline bitfld.word 0x02 1. " STARTMSK_H17 ,Event 17 counter started" "Not started,Started" bitfld.word 0x02 0. " STARTMSK_H16 ,Event 16 counter started" "Not started,Started" endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "DITHER_L,SCT Dither Condition Register" bitfld.long 0x00 15. " DITHMSK_L15 ,Event 15 dither mask" "Not dithered,Dithered" bitfld.long 0x00 14. " DITHMSK_L14 ,Event 14 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 13. " DITHMSK_L13 ,Event 13 dither mask" "Not dithered,Dithered" bitfld.long 0x00 12. " DITHMSK_L12 ,Event 12 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 11. " DITHMSK_L11 ,Event 11 dither mask" "Not dithered,Dithered" bitfld.long 0x00 10. " DITHMSK_L10 ,Event 10 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 9. " DITHMSK_L9 ,Event 9 dither mask" "Not dithered,Dithered" bitfld.long 0x00 8. " DITHMSK_L8 ,Event 8 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 7. " DITHMSK_L7 ,Event 7 dither mask" "Not dithered,Dithered" bitfld.long 0x00 6. " DITHMSK_L6 ,Event 6 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 5. " DITHMSK_L5 ,Event 5 dither mask" "Not dithered,Dithered" bitfld.long 0x00 4. " DITHMSK_L4 ,Event 4 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 3. " DITHMSK_L3 ,Event 3 dither mask" "Not dithered,Dithered" bitfld.long 0x00 2. " DITHMSK_L2 ,Event 2 dither mask" "Not dithered,Dithered" newline bitfld.long 0x00 1. " DITHMSK_L1 ,Event 1 dither mask" "Not dithered,Dithered" bitfld.long 0x00 0. " DITHMSK_L0 ,Event 0 dither mask" "Not dithered,Dithered" else group.word 0x18++0x03 line.word 0x00 "DITHER_L,SCT Dither Condition Register" bitfld.word 0x00 15. " DITHMSK_L15 ,Event 15 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 14. " DITHMSK_L14 ,Event 14 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 13. " DITHMSK_L13 ,Event 13 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 12. " DITHMSK_L12 ,Event 12 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 11. " DITHMSK_L11 ,Event 11 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 10. " DITHMSK_L10 ,Event 10 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 9. " DITHMSK_L9 ,Event 9 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 8. " DITHMSK_L8 ,Event 8 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 7. " DITHMSK_L7 ,Event 7 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 6. " DITHMSK_L6 ,Event 6 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 5. " DITHMSK_L5 ,Event 5 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 4. " DITHMSK_L4 ,Event 4 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 3. " DITHMSK_L3 ,Event 3 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 2. " DITHMSK_L2 ,Event 2 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x00 1. " DITHMSK_L1 ,Event 1 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x00 0. " DITHMSK_L0 ,Event 0 dither pattern mask" "Not dithered,Dithered" line.word 0x02 "DITHER_H,SCT Dither Condition Register" bitfld.word 0x02 15. " DITHMSK_H31 ,Event 31 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 14. " DITHMSK_H30 ,Event 30 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 13. " DITHMSK_H29 ,Event 29 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 12. " DITHMSK_H28 ,Event 28 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 11. " DITHMSK_H27 ,Event 27 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 10. " DITHMSK_H26 ,Event 26 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 9. " DITHMSK_H25 ,Event 25 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 8. " DITHMSK_H24 ,Event 24 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 7. " DITHMSK_H23 ,Event 23 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 6. " DITHMSK_H22 ,Event 22 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 5. " DITHMSK_H21 ,Event 21 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 4. " DITHMSK_H20 ,Event 20 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 3. " DITHMSK_H19 ,Event 19 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 2. " DITHMSK_H18 ,Event 18 dither pattern mask" "Not dithered,Dithered" newline bitfld.word 0x02 1. " DITHMSK_H17 ,Event 17 dither pattern mask" "Not dithered,Dithered" bitfld.word 0x02 0. " DITHMSK_H16 ,Event 16 dither pattern mask" "Not dithered,Dithered" endif endif newline width 15. if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "COUNT,SCT Counter Register" hexmask.long.word 0x00 0.--15. 1. " CTR_L ,L counter value" else group.word 0x40++0x03 line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit" line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit" endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x44++0x03 line.long 0x00 "STATE,SCT State Register" bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word 0x44++0x03 line.word 0x00 "STATE_L,SCT State Register Low Counter 16-bit" bitfld.word 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x02 "STATE_H,SCT State Register High Counter 16-bit" bitfld.word 0x02 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT Input Register" sif !cpuis("LPC11E*") bitfld.long 0x00 23. " SIN7 ,Input 7 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 22. " SIN6 ,Input 6 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 21. " SIN5 ,Input 5 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 20. " SIN4 ,Input 4 state synchronized to the SCT clock" "0,1" newline endif bitfld.long 0x00 19. " SIN3 ,Input 3 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 18. " SIN2 ,Input 2 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 17. " SIN1 ,Input 1 state synchronized to the SCT clock" "0,1" bitfld.long 0x00 16. " SIN0 ,Input 0 state synchronized to the SCT clock" "0,1" newline sif !cpuis("LPC11E*") bitfld.long 0x00 7. " AIN7 ,Real-time status of input 7" "0,1" bitfld.long 0x00 6. " AIN6 ,Real-time status of input 6" "0,1" bitfld.long 0x00 5. " AIN5 ,Real-time status of input 5" "0,1" bitfld.long 0x00 4. " AIN4 ,Real-time status of input 4" "0,1" newline endif bitfld.long 0x00 3. " AIN3 ,Real-time status of input 3" "0,1" bitfld.long 0x00 2. " AIN2 ,Real-time status of input 2" "0,1" bitfld.long 0x00 1. " AIN1 ,Real-time status of input 1" "0,1" bitfld.long 0x00 0. " AIN0 ,Real-time status of input 0" "0,1" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x4C++0x03 line.long 0x00 "REGMODE,SCT Match/Capture Registers Mode Register" sif cpuis("LPC11E*") bitfld.long 0x00 4. " REGMOD[4] ,5th pair of match/capture registers" "Match,Capture" else newline bitfld.long 0x00 15. " REGMOD[15] ,16th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture" newline bitfld.long 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture" newline bitfld.long 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture" endif newline bitfld.long 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture" bitfld.long 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture" bitfld.long 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture" bitfld.long 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture" else group.word 0x4C++0x03 line.word 0x00 "REGMODE_L,SCT Match/Capture Registers Mode Register Low Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x00 4. " REGMOD_L[4] ,5th pair of match/capture registers" "Match,Capture" newline else bitfld.word 0x00 15. " REGMOD_L[15] ,16th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 14. " [14] ,15th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 13. " [13] ,14th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 12. " [12] ,13th pair of match/capture registers" "Match,Capture" newline bitfld.word 0x00 11. " [11] ,12th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 10. " [10] ,11th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 9. " [9] ,10th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 8. " [8] ,9th pair of match/capture registers" "Match,Capture" newline bitfld.word 0x00 7. " [7] ,8th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 6. " [6] ,7th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 5. " [5] ,6th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 4. " [4] ,5th pair of match/capture registers" "Match,Capture" newline endif bitfld.word 0x00 3. " [3] ,4th pair of match/capture registers" "Match,Capture" bitfld.word 0x00 2. " [2] ,3rd pair of match/capture registers" "Match,Capture" bitfld.word 0x00 1. " [1] ,2nd pair of match/capture registers" "Match,Capture" bitfld.word 0x00 0. " [0] ,1th pair of match/capture registers" "Match,Capture" line.word 0x02 "REGMODE_H,SCT Match/Capture Registers Mode Register High Counter 16-bit" sif cpuis("LPC11E*") bitfld.word 0x02 4. " REGMOD_H[4] ,5th pair of match/capture registers" "Match,Capture" newline else bitfld.word 0x02 15. " REGMOD_H[15] ,16th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 14. " [14] ,15th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 13. " [13] ,14th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 12. " [12] ,13th pair of match/capture registers" "Match,Capture" newline bitfld.word 0x02 11. " [11] ,12th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 10. " [10] ,11th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 9. " [9] ,10th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 8. " [8] ,9th pair of match/capture registers" "Match,Capture" newline bitfld.word 0x02 7. " [7] ,8th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 6. " [6] ,7th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 5. " [5] ,6th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 4. " [4] ,5th pair of match/capture registers" "Match,Capture" newline endif bitfld.word 0x02 3. " [3] ,4th pair of match/capture registers" "Match,Capture" bitfld.word 0x02 2. " [2] ,3rd pair of match/capture registers" "Match,Capture" bitfld.word 0x02 1. " [1] ,2nd pair of match/capture registers" "Match,Capture" bitfld.word 0x02 0. " [0] ,1th pair of match/capture registers" "Match,Capture" endif sif cpuis("LPC11E*") if (((((per.w(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.w(ad:0x50004000+0x06))&0x04)==0x04)&&(((per.l(ad:0x50004000))&0x01)==0x00))||((((per.l(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.l(ad:0x50004000))&0x01)==0x01))) group.long 0x50++0x13 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High" bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High" bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High" bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High" else rgroup.long 0x50++0x13 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High" bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High" bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High" bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High" endif else group.long 0x50++0x13 line.long 0x00 "OUTPUT,SCT Output Register" sif !cpuis("LPC11E*") bitfld.long 0x00 15. " OUT15 ,Output 15" "Low,High" bitfld.long 0x00 14. " OUT14 ,Output 14" "Low,High" bitfld.long 0x00 13. " OUT13 ,Output 13" "Low,High" bitfld.long 0x00 12. " OUT12 ,Output 12" "Low,High" newline bitfld.long 0x00 11. " OUT11 ,Output 11" "Low,High" bitfld.long 0x00 10. " OUT10 ,Output 10" "Low,High" bitfld.long 0x00 9. " OUT9 ,Output 9" "Low,High" bitfld.long 0x00 8. " OUT8 ,Output 8" "Low,High" newline bitfld.long 0x00 7. " OUT7 ,Output 7" "Low,High" bitfld.long 0x00 6. " OUT6 ,Output 6" "Low,High" bitfld.long 0x00 5. " OUT5 ,Output 5" "Low,High" bitfld.long 0x00 4. " OUT4 ,Output 4" "Low,High" newline endif bitfld.long 0x00 3. " OUT3 ,Output 3" "Low,High" bitfld.long 0x00 2. " OUT2 ,Output 2" "Low,High" bitfld.long 0x00 1. " OUT1 ,Output 1" "Low,High" bitfld.long 0x00 0. " OUT0 ,Output 0" "Low,High" endif newline if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register" sif !cpuis("LPC11E*") bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,?..." bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,?..." bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,?..." newline bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,?..." bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,?..." bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,?..." newline bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,?..." bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,?..." bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,?..." newline bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,?..." bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,?..." bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,?..." newline endif bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,?..." bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,?..." bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,?..." newline bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Bidirectional Output Control Register" sif !cpuis("LPC11E*") bitfld.long 0x00 30.--31. " SETCLR15 ,Set/clear operation on output 15" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 28.--29. " SETCLR14 ,Set/clear operation on output 14" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 26.--27. " SETCLR13 ,Set/clear operation on output 13" "Not depend,L is counting down,H is counting down,?..." newline bitfld.long 0x00 24.--25. " SETCLR12 ,Set/clear operation on output 12" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 22.--23. " SETCLR11 ,Set/clear operation on output 11" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 20.--21. " SETCLR10 ,Set/clear operation on output 10" "Not depend,L is counting down,H is counting down,?..." newline bitfld.long 0x00 18.--19. " SETCLR9 ,Set/clear operation on output 9" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 16.--17. " SETCLR8 ,Set/clear operation on output 8" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 14.--15. " SETCLR7 ,Set/clear operation on output 7" "Not depend,L is counting down,H is counting down,?..." newline bitfld.long 0x00 12.--13. " SETCLR6 ,Set/clear operation on output 6" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 10.--11. " SETCLR5 ,Set/clear operation on output 5" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depend,L is counting down,H is counting down,?..." newline endif bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depend,L is counting down,H is counting down,?..." bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depend,L is counting down,H is counting down,?..." newline bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depend,L is counting down,H is counting down,?..." endif group.long 0x58++0x0B line.long 0x00 "RES,SCT Conflict Resolution Register" sif !cpuis("LPC11E*") bitfld.long 0x00 30.--31. " O15RES ,Effect of simultaneous set and clear on output 15" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 28.--29. " O14RES ,Effect of simultaneous set and clear on output 14" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 26.--27. " O13RES ,Effect of simultaneous set and clear on output 13" "No change,Set output,Clear output,Toggle output" newline bitfld.long 0x00 24.--25. " O12RES ,Effect of simultaneous set and clear on output 12" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 22.--23. " O11RES ,Effect of simultaneous set and clear on output 11" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 20.--21. " O10RES ,Effect of simultaneous set and clear on output 10" "No change,Set output,Clear output,Toggle output" newline bitfld.long 0x00 18.--19. " O9RES ,Effect of simultaneous set and clear on output 9" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 16.--17. " O8RES ,Effect of simultaneous set and clear on output 8" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 14.--15. " O7RES ,Effect of simultaneous set and clear on output 7" "No change,Set output,Clear output,Toggle output" newline bitfld.long 0x00 12.--13. " O6RES ,Effect of simultaneous set and clear on output 6" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set output,Clear output,Toggle output" newline endif bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set output,Clear output,Toggle output" bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set output,Clear output,Toggle output" newline bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set output,Clear output,Toggle output" line.long 0x04 "DMAREQ0,SCT DMA 0 Request Register" rbitfld.long 0x04 31. " DRQ0 ,Indicates the state of DMA request 0" "Not requested,Requested" bitfld.long 0x04 30. " DRL0 ,The SCT set DMA request 0 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested" sif !cpuis("LPC11E*") bitfld.long 0x04 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set" newline bitfld.long 0x04 14. " [14] ,Event 14 sets DMA request 0" "Not set,Set" bitfld.long 0x04 13. " [13] ,Event 13 sets DMA request 0" "Not set,Set" bitfld.long 0x04 12. " [12] ,Event 12 sets DMA request 0" "Not set,Set" newline bitfld.long 0x04 11. " [11] ,Event 11 sets DMA request 0" "Not set,Set" bitfld.long 0x04 10. " [10] ,Event 10 sets DMA request 0" "Not set,Set" bitfld.long 0x04 9. " [9] ,Event 9 sets DMA request 0" "Not set,Set" newline bitfld.long 0x04 8. " [8] ,Event 8 sets DMA request 0" "Not set,Set" bitfld.long 0x04 7. " [7] ,Event 7 sets DMA request 0" "Not set,Set" bitfld.long 0x04 6. " [6] ,Event 6 sets DMA request 0" "Not set,Set" endif newline sif cpuis("LPC11E*") bitfld.long 0x04 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set" else bitfld.long 0x04 5. " [5] ,Event 5 sets DMA request 0" "Not set,Set" endif bitfld.long 0x04 4. " [4] ,Event 4 sets DMA request 0" "Not set,Set" bitfld.long 0x04 3. " [3] ,Event 3 sets DMA request 0" "Not set,Set" newline bitfld.long 0x04 2. " [2] ,Event 2 sets DMA request 0" "Not set,Set" bitfld.long 0x04 1. " [1] ,Event 1 sets DMA request 0" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 sets DMA request 0" "Not set,Set" line.long 0x08 "DMAREQ1,SCT DMA 1 Request Register" rbitfld.long 0x08 31. " DRQ1 ,Indicates the state of DMA request 1" "Not requested,Requested" bitfld.long 0x08 30. " DRL1 ,The SCT set DMA request 1 when it loads the match_l/unified registers from the reload_l/unified registers" "Not requested,Requested" sif !cpuis("LPC11E*") bitfld.long 0x08 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set" newline bitfld.long 0x08 14. " [14] ,Event 14 sets DMA request 1" "Not set,Set" bitfld.long 0x08 13. " [13] ,Event 13 sets DMA request 1" "Not set,Set" bitfld.long 0x08 12. " [12] ,Event 12 sets DMA request 1" "Not set,Set" newline bitfld.long 0x08 11. " [11] ,Event 11 sets DMA request 1" "Not set,Set" bitfld.long 0x08 10. " [10] ,Event 10 sets DMA request 1" "Not set,Set" bitfld.long 0x08 9. " [9] ,Event 9 sets DMA request 1" "Not set,Set" newline bitfld.long 0x08 8. " [8] ,Event 8 sets DMA request 1" "Not set,Set" bitfld.long 0x08 7. " [7] ,Event 7 sets DMA request 1" "Not set,Set" bitfld.long 0x08 6. " [6] ,Event 6 sets DMA request 1" "Not set,Set" endif newline sif cpuis("LPC11E*") bitfld.long 0x08 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set" else bitfld.long 0x08 5. " [5] ,Event 5 sets DMA request 1" "Not set,Set" endif bitfld.long 0x08 4. " [4] ,Event 4 sets DMA request 1" "Not set,Set" bitfld.long 0x08 3. " [3] ,Event 3 sets DMA request 1" "Not set,Set" newline bitfld.long 0x08 2. " [2] ,Event 2 sets DMA request 1" "Not set,Set" bitfld.long 0x08 1. " [1] ,Event 1 sets DMA request 1" "Not set,Set" bitfld.long 0x08 0. " [0] ,Event 0 sets DMA request 1" "Not set,Set" sif cpuis("LPC11E*") group.long 0xF0++0x07 line.long 0x00 "EVEN,SCT Flag Enable Register" bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled" line.long 0x04 "EVFLAG,SCT Event Flag Register" bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred" "Not occurred,Occurred" bitfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred" bitfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred" newline bitfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred" bitfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred" bitfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred" else group.long 0xF0++0x07 line.long 0x00 "EVEN,SCT Flag Enable Register" bitfld.long 0x00 15. " IEN15 ,Event 15 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Event 14 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Event 13 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Event 12 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Event 11 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Event 10 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Event 9 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Event 8 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Event 7 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Event 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Event 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Event 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Event 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Event 1 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Event 0 interrupt enable" "Disabled,Enabled" line.long 0x04 "EVFLAG,SCT Event Flag Register" eventfld.long 0x04 15. " FLAG15 ,Event 15occurred" "Not occurred,Occurred" eventfld.long 0x04 14. " [14] ,Event 14 occurred" "Not occurred,Occurred" eventfld.long 0x04 13. " [13] ,Event 13 occurred" "Not occurred,Occurred" newline eventfld.long 0x04 12. " [12] ,Event 12 occurred" "Not occurred,Occurred" eventfld.long 0x04 11. " [11] ,Event 11 occurred" "Not occurred,Occurred" eventfld.long 0x04 10. " [10] ,Event 10 occurred" "Not occurred,Occurred" newline eventfld.long 0x04 9. " [9] ,Event 9 occurred" "Not occurred,Occurred" eventfld.long 0x04 8. " [8] ,Event 8 occurred" "Not occurred,Occurred" eventfld.long 0x04 7. " [7] ,Event 7 occurred" "Not occurred,Occurred" newline eventfld.long 0x04 6. " [6] ,Event 6 occurred" "Not occurred,Occurred" eventfld.long 0x04 5. " [5] ,Event 5 occurred" "Not occurred,Occurred" eventfld.long 0x04 4. " [4] ,Event 4 occurred" "Not occurred,Occurred" newline eventfld.long 0x04 3. " [3] ,Event 3 occurred" "Not occurred,Occurred" eventfld.long 0x04 2. " [2] ,Event 2 occurred" "Not occurred,Occurred" eventfld.long 0x04 1. " [1] ,Event 1 occurred" "Not occurred,Occurred" newline eventfld.long 0x04 0. " [0] ,Event 0 occurred" "Not occurred,Occurred" endif group.long 0xF8++0x03 line.long 0x00 "CONEN,SCT Conflict Enable Register" sif cpuis("LPC11E*") bitfld.long 0x00 3. " NCEN[3] ,No change conflict event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled" else bitfld.long 0x00 15. " NCEN[15] ,No change conflict event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,No change conflict event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,No change conflict event 13 enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,No change conflict event 12 enable" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,No change conflict event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,No change conflict event 10 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,No change conflict event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,No change conflict event 8 enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,No change conflict event 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,No change conflict event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,No change conflict event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,No change conflict event 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,No change conflict event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,No change conflict event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,No change conflict event 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,No change conflict event 0 enable" "Disabled,Enabled" endif sif cpuis("LPC11E*") group.long 0xFC++0x03 line.long 0x00 "CONFLAG,SCT Conflict Flag Register" bitfld.long 0x00 31. " BUSERRH ,Bus error from this SCT involved writing CTR H/STATE H/MATCH H/Output register" "No error,Error" bitfld.long 0x00 30. " BUSERRL ,Bus error from this SCT involved writing CTR L-Unified/STATE L-Unified/MATCH L-Unified/Output register" "No error,Error" bitfld.long 0x00 3. " NCFLAG[3] ,No-change conflict event 3 occurred" "Not occurred,Occurred" newline bitfld.long 0x00 2. " [2] ,No-change conflict event 2 occurred" "Not occurred,Occurred" bitfld.long 0x00 1. " [1] ,No-change conflict event 1 occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,No-change conflict event 0 occurred" "Not occurred,Occurred" else group.long 0xFC++0x03 line.long 0x00 "CONFLAG,SCT Conflict Flag Register" bitfld.long 0x00 31. " BUSERRH ,Bus error" "No error,Error" bitfld.long 0x00 30. " BUSERRL ,Bus error" "No error,Error" bitfld.long 0x00 15. " NCFLAG15 ,No-change conflict event 15 occurred" "Not occurred,Occurred" newline bitfld.long 0x00 14. " NCFLAG14 ,No-change conflict event 14 occurred" "Not occurred,Occurred" bitfld.long 0x00 13. " NCFLAG13 ,No-change conflict event 13 occurred" "Not occurred,Occurred" bitfld.long 0x00 12. " NCFLAG12 ,No-change conflict event 12 occurred" "Not occurred,Occurred" newline bitfld.long 0x00 11. " NCFLAG11 ,No-change conflict event 11 occurred" "Not occurred,Occurred" bitfld.long 0x00 10. " NCFLAG10 ,No-change conflict event 10 occurred" "Not occurred,Occurred" bitfld.long 0x00 9. " NCFLAG9 ,No-change conflict event 9 occurred" "Not occurred,Occurred" newline bitfld.long 0x00 8. " NCFLAG8 ,No-change conflict event 8 occurred" "Not occurred,Occurred" bitfld.long 0x00 7. " NCFLAG7 ,No-change conflict event 7 occurred" "Not occurred,Occurred" bitfld.long 0x00 6. " NCFLAG6 ,No-change conflict event 6 occurred" "Not occurred,Occurred" newline bitfld.long 0x00 5. " NCFLAG5 ,No-change conflict event 5 occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " NCFLAG4 ,No-change conflict event 4 occurred" "Not occurred,Occurred" bitfld.long 0x00 3. " NCFLAG3 ,No-change conflict event 3 occurred" "Not occurred,Occurred" newline bitfld.long 0x00 2. " NCFLAG2 ,No-change conflict event 2 occurred" "Not occurred,Occurred" bitfld.long 0x00 1. " NCFLAG1 ,No-change conflict event 1 occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " NCFLAG0 ,No-change conflict event 0 occurred" "Not occurred,Occurred" endif width 26. tree "Event 0 (Regmode0 0/1)" if (((per.l(ad:0x50004000))&0x01)==0x01) if (((per.l(ad:0x50004000+0x04))&0x04)==0x00) if (((per.l(ad:0x50004000+0x4C))&(1<<0.))==(1<<0.)) rgroup.long 0x100++0x03 line.long 0x00 "CAP0,SCT Capture Register 0" else rgroup.long 0x100++0x03 line.long 0x00 "MATCH0,SCT Match Register 0" endif else if (((per.l(ad:0x50004000+0x4C))&(1<<0.))==(1<<0.)) group.long 0x100++0x03 line.long 0x00 "CAP0,SCT Capture Register 0" else group.long 0x100++0x03 line.long 0x00 "MATCH0,SCT Match Register 0" endif endif else if (((per.w(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<0.))==(1<<0.)) group.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit" else group.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<0.))==(1<<0.)) group.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit" else group.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<0.))==(1<<0.)) rgroup.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit" else rgroup.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<0.))==(1<<0.)) group.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit" else group.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x04))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<0.))==(1<<0.)) group.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit" else group.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<0.))==(1<<0.)) rgroup.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register 0 Low Counter 16-bit" else rgroup.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Register 0 Low Counter 16-bit" endif else if (((per.w(ad:0x50004000+0x4C))&(1<<0.))==(1<<0.)) rgroup.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register 0 Low Counter 16-bit" else rgroup.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Register 0 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<0.))==(1<<0.)) rgroup.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register 0 High Counter 16-bit" else rgroup.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Register 0 High Counter 16-bit" endif endif endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x140++0x03 line.long 0x00 "FRACMAT0_L,SCT Fractional Match Register 0" bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word 0x140++0x03 line.word 0x00 "FRACMAT0_L,SCT Fractional Match Register 0" bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMAT0_H,SCT Fractional Match Register 0" bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x100+0x100)++0x03 line.long 0x00 "MATCHREL0/CAPCTRL0,SCT Match/capture Reload Register 0" bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled" bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word (0x100+0x100)++0x03 line.word 0x00 "MATCHREL0_L/CAPCTRL0_L,SCT Match/capture Reload Register 0" bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL0_H/CAPCTRL0_H,SCT Match/capture Reload Register 0" bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled" endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x140+0x100)++0x03 line.long 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0" bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word (0x140+0x100)++0x03 line.word 0x00 "FRACMATREL0_L,SCT Fractional Match Reload Register 0" bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMATREL0_H,SCT Fractional Match Reload Register 0" bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif group.long (0x100+0x200)++0x03 line.long 0x00 "EV0_STATE,SCT Event State Mask 0" sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*")) bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked" newline bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked" newline bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked" newline bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked" newline bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked" newline bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked" newline bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" newline bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline else bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" newline bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline endif bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x100+0x204)++0x03 line.long 0x00 "EVCTRL0,SCT Event Control Register 0" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" textfld " " bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x100+0x204)++0x03 line.long 0x00 "EVCTRL0,SCT Event Control Register 0" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("LPC11E*") group.long (0x100+0x400)++0x07 line.long 0x00 "OUT0_SET,SCT Output Set Register 0" bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set" bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set" line.long 0x04 "OUT0_CLR,SCT Output Clear Register 0" bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared" newline bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared" else group.long (0x100+0x400)++0x07 line.long 0x00 "OUTPUTSET0,SCT Output Set Register 0" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set" newline else bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 0" "Not set,Set" bitfld.long 0x00 14. " [14] ,Event 14 to set output 0" "Not set,Set" bitfld.long 0x00 13. " [13] ,Event 13 to set output 0" "Not set,Set" bitfld.long 0x00 12. " [12] ,Event 12 to set output 0" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Event 11 to set output 0" "Not set,Set" bitfld.long 0x00 10. " [10] ,Event 10 to set output 0" "Not set,Set" bitfld.long 0x00 9. " [9] ,Event 9 to set output 0" "Not set,Set" bitfld.long 0x00 8. " [8] ,Event 8 to set output 0" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Event 7 to set output 0" "Not set,Set" bitfld.long 0x00 6. " [6] ,Event 6 to set output 0" "Not set,Set" bitfld.long 0x00 5. " [5] ,Event 5 to set output 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 0" "Not set,Set" newline endif bitfld.long 0x00 3. " [3] ,Event 3 to set output 0" "Not set,Set" bitfld.long 0x00 2. " [2] ,Event 2 to set output 0" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 0" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 0" "Not set,Set" line.long 0x04 "OUTPUTCL0,SCT Output Clear Register 0" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared" newline else bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Event 14 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 13. " [13] ,Event 13 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Event 12 to clear output 0" "Not cleared,Cleared" newline bitfld.long 0x04 11. " [11] ,Event 11 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Event 10 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 9. " [9] ,Event 9 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Event 8 to clear output 0" "Not cleared,Cleared" newline bitfld.long 0x04 7. " [7] ,Event 7 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Event 6 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 5. " [5] ,Event 5 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 0" "Not cleared,Cleared" newline endif bitfld.long 0x04 3. " [3] ,Event 3 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 0" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 0" "Not cleared,Cleared" endif tree.end tree "Event 1 (Regmode1 0/1)" if (((per.l(ad:0x50004000))&0x01)==0x01) if (((per.l(ad:0x50004000+0x04))&0x04)==0x00) if (((per.l(ad:0x50004000+0x4C))&(1<<1.))==(1<<1.)) rgroup.long 0x104++0x03 line.long 0x00 "CAP1,SCT Capture Register 1" else rgroup.long 0x104++0x03 line.long 0x00 "MATCH1,SCT Match Register 1" endif else if (((per.l(ad:0x50004000+0x4C))&(1<<1.))==(1<<1.)) group.long 0x104++0x03 line.long 0x00 "CAP1,SCT Capture Register 1" else group.long 0x104++0x03 line.long 0x00 "MATCH1,SCT Match Register 1" endif endif else if (((per.w(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<1.))==(1<<1.)) group.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit" else group.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<1.))==(1<<1.)) group.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit" else group.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<1.))==(1<<1.)) rgroup.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit" else rgroup.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<1.))==(1<<1.)) group.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit" else group.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x04))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<1.))==(1<<1.)) group.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit" else group.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<1.))==(1<<1.)) rgroup.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register 1 Low Counter 16-bit" else rgroup.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Register 1 Low Counter 16-bit" endif else if (((per.w(ad:0x50004000+0x4C))&(1<<1.))==(1<<1.)) rgroup.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register 1 Low Counter 16-bit" else rgroup.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Register 1 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<1.))==(1<<1.)) rgroup.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register 1 High Counter 16-bit" else rgroup.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Register 1 High Counter 16-bit" endif endif endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x144++0x03 line.long 0x00 "FRACMAT1_L,SCT Fractional Match Register 1" bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word 0x144++0x03 line.word 0x00 "FRACMAT1_L,SCT Fractional Match Register 1" bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMAT1_H,SCT Fractional Match Register 1" bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x104+0x100)++0x03 line.long 0x00 "MATCHREL1/CAPCTRL1,SCT Match/capture Reload Register 1" bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled" bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word (0x104+0x100)++0x03 line.word 0x00 "MATCHREL1_L/CAPCTRL1_L,SCT Match/capture Reload Register 1" bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL1_H/CAPCTRL1_H,SCT Match/capture Reload Register 1" bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled" endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x144+0x100)++0x03 line.long 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1" bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word (0x144+0x100)++0x03 line.word 0x00 "FRACMATREL1_L,SCT Fractional Match Reload Register 1" bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMATREL1_H,SCT Fractional Match Reload Register 1" bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif group.long (0x108+0x200)++0x03 line.long 0x00 "EV1_STATE,SCT Event State Mask 1" sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*")) bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked" newline bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked" newline bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked" newline bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked" newline bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked" newline bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked" newline bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" newline bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline else bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" newline bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline endif bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x108+0x204)++0x03 line.long 0x00 "EVCTRL1,SCT Event Control Register 1" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" textfld " " bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x108+0x204)++0x03 line.long 0x00 "EVCTRL1,SCT Event Control Register 1" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("LPC11E*") group.long (0x108+0x400)++0x07 line.long 0x00 "OUT1_SET,SCT Output Set Register 1" bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set" bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set" line.long 0x04 "OUT1_CLR,SCT Output Clear Register 1" bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared" else group.long (0x108+0x400)++0x07 line.long 0x00 "OUTPUTSET1,SCT Output Set Register 1" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 1" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set" newline else bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 1" "Not set,Set" bitfld.long 0x00 14. " [14] ,Event 14 to set output 1" "Not set,Set" bitfld.long 0x00 13. " [13] ,Event 13 to set output 1" "Not set,Set" bitfld.long 0x00 12. " [12] ,Event 12 to set output 1" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Event 11 to set output 1" "Not set,Set" bitfld.long 0x00 10. " [10] ,Event 10 to set output 1" "Not set,Set" bitfld.long 0x00 9. " [9] ,Event 9 to set output 1" "Not set,Set" bitfld.long 0x00 8. " [8] ,Event 8 to set output 1" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Event 7 to set output 1" "Not set,Set" bitfld.long 0x00 6. " [6] ,Event 6 to set output 1" "Not set,Set" bitfld.long 0x00 5. " [5] ,Event 5 to set output 1" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 1" "Not set,Set" newline endif bitfld.long 0x00 3. " [3] ,Event 3 to set output 1" "Not set,Set" bitfld.long 0x00 2. " [2] ,Event 2 to set output 1" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 1" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 1" "Not set,Set" line.long 0x04 "OUTPUTCL1,SCT Output Clear Register 1" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared" newline else bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Event 14 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 13. " [13] ,Event 13 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Event 12 to clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 11. " [11] ,Event 11 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Event 10 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 9. " [9] ,Event 9 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Event 8 to clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 7. " [7] ,Event 7 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Event 6 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 5. " [5] ,Event 5 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 1" "Not cleared,Cleared" newline endif bitfld.long 0x04 3. " [3] ,Event 3 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 1" "Not cleared,Cleared" endif tree.end tree "Event 2 (Regmode2 0/1)" if (((per.l(ad:0x50004000))&0x01)==0x01) if (((per.l(ad:0x50004000+0x04))&0x04)==0x00) if (((per.l(ad:0x50004000+0x4C))&(1<<2.))==(1<<2.)) rgroup.long 0x108++0x03 line.long 0x00 "CAP2,SCT Capture Register 2" else rgroup.long 0x108++0x03 line.long 0x00 "MATCH2,SCT Match Register 2" endif else if (((per.l(ad:0x50004000+0x4C))&(1<<2.))==(1<<2.)) group.long 0x108++0x03 line.long 0x00 "CAP2,SCT Capture Register 2" else group.long 0x108++0x03 line.long 0x00 "MATCH2,SCT Match Register 2" endif endif else if (((per.w(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<2.))==(1<<2.)) group.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit" else group.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<2.))==(1<<2.)) group.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit" else group.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<2.))==(1<<2.)) rgroup.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit" else rgroup.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<2.))==(1<<2.)) group.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit" else group.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x04))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<2.))==(1<<2.)) group.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit" else group.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<2.))==(1<<2.)) rgroup.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register 2 Low Counter 16-bit" else rgroup.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Register 2 Low Counter 16-bit" endif else if (((per.w(ad:0x50004000+0x4C))&(1<<2.))==(1<<2.)) rgroup.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register 2 Low Counter 16-bit" else rgroup.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Register 2 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<2.))==(1<<2.)) rgroup.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register 2 High Counter 16-bit" else rgroup.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Register 2 High Counter 16-bit" endif endif endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x148++0x03 line.long 0x00 "FRACMAT2_L,SCT Fractional Match Register 2" bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word 0x148++0x03 line.word 0x00 "FRACMAT2_L,SCT Fractional Match Register 2" bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMAT2_H,SCT Fractional Match Register 2" bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x108+0x100)++0x03 line.long 0x00 "MATCHREL2/CAPCTRL2,SCT Match/capture Reload Register 2" bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled" bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word (0x108+0x100)++0x03 line.word 0x00 "MATCHREL2_L/CAPCTRL2_L,SCT Match/capture Reload Register 2" bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL2_H/CAPCTRL2_H,SCT Match/capture Reload Register 2" bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled" endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x148+0x100)++0x03 line.long 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2" bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word (0x148+0x100)++0x03 line.word 0x00 "FRACMATREL2_L,SCT Fractional Match Reload Register 2" bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMATREL2_H,SCT Fractional Match Reload Register 2" bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif group.long (0x110+0x200)++0x03 line.long 0x00 "EV2_STATE,SCT Event State Mask 2" sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*")) bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked" newline bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked" newline bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked" newline bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked" newline bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked" newline bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked" newline bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" newline bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline else bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" newline bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline endif bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x110+0x204)++0x03 line.long 0x00 "EVCTRL2,SCT Event Control Register 2" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" textfld " " bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x110+0x204)++0x03 line.long 0x00 "EVCTRL2,SCT Event Control Register 2" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("LPC11E*") group.long (0x110+0x400)++0x07 line.long 0x00 "OUT2_SET,SCT Output Set Register 2" bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set" bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set" line.long 0x04 "OUT2_CLR,SCT Output Clear Register 2" bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared" else group.long (0x110+0x400)++0x07 line.long 0x00 "OUTPUTSET2,SCT Output Set Register 2" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 2" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set" newline else bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 2" "Not set,Set" bitfld.long 0x00 14. " [14] ,Event 14 to set output 2" "Not set,Set" bitfld.long 0x00 13. " [13] ,Event 13 to set output 2" "Not set,Set" bitfld.long 0x00 12. " [12] ,Event 12 to set output 2" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Event 11 to set output 2" "Not set,Set" bitfld.long 0x00 10. " [10] ,Event 10 to set output 2" "Not set,Set" bitfld.long 0x00 9. " [9] ,Event 9 to set output 2" "Not set,Set" bitfld.long 0x00 8. " [8] ,Event 8 to set output 2" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Event 7 to set output 2" "Not set,Set" bitfld.long 0x00 6. " [6] ,Event 6 to set output 2" "Not set,Set" bitfld.long 0x00 5. " [5] ,Event 5 to set output 2" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 2" "Not set,Set" newline endif bitfld.long 0x00 3. " [3] ,Event 3 to set output 2" "Not set,Set" bitfld.long 0x00 2. " [2] ,Event 2 to set output 2" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 2" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 2" "Not set,Set" line.long 0x04 "OUTPUTCL2,SCT Output Clear Register 2" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared" newline else bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Event 14 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 13. " [13] ,Event 13 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Event 12 to clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 11. " [11] ,Event 11 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Event 10 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 9. " [9] ,Event 9 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Event 8 to clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 7. " [7] ,Event 7 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Event 6 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 5. " [5] ,Event 5 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 2" "Not cleared,Cleared" newline endif bitfld.long 0x04 3. " [3] ,Event 3 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 2" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 2" "Not cleared,Cleared" endif tree.end tree "Event 3 (Regmode3 0/1)" if (((per.l(ad:0x50004000))&0x01)==0x01) if (((per.l(ad:0x50004000+0x04))&0x04)==0x00) if (((per.l(ad:0x50004000+0x4C))&(1<<3.))==(1<<3.)) rgroup.long 0x10C++0x03 line.long 0x00 "CAP3,SCT Capture Register 3" else rgroup.long 0x10C++0x03 line.long 0x00 "MATCH3,SCT Match Register 3" endif else if (((per.l(ad:0x50004000+0x4C))&(1<<3.))==(1<<3.)) group.long 0x10C++0x03 line.long 0x00 "CAP3,SCT Capture Register 3" else group.long 0x10C++0x03 line.long 0x00 "MATCH3,SCT Match Register 3" endif endif else if (((per.w(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<3.))==(1<<3.)) group.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit" else group.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<3.))==(1<<3.)) group.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit" else group.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<3.))==(1<<3.)) rgroup.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit" else rgroup.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<3.))==(1<<3.)) group.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit" else group.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x04))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&(1<<3.))==(1<<3.)) group.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit" else group.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<3.))==(1<<3.)) rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register 3 Low Counter 16-bit" else rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Register 3 Low Counter 16-bit" endif else if (((per.w(ad:0x50004000+0x4C))&(1<<3.))==(1<<3.)) rgroup.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register 3 Low Counter 16-bit" else rgroup.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Register 3 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&(1<<3.))==(1<<3.)) rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register 3 High Counter 16-bit" else rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Register 3 High Counter 16-bit" endif endif endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S*")||cpuis("LPC43S37*")||cpuis("LPC43S57*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long 0x14C++0x03 line.long 0x00 "FRACMAT3_L,SCT Fractional Match Register 3" bitfld.long 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word 0x14C++0x03 line.word 0x00 "FRACMAT3_L,SCT Fractional Match Register 3" bitfld.word 0x00 0.--3. " FRACMAT_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMAT3_H,SCT Fractional Match Register 3" bitfld.word 0x02 0.--3. " FRACMAT_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x10C+0x100)++0x03 line.long 0x00 "MATCHREL3/CAPCTRL3,SCT Match/capture Reload Register 3" bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled" bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word (0x10C+0x100)++0x03 line.word 0x00 "MATCHREL3_L/CAPCTRL3_L,SCT Match/capture Reload Register 3" bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL3_H/CAPCTRL3_H,SCT Match/capture Reload Register 3" bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled" endif sif cpuis("LPC1812")||cpuis("LPC1813")||cpuis("LPC1815")||cpuis("LPC1817")||cpuis("LPC1822")||cpuis("LPC1823")||cpuis("LPC1825")||cpuis("LPC1827")||cpuis("LPC1833")||cpuis("LPC1837")||cpuis("LPC1853")||cpuis("LPC1857")||cpuis("LPC4312*")||cpuis("LPC4313*")||cpuis("LPC4315*")||cpuis("LPC4317*")||cpuis("LPC4322*")||cpuis("LPC4323*")||cpuis("LPC4325*")||cpuis("LPC4327*")||cpuis("LPC4333*")||cpuis("LPC4337*")||cpuis("LPC4353*")||cpuis("LPC4357*")||cpuis("LPC43S37*")||cpuis("LPC43S57*")||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*") if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x14C+0x100)++0x03 line.long 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3" bitfld.long 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.word (0x14C+0x100)++0x03 line.word 0x00 "FRACMATREL3_L,SCT Fractional Match Reload Register 3" bitfld.word 0x00 0.--3. " RELFRAC_L ,Dither pattern for MATCH3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x02 "FRACMATREL3_H,SCT Fractional Match Reload Register 3" bitfld.word 0x02 0.--3. " RELFRAC_H ,Dither pattern for MATCH3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif group.long (0x118+0x200)++0x03 line.long 0x00 "EV3_STATE,SCT Event State Mask 3" sif (cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812M101FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC11E*")) bitfld.long 0x00 31. " STATEMSK[31] ,SCT event state mask 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,SCT event state mask 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,SCT event state mask 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,SCT event state mask 28" "Masked,Not masked" newline bitfld.long 0x00 27. " [27] ,SCT event state mask 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,SCT event state mask 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,SCT event state mask 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,SCT event state mask 24" "Masked,Not masked" newline bitfld.long 0x00 23. " [23] ,SCT event state mask 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,SCT event state mask 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,SCT event state mask 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,SCT event state mask 20" "Masked,Not masked" newline bitfld.long 0x00 19. " [19] ,SCT event state mask 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,SCT event state mask 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,SCT event state mask 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,SCT event state mask 16" "Masked,Not masked" newline bitfld.long 0x00 15. " [15] ,SCT event state mask 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,SCT event state mask 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,SCT event state mask 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,SCT event state mask 12" "Masked,Not masked" newline bitfld.long 0x00 11. " [11] ,SCT event state mask 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,SCT event state mask 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,SCT event state mask 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,SCT event state mask 8" "Masked,Not masked" newline bitfld.long 0x00 7. " [7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" newline bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline else bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" newline bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline endif bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked" if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x118+0x204)++0x03 line.long 0x00 "EVCTRL3,SCT Event Control Register 3" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" textfld " " bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x118+0x204)++0x03 line.long 0x00 "EVCTRL3,SCT Event Control Register 3" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC181*")||cpuis("LPC182*")||cpuis("LPC183*")||cpuis("LPC185*")||cpuis("LPC43S2*")||cpuis("LPC43S3*")||cpuis("LPC43S5*"))||cpuis("LPC811M001JDH16")||cpuis("LPC832M101FDH20")||cpuis("LPC834M101FHI33")||cpuis("LPC84*")||cpuis("LPC11E*") bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline endif bitfld.long 0x00 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("LPC11E*") group.long (0x118+0x400)++0x07 line.long 0x00 "OUT3_SET,SCT Output Set Register 3" bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set" bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set" line.long 0x04 "OUT3_CLR,SCT Output Clear Register 3" bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared" else group.long (0x118+0x400)++0x07 line.long 0x00 "OUTPUTSET3,SCT Output Set Register 3" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x00 5. " SET[5] ,Event 5 to set output 3" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set" newline else bitfld.long 0x00 15. " SET[15] ,Event 15 to set output 3" "Not set,Set" bitfld.long 0x00 14. " [14] ,Event 14 to set output 3" "Not set,Set" bitfld.long 0x00 13. " [13] ,Event 13 to set output 3" "Not set,Set" bitfld.long 0x00 12. " [12] ,Event 12 to set output 3" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Event 11 to set output 3" "Not set,Set" bitfld.long 0x00 10. " [10] ,Event 10 to set output 3" "Not set,Set" bitfld.long 0x00 9. " [9] ,Event 9 to set output 3" "Not set,Set" bitfld.long 0x00 8. " [8] ,Event 8 to set output 3" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Event 7 to set output 3" "Not set,Set" bitfld.long 0x00 6. " [6] ,Event 6 to set output 3" "Not set,Set" bitfld.long 0x00 5. " [5] ,Event 5 to set output 3" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 to set output 3" "Not set,Set" newline endif bitfld.long 0x00 3. " [3] ,Event 3 to set output 3" "Not set,Set" bitfld.long 0x00 2. " [2] ,Event 2 to set output 3" "Not set,Set" bitfld.long 0x00 1. " [1] ,Event 1 to set output 3" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 to set output 3" "Not set,Set" line.long 0x04 "OUTPUTCL3,SCT Output Clear Register 3" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20") bitfld.long 0x04 5. " CLR[5] ,Event 5 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared" newline else bitfld.long 0x04 15. " CLR[15] ,Event 15 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Event 14 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 13. " [13] ,Event 13 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Event 12 to clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 11. " [11] ,Event 11 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Event 10 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 9. " [9] ,Event 9 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Event 8 to clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 7. " [7] ,Event 7 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Event 6 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 5. " [5] ,Event 5 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Event 4 to clear output 3" "Not cleared,Cleared" newline endif bitfld.long 0x04 3. " [3] ,Event 3 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Event 1 to clear output 3" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Event 0 to clear output 3" "Not cleared,Cleared" endif tree.end sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20")||cpuis("LPC11E*") tree "Event 4 (Regmode4 0/1)" if (((per.l(ad:0x50004000))&0x01)==0x01) if (((per.l(ad:0x50004000+0x04))&0x04)==0x00) if (((per.l(ad:0x50004000+0x4C))&0x10)==0x10) rgroup.long 0x110++0x03 line.long 0x00 "CAP4,SCT Capture Register 4" else rgroup.long 0x110++0x03 line.long 0x00 "MATCH4,SCT Match Register 4" endif else if (((per.l(ad:0x50004000+0x4C))&0x10)==0x10) group.long 0x110++0x03 line.long 0x00 "CAP4,SCT Capture Register 4" else group.long 0x110++0x03 line.long 0x00 "MATCH4,SCT Match Register 4" endif endif else if (((per.w(ad:0x50004000+0x04))&0x04)==0x04)&&(((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&0x10)==0x10) group.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit" else group.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&0x10)==0x10) group.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit" else group.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x06))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&0x10)==0x10) rgroup.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit" else rgroup.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&0x10)==0x10) group.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit" else group.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit" endif elif (((per.w(ad:0x50004000+0x04))&0x04)==0x04) if (((per.w(ad:0x50004000+0x4C))&0x10)==0x10) group.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit" else group.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&0x10)==0x10) rgroup.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register 4 Low Counter 16-bit" else rgroup.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Register 4 Low Counter 16-bit" endif else if (((per.w(ad:0x50004000+0x4C))&0x10)==0x10) rgroup.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register 4 Low Counter 16-bit" else rgroup.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Register 4 Low Counter 16-bit" endif if (((per.w(ad:0x50004000+0x4E))&0x10)==0x10) rgroup.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register 4 High Counter 16-bit" else rgroup.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Register 4 High Counter 16-bit" endif endif endif if (((per.l(ad:0x50004000))&0x01)==0x01) group.long (0x210)++0x03 line.long 0x00 "MATCHREL4/CAPCTRL4,SCT Match/capture Reload Register 4" bitfld.long 0x00 31. " RELOAD31_H/CAPCON31_H ,SCT match/capture reload register 31" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD30_H/CAPCON30_H ,SCT match/capture reload register 30" "Disabled,Enabled" bitfld.long 0x00 29. " RELOAD29_H/CAPCON29_H ,SCT match/capture reload register 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " RELOAD28_H/CAPCON28_H ,SCT match/capture reload register 28" "Disabled,Enabled" bitfld.long 0x00 27. " RELOAD27_H/CAPCON27_H ,SCT match/capture reload register 27" "Disabled,Enabled" bitfld.long 0x00 26. " RELOAD26_H/CAPCON26_H ,SCT match/capture reload register 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " RELOAD25_H/CAPCON25_H ,SCT match/capture reload register 25" "Disabled,Enabled" bitfld.long 0x00 24. " RELOAD24_H/CAPCON24_H ,SCT match/capture reload register 24" "Disabled,Enabled" bitfld.long 0x00 23. " RELOAD23_H/CAPCON23_H ,SCT match/capture reload register 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " RELOAD22_H/CAPCON22_H ,SCT match/capture reload register 22" "Disabled,Enabled" bitfld.long 0x00 21. " RELOAD21_H/CAPCON21_H ,SCT match/capture reload register 21" "Disabled,Enabled" bitfld.long 0x00 20. " RELOAD20_H/CAPCON20_H ,SCT match/capture reload register 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " RELOAD19_H/CAPCON19_H ,SCT match/capture reload register 19" "Disabled,Enabled" bitfld.long 0x00 18. " RELOAD18_H/CAPCON18_H ,SCT match/capture reload register 18" "Disabled,Enabled" bitfld.long 0x00 17. " RELOAD17_H/CAPCON17_H ,SCT match/capture reload register 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " RELOAD16_H/CAPCON16_H ,SCT match/capture reload register 16" "Disabled,Enabled" bitfld.long 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.long 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" bitfld.long 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.long 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" bitfld.long 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.long 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" bitfld.long 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.long 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" bitfld.long 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.long 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" bitfld.long 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" else group.word (0x210)++0x03 line.word 0x00 "MATCHREL4_L/CAPCTRL4_L,SCT Match/capture Reload Register 4" bitfld.word 0x00 15. " RELOAD15_L/CAPCON15_L ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x00 14. " RELOAD14_L/CAPCON14_L ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x00 13. " RELOAD13_L/CAPCON13_L ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x00 12. " RELOAD12_L/CAPCON12_L ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x00 11. " RELOAD11_L/CAPCON11_L ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x00 10. " RELOAD10_L/CAPCON10_L ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x00 9. " RELOAD9_L/CAPCON9_L ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x00 8. " RELOAD8_L/CAPCON8_L ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x00 7. " RELOAD7_L/CAPCON7_L ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x00 6. " RELOAD6_L/CAPCON6_L ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x00 5. " RELOAD5_L/CAPCON5_L ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x00 4. " RELOAD4_L/CAPCON4_L ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x00 3. " RELOAD3_L/CAPCON3_L ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x00 2. " RELOAD2_L/CAPCON2_L ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x00 1. " RELOAD1_L/CAPCON1_L ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x00 0. " RELOAD0_L/CAPCON0_L ,SCT match/capture reload register 0" "Disabled,Enabled" line.word 0x02 "MATCHREL4_H/CAPCTRL4_H,SCT Match/capture Reload Register 4" bitfld.word 0x02 15. " RELOAD15_H/CAPCON15_H ,SCT match/capture reload register 15" "Disabled,Enabled" bitfld.word 0x02 14. " RELOAD14_H/CAPCON14_H ,SCT match/capture reload register 14" "Disabled,Enabled" bitfld.word 0x02 13. " RELOAD13_H/CAPCON13_H ,SCT match/capture reload register 13" "Disabled,Enabled" newline bitfld.word 0x02 12. " RELOAD12_H/CAPCON12_H ,SCT match/capture reload register 12" "Disabled,Enabled" bitfld.word 0x02 11. " RELOAD11_H/CAPCON11_H ,SCT match/capture reload register 11" "Disabled,Enabled" bitfld.word 0x02 10. " RELOAD10_H/CAPCON10_H ,SCT match/capture reload register 10" "Disabled,Enabled" newline bitfld.word 0x02 9. " RELOAD9_H/CAPCON9_H ,SCT match/capture reload register 9" "Disabled,Enabled" bitfld.word 0x02 8. " RELOAD8_H/CAPCON8_H ,SCT match/capture reload register 8" "Disabled,Enabled" bitfld.word 0x02 7. " RELOAD7_H/CAPCON7_H ,SCT match/capture reload register 7" "Disabled,Enabled" newline bitfld.word 0x02 6. " RELOAD6_H/CAPCON6_H ,SCT match/capture reload register 6" "Disabled,Enabled" bitfld.word 0x02 5. " RELOAD5_H/CAPCON5_H ,SCT match/capture reload register 5" "Disabled,Enabled" bitfld.word 0x02 4. " RELOAD4_H/CAPCON4_H ,SCT match/capture reload register 4" "Disabled,Enabled" newline bitfld.word 0x02 3. " RELOAD3_H/CAPCON3_H ,SCT match/capture reload register 3" "Disabled,Enabled" bitfld.word 0x02 2. " RELOAD2_H/CAPCON2_H ,SCT match/capture reload register 2" "Disabled,Enabled" bitfld.word 0x02 1. " RELOAD1_H/CAPCON1_H ,SCT match/capture reload register 1" "Disabled,Enabled" newline bitfld.word 0x02 0. " RELOAD0_H/CAPCON0_H ,SCT match/capture reload register 0" "Disabled,Enabled" endif group.long (0x320)++0x07 line.long 0x00 "EVSTATEMSK4,SCT Event State Mask 4" sif cpuis("LPC11E*") bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" newline bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline endif bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked" line.long 0x04 "EVCTRL4,SCT Event Control Register 4" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Event 5 (Regmode5 0/1)" group.long (0x328)++0x07 line.long 0x00 "EVSTATEMSK5,SCT Event State Mask 5" sif cpuis("LPC11E*") bitfld.long 0x00 7. " STATEMSK[7] ,SCT event state mask 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,SCT event state mask 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,SCT event state mask 5" "Masked,Not masked" newline bitfld.long 0x00 4. " [4] ,SCT event state mask 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,SCT event state mask 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,SCT event state mask 2" "Masked,Not masked" newline endif bitfld.long 0x00 1. " [1] ,SCT event state mask 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,SCT event state mask 0" "Masked,Not masked" line.long 0x04 "EVCTRL5,SCT Event Control Register 5" bitfld.long 0x04 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x04 20. " MATCHMEM ,Match component for event triggering when combmode=match" "Equal,Greater/less or equal" newline bitfld.long 0x04 15.--19. " STATEV ,This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " STATELD ,This bit controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded" bitfld.long 0x04 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND" bitfld.long 0x04 10.--11. " IOCOND ,Selects the I/O condition for event n" "LOW,Rise,Fall,HIGH" newline bitfld.long 0x04 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. " OUTSEL ,Input/output select" "Input,Output" bitfld.long 0x04 4. " HEVENT ,Select L/H counter" "L,H" bitfld.long 0x04 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end endif width 0x0B endif tree.end endif sif !cpuis("LPC8N04") tree "MRT (Multi-Rate Timer)" base ad:0x40004000 width 10. tree "Channel 0" group.long (0x00+0x0)++0x03 line.long 0x00 "INTVAL0,Time Interval Register 0" bitfld.long 0x00 31. " LOAD ,IVALUE loading method" "No force load,Force load" textline " " hexmask.long 0x00 0.--30. 1. " IVALUE ,Timer interval load value" rgroup.long (0x04+0x0)++0x03 line.long 0x00 "TIMER0,Time Register 0" hexmask.long 0x00 0.--30. 1. " VALUE ,Current down-counter timer value" group.long (0x08+0x0)++0x07 line.long 0x00 "CTRL0,Control Register 0" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,One-shot bus stall,?..." else bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,?..." endif textline " " bitfld.long 0x00 0. " INTEN ,TIMER0 interrupt enable" "Disabled,Enabled" line.long 0x04 "STAT0,Status Register 0" rbitfld.long 0x04 1. " RUN ,TIMER0 state" "Idle,Running" textline " " bitfld.long 0x04 0. " INTFLAG ,Interrupt flag monitor" "Not pending,Pending" tree.end tree "Channel 1" group.long (0x00+0x10)++0x03 line.long 0x00 "INTVAL1,Time Interval Register 1" bitfld.long 0x00 31. " LOAD ,IVALUE loading method" "No force load,Force load" textline " " hexmask.long 0x00 0.--30. 1. " IVALUE ,Timer interval load value" rgroup.long (0x04+0x10)++0x03 line.long 0x00 "TIMER1,Time Register 1" hexmask.long 0x00 0.--30. 1. " VALUE ,Current down-counter timer value" group.long (0x08+0x10)++0x07 line.long 0x00 "CTRL1,Control Register 1" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,One-shot bus stall,?..." else bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,?..." endif textline " " bitfld.long 0x00 0. " INTEN ,TIMER1 interrupt enable" "Disabled,Enabled" line.long 0x04 "STAT1,Status Register 1" rbitfld.long 0x04 1. " RUN ,TIMER1 state" "Idle,Running" textline " " bitfld.long 0x04 0. " INTFLAG ,Interrupt flag monitor" "Not pending,Pending" tree.end tree "Channel 2" group.long (0x00+0x20)++0x03 line.long 0x00 "INTVAL2,Time Interval Register 2" bitfld.long 0x00 31. " LOAD ,IVALUE loading method" "No force load,Force load" textline " " hexmask.long 0x00 0.--30. 1. " IVALUE ,Timer interval load value" rgroup.long (0x04+0x20)++0x03 line.long 0x00 "TIMER2,Time Register 2" hexmask.long 0x00 0.--30. 1. " VALUE ,Current down-counter timer value" group.long (0x08+0x20)++0x07 line.long 0x00 "CTRL2,Control Register 2" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,One-shot bus stall,?..." else bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,?..." endif textline " " bitfld.long 0x00 0. " INTEN ,TIMER2 interrupt enable" "Disabled,Enabled" line.long 0x04 "STAT2,Status Register 2" rbitfld.long 0x04 1. " RUN ,TIMER2 state" "Idle,Running" textline " " bitfld.long 0x04 0. " INTFLAG ,Interrupt flag monitor" "Not pending,Pending" tree.end tree "Channel 3" group.long (0x00+0x30)++0x03 line.long 0x00 "INTVAL3,Time Interval Register 3" bitfld.long 0x00 31. " LOAD ,IVALUE loading method" "No force load,Force load" textline " " hexmask.long 0x00 0.--30. 1. " IVALUE ,Timer interval load value" rgroup.long (0x04+0x30)++0x03 line.long 0x00 "TIMER3,Time Register 3" hexmask.long 0x00 0.--30. 1. " VALUE ,Current down-counter timer value" group.long (0x08+0x30)++0x07 line.long 0x00 "CTRL3,Control Register 3" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,One-shot bus stall,?..." else bitfld.long 0x00 1.--2. " MODE ,Timer mode select" "Repeat interrupt,One-shot interrupt,?..." endif textline " " bitfld.long 0x00 0. " INTEN ,TIMER3 interrupt enable" "Disabled,Enabled" line.long 0x04 "STAT3,Status Register 3" rbitfld.long 0x04 1. " RUN ,TIMER3 state" "Idle,Running" textline " " bitfld.long 0x04 0. " INTFLAG ,Interrupt flag monitor" "Not pending,Pending" tree.end textline " " sif cpuis("LPC802*")||cpuis("LPC804*") group.long 0xF0++0x03 line.long 0x00 "MODCFG,Module Configuration Register" bitfld.long 0x00 31. " MULTITASK ,Selects the operating mode for the INUSE flags and the IDLE_CH register" "Hardware status,Multi-task" bitfld.long 0x00 4.--8. " NOB ,Identifies the number of timer bits in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " NOC ,Identifies the number of channels in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0xF4++0x03 line.long 0x00 "IDLE_CH,Idle Channel Register" bitfld.long 0x00 4.--7. " CHAN ,Idle channel" "0,1,2,3,All,?..." group.long 0xF8++0x03 line.long 0x00 "IRQ_FLAG,Global Interrupt Flag Register" sif !cpuis("LPC802*")&&!cpuis("LPC804*") bitfld.long 0x00 3. " GFLAG3 ,TIMER3 interrupt flag" "Not pending,Pending" bitfld.long 0x00 2. " GFLAG2 ,TIMER2 interrupt flag" "Not pending,Pending" textline " " endif bitfld.long 0x00 1. " GFLAG1 ,TIMER1 interrupt flag" "Not pending,Pending" bitfld.long 0x00 0. " GFLAG0 ,TIMER0 interrupt flag" "Not pending,Pending" width 0x0B tree.end endif tree "WWDT (Windowed Watchdog Timer)" sif cpuis("LPC8N04") base ad:0x40004000 else base ad:0x40000000 endif width 11. group.long 0x00++0x07 line.long 0x00 "WDMOD,Watchdog Mode Register" sif cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC111D14"||cpuis("LPC1115*")||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*") bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected" textline " " elif (cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC11E*")||cpuis("LPC11U6*")) bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked" bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected" textline " " elif (cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 5. " LOCK ,Watchdog oscillator lock" "Not locked,Locked" bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected" textline " " elif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227") bitfld.long 0x00 7. " WDLOCKEN ,Watchdog enable and reset lockout" "Not locked,Locked" bitfld.long 0x00 6. " WDLOCKDP ,Deep Power-down enable lock" "Not locked,Locked" textline " " bitfld.long 0x00 5. " CSLOCK ,Clock source lock" "Not locked,Locked" bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Not protected,Protected" textline " " endif sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04") eventfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "Not occurred,Occurred" endif bitfld.long 0x00 2. " WDTOF ,Watchdog Time-out flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable" "Disabled,Enabled" sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04") bitfld.long 0x00 0. " WDEN ,Watchdog enable" "Disabled,Enabled" else bitfld.long 0x00 0. " WDEN ,Watchdog interrupt enable" "Disabled,Enabled" endif sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpu()=="LPC11U24"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")||cpu()==("LPC8N04")||cpuis("LPC11D14")) line.long 0x04 "WDTC,Watchdog Timer Constant Register" hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value" else line.long 0x04 "WDTC,Watchdog Timer Constant Register" hexmask.long 0x04 0.--31. 1. " COUNT ,Watchdog time-out interval" endif wgroup.long 0x08++0x03 line.long 0x00 "WDFEED,Watchdog Feed Sequence Register" hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value" sif (cpu()=="EM773"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11C12"||cpu()=="LPC11C14"||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC11C22"||cpu()=="LPC11C24"||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpuis("LPC11E*")||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*"))||cpuis("LPC43S*")||cpuis("LPC11U6")||cpuis("LPC84*")||(cpu()=="LPC811M001JDH16")||(cpu()=="LPC832M101FDH20")||(cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*"))||cpu()=="LPC8N04"||cpuis("LPC11D14") rgroup.long 0x0C++0x03 line.long 0x00 "WDTV,Watchdog Timer Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value" else rgroup.long 0x0C++0x03 line.long 0x00 "WDTV,Watchdog Timer Value Register" hexmask.long 0x00 0.--31. 1. " COUNT ,Counter timer value" endif sif (cpu()!="EM773"&&cpu()!="LPC1311"&&cpu()!="LPC1313"&&cpu()!="LPC1342"&&cpu()!="LPC1343"&&!cpuis("LPC1111*")&&cpu()!="LPC11D14"&&!cpuis("LPC1112*")&&!cpuis("LPC1113*")&&!cpuis("LPC1114*")&&cpu()!="LPC11C12"&&cpu()!="LPC11C14"&&cpu()!="LPC1102"&&cpu()!="LPC1102LV"&&cpu()!="LPC1772"&&cpu()!="LPC1774"&&cpu()!="LPC1776"&&cpu()!="LPC1777"&&cpu()!="LPC1778"&&cpu()!="LPC1785"&&cpu()!="LPC1786"&&cpu()!="LPC1787"&&cpu()!="LPC1788"&&cpu()!="LPC11C22"&&cpu()!="LPC11C24"&&cpu()!="LPC1810"&&cpu()!="LPC1820"&&cpu()!="LPC1830"&&cpu()!="LPC1850"&&cpu()!="LPC1853"&&cpu()!="LPC1857"&&cpu()!="LPC810M021FN8"&&cpu()!="LPC811M001FDH16"&&cpu()!="LPC812M101FD20"&&cpu()!="LPC812FDH16"&&cpu()!="LPC812M101FDH20"&&!cpuis("LPC43*")&&!cpuis("LPC82*")&&!cpuis("LPC812M101J*")&&!cpuis("LPC43S*")&&!cpuis("LPC84*")&&cpu()!="LPC811M001JDH16"&&cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&cpu()!="LPC8N04"&&!cpuis("LPC802*")&&!cpuis("LPC804*")) group.long 0x10++0x03 line.long 0x00 "WDCLKSEL,Watchdog Timer Clock Source Selection Register" bitfld.long 0x00 31. " WDLOCK ,Watchdog lock" "Not locked,Locked" sif (cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227") bitfld.long 0x00 0.--1. " WDSEL1 ,Select the clock source for the watchdog timer" "Internal RC,Watchdog,?..." elif (cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpuis("LPC11U6*")) textline " " bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,Watchdog oscillator" else bitfld.long 0x00 0.--1. " WDSEL2 ,Select the clock source for the watchdog timer" "RC,APB clock,RTC,?..." endif endif sif (cpu()=="LPC1772"||cpu()=="LPC1774"||cpu()=="LPC1776"||cpu()=="LPC1777"||cpu()=="LPC1778"||cpu()=="LPC1785"||cpu()=="LPC1786"||cpu()=="LPC1787"||cpu()=="LPC1788"||cpu()=="LPC1110"||cpuis("LPC1111*")||cpuis("LPC1112*")||cpu()=="LPC1112LV"||cpuis("LPC1113*")||cpuis("LPC1114*")||cpu()=="LPC1114LV"||cpu()=="LPC11D14"||cpuis("LPC1115*")||cpu()=="LPC11U12/201"||cpu()=="LPC11U13/201"||cpu()=="LPC11U14/201"||cpu()=="LPC11U23/301"||cpuis("LPC11U24*")||cpuis("LPC11U3*")||cpu()=="LPC1102"||cpu()=="LPC1102LV"||cpu()=="LPC11A02"||cpu()=="LPC11A04"||cpu()=="LPC11A11"||cpu()=="LPC11A12"||cpu()=="LPC11A13"||cpu()=="LPC11A14"||cpuis("LPC11E*")||cpu()=="LPC1224"||cpu()=="LPC1225"||cpu()=="LPC1226"||cpu()=="LPC1227"||cpu()=="LPC1810"||cpu()=="LPC1820"||cpu()=="LPC1830"||cpu()=="LPC1850"||cpu()=="LPC1853"||cpu()=="LPC1857"||cpu()=="LPC810M021FN8"||cpu()=="LPC811M001FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812FDH16"||cpu()=="LPC812M101FDH20"||(cpu()=="LPC4072FBD80")||(cpu()=="LPC4072FET80")||(cpu()=="LPC4074FBD144")||(cpu()=="LPC4076FBD144")||(cpu()=="LPC4076FET180")||(cpu()=="LPC4078FBD100")||(cpu()=="LPC4078FBD144")||(cpu()=="LPC4078FBD208")||(cpu()=="LPC4078FBD80")||(cpu()=="LPC4078FET180")||(cpu()=="LPC4078FET208")||(cpu()=="LPC4088FBD144")||(cpu()=="LPC4088FBD208")||(cpu()=="LPC4088FET180")||(cpu()=="LPC4088FET208")||cpuis("LPC43*")||cpuis("LPC82*")||cpuis("LPC812M101J*")||cpuis("LPC11U6*")||cpuis("LPC84*")||cpu()=="LPC811M001JDH16"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x14++0x07 line.long 0x00 "WDWARNINT,Watchdog Timer Warning Interrupt Register" hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value" line.long 0x04 "WDWINDOW,Watchdog Timer Window Register" hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value" endif width 0x0B tree.end sif (cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&!cpuis("LPC8N04")) tree "AC (Analog Comparator)" base ad:0x40024000 width 5. group.long 0x00++0x03 line.long 0x00 "CTL,Comparator Control Register" bitfld.long 0x00 25.--26. " HYS ,Controls the hysteresis of the comparator" "None,5 mV,10 mV,20 mV" textline " " sif (cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 24. " INTENA ,Interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " COMPEDGE ,Comparator edge-detect status" "Not detected,Detected" bitfld.long 0x00 21. " COMPSTAT ,Comparator status" "0,1" textline " " bitfld.long 0x00 20. " EDGECLR ,Interrupt clear bit" "0,1" sif (cpu()=="LPC810M021FN8"||cpu()=="LPC811M101FDH16"||cpu()=="LPC812M101FD20"||cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpuis("LPC812M101J*")||cpu()=="LPC811M001JDH16") bitfld.long 0x00 11.--13. " COMP_VM_SEL ,Selects negative voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,,,,Internal reference voltage,?..." bitfld.long 0x00 8.--10. " COMP_VP_SEL ,Selects positive voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,,,,Internal reference voltage,?..." elif (cpuis("LPC82*")) bitfld.long 0x00 11.--13. " COMP_VM_SEL ,Selects negative voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,Internal reference voltage,ADC_0,?..." bitfld.long 0x00 8.--10. " COMP_VP_SEL ,Selects positive voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,Internal reference voltage,ADC_0,?..." elif (cpuis("LPC84*")||cpuis("LPC804*")) bitfld.long 0x00 11.--13. " COMP_VM_SEL ,Selects negative voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,ACMP_I5,Internal reference voltage,DACOUT0" bitfld.long 0x00 8.--10. " COMP_VP_SEL ,Selects positive voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,ACMP_I5,Internal reference voltage,DACOUT0" elif (cpuis("LPC802*")) bitfld.long 0x00 11.--13. " COMP_VM_SEL ,Selects negative voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,ACMP_I5,Internal reference voltage,GND" bitfld.long 0x00 8.--10. " COMP_VP_SEL ,Selects positive voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,GND,Internal reference voltage,GND" else bitfld.long 0x00 11.--13. " COMP_VM_SEL ,Selects negative voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,ACMP_I5,Internal reference voltage,?..." bitfld.long 0x00 8.--10. " COMP_VP_SEL ,Selects positive voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACMP_I4,ACMP_I5,Internal reference voltage,?..." endif textline " " bitfld.long 0x00 6. " COMPSA ,Comparator output control" "Directly,Bus clock" bitfld.long 0x00 3.--4. " EDGESEL ,This field controls which edges on the comparator output set the COMPEDGE bit" "Falling,Rising,Both,Both" sif (!cpuis("LPC822M101JDH20")) group.long 0x04++0x03 line.long 0x00 "LAD,Voltage Ladder Register" sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 6. " LADREF ,Selects the reference voltage Vref for the voltage ladder" "VDD,VDDCMP" textfld " " else bitfld.long 0x00 6. " LADREF ,Selects the reference voltage Vref for the voltage ladder" "VDD/VDD(3V3),VDDCMP" endif bitfld.long 0x00 1.--5. " LADSEL ,Voltage ladder value" "V_SS,1xV_ref/31,2xV_ref/31,3xV_ref/31,4xV_ref/31,5xV_ref/31,6xV_ref/31,7xV_ref/31,8xV_ref/31,9xV_ref/31,10xV_ref/31,11xV_ref/31,12xV_ref/31,13xV_ref/31,14xV_ref/31,15xV_ref/31,16xV_ref/31,17xV_ref/31,18xV_ref/31,19xV_ref/31,20xV_ref/31,21xV_ref/31,22xV_ref/31,23xV_ref/31,24xV_ref/31,25xV_ref/31,26xV_ref/31,27xV_ref/31,28xV_ref/31,29xV_ref/31,30xV_ref/31,V_ref" bitfld.long 0x00 0. " LADEN ,Voltage ladder enable" "Disabled,Enabled" endif width 0x0B tree.end endif sif !cpuis("LPC8N04") tree "WKT (Self Wake-up Timer)" base ad:0x40008000 width 7. group.long 0x00++0x3 line.long 0x00 "CTRL,Control Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 3. " SEL_EXTCLK ,Select clock source for the self-wake-up timer" "Internal,External" textline " " endif bitfld.long 0x00 2. " CLEARCTR ,Self wake-up timer clear" "No effect,Clear" eventfld.long 0x00 1. " ALARMFLAG ,Wake-up or alarm timer flag" "No time-out,Time-out" bitfld.long 0x00 0. " CLKSEL ,Self wake-up timer clock source" "Divided FRO,Low power" group.long 0x0C++0x03 line.long 0x00 "COUNT,Count Register" width 0x0B tree.end endif sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) tree "ADC (Analog to Digital Converter)" base ad:0x4001C000 width 13. sif cpuis("LPC802*") if (((per.l(ad:0x4001C000))&0x100)==0x100) group.long 0x00++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled" newline bitfld.long 0x00 8. " ASYNCMODE ,Asynchronous operation mode" "Synchronous,Asynchronous" else group.long 0x00++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled" newline bitfld.long 0x00 8. " ASYNCMODE ,Asynchronous operation mode" "Synchronous,Asynchronous" hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,System clock divide value" endif else group.long 0x00++0x03 line.long 0x00 "CTRL,Control Register" sif !cpuis("LPC804*") bitfld.long 0x00 30. " CALMODE ,Self-calibration cycle enable" "Disabled,Enabled" newline endif bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled" sif (cpuis("LPC84*")) bitfld.long 0x00 8. " ASYNCMODE ,Asynchronous operation mode" "Synchronous,Asynchronous" endif newline hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,System clock divide value" newline endif group.long 0x08++0x07 line.long 0x00 "SEQA_CTRL,Conversion Sequence A Control Register" bitfld.long 0x00 31. " SEQA_ENA ,Sequence enable" "Disabled,Enabled" bitfld.long 0x00 30. " MODE ,Primary method for retrieving conversion results for this sequence selector" "End of conversion,End of sequence" bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High" bitfld.long 0x00 28. " SINGLESTEP ,Launch only a single conversion on the next channel in the sequence" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled" bitfld.long 0x00 26. " START ,Launch one pass through this conversion sequence" "Not started,Started" bitfld.long 0x00 19. " SYNCBYPASS ,Allows the hardware trigger input to bypass synchronization flip-flops stages" "Not allowed,Allowed" bitfld.long 0x00 18. " TRIGPOL ,Polarity of the selected input trigger for this conversion sequence" "Negative,Positive" newline bitfld.long 0x00 12.--14. " TRIGGER ,Select trigger source to cause this conversion sequence to be initiated" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " CHANNELS ,Selects which one or more of channels will be sampled and converted when this sequence is launched" line.long 0x04 "SEQB_CTRL,Conversion Sequence B Control Register" bitfld.long 0x04 31. " SEQB_ENA ,Sequence Enable" "Disabled,Enabled" bitfld.long 0x04 30. " MODE ,Primary method for retrieving conversion results for this sequence selector" "End of conversion,End of sequence" bitfld.long 0x04 28. " SINGLESTEP ,Launch only a single conversion on the next channel in the sequence" "Disabled,Enabled" bitfld.long 0x04 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled" newline bitfld.long 0x04 26. " START ,Launch one pass through this conversion sequence" "Not started,Started" bitfld.long 0x04 19. " SYNCBYPASS ,Allows the hardware trigger input to bypass synchronization flip-flops stages" "Not allowed,Allowed" bitfld.long 0x04 18. " TRIGPOL ,Polarity of the selected input trigger for this conversion sequence" "Negative,Positive" bitfld.long 0x04 12.--14. " TRIGGER ,Select trigger source to cause this conversion sequence to be initiated" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x04 0.--11. 1. " CHANNELS ,Selects which one or more of channels will be sampled and converted when this sequence is launched" newline hgroup.long 0x010++0x03 hide.long 0x00 "SEQA_GDAT,Global Data Register A" textfld " " in hgroup.long 0x14++0x03 hide.long 0x00 "SEQB_GDAT,Global Data Register B" textfld " " in newline sif (cpuis("LPC824M201JHI33")||cpuis("LPC822M101JHI33")||cpuis("LPC84*")||cpu()=="LPC834M101FHI33"||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")||cpuis("LPC804M111JDH24")) rgroup.long 0x20++0x03 line.long 0x00 "DAT0,Channel Data Register 0" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x24++0x03 line.long 0x00 "DAT1,Channel Data Register 1" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x28++0x03 line.long 0x00 "DAT2,Channel Data Register 2" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x2C++0x03 line.long 0x00 "DAT3,Channel Data Register 3" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x30++0x03 line.long 0x00 "DAT4,Channel Data Register 4" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x34++0x03 line.long 0x00 "DAT5,Channel Data Register 5" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x38++0x03 line.long 0x00 "DAT6,Channel Data Register 6" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x3C++0x03 line.long 0x00 "DAT7,Channel Data Register 7" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x40++0x03 line.long 0x00 "DAT8,Channel Data Register 8" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x44++0x03 line.long 0x00 "DAT9,Channel Data Register 9" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x48++0x03 line.long 0x00 "DAT10,Channel Data Register 10" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x4C++0x03 line.long 0x00 "DAT11,Channel Data Register 11" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" elif cpuis("LPC802M001JDH16") rgroup.long 0x20++0x03 line.long 0x00 "DAT0,Channel Data Register 0" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x24++0x03 line.long 0x00 "DAT1,Channel Data Register 1" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x30++0x03 line.long 0x00 "DAT4,Channel Data Register 4" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x34++0x03 line.long 0x00 "DAT5,Channel Data Register 5" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x38++0x03 line.long 0x00 "DAT6,Channel Data Register 6" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x44++0x03 line.long 0x00 "DAT9,Channel Data Register 9" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x48++0x03 line.long 0x00 "DAT10,Channel Data Register 10" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x4C++0x03 line.long 0x00 "DAT11,Channel Data Register 11" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" elif cpuis("LPC802M011JDH20")||cpuis("LPC804M111JDH24") rgroup.long 0x20++0x03 line.long 0x00 "DAT0,Channel Data Register 0" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x24++0x03 line.long 0x00 "DAT1,Channel Data Register 1" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x28++0x03 line.long 0x00 "DAT2,Channel Data Register 2" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x2C++0x03 line.long 0x00 "DAT3,Channel Data Register 3" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x30++0x03 line.long 0x00 "DAT4,Channel Data Register 4" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x34++0x03 line.long 0x00 "DAT5,Channel Data Register 5" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x38++0x03 line.long 0x00 "DAT6,Channel Data Register 6" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x3C++0x03 line.long 0x00 "DAT7,Channel Data Register 7" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x40++0x03 line.long 0x00 "DAT8,Channel Data Register 8" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x48++0x03 line.long 0x00 "DAT10,Channel Data Register 10" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x4C++0x03 line.long 0x00 "DAT11,Channel Data Register 11" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" "DAT0,DAT1,DAT2,DAT3,DAT4,DAT5,DAT6,DAT7,DAT8,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" else rgroup.long 0x28++0x07 line.long 0x00 "DAT2,Channel Data Register 2" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" ",,DAT2,DAT3,,,,,,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range," hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" line.long 0x04 "DAT3,Channel Data Register 3" bitfld.long 0x04 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x04 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x04 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" ",,DAT2,DAT3,,,,,,DAT9,DAT10,DAT11,?..." bitfld.long 0x04 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x04 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range," hexmask.long.word 0x04 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" rgroup.long 0x44++0x0B line.long 0x00 "DAT9,Channel Data Register 9" bitfld.long 0x00 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x00 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" ",,DAT2,DAT3,,,,,,DAT9,DAT10,DAT11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range," hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" line.long 0x04 "DAT10,Channel Data Register 10" bitfld.long 0x04 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x04 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x04 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" ",,DAT2,DAT3,,,,,,DAT9,DAT10,DAT11,?..." bitfld.long 0x04 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x04 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range," hexmask.long.word 0x04 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" line.long 0x08 "DAT11,Channel Data Register 11" bitfld.long 0x08 31. " DATAVALID ,A/D conversion on this channel is completed" "Not completed,Completed" bitfld.long 0x08 30. " OVERRUN ,New conversion on this channel is completed and overwrites the previous contents" "Not overrun,Overrun" bitfld.long 0x08 26.--29. " CHANNEL ,Contain the channel number that this particular register relates" ",,DAT2,DAT3,,,,,,DAT9,DAT10,DAT11,?..." bitfld.long 0x08 18.--19. " THCMPCROSS ,Threshold crossing comparison result" "Not detected,,Downward direction,Upward direction" newline bitfld.long 0x08 16.--17. " THCMPRANGE ,Threshold range comparison result" "In range,Below range,Above range," hexmask.long.word 0x08 4.--15. 1. " RESULT ,Conversion result from the last conversion performed (on this channel)" endif sif (cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x50++0x03 line.long 0x00 "THR0_LOW,Compare Low Threshold Registers 0" hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value to compare with A/D results" group.long 0x54++0x03 line.long 0x00 "THR1_LOW,Compare Low Threshold Registers 1" hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value to compare with A/D results" group.long 0x58++0x03 line.long 0x00 "THR0_HIGH,Compare High Threshold Registers 0" hexmask.long.word 0x00 4.--15. 1. " THRHIGH ,High threshold value to compare with A/D results" group.long 0x5C++0x03 line.long 0x00 "THR1_HIGH,Compare High Threshold Registers 1" hexmask.long.word 0x00 4.--15. 1. " THRHIGH ,High threshold value to compare with A/D results" else group.long 0x50++0x03 line.long 0x00 "THR0_LOW,Compare Low Threshold Registers 0" hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value to compare with A/D results" group.long 0x58++0x03 line.long 0x00 "THR1_LOW,Compare Low Threshold Registers 1" hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value to compare with A/D results" group.long 0x50++0x03 line.long 0x00 "THR0_HIGH,Compare High Threshold Registers 0" hexmask.long.word 0x00 4.--15. 1. " THRHIGH ,High threshold value to compare with A/D results" group.long 0x58++0x03 line.long 0x00 "THR1_HIGH,Compare High Threshold Registers 1" hexmask.long.word 0x00 4.--15. 1. " THRHIGH ,High threshold value to compare with A/D results" endif newline sif (cpuis("LPC802M001JDH16")) group.long 0x60++0x07 line.long 0x00 "CHAN_THRSEL,Channel Threshold Select Register" bitfld.long 0x00 11. " CH11_THRSEL ,Threshold select for channel 11" "Threshold 0,Threshold 1" bitfld.long 0x00 10. " CH10_THRSEL ,Threshold select for channel 10" "Threshold 0,Threshold 1" bitfld.long 0x00 9. " CH9_THRSEL ,Threshold select for channel 9" "Threshold 0,Threshold 1" newline bitfld.long 0x00 6. " CH6_THRSEL ,Threshold select for channel 6" "Threshold 0,Threshold 1" bitfld.long 0x00 5. " CH5_THRSEL ,Threshold select for channel 5" "Threshold 0,Threshold 1" bitfld.long 0x00 4. " CH4_THRSEL ,Threshold select for channel 4" "Threshold 0,Threshold 1" newline bitfld.long 0x00 1. " CH1_THRSEL ,Threshold select for channel 1" "Threshold 0,Threshold 1" bitfld.long 0x00 0. " CH0_THRSEL ,Threshold select for channel 0" "Threshold 0,Threshold 1" line.long 0x04 "INTEN,Interrupt Enable Register" bitfld.long 0x04 25.--26. " ADCMPINTEN11 ,Threshold comparison interrupt enable for channel 11" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 23.--24. " ADCMPINTEN10 ,Threshold comparison interrupt enable for channel 10" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 21.--22. " ADCMPINTEN9 ,Threshold comparison interrupt enable for channel 9" "Disabled,Outside,Crossing?...," bitfld.long 0x04 15.--16. " ADCMPINTEN6 ,Threshold comparison interrupt enable for channel 6" "Disabled,Outside,Crossing,?..." newline bitfld.long 0x04 13.--14. " ADCMPINTEN5 ,Threshold comparison interrupt enable for channel 5" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 11.--12. " ADCMPINTEN4 ,Threshold comparison interrupt enable for channel 4" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 5.--6. " ADCMPINTEN1 ,Threshold comparison interrupt enable for channel 1" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 3.--4. " ADCMPINTEN0 ,Threshold comparison interrupt enable for channel 0" "Disabled,Outside,Crossing,?..." newline bitfld.long 0x04 2. " OVR_INTEN ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " SEQB_INTEN ,Sequence B interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " SEQA_INTEN ,Sequence A interrupt enable" "Disabled,Enabled" else group.long 0x60++0x07 line.long 0x00 "CHAN_THRSEL,Channel Threshold Select Register" bitfld.long 0x00 11. " CH11_THRSEL ,Threshold select for channel 11" "Threshold 0,Threshold 1" bitfld.long 0x00 10. " CH10_THRSEL ,Threshold select for channel 10" "Threshold 0,Threshold 1" sif !cpuis("LPC802M011JDH20") bitfld.long 0x00 9. " CH9_THRSEL ,Threshold select for channel 9" "Threshold 0,Threshold 1" endif newline sif (cpuis("LPC824M201JHI33")||cpuis("LPC822M101JHI33")||cpuis("LPC84*")||cpu()=="LPC834M101FHI33"||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M111JDH24")) bitfld.long 0x00 8. " CH8_THRSEL ,Threshold select for channel 8" "Threshold 0,Threshold 1" bitfld.long 0x00 7. " CH7_THRSEL ,Threshold select for channel 7" "Threshold 0,Threshold 1" bitfld.long 0x00 6. " CH6_THRSEL ,Threshold select for channel 6" "Threshold 0,Threshold 1" newline bitfld.long 0x00 5. " CH5_THRSEL ,Threshold select for channel 5" "Threshold 0,Threshold 1" bitfld.long 0x00 4. " CH4_THRSEL ,Threshold select for channel 4" "Threshold 0,Threshold 1" bitfld.long 0x00 3. " CH3_THRSEL ,Threshold select for channel 3" "Threshold 0,Threshold 1" newline bitfld.long 0x00 2. " CH2_THRSEL ,Threshold select for channel 2" "Threshold 0,Threshold 1" bitfld.long 0x00 1. " CH1_THRSEL ,Threshold select for channel 1" "Threshold 0,Threshold 1" bitfld.long 0x00 0. " CH0_THRSEL ,Threshold select for channel 0" "Threshold 0,Threshold 1" else bitfld.long 0x00 3. " CH3_THRSEL ,Threshold select for channel 3" "Threshold 0,Threshold 1" bitfld.long 0x00 2. " CH2_THRSEL ,Threshold select for channel 2" "Threshold 0,Threshold 1" endif line.long 0x04 "INTEN,Interrupt Enable Register" bitfld.long 0x04 25.--26. " ADCMPINTEN11 ,Threshold comparison interrupt enable for channel 11" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 23.--24. " ADCMPINTEN10 ,Threshold comparison interrupt enable for channel 10" "Disabled,Outside,Crossing,?..." sif !cpuis("LPC802M011JDH20")&&!cpuis("LPC804M111JDH24") bitfld.long 0x04 21.--22. " ADCMPINTEN9 ,Threshold comparison interrupt enable for channel 9" "Disabled,Outside,Crossing?...," endif newline sif (cpuis("LPC824M201JHI33")||cpuis("LPC822M101JHI33")||cpuis("LPC84*")||cpu()=="LPC834M101FHI33"||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M111JDH24")) bitfld.long 0x04 19.--20. " ADCMPINTEN8 ,Threshold comparison interrupt enable for channel 8" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 17.--18. " ADCMPINTEN7 ,Threshold comparison interrupt enable for channel 7" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 15.--16. " ADCMPINTEN6 ,Threshold comparison interrupt enable for channel 6" "Disabled,Outside,Crossing,?..." newline bitfld.long 0x04 13.--14. " ADCMPINTEN5 ,Threshold comparison interrupt enable for channel 5" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 11.--12. " ADCMPINTEN4 ,Threshold comparison interrupt enable for channel 4" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 9.--10. " ADCMPINTEN3 ,Threshold comparison interrupt enable for channel 3" "Disabled,Outside,Crossing,?..." newline bitfld.long 0x04 7.--8. " ADCMPINTEN2 ,Threshold comparison interrupt enable for channel 2" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 5.--6. " ADCMPINTEN1 ,Threshold comparison interrupt enable for channel 1" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 3.--4. " ADCMPINTEN0 ,Threshold comparison interrupt enable for channel 0" "Disabled,Outside,Crossing,?..." else bitfld.long 0x04 9.--10. " ADCMPINTEN3 ,Threshold comparison interrupt enable for channel 3" "Disabled,Outside,Crossing,?..." bitfld.long 0x04 7.--8. " ADCMPINTEN2 ,Threshold comparison interrupt enable for channel 2" "Disabled,Outside,Crossing,?..." endif newline bitfld.long 0x04 2. " OVR_INTEN ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " SEQB_INTEN ,Sequence B interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " SEQA_INTEN ,Sequence A interrupt enable" "Disabled,Enabled" endif newline hgroup.long 0x68++0x03 hide.long 0x00 "FLAGS,Interrupt Request Flags Register" textfld " " in newline sif !cpuis("LPC802*")&&!cpuis("LPC804*") group.long 0x6C++0x03 line.long 0x00 "TRM,Trim Analog Supply Voltage Register" bitfld.long 0x00 5. " VRANGE ,Voltage range select" "2.7V - 3.6V,2.4V - 2.7V" endif width 0x0B tree.end endif sif (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpu()=="LPC811M001JDH16") tree "SysTick (SysTick Timer)" base ad:0xE000E000 width 7. group.long 0x10++0x0B line.long 0x00 "CSR,System Timer Control And Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if SysTick timer counted to 0 since the last read of this register" "Not occurred,Occurred" sif cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04") bitfld.long 0x00 2. " CLKSOURCE ,System Tick clock source selection" "Clock/2,CPU" textfld " " else bitfld.long 0x00 2. " CLKSOURCE ,System Tick clock source selection" "SYSTICKDIV,CPU" endif bitfld.long 0x00 1. " TICKINT ,System Tick interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,System Tick counter enable" "Disabled,Enabled" line.long 0x04 "RVR,System Timer Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value that is loaded into the System Tick counter when it counts down to 0" line.long 0x08 "CVR,System Timer Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Returns the current value of the System Tick counter" sif (cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpu()=="LPC811M001JDH16"||cpuis("LPC54*")) rgroup.long 0x1C++0x03 line.long 0x00 "CALIB,System Timer Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reload value set by the SYSCON block" "Low,High" bitfld.long 0x00 30. " SKEW ,Reload value set by the SYSCON block" "Low,High" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Reload value set by the SYSCON block" else group.long 0x1C++0x03 line.long 0x00 "CALIB,System Timer Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reload value set by the SYSCON block" "Low,High" bitfld.long 0x00 30. " SKEW ,Reload value set by the SYSCON block" "Low,High" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Reload value set by the SYSCON block" endif width 0x0B tree.end endif sif !cpuis("LPC8N04") tree.open "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)" tree "USART_0" base ad:0x40064000 width 15. group.long 0x00++0x0B line.long 0x00 "CFG,USART Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not changed,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not changed,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" textline " " bitfld.long 0x00 20. " OESEL ,Output enable select" "Flow control,Output enable" bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable" "De-asserted,Asserted" textline " " endif bitfld.long 0x00 15. " LOOP ,Data loopback select" "Normal operation,Loopback mode" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" bitfld.long 0x00 12. " CLKPOL ,Clock polarity and received data sampling edge select" "Falling edge,Rising edge" textline " " bitfld.long 0x00 11. " SYNCEN ,Synchronous/asynchronous operation select" "Asynchronous mode,Synchronous mode" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " STOPLEN ,Number of stop bits" "1,2" textline " " bitfld.long 0x00 4.--5. " PARITYSEL ,Parity type select" "No parity,,Even parity,Odd parity" bitfld.long 0x00 2.--3. " DATALEN ,Data size select" "7-bit,8-bit,9-bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" line.long 0x04 "CTL,USART Control Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 9. " CLRCC ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x04 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x04 6. " TXDIS ,Transmit disable" "No,Yes" textline " " bitfld.long 0x04 2. " ADDRDET ,Address detect enable" "Enabled,Disabled" bitfld.long 0x04 1. " TXBRKEN ,Break enable" "Normal operation,Break sent" line.long 0x08 "STAT,UART Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) eventfld.long 0x08 16. " ABERR ,Autobaud Error" "No error,Error" textline " " endif eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 12. " START ,Start detected on receiver input" "Not detected,Detected" eventfld.long 0x08 11. " DELTARXBRK ,State change of receiver break detection" "Not detected,Detected" rbitfld.long 0x08 10. " RXBRK ,Received break" "Not received,Received" textline " " eventfld.long 0x08 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" rbitfld.long 0x08 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 5. " DELTACTS ,State change of CTS flag" "Not detected,Detected" textline " " rbitfld.long 0x08 4. " CTS ,State of CTS signal" "Low,High" rbitfld.long 0x08 3. " TXIDLE ,Transmitter idle" "Busy,Idle" rbitfld.long 0x08 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" textline " " rbitfld.long 0x08 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x08 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x0C++0x07 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERREN ,Autobaud error occurred interrupt enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEEN ,Received noise interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x04 12. " STARTEN ,Start detected on receiver input interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRKEN ,State change of receiver break detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISEN ,Transmitter disabled interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTSEN ,State change of CTS signal interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLEEN ,Transmitter becomes idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif textline "" hgroup.long 0x14++0x03 hide.long 0x00 "RXDATA,Receiver Data Register" textfld " " in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATASTAT,Receiver Data With Status Register" textfld " " in textline "" group.long 0x1C++0x07 line.long 0x00 "TXDATA,Transmitter Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,Transmitter data" line.long 0x04 "BRG,USART Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divider value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,USART Interrupt Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " START ,Start detected on receiver input interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,State change of receiver break detection interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " DELTACTS ,State change of CTS signal interrupt flag" "No interrupt,Interrupt" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" else bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" endif sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,Address used with automatic address matching" endif width 0x0B tree.end sif (cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33") tree "USART_1" base ad:0x40068000 width 15. group.long 0x00++0x0B line.long 0x00 "CFG,USART Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not changed,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not changed,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" textline " " bitfld.long 0x00 20. " OESEL ,Output enable select" "Flow control,Output enable" bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable" "De-asserted,Asserted" textline " " endif bitfld.long 0x00 15. " LOOP ,Data loopback select" "Normal operation,Loopback mode" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" bitfld.long 0x00 12. " CLKPOL ,Clock polarity and received data sampling edge select" "Falling edge,Rising edge" textline " " bitfld.long 0x00 11. " SYNCEN ,Synchronous/asynchronous operation select" "Asynchronous mode,Synchronous mode" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " STOPLEN ,Number of stop bits" "1,2" textline " " bitfld.long 0x00 4.--5. " PARITYSEL ,Parity type select" "No parity,,Even parity,Odd parity" bitfld.long 0x00 2.--3. " DATALEN ,Data size select" "7-bit,8-bit,9-bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" line.long 0x04 "CTL,USART Control Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 9. " CLRCC ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x04 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x04 6. " TXDIS ,Transmit disable" "No,Yes" textline " " bitfld.long 0x04 2. " ADDRDET ,Address detect enable" "Enabled,Disabled" bitfld.long 0x04 1. " TXBRKEN ,Break enable" "Normal operation,Break sent" line.long 0x08 "STAT,UART Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) eventfld.long 0x08 16. " ABERR ,Autobaud Error" "No error,Error" textline " " endif eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 12. " START ,Start detected on receiver input" "Not detected,Detected" eventfld.long 0x08 11. " DELTARXBRK ,State change of receiver break detection" "Not detected,Detected" rbitfld.long 0x08 10. " RXBRK ,Received break" "Not received,Received" textline " " eventfld.long 0x08 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" rbitfld.long 0x08 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 5. " DELTACTS ,State change of CTS flag" "Not detected,Detected" textline " " rbitfld.long 0x08 4. " CTS ,State of CTS signal" "Low,High" rbitfld.long 0x08 3. " TXIDLE ,Transmitter idle" "Busy,Idle" rbitfld.long 0x08 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" textline " " rbitfld.long 0x08 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x08 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x0C++0x07 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERREN ,Autobaud error occurred interrupt enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEEN ,Received noise interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x04 12. " STARTEN ,Start detected on receiver input interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRKEN ,State change of receiver break detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISEN ,Transmitter disabled interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTSEN ,State change of CTS signal interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLEEN ,Transmitter becomes idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif textline "" hgroup.long 0x14++0x03 hide.long 0x00 "RXDATA,Receiver Data Register" textfld " " in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATASTAT,Receiver Data With Status Register" textfld " " in textline "" group.long 0x1C++0x07 line.long 0x00 "TXDATA,Transmitter Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,Transmitter data" line.long 0x04 "BRG,USART Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divider value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,USART Interrupt Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " START ,Start detected on receiver input interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,State change of receiver break detection interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " DELTACTS ,State change of CTS signal interrupt flag" "No interrupt,Interrupt" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" else bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" endif sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,Address used with automatic address matching" endif width 0x0B tree.end endif sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpu()=="LPC812M101JTB16"||cpu()=="LPC812M101JDH20"||cpu()=="LPC812M101JDH16"||cpu()=="LPC824M201JHI33"||cpu()=="LPC822M101JHI33"||cpu()=="LPC824M201JDH20"||cpu()=="LPC822M101JDH20"||cpuis("LPC84*")) tree "USART_2" base ad:0x4006C000 width 15. group.long 0x00++0x0B line.long 0x00 "CFG,USART Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not changed,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not changed,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" textline " " bitfld.long 0x00 20. " OESEL ,Output enable select" "Flow control,Output enable" bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable" "De-asserted,Asserted" textline " " endif bitfld.long 0x00 15. " LOOP ,Data loopback select" "Normal operation,Loopback mode" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" bitfld.long 0x00 12. " CLKPOL ,Clock polarity and received data sampling edge select" "Falling edge,Rising edge" textline " " bitfld.long 0x00 11. " SYNCEN ,Synchronous/asynchronous operation select" "Asynchronous mode,Synchronous mode" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " STOPLEN ,Number of stop bits" "1,2" textline " " bitfld.long 0x00 4.--5. " PARITYSEL ,Parity type select" "No parity,,Even parity,Odd parity" bitfld.long 0x00 2.--3. " DATALEN ,Data size select" "7-bit,8-bit,9-bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" line.long 0x04 "CTL,USART Control Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 9. " CLRCC ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x04 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x04 6. " TXDIS ,Transmit disable" "No,Yes" textline " " bitfld.long 0x04 2. " ADDRDET ,Address detect enable" "Enabled,Disabled" bitfld.long 0x04 1. " TXBRKEN ,Break enable" "Normal operation,Break sent" line.long 0x08 "STAT,UART Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) eventfld.long 0x08 16. " ABERR ,Autobaud Error" "No error,Error" textline " " endif eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 12. " START ,Start detected on receiver input" "Not detected,Detected" eventfld.long 0x08 11. " DELTARXBRK ,State change of receiver break detection" "Not detected,Detected" rbitfld.long 0x08 10. " RXBRK ,Received break" "Not received,Received" textline " " eventfld.long 0x08 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" rbitfld.long 0x08 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 5. " DELTACTS ,State change of CTS flag" "Not detected,Detected" textline " " rbitfld.long 0x08 4. " CTS ,State of CTS signal" "Low,High" rbitfld.long 0x08 3. " TXIDLE ,Transmitter idle" "Busy,Idle" rbitfld.long 0x08 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" textline " " rbitfld.long 0x08 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x08 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x0C++0x07 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERREN ,Autobaud error occurred interrupt enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEEN ,Received noise interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x04 12. " STARTEN ,Start detected on receiver input interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRKEN ,State change of receiver break detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISEN ,Transmitter disabled interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTSEN ,State change of CTS signal interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLEEN ,Transmitter becomes idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif textline "" hgroup.long 0x14++0x03 hide.long 0x00 "RXDATA,Receiver Data Register" textfld " " in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATASTAT,Receiver Data With Status Register" textfld " " in textline "" group.long 0x1C++0x07 line.long 0x00 "TXDATA,Transmitter Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,Transmitter data" line.long 0x04 "BRG,USART Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divider value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,USART Interrupt Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " START ,Start detected on receiver input interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,State change of receiver break detection interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " DELTACTS ,State change of CTS signal interrupt flag" "No interrupt,Interrupt" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" else bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" endif sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,Address used with automatic address matching" endif width 0x0B tree.end endif sif (cpuis("LPC84*")) tree "USART_3" base ad:0x40070000 width 15. group.long 0x00++0x0B line.long 0x00 "CFG,USART Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not changed,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not changed,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" textline " " bitfld.long 0x00 20. " OESEL ,Output enable select" "Flow control,Output enable" bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable" "De-asserted,Asserted" textline " " endif bitfld.long 0x00 15. " LOOP ,Data loopback select" "Normal operation,Loopback mode" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" bitfld.long 0x00 12. " CLKPOL ,Clock polarity and received data sampling edge select" "Falling edge,Rising edge" textline " " bitfld.long 0x00 11. " SYNCEN ,Synchronous/asynchronous operation select" "Asynchronous mode,Synchronous mode" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " STOPLEN ,Number of stop bits" "1,2" textline " " bitfld.long 0x00 4.--5. " PARITYSEL ,Parity type select" "No parity,,Even parity,Odd parity" bitfld.long 0x00 2.--3. " DATALEN ,Data size select" "7-bit,8-bit,9-bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" line.long 0x04 "CTL,USART Control Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 9. " CLRCC ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x04 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x04 6. " TXDIS ,Transmit disable" "No,Yes" textline " " bitfld.long 0x04 2. " ADDRDET ,Address detect enable" "Enabled,Disabled" bitfld.long 0x04 1. " TXBRKEN ,Break enable" "Normal operation,Break sent" line.long 0x08 "STAT,UART Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) eventfld.long 0x08 16. " ABERR ,Autobaud Error" "No error,Error" textline " " endif eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 12. " START ,Start detected on receiver input" "Not detected,Detected" eventfld.long 0x08 11. " DELTARXBRK ,State change of receiver break detection" "Not detected,Detected" rbitfld.long 0x08 10. " RXBRK ,Received break" "Not received,Received" textline " " eventfld.long 0x08 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" rbitfld.long 0x08 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 5. " DELTACTS ,State change of CTS flag" "Not detected,Detected" textline " " rbitfld.long 0x08 4. " CTS ,State of CTS signal" "Low,High" rbitfld.long 0x08 3. " TXIDLE ,Transmitter idle" "Busy,Idle" rbitfld.long 0x08 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" textline " " rbitfld.long 0x08 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x08 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x0C++0x07 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERREN ,Autobaud error occurred interrupt enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEEN ,Received noise interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x04 12. " STARTEN ,Start detected on receiver input interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRKEN ,State change of receiver break detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISEN ,Transmitter disabled interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTSEN ,State change of CTS signal interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLEEN ,Transmitter becomes idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif textline "" hgroup.long 0x14++0x03 hide.long 0x00 "RXDATA,Receiver Data Register" textfld " " in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATASTAT,Receiver Data With Status Register" textfld " " in textline "" group.long 0x1C++0x07 line.long 0x00 "TXDATA,Transmitter Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,Transmitter data" line.long 0x04 "BRG,USART Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divider value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,USART Interrupt Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " START ,Start detected on receiver input interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,State change of receiver break detection interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " DELTACTS ,State change of CTS signal interrupt flag" "No interrupt,Interrupt" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" else bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" endif sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,Address used with automatic address matching" endif width 0x0B tree.end tree "USART_4" base ad:0x40074000 width 15. group.long 0x00++0x0B line.long 0x00 "CFG,USART Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not changed,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not changed,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" textline " " bitfld.long 0x00 20. " OESEL ,Output enable select" "Flow control,Output enable" bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable" "De-asserted,Asserted" textline " " endif bitfld.long 0x00 15. " LOOP ,Data loopback select" "Normal operation,Loopback mode" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" bitfld.long 0x00 12. " CLKPOL ,Clock polarity and received data sampling edge select" "Falling edge,Rising edge" textline " " bitfld.long 0x00 11. " SYNCEN ,Synchronous/asynchronous operation select" "Asynchronous mode,Synchronous mode" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " STOPLEN ,Number of stop bits" "1,2" textline " " bitfld.long 0x00 4.--5. " PARITYSEL ,Parity type select" "No parity,,Even parity,Odd parity" bitfld.long 0x00 2.--3. " DATALEN ,Data size select" "7-bit,8-bit,9-bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" line.long 0x04 "CTL,USART Control Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 9. " CLRCC ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x04 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x04 6. " TXDIS ,Transmit disable" "No,Yes" textline " " bitfld.long 0x04 2. " ADDRDET ,Address detect enable" "Enabled,Disabled" bitfld.long 0x04 1. " TXBRKEN ,Break enable" "Normal operation,Break sent" line.long 0x08 "STAT,UART Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) eventfld.long 0x08 16. " ABERR ,Autobaud Error" "No error,Error" textline " " endif eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 12. " START ,Start detected on receiver input" "Not detected,Detected" eventfld.long 0x08 11. " DELTARXBRK ,State change of receiver break detection" "Not detected,Detected" rbitfld.long 0x08 10. " RXBRK ,Received break" "Not received,Received" textline " " eventfld.long 0x08 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" rbitfld.long 0x08 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" eventfld.long 0x08 5. " DELTACTS ,State change of CTS flag" "Not detected,Detected" textline " " rbitfld.long 0x08 4. " CTS ,State of CTS signal" "Low,High" rbitfld.long 0x08 3. " TXIDLE ,Transmitter idle" "Busy,Idle" rbitfld.long 0x08 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" textline " " rbitfld.long 0x08 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x08 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x0C++0x07 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERREN ,Autobaud error occurred interrupt enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEEN ,Received noise interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x04 12. " STARTEN ,Start detected on receiver input interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRKEN ,State change of receiver break detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISEN ,Transmitter disabled interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTSEN ,State change of CTS signal interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLEEN ,Transmitter becomes idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif textline "" hgroup.long 0x14++0x03 hide.long 0x00 "RXDATA,Receiver Data Register" textfld " " in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATASTAT,Receiver Data With Status Register" textfld " " in textline "" group.long 0x1C++0x07 line.long 0x00 "TXDATA,Transmitter Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,Transmitter data" line.long 0x04 "BRG,USART Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divider value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,USART Interrupt Status Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " START ,Start detected on receiver input interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,State change of receiver break detection interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " DELTACTS ,State change of CTS signal interrupt flag" "No interrupt,Interrupt" textline " " sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" else bitfld.long 0x00 2. " TXRDY ,Transmitter ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready interrupt flag" "No interrupt,Interrupt" endif sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,Address used with automatic address matching" endif width 0x0B tree.end endif tree.end endif sif (cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")) tree "I2C (I2C-Bus Interface)" base ad:0x40050000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40050000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end elif cpuis("LPC804*") tree "I2C (I2C-Bus Interface)" tree "I2C_0" base ad:0x40050000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40050000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end tree "I2C_1" base ad:0x40054000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40054000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end tree.end elif cpuis("LPC8N04") tree "I2C (I2C-Bus Interface)" base ad:0x40000000 width 17. group.long 0x00++0x03 line.long 0x00 "CONSET,Control Set Register" setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_SET/CLR ,I2C-bus interface enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_SET/CLR ,START flag" "Not started,Started" newline bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop" setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_SET/CLR ,I2C interrupt flag" "Not occurred,Occurred" newline setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_SET/CLR ,Assert acknowledge flag" "No acknowledge,Acknowledge" newline rgroup.long 0x04++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0" newline group.long 0x08++0x0F line.long 0x00 "DAT,Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data" line.long 0x04 "ADR0,Slave Address Register" hexmask.long.byte 0x04 1.--7. 0x2 " ADDRESS ,Device address in Slave mode" bitfld.long 0x04 0. " GC ,General call bit enable" "Disabled,Enabled" line.long 0x08 "SCLH,SSCH High Duty Cycle Registers" hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL high time period selection" line.long 0x0C "SCLL,SSCL Low Duty Cycle Registers" hexmask.long.word 0x0C 0.--15. 1. " SCLH ,Count for SCL low time period selection" group.long 0x1C++0x3 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Disabled,Enabled" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" group.long 0x20++0x3 line.long 0x00 "ADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Disabled,Enabled" group.long 0x24++0x3 line.long 0x00 "ADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Disabled,Enabled" group.long 0x28++0x3 line.long 0x00 "ADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Disabled,Enabled" rgroup.long 0x2C++0x03 line.long 0x00 "DATA_BUFFER,Data Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data" group.long (0x30+0x0)++0x03 line.long 0x00 "MASK0,I2C Mask Register" bitfld.long 0x00 7. " MASK[6] ,Mask for bit 6 of ADDR0" "Inactive,Active" bitfld.long 0x00 6. " [5] ,Mask for bit 5 of ADDR0" "Inactive,Active" bitfld.long 0x00 5. " [4] ,Mask for bit 4 of ADDR0" "Inactive,Active" bitfld.long 0x00 4. " [3] ,Mask for bit 3 of ADDR0" "Inactive,Active" newline bitfld.long 0x00 3. " [2] ,Mask for bit 2 of ADDR0" "Inactive,Active" bitfld.long 0x00 2. " [1] ,Mask for bit 1 of ADDR0" "Inactive,Active" bitfld.long 0x00 1. " [0] ,Mask for bit 0 of ADDR0" "Inactive,Active" group.long (0x30+0x4)++0x03 line.long 0x00 "MASK1,I2C Mask Register" bitfld.long 0x00 7. " MASK[6] ,Mask for bit 6 of ADDR1" "Inactive,Active" bitfld.long 0x00 6. " [5] ,Mask for bit 5 of ADDR1" "Inactive,Active" bitfld.long 0x00 5. " [4] ,Mask for bit 4 of ADDR1" "Inactive,Active" bitfld.long 0x00 4. " [3] ,Mask for bit 3 of ADDR1" "Inactive,Active" newline bitfld.long 0x00 3. " [2] ,Mask for bit 2 of ADDR1" "Inactive,Active" bitfld.long 0x00 2. " [1] ,Mask for bit 1 of ADDR1" "Inactive,Active" bitfld.long 0x00 1. " [0] ,Mask for bit 0 of ADDR1" "Inactive,Active" group.long (0x30+0x8)++0x03 line.long 0x00 "MASK2,I2C Mask Register" bitfld.long 0x00 7. " MASK[6] ,Mask for bit 6 of ADDR2" "Inactive,Active" bitfld.long 0x00 6. " [5] ,Mask for bit 5 of ADDR2" "Inactive,Active" bitfld.long 0x00 5. " [4] ,Mask for bit 4 of ADDR2" "Inactive,Active" bitfld.long 0x00 4. " [3] ,Mask for bit 3 of ADDR2" "Inactive,Active" newline bitfld.long 0x00 3. " [2] ,Mask for bit 2 of ADDR2" "Inactive,Active" bitfld.long 0x00 2. " [1] ,Mask for bit 1 of ADDR2" "Inactive,Active" bitfld.long 0x00 1. " [0] ,Mask for bit 0 of ADDR2" "Inactive,Active" group.long (0x30+0xC)++0x03 line.long 0x00 "MASK3,I2C Mask Register" bitfld.long 0x00 7. " MASK[6] ,Mask for bit 6 of ADDR3" "Inactive,Active" bitfld.long 0x00 6. " [5] ,Mask for bit 5 of ADDR3" "Inactive,Active" bitfld.long 0x00 5. " [4] ,Mask for bit 4 of ADDR3" "Inactive,Active" bitfld.long 0x00 4. " [3] ,Mask for bit 3 of ADDR3" "Inactive,Active" newline bitfld.long 0x00 3. " [2] ,Mask for bit 2 of ADDR3" "Inactive,Active" bitfld.long 0x00 2. " [1] ,Mask for bit 1 of ADDR3" "Inactive,Active" bitfld.long 0x00 1. " [0] ,Mask for bit 0 of ADDR3" "Inactive,Active" width 0x0B tree.end else tree.open "I2C (I2C-Bus Interface)" tree "I2C_0" base ad:0x40050000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40050000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end tree "I2C_1" base ad:0x40054000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40054000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end sif (cpuis("LPC84*")) tree "I2C_2" base ad:0x40030000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40030000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end tree "I2C_3" base ad:0x40034000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40034000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end else tree "I2C_2" base ad:0x40070000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40070000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end tree "I2C_3" base ad:0x40074000 width 15. group.long 0x00++0x0B "Common registers" line.long 0x00 "CFG,I2C Configuration Register" bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled" bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus time-out enable" "Disabled,Enabled" bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled" bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled" line.long 0x04 "STAT,I2C Status Register" eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not occurred,Occurred" rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Not occurred,Occurred" newline eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "Not occurred,Occurred" rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "Not occurred,Occurred" eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not occurred,Occurred" rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not occurred,Occurred" newline rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Address 0,Address 1,Address 2,Address 3" rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "No,Yes" rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..." rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending" newline eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred" eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred" rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive Ready,Transmit Ready,NACK Address,NACK Data,?..." rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending" line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN ,SCL time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN ,Event time-out interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN ,Monitor idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN ,Monitor overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN ,Monitor data ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN ,Slave deselect interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN ,Slave not stretching interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENDINGEN ,Slave pending interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN ,Master start/stop error interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN ,Master arbitration loss interrupt enable" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN ,Master pending interrupt enable" "Disabled,Enabled" group.long 0x10++0x07 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out value" sif cpuis("LPC82*")||cpuis("LPC81*")||cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" ",,,,,,,,,,,,,,,16" else bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value (bottom four bits)" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" endif line.long 0x04 "DIV,I2C Clock Divider Register" hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,PLCK clock division value" sif (cpuis("LPC82*")||cpuis("LPC81*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")) rgroup.long 0x18++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out Interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " MONRDY ,Monitor ready" "No interrupt,Interrupt" bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "No interrupt,Interrupt" bitfld.long 0x00 8. " SLVPENDING ,Slave pending" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " MSTPENDING ,Master pending" "No interrupt,Interrupt" endif sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40074000+0x04))&0x01)==0x01) wgroup.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" else hgroup.long 0x20++0x03 "Master Function Registers" hide.long 0x00 "MSTCTL,Master Control Register" endif else group.long 0x20++0x03 "Master Function Registers" line.long 0x00 "MSTCTL,Master Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stop" bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Start" bitfld.long 0x00 0. " MSTCONTINUE ,Master continue control" "No effect,Continue" endif group.long 0x24++0x07 line.long 0x00 "MSTTIME,Master Time Register" bitfld.long 0x00 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" bitfld.long 0x00 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks" line.long 0x04 "MSTDAT,Master Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Master function data Register" group.long 0x40++0x07 "Slave Function Registers" line.long 0x00 "SLVCTL,Slave Control Register" sif (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")) bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " SLVNACK ,Slave NACK control" "No effect,NACK" bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue control" "No effect,Continue" line.long 0x04 "SLVDAT,Slave Data Register" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Slave function data Register" group.long 0x48++0x03 line.long 0x00 "SLVADR0,Slave Address Register 0" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 0 disable" "No,Yes" group.long 0x4C++0x03 line.long 0x00 "SLVADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 1 disable" "No,Yes" group.long 0x50++0x03 line.long 0x00 "SLVADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 2 disable" "No,Yes" group.long 0x54++0x03 line.long 0x00 "SLVADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address" bitfld.long 0x00 0. " SADISABLE ,Slave address 3 disable" "No,Yes" group.long 0x58++0x03 line.long 0x00 "SLVQUAL0,Slave Address Qualifier 0 Register" hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0 ,Slave address qualifier for address 0" bitfld.long 0x00 0. " QUALMODE0 ,Address qualifier mode" "Mask,Extend" newline hgroup.long 0x80++0x03 hide.long 0x00 "MONRXDAT,Monitor Data Register" in width 0x0B tree.end endif tree.end endif sif (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpu()=="LPC812M101JTB16"||cpu()=="LPC812M101JDH16"||cpu()=="LPC812M101JDH20"||cpu()=="LPC824M201JHI33"||cpu()=="LPC822M101JHI33"||cpu()=="LPC824M201JDH20"||cpu()=="LPC822M101JDH20"||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpu()=="LPC811M001JDH16") tree.open "SPI (Serial Peripheral Interface)" tree "SPI_0" base ad:0x40058000 width 15. group.long 0x00++0x07 line.long 0x00 "CFG,SPI Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x00 11. " SPOL3 ,SSEL3 polarity select" "Low,High" bitfld.long 0x00 10. " SPOL2 ,SSEL2 polarity select" "Low,High" bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High" newline bitfld.long 0x00 8. " SPOL0 ,SSEL0 polarity select" "Low,High" newline elif (cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")||cpuis("LPC804M111JDH24")) bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High" bitfld.long 0x00 8. " SPOL0 ,SSEL0 polarity select" "Low,High" newline else bitfld.long 0x00 8. " SPOL ,SSEL polarity select" "Low,High" newline endif bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPOL ,Clock polarity select" "Low,High" bitfld.long 0x00 4. " CPHA ,Clock phase select" "Changed,Captured" bitfld.long 0x00 3. " LSBF ,LSB first mode enable" "Standard,Reverse" newline bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave mode,Master mode" bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled" line.long 0x04 "DLY,SPI Delay Register" bitfld.long 0x04 12.--15. " TRANSFER_DELAY ,Minimum amount of time SSEL is deasserted between transfers" "1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks,16 SPI clocks" bitfld.long 0x04 8.--11. " FRAME_DELAY ,Minimum amount of time between adjacent data frames" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" bitfld.long 0x04 4.--7. " POST_DELAY ,Amount of time between end of data and SSEL deassertion" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" bitfld.long 0x04 0.--3. " PRE_DELAY ,Amount of time between SSEL assertion an beginning of data frame" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" if (((per.l(ad:0x40058000))&0x4)==0x4) group.long 0x08++0x03 line.long 0x00 "STAT,SPI Status Register" rbitfld.long 0x00 8. " MSTIDLE ,Idle status flag" "Not occurred,Occurred" eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Not EOF,EOF" rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not occurred,Occurred" eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted" newline eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted" rbitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "Not occurred,Occurred" newline rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not occurred,Occurred" else group.long 0x08++0x03 line.long 0x00 "STAT,SPI Status Register" rbitfld.long 0x00 8. " MSTIDLE ,Idle status flag" "Not occurred,Occurred" eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Not EOF,EOF" rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not occurred,Occurred" eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted" newline eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted" eventfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No overrun,Overrun" rbitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "Not occurred,Occurred" newline rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not occurred,Occurred" endif sif cpuis("LPC804*")||cpuis("LPC802*") if (((per.l(ad:0x40058000))&0x04)==0x04) group.long 0x0C++0x03 line.long 0x00 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MSTIDLEEN ,Master idle interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MSTIDLEEN ,Master idle interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN ,Transmitter underrun interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN ,Receiver overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x00 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif else group.long 0x0C++0x03 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN ,Transmitter underrun interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN ,Receiver overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x00 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif rgroup.long 0x14++0x03 line.long 0x00 "RXDAT,SPI Receiver Data Register" bitfld.long 0x00 20. " SOT ,Start of transfer flag" "Not occurred,Occurred" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) newline bitfld.long 0x00 19. " RXSSEL3_N ,Slave select 3 for receive" "Not selected,Selected" bitfld.long 0x00 18. " RXSSEL2_N ,Slave select 2 for receive" "Not selected,Selected" newline bitfld.long 0x00 17. " RXSSEL1_N ,Slave select 1 for receive" "Not selected,Selected" endif newline bitfld.long 0x00 16. " RXSSEL0_N ,Slave select 0 for receive" "Not selected,Selected" hexmask.long.word 0x00 0.--15. 1. " RXDAT ,Receiver data" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x18++0x0B line.long 0x00 "TXDATCTL,SPI Transmitter Data And Control Register" bitfld.long 0x00 24.--27. " LEN ,Data length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x00 20. " EOT ,End of transfer" "Not EOT,EOT" newline sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x00 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" newline else bitfld.long 0x00 19. " TXSSEL3_N ,Asserts SSEL3 in master mode" "Asserted,Not asserted" bitfld.long 0x00 18. " TXSSEL2_N ,Asserts SSEL2 in master mode" "Asserted,Not asserted" bitfld.long 0x00 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x00 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit data" line.long 0x04 "TXDAT,Transmitter Data Register" hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit data" line.long 0x08 "TXCTL,Transmitter Control Register" bitfld.long 0x08 24.--27. " LEN ,Data length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x08 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x08 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x08 20. " EOT ,End of transfer" "Not EOT,EOT" newline sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x08 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x08 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" else bitfld.long 0x08 19. " TXSSEL3_N ,Asserts SSEL3 in master mode" "Asserted,Not asserted" bitfld.long 0x08 18. " TXSSEL2_N ,Asserts SSEL2 in master mode" "Asserted,Not asserted" bitfld.long 0x08 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x08 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" endif else group.long 0x18++0x0B line.long 0x00 "TXDATCTL,SPI Transmitter Data And Control Register" bitfld.long 0x00 24.--27. " FLEN ,Frame length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x00 20. " EOT ,End of transfer" "Not EOT,EOT" newline bitfld.long 0x00 16. " TXSSELN ,Transmit slave select (SSEL assert)" "Asserted,Not asserted" hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit data" line.long 0x04 "TXDAT,Transmitter Data Register" hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit data" line.long 0x08 "TXCTL,Transmitter Control Register" bitfld.long 0x08 24.--27. " FLEN ,Frame length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x08 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x08 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x08 20. " EOT ,End of transfer" "Not EOT,EOT" newline bitfld.long 0x08 16. " TXSSEL_N ,Transmit slave select (SSEL assert)" "Asserted,Not asserted" endif group.long 0x24++0x03 line.long 0x00 "DIV,SPI Divider Register" hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value" sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40058000))&0x04)==0x04) rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not occurred,Occurred" newline bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" else rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not occurred,Occurred" newline bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" endif else rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" endif width 0xB tree.end tree "SPI_1" base ad:0x4005C000 width 15. group.long 0x00++0x07 line.long 0x00 "CFG,SPI Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x00 11. " SPOL3 ,SSEL3 polarity select" "Low,High" bitfld.long 0x00 10. " SPOL2 ,SSEL2 polarity select" "Low,High" bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High" newline bitfld.long 0x00 8. " SPOL0 ,SSEL0 polarity select" "Low,High" newline elif (cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")||cpuis("LPC804M111JDH24")) bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High" bitfld.long 0x00 8. " SPOL0 ,SSEL0 polarity select" "Low,High" newline else bitfld.long 0x00 8. " SPOL ,SSEL polarity select" "Low,High" newline endif bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPOL ,Clock polarity select" "Low,High" bitfld.long 0x00 4. " CPHA ,Clock phase select" "Changed,Captured" bitfld.long 0x00 3. " LSBF ,LSB first mode enable" "Standard,Reverse" newline bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave mode,Master mode" bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled" line.long 0x04 "DLY,SPI Delay Register" bitfld.long 0x04 12.--15. " TRANSFER_DELAY ,Minimum amount of time SSEL is deasserted between transfers" "1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks,16 SPI clocks" bitfld.long 0x04 8.--11. " FRAME_DELAY ,Minimum amount of time between adjacent data frames" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" bitfld.long 0x04 4.--7. " POST_DELAY ,Amount of time between end of data and SSEL deassertion" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" bitfld.long 0x04 0.--3. " PRE_DELAY ,Amount of time between SSEL assertion an beginning of data frame" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" if (((per.l(ad:0x4005C000))&0x4)==0x4) group.long 0x08++0x03 line.long 0x00 "STAT,SPI Status Register" rbitfld.long 0x00 8. " MSTIDLE ,Idle status flag" "Not occurred,Occurred" eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Not EOF,EOF" rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not occurred,Occurred" eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted" newline eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted" rbitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "Not occurred,Occurred" newline rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not occurred,Occurred" else group.long 0x08++0x03 line.long 0x00 "STAT,SPI Status Register" rbitfld.long 0x00 8. " MSTIDLE ,Idle status flag" "Not occurred,Occurred" eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Not EOF,EOF" rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not occurred,Occurred" eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted" newline eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted" eventfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No overrun,Overrun" rbitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "Not occurred,Occurred" newline rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not occurred,Occurred" endif sif cpuis("LPC804*")||cpuis("LPC802*") if (((per.l(ad:0x4005C000))&0x04)==0x04) group.long 0x0C++0x03 line.long 0x00 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MSTIDLEEN ,Master idle interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MSTIDLEEN ,Master idle interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN ,Transmitter underrun interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN ,Receiver overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x00 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif else group.long 0x0C++0x03 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN ,Transmitter underrun interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN ,Receiver overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x00 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif rgroup.long 0x14++0x03 line.long 0x00 "RXDAT,SPI Receiver Data Register" bitfld.long 0x00 20. " SOT ,Start of transfer flag" "Not occurred,Occurred" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) newline bitfld.long 0x00 19. " RXSSEL3_N ,Slave select 3 for receive" "Not selected,Selected" bitfld.long 0x00 18. " RXSSEL2_N ,Slave select 2 for receive" "Not selected,Selected" newline bitfld.long 0x00 17. " RXSSEL1_N ,Slave select 1 for receive" "Not selected,Selected" endif newline bitfld.long 0x00 16. " RXSSEL0_N ,Slave select 0 for receive" "Not selected,Selected" hexmask.long.word 0x00 0.--15. 1. " RXDAT ,Receiver data" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x18++0x0B line.long 0x00 "TXDATCTL,SPI Transmitter Data And Control Register" bitfld.long 0x00 24.--27. " LEN ,Data length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x00 20. " EOT ,End of transfer" "Not EOT,EOT" newline sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x00 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" newline else bitfld.long 0x00 19. " TXSSEL3_N ,Asserts SSEL3 in master mode" "Asserted,Not asserted" bitfld.long 0x00 18. " TXSSEL2_N ,Asserts SSEL2 in master mode" "Asserted,Not asserted" bitfld.long 0x00 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x00 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit data" line.long 0x04 "TXDAT,Transmitter Data Register" hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit data" line.long 0x08 "TXCTL,Transmitter Control Register" bitfld.long 0x08 24.--27. " LEN ,Data length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x08 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x08 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x08 20. " EOT ,End of transfer" "Not EOT,EOT" newline sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x08 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x08 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" else bitfld.long 0x08 19. " TXSSEL3_N ,Asserts SSEL3 in master mode" "Asserted,Not asserted" bitfld.long 0x08 18. " TXSSEL2_N ,Asserts SSEL2 in master mode" "Asserted,Not asserted" bitfld.long 0x08 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x08 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" endif else group.long 0x18++0x0B line.long 0x00 "TXDATCTL,SPI Transmitter Data And Control Register" bitfld.long 0x00 24.--27. " FLEN ,Frame length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x00 20. " EOT ,End of transfer" "Not EOT,EOT" newline bitfld.long 0x00 16. " TXSSELN ,Transmit slave select (SSEL assert)" "Asserted,Not asserted" hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit data" line.long 0x04 "TXDAT,Transmitter Data Register" hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit data" line.long 0x08 "TXCTL,Transmitter Control Register" bitfld.long 0x08 24.--27. " FLEN ,Frame length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x08 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x08 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x08 20. " EOT ,End of transfer" "Not EOT,EOT" newline bitfld.long 0x08 16. " TXSSEL_N ,Transmit slave select (SSEL assert)" "Asserted,Not asserted" endif group.long 0x24++0x03 line.long 0x00 "DIV,SPI Divider Register" hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value" sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x4005C000))&0x04)==0x04) rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not occurred,Occurred" newline bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" else rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not occurred,Occurred" newline bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" endif else rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" endif width 0xB tree.end tree.end elif cpuis("LPC8N04") tree "SPI/SSP (Serial Peripheral Interface)" base ad:0x40040000 width 7. if (((per.l(ad:0x40040000))&0x30)==0x00) group.long 0x00++0x03 line.long 0x00 "CR0,Control Register 0" hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate" bitfld.long 0x00 7. " CPHA ,Clock out phase" "First transition,Second transition" bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High" newline bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..." bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" else group.long 0x00++0x03 line.long 0x00 "CR0,Control Register 0" hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate" newline bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..." bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" endif if (((per.l(ad:0x40040000+0x04))&0x02)==0x02) group.long 0x04++0x03 line.long 0x00 "CR1,Control Register 1" bitfld.long 0x00 3. " SOD ,Slave output disabled" "No,Yes" rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave" bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled" bitfld.long 0x00 0. " LBM ,Loop back mode" "Serial input,Serial output" else group.long 0x04++0x03 line.long 0x00 "CR1,Control Register 1" bitfld.long 0x00 3. " SOD ,Slave output disabled" "No,Yes" bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave" bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled" bitfld.long 0x00 0. " LBM ,Loop back mode" "Serial input,Serial output" endif hgroup.long 0x08++0x03 hide.long 0x00 "DR,Data Register" in rgroup.long 0x0C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 4. " BSY ,Busy" "Not busy,Busy" bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full" bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "No,Yes" newline bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "No,Yes" bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty" group.long 0x10++0x07 line.long 0x00 "CPSR,Clock Prescale Register" hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Prescaler output clock" line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register" bitfld.long 0x04 3. " TXIM ,Tx FIFO half empty interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " RXIM ,Rx FIFO half full interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " RTIM ,Rx FIFO receive time-out condition interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " RORIM ,Rx FIFO receive overrun interrupt enable" "Disabled,Enabled" rgroup.long 0x18++0x07 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty raw interrupt status" "Not occurred,Occurred" bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full raw interrupt status" "Not occurred,Occurred" bitfld.long 0x00 1. " RTRIS ,Rx FIFO not empty raw interrupt status" "Not occurred,Occurred" bitfld.long 0x00 0. " RORRIS ,Rx FIFO full raw interrupt status" "Not occurred,Occurred" line.long 0x04 "MIS,Masked Interrupt Status Register" bitfld.long 0x04 3. " TXMIS ,Tx FIFO half empty masked interrupt status" "Not occurred,Occurred" bitfld.long 0x04 2. " RXMIS ,Rx FIFO half full masked interrupt status" "Not occurred,Occurred" bitfld.long 0x04 1. " RTMIS ,Rx FIFO not empty masked interrupt status" "Not occurred,Occurred" bitfld.long 0x04 0. " RORMIS ,Rx FIFO full masked interrupt status" "Not occurred,Occurred" wgroup.long 0x20++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 1. " RTIC ,RX FIFO was not empty interrupt clear" "Not cleared,Cleared" bitfld.long 0x00 0. " RORIC ,Frame was received when RX FIFO was full interrupt clear" "Not cleared,Cleared" sif cpuis("LPC11E6*") group.long 0x24++0x03 line.long 0x00 "DMACR,DMA Control Register" bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled" endif width 0x0B tree.end else tree "SPI (Serial Peripheral Interface)" base ad:0x40058000 width 15. group.long 0x00++0x07 line.long 0x00 "CFG,SPI Configuration Register" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33") bitfld.long 0x00 11. " SPOL3 ,SSEL3 polarity select" "Low,High" bitfld.long 0x00 10. " SPOL2 ,SSEL2 polarity select" "Low,High" bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High" newline bitfld.long 0x00 8. " SPOL0 ,SSEL0 polarity select" "Low,High" newline elif (cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")||cpuis("LPC804M111JDH24")) bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High" bitfld.long 0x00 8. " SPOL0 ,SSEL0 polarity select" "Low,High" newline else bitfld.long 0x00 8. " SPOL ,SSEL polarity select" "Low,High" newline endif bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPOL ,Clock polarity select" "Low,High" bitfld.long 0x00 4. " CPHA ,Clock phase select" "Changed,Captured" bitfld.long 0x00 3. " LSBF ,LSB first mode enable" "Standard,Reverse" newline bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave mode,Master mode" bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled" line.long 0x04 "DLY,SPI Delay Register" bitfld.long 0x04 12.--15. " TRANSFER_DELAY ,Minimum amount of time SSEL is deasserted between transfers" "1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks,16 SPI clocks" bitfld.long 0x04 8.--11. " FRAME_DELAY ,Minimum amount of time between adjacent data frames" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" bitfld.long 0x04 4.--7. " POST_DELAY ,Amount of time between end of data and SSEL deassertion" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" bitfld.long 0x04 0.--3. " PRE_DELAY ,Amount of time between SSEL assertion an beginning of data frame" "No added time,1 SPI clock,2 SPI clocks,3 SPI clocks,4 SPI clocks,5 SPI clocks,6 SPI clocks,7 SPI clocks,8 SPI clocks,9 SPI clocks,10 SPI clocks,11 SPI clocks,12 SPI clocks,13 SPI clocks,14 SPI clocks,15 SPI clocks" if (((per.l(ad:0x40058000))&0x4)==0x4) group.long 0x08++0x03 line.long 0x00 "STAT,SPI Status Register" rbitfld.long 0x00 8. " MSTIDLE ,Idle status flag" "Not occurred,Occurred" eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Not EOF,EOF" rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not occurred,Occurred" eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted" newline eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted" rbitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "Not occurred,Occurred" newline rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not occurred,Occurred" else group.long 0x08++0x03 line.long 0x00 "STAT,SPI Status Register" rbitfld.long 0x00 8. " MSTIDLE ,Idle status flag" "Not occurred,Occurred" eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Not EOF,EOF" rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not occurred,Occurred" eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted" newline eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted" eventfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No overrun,Overrun" rbitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "Not occurred,Occurred" newline rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not occurred,Occurred" endif sif cpuis("LPC804*")||cpuis("LPC802*") if (((per.l(ad:0x40058000))&0x04)==0x04) group.long 0x0C++0x03 line.long 0x00 "INTEN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MSTIDLEEN ,Master idle interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MSTIDLEEN ,Master idle interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN ,Transmitter underrun interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN ,Receiver overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x00 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif else group.long 0x0C++0x03 line.long 0x00 "INTEN_set/clr,Interrupt Enable Register" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN ,Slave select deasserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN ,Slave select Asserted interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN ,Transmitter underrun interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN ,Receiver overrun interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x00 1. " TXRDYEN ,Transmitter ready interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDYEN ,Receiver ready interrupt enable" "Disabled,Enabled" endif rgroup.long 0x14++0x03 line.long 0x00 "RXDAT,SPI Receiver Data Register" bitfld.long 0x00 20. " SOT ,Start of transfer flag" "Not occurred,Occurred" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) newline bitfld.long 0x00 19. " RXSSEL3_N ,Slave select 3 for receive" "Not selected,Selected" bitfld.long 0x00 18. " RXSSEL2_N ,Slave select 2 for receive" "Not selected,Selected" newline bitfld.long 0x00 17. " RXSSEL1_N ,Slave select 1 for receive" "Not selected,Selected" endif newline bitfld.long 0x00 16. " RXSSEL0_N ,Slave select 0 for receive" "Not selected,Selected" hexmask.long.word 0x00 0.--15. 1. " RXDAT ,Receiver data" sif (cpuis("LPC82*")||cpuis("LPC84*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC802*")||cpuis("LPC804*")) group.long 0x18++0x0B line.long 0x00 "TXDATCTL,SPI Transmitter Data And Control Register" bitfld.long 0x00 24.--27. " LEN ,Data length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x00 20. " EOT ,End of transfer" "Not EOT,EOT" newline sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x00 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x00 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" newline else bitfld.long 0x00 19. " TXSSEL3_N ,Asserts SSEL3 in master mode" "Asserted,Not asserted" bitfld.long 0x00 18. " TXSSEL2_N ,Asserts SSEL2 in master mode" "Asserted,Not asserted" bitfld.long 0x00 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x00 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit data" line.long 0x04 "TXDAT,Transmitter Data Register" hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit data" line.long 0x08 "TXCTL,Transmitter Control Register" bitfld.long 0x08 24.--27. " LEN ,Data length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x08 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x08 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x08 20. " EOT ,End of transfer" "Not EOT,EOT" newline sif cpuis("LPC802*")||cpuis("LPC804*") bitfld.long 0x08 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x08 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" else bitfld.long 0x08 19. " TXSSEL3_N ,Asserts SSEL3 in master mode" "Asserted,Not asserted" bitfld.long 0x08 18. " TXSSEL2_N ,Asserts SSEL2 in master mode" "Asserted,Not asserted" bitfld.long 0x08 17. " TXSSEL1_N ,Asserts SSEL1 in master mode" "Asserted,Not asserted" bitfld.long 0x08 16. " TXSSEL0_N ,Asserts SSEL0 in master mode" "Asserted,Not asserted" endif else group.long 0x18++0x0B line.long 0x00 "TXDATCTL,SPI Transmitter Data And Control Register" bitfld.long 0x00 24.--27. " FLEN ,Frame length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x00 20. " EOT ,End of transfer" "Not EOT,EOT" newline bitfld.long 0x00 16. " TXSSELN ,Transmit slave select (SSEL assert)" "Asserted,Not asserted" hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit data" line.long 0x04 "TXDAT,Transmitter Data Register" hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit data" line.long 0x08 "TXCTL,Transmitter Control Register" bitfld.long 0x08 24.--27. " FLEN ,Frame length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x08 22. " RXIGNORE ,Receive ignore" "Read data,Ignore data" bitfld.long 0x08 21. " EOF ,End of frame" "Not EOF,EOF" bitfld.long 0x08 20. " EOT ,End of transfer" "Not EOT,EOT" newline bitfld.long 0x08 16. " TXSSEL_N ,Transmit slave select (SSEL assert)" "Asserted,Not asserted" endif group.long 0x24++0x03 line.long 0x00 "DIV,SPI Divider Register" hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value" sif cpuis("LPC802*")||cpuis("LPC804*") if (((per.l(ad:0x40058000))&0x04)==0x04) rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not occurred,Occurred" newline bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" else rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not occurred,Occurred" newline bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" endif else rgroup.long 0x28++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status Register" bitfld.long 0x00 5. " SSD ,Slave select deassert" "No interrupt,Interrupt" bitfld.long 0x00 4. " SSA ,Slave select assert" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " TXUR ,Transmitter underrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXOV ,Receiver overrun interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXRDY ,Transmitter ready flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "No interrupt,Interrupt" endif width 0xB tree.end endif sif (cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04")) sif (cpuis("LPC8N04")) tree "CTIMER (Standard Counter/Timer)" tree "CT16B (16-bit Timer)" base ad:0x4000C000 width 6. group.long 0x00++0x07 line.long 0x00 "IR,Interrupt Register" sif cpuis("LPC11E*") bitfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt" bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt" newline endif bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt" line.long 0x04 "TCR,Timer Control Register" bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset" bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled" sif cpuis("LPC11E*") group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value" else group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value" endif group.long 0x0C++0x07 line.long 0x00 "PR,Timer Prescale Register" hexmask.long.word 0x00 0.--15. 1. " PR ,Prescale max value" line.long 0x04 "PC,Timer Prescale Counter Register" hexmask.long.word 0x04 0.--15. 1. " PC ,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled" newline bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled" newline bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" sif cpuis("LPC11E*") group.long 0x18++0x03 line.long 0x00 "MR0,Match Register 0" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value" group.long 0x1C++0x03 line.long 0x00 "MR1,Match Register 1" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value" group.long 0x20++0x03 line.long 0x00 "MR2,Match Register 2" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value" group.long 0x24++0x03 line.long 0x00 "MR3,Match Register 3" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value" group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 8. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled" bitfld.long 0x00 6. " CAP1RE ,Capture on CT16B0_CAP1 rising edge" "Disabled,Enabled" newline bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B0_CAP0 event" "Disabled,Enabled" bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B0_CAP0 falling edge" "Disabled,Enabled" bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B0_CAP0 rising edge" "Disabled,Enabled" sif cpuis("LPC11E6*") rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" rgroup.long 0x30++0x03 line.long 0x00 "CR1,Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" rgroup.long 0x34++0x03 line.long 0x00 "CR2,Capture Register 2" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" else rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" rgroup.long 0x34++0x03 line.long 0x00 "CR1,Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" endif else group.long 0x18++0x03 line.long 0x00 "MR0,Match Register 0" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value" group.long 0x1C++0x03 line.long 0x00 "MR1,Match Register 1" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value" group.long 0x20++0x03 line.long 0x00 "MR2,Match Register 2" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value" group.long 0x24++0x03 line.long 0x00 "MR3,Match Register 3" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer-counter match value" endif sif cpuis("LPC11E*") group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle" newline bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High" bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High" bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High" bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising edge of CAP0,Falling edge of CAP0,,,Rising edge of CAP1,Falling edge of CAP1,?..." bitfld.long 0x00 4. " ENCC ,Clearing of timer and the prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " CIS ,Count input select" "CT16B0_CAP0,,CT16B0_CAP1,?..." bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer: rising edges,Counter: rising edges,Counter: falling edges,Counter: both edges" else group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle" newline bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High" bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High" endif group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" sif cpuis("LPC11E*") bitfld.long 0x00 3. " PWMEN3 ,PWM mode enable for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " PWMEN2 ,PWM mode enable for channel 2" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " PWMEN1 ,PWM mode enable for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " PWMEN0 ,PWM mode enable for channel 0" "Disabled,Enabled" width 0x0B tree.end tree "CT32B (32-bit Timer)" base ad:0x40014000 width 6. group.long 0x00++0x07 line.long 0x00 "IR,Interrupt Register" sif cpuis("LPC11E*") bitfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt" bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt" newline endif bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt" line.long 0x04 "TCR,Timer Control Register" bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset" bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled" sif cpuis("LPC11E*") group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter Register" else group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value" endif group.long 0x0C++0x07 line.long 0x00 "PR,Timer Prescale Register" line.long 0x04 "PC,Timer Prescale Counter Register" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled" newline bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled" newline bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" sif cpuis("LPC11E*") group.long 0x18++0x03 line.long 0x00 "MR0,Match Register 0" group.long 0x1C++0x03 line.long 0x00 "MR1,Match Register 1" group.long 0x20++0x03 line.long 0x00 "MR2,Match Register 2" group.long 0x24++0x03 line.long 0x00 "MR3,Match Register 3" group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 8. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled" bitfld.long 0x00 6. " CAP1RE ,Capture on CT32B0_CAP1 rising edge" "Disabled,Enabled" newline bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B0_CAP0 event" "Disabled,Enabled" bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B0_CAP0 falling edge" "Disabled,Enabled" bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B0_CAP0 rising edge" "Disabled,Enabled" sif cpuis("LPC11E6*") rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" rgroup.long 0x30++0x03 line.long 0x00 "CR1,Capture Register 1" rgroup.long 0x34++0x03 line.long 0x00 "CR2,Capture Register 2" else rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" rgroup.long 0x34++0x03 line.long 0x00 "CR1,Capture Register 1" endif else group.long 0x18++0x03 line.long 0x00 "MR0,Match Register 0" group.long 0x1C++0x03 line.long 0x00 "MR1,Match Register 1" group.long 0x20++0x03 line.long 0x00 "MR2,Match Register 2" group.long 0x24++0x03 line.long 0x00 "MR3,Match Register 3" endif sif cpuis("LPC11E*") group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle" newline bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High" bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High" bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High" bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising edge of CAP0,Falling edge of CAP0,,,Rising edge of CAP1,Falling edge of CAP1,?..." bitfld.long 0x00 4. " ENCC ,Clearing of timer and the prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " CIS ,Count input select" "CT32B0_CAP0,,CT32B0_CAP1,?..." bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer: rising edges,Counter: rising edges,Counter: falling edges,Counter: both edges" else group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle" bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle" newline bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High" bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High" endif group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" sif cpuis("LPC11E*") bitfld.long 0x00 3. " PWMEN3 ,PWM mode enable for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " PWMEN2 ,PWM mode enable for channel 2" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " PWMEN1 ,PWM mode enable for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " PWMEN0 ,PWM mode enable for channel 0" "Disabled,Enabled" width 0x0B tree.end tree.end else tree "CTIMER (Standard Counter/Timer)" base ad:0x40038000 width 6. group.long 0x00++0x3F line.long 0x00 "IR,Interrupt Register" sif (cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")) bitfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "No interrupt,Interrupt" bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt" bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt" textline " " else bitfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "No interrupt,Interrupt" bitfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "No interrupt,Interrupt" bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No interrupt,Interrupt" bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "No interrupt,Interrupt" line.long 0x04 "TCR,Timer Control Register" bitfld.long 0x04 1. " CRST ,Counter reset" "Disabled,Enabled" bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled" line.long 0x08 "TC,Timer Counter Register" line.long 0x0C "PR,Timer Prescale Register" line.long 0x10 "PC,Timer Prescale Counter Register" line.long 0x14 "MCR,Match Control Register" bitfld.long 0x14 27. " MR3RL ,MR3 reload" "Disabled,Enabled" bitfld.long 0x14 26. " MR2RL ,MR2 reload" "Disabled,Enabled" bitfld.long 0x14 25. " MR1RL ,MR1 reload" "Disabled,Enabled" bitfld.long 0x14 24. " MR0RL ,MR0 reload" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x14 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x14 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" bitfld.long 0x14 8. " MR2S ,Stop on MR2" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x14 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" bitfld.long 0x14 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x14 4. " MR1R ,Reset on MR1" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" bitfld.long 0x14 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x14 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x14 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" line.long 0x18 "MR0,Match Register" line.long 0x1C "MR1,Match Register" line.long 0x20 "MR2,Match Register" line.long 0x24 "MR3,Match Register" line.long 0x28 "CCR,Capture Control Register" sif (cpuis("LPC802M001JDH16")||cpuis("LPC802M001JDH20")||cpuis("LPC802M001JHI33")||cpuis("LPC802M011JDH20")||cpuis("LPC804M101JDH20")||cpuis("LPC804M101JDH24")||cpuis("LPC804M101JHI33")) bitfld.long 0x28 8. " CAP2I ,Generate interrupt on channel 2 capture event" "No interrupt,Interrupt" textline " " else bitfld.long 0x28 11. " CAP3I ,Generate interrupt on channel 3 capture event" "No interrupt,Interrupt" bitfld.long 0x28 10. " CAP3FE ,Falling edge of capture channel 3:" "Disabled,Enabled" bitfld.long 0x28 9. " CAP3RE ,Rising edge of capture channel 3" "Disabled,Enabled" bitfld.long 0x28 8. " CAP2I ,Generate interrupt on channel 2 capture event" "No interrupt,Interrupt" textline " " endif bitfld.long 0x28 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled" bitfld.long 0x28 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled" bitfld.long 0x28 5. " CAP1I ,Generate interrupt on channel 1 capture event" "No interrupt,Interrupt" bitfld.long 0x28 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" textline " " bitfld.long 0x28 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x28 2. " CAP0I ,Generate interrupt on channel 0 capture event" "No interrupt,Interrupt" bitfld.long 0x28 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled" bitfld.long 0x28 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enabled" line.long 0x2C "CR0,Capture Register" line.long 0x30 "CR1,Capture Register" line.long 0x34 "CR2,Capture Register" line.long 0x38 "CR3,Capture Register" line.long 0x3C "EMR,External Match Register" bitfld.long 0x3C 10.--11. " EMC3 ,External match control 3" "Do nothing,Clear,Set,Toggle" bitfld.long 0x3C 8.--9. " EMC2 ,External match control 2" "Do nothing,Clear,Set,Toggle" bitfld.long 0x3C 6.--7. " EMC1 ,External match control 1" "Do nothing,Clear,Set,Toggle" bitfld.long 0x3C 4.--5. " EMC0 ,External match control 0" "Do nothing,Clear,Set,Toggle" textline " " bitfld.long 0x3C 3. " EM3 ,External match 3" "LOW,HIGH" bitfld.long 0x3C 2. " EM2 ,External match 2" "LOW,HIGH" bitfld.long 0x3C 1. " EM1 ,External match 1" "LOW,HIGH" bitfld.long 0x3C 0. " EM0 ,External match 0" "LOW,HIGH" group.long 0x70++0x17 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Ch0 Rising Edge,Ch0 Falling Edge,Ch1 Rising Edge,Ch1 Falling Edge,Ch2 Rising Edge,Ch2 Falling Edge,Ch3 Rising Edge,Ch3 Falling Edge" bitfld.long 0x00 4. " ENCC ,Clearing of the timer enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "CAP0,CAP1,CAP2,CAP3" bitfld.long 0x00 0.--1. " CTMODE ,Counter/Timer Mode" "Timer Mode,Counter Mode rising edge,Counter Mode falling edge,Counter Mode dual edge" line.long 0x04 "PWMC,PWM Control Register" bitfld.long 0x04 3. " PWMEN3 ,PWM mode enable for channel 3" "Match,PWM" bitfld.long 0x04 2. " PWMEN2 ,PWM mode enable for channel 2" "Match,PWM" bitfld.long 0x04 1. " PWMEN1 ,PWM mode enable for channel 1" "Match,PWM" bitfld.long 0x04 0. " PWMEN0 ,PWM mode enable for channel 0" "Match,PWM" line.long 0x08 "MSR0,Match Shadow Registers" line.long 0x0C "MSR1,Match Shadow Registers" line.long 0x10 "MSR2,Match Shadow Registers" line.long 0x14 "MSR3,Match Shadow Registers" width 0x0B tree.end endif sif (cpu()=="LPC845M301JBD64"||cpu()=="LPC845M301JBD48"||cpu()=="LPC845M301JHI48"||cpuis("LPC804*")) tree "CT (Capacitive Touch)" base ad:0x40060000 width 16. group.long 0x00++0x07 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " XPINSEL[15] ,X15 pin enable" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,X14 pin enable" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,X13 pin enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [12] ,X12 pin enable" "Disabled,Enabled" bitfld.long 0x00 27. " [11] ,X11 pin enable" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,X10 pin enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " [9] ,X9 pin enable" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,X8 pin enable" "Disabled,Enabled" bitfld.long 0x00 23. " [7] ,X7 pin enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " [6] ,X6 pin enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,X5 pin enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,X4 pin enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,X3 pin enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,X2 pin enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,X1 pin enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " [0] ,X0 pin enable" "Disabled,Enabled" rbitfld.long 0x00 15. " INCHANGE ,Shows the status of the most recent update to the control register" "Propagated,Not propagated" bitfld.long 0x00 12.--13. " XPINUSE ,Determines how enabled pins are controlled when not active" "High-Z,Driven low,?..." newline sif cpuis("LPC804*") bitfld.long 0x00 8.--11. " FDIV ,Function clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 5. " WAIT ,Controls when the next X measurement in the sequence may commence" "Normal time,Wait until is read/Continued" newline else bitfld.long 0x00 8.--11. " FDIV ,Function clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 6.--7. " DMA ,Controls how DMA triggers are generated" "No DMA,On touch,Both touch/No-touch,Both + time-out" bitfld.long 0x00 5. " WAIT ,Controls when the next X measurement in the sequence may commence" "Normal time,Wait until is read/Continued" newline endif bitfld.long 0x00 4. " TRIGGER ,Selects the measurement method" "YH port pin time,Analog comparator" bitfld.long 0x00 2.--3. " TYPE ,Selects the polling type and sensor arrangement" "Normal,?..." bitfld.long 0x00 0.--1. " POLLMODE ,Selects the method of polling" "Inactive,Poll Now,Continuous,?..." line.long 0x04 "STATUS,Status Register" rbitfld.long 0x04 16.--19. " XMAX ,Number of X pins available" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rbitfld.long 0x04 8. " BUSY ,BUSY status" "Not busy,Busy" eventfld.long 0x04 4. " OVERRUN ,Set if Touch Data has been updated before previous data was read" "Not overrun,Overrun" newline eventfld.long 0x04 3. " TIMEOUT ,Set if the count reaches the time-out count value before a trigger occurs" "Not reached,Reached" eventfld.long 0x04 2. " POLLDONE ,Set at the end of a polling round" "Not ended,Ended" eventfld.long 0x04 1. " NOTOUCH ,Set if a no-touch has been detected" "Not detected,Detected" newline eventfld.long 0x04 0. " YESTOUCH ,Set if a touch has been detected" "Not detected,Detected" if (((per.l(ad:0x40060000))&0x03)==0x00) group.long 0x08++0x03 line.long 0x00 "POLL_TCNT,Poll and Measurement Counter Register" bitfld.long 0x00 31. " TCHLOW-ER ,Specifies whether a touched sensor triggers at a lower or higher count than an untouched sensor" "> TCNT is a touch/<= TCNT is a no-touch,<= TCNT is a touch/> TCNT is a no-touch" sif cpuis("LPC804*") bitfld.long 0x00 26.--27. " RDELAY ,Specifies the number of divided FCLKs the module will remain in step 0" "1/FCLK,2/FCLKs,4/FCLKs,8/FCLKs" endif newline bitfld.long 0x00 24.--25. " MDELAY ,Specifies the time delay after entering step 3" "Don't wait,3/FCLKs,5/FCLKs,9/FCLKs" hexmask.long.byte 0x00 16.--23. 1. " POLL ,Sets the time delay between polling rounds" newline bitfld.long 0x00 12.--15. " TOUT ,Sets the count value at which a time-out event occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." hexmask.long.word 0x00 0.--11. 1. " TCNT ,Sets the count boundary in divided FCLKs between touch and no-touch" else rgroup.long 0x08++0x03 line.long 0x00 "POLL_TCNT,Poll and Measurement Counter Register" bitfld.long 0x00 31. " TCHLOW-ER ,Specifies whether a touched sensor triggers at a lower or higher count than an untouched sensor" "> TCNT is a touch/<= TCNT is a no-touch,<= TCNT is a touch/> TCNT is a no-touch" sif cpuis("LPC804*") bitfld.long 0x00 26.--27. " RDELAY ,Specifies the number of divided FCLKs the module will remain in step 0" "1/FCLK,2/FCLKs,4/FCLKs,8/FCLKs" endif newline bitfld.long 0x00 24.--25. " MDELAY ,Specifies the time delay after entering step 3" "Don't wait,3/FCLKs,5/FCLKs,9/FCLKs" hexmask.long.byte 0x00 16.--23. 1. " POLL ,Sets the time delay between polling rounds" newline bitfld.long 0x00 12.--15. " TOUT ,Sets the count value at which a time-out event occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." hexmask.long.word 0x00 0.--11. 1. " TCNT ,Sets the count boundary in divided FCLKs between touch and no-touch" endif group.long 0x18++0x03 line.long 0x00 "INTEN_SET/CLR,Interrupt Enable" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " OVERRUN ,OVERRUN interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIMEOUT ,TIMEOUT interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " POLLDONE ,POLLDONE interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. -0x08 1. -0x04 1. " NOTOUCH ,NOTOUCH interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " YESTOUCH ,YESTOUCH interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40060000+0x20))&0x80000000)==0x00) rgroup.long 0x20++0x03 line.long 0x00 "TOUCH,Touch Data Register" bitfld.long 0x00 31. " CHANGE ,CHANGE status" "Changed,In progress" bitfld.long 0x00 20.--23. " SEQ ,Contains the 4-bit sequence number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " ISTO ,Measurement resulted in a time-out event" "Not timed-out,Timed-out" newline bitfld.long 0x00 16. " ISTOUCH ,Trigger is due to touch or no-touch event" "No-touch,Touch" bitfld.long 0x00 12.--15. " XVAL ,Contains the index of the X pin for the current measurement" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Contains the count value reached at trigger or time-out" else hgroup.long 0x20++0x03 hide.long 0x00 "TOUCH,Touch Data Register" endif rgroup.long 0xFFC++0x03 line.long 0x00 "ID,ID Register" hexmask.long.word 0x00 16.--31. 1. " ID ,Unique module identifier for this IP block" bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture" width 0x0B tree.end endif sif !cpuis("LPC802*")&&!cpuis("LPC804*")&&!cpuis("LPC8N04") tree.open "DAC (Digital-to-Analog Converter)" tree "DAC0" base ad:0x40014000 width 11. group.long 0x00++0xb line.long 0x00 "DACR,D/A Converter Register" bitfld.long 0x00 16. " BIAS ,Settling time\maximum current\maximum update rate" "1us/700uA/1MHz,2.5us/350uA/400kHz" hexmask.long.word 0x00 6.--15. 1. " VALUE ,Value" line.long 0x04 "DACCTRL,D/A Converter Control Register" bitfld.long 0x04 3. " DMA_ENA ,DMA access enable" "Disabled,Enabled" bitfld.long 0x04 2. " CNT_ENA ,Time-out counter operation enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " DBLBUF_ENA ,DACR double-buffering enable" "Disabled,Enabled" bitfld.long 0x04 0. " INT_DMA_REQ ,Interrupt DMA Request" "Not requested,Requested" line.long 0x08 "DACCNTVAL,D/A Converter Counter Value Register" hexmask.long.word 0x08 0.--15. 1. " VALUE ,16-bit reload value for the DAC interrupt/DMA timer" width 0xb tree.end tree "DAC1" base ad:0x40018000 width 11. group.long 0x00++0xb line.long 0x00 "DACR,D/A Converter Register" bitfld.long 0x00 16. " BIAS ,Settling time\maximum current\maximum update rate" "1us/700uA/1MHz,2.5us/350uA/400kHz" hexmask.long.word 0x00 6.--15. 1. " VALUE ,Value" line.long 0x04 "DACCTRL,D/A Converter Control Register" bitfld.long 0x04 3. " DMA_ENA ,DMA access enable" "Disabled,Enabled" bitfld.long 0x04 2. " CNT_ENA ,Time-out counter operation enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " DBLBUF_ENA ,DACR double-buffering enable" "Disabled,Enabled" bitfld.long 0x04 0. " INT_DMA_REQ ,Interrupt DMA Request" "Not requested,Requested" line.long 0x08 "DACCNTVAL,D/A Converter Counter Value Register" hexmask.long.word 0x08 0.--15. 1. " VALUE ,16-bit reload value for the DAC interrupt/DMA timer" width 0xb tree.end tree.end endif endif sif cpuis("LPC804M101JDH24")||cpuis("LPC804M111JDH24")||cpuis("LPC804M101JHI33") tree "DAC (Digital-to-Analog Converter)" base ad:0x40014000 width 11. group.long 0x00++0x0B line.long 0x00 "CR,Converter Register" bitfld.long 0x00 16. " BIAS ,Settling time" "1 MHz,400 kHz" hexmask.long.word 0x00 6.--15. 1. " VALUE ,Value" line.long 0x04 "CTRL,DAC Control Register" bitfld.long 0x04 2. " CNT_ENA ,Time-out counter operation enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " DBLBUF_ENA ,Double-buffering enable" "Disabled,Enabled" bitfld.long 0x04 0. " INT_CPU_REQ ,Interrupt request to CPU" "Not requested,Requested" line.long 0x08 "CNTVAL,DAC Counter Value Register" hexmask.long.word 0x08 0.--15. 1. " VALUE ,16-bit reload value for the DAC interrupt timer" width 0x0B tree.end endif sif cpuis("LPC804*") tree "PLU (Programmable Logic Unit)" base ad:0x40028000 width 17. group.long 0x0++0x13 "LUT0 " line.long 0x00 "LUT0 _INP0_MUX,PLU LUT 0 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT0 _INP0 ,Selects the input source to be connected to LUT0 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT0 _INP1_MUX,PLU LUT 0 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT0 _INP1 ,Selects the input source to be connected to LUT0 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT0 _INP2_MUX,PLU LUT 0 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT0 _INP2 ,Selects the input source to be connected to LUT0 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT0 _INP3_MUX,PLU LUT 0 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT0 _INP3 ,Selects the input source to be connected to LUT0 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT0 _INP4_MUX,PLU LUT 0 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT0 _INP4 ,Selects the input source to be connected to LUT0 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x13 "LUT1 " line.long 0x00 "LUT1 _INP0_MUX,PLU LUT 1 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT1 _INP0 ,Selects the input source to be connected to LUT1 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT1 _INP1_MUX,PLU LUT 1 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT1 _INP1 ,Selects the input source to be connected to LUT1 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT1 _INP2_MUX,PLU LUT 1 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT1 _INP2 ,Selects the input source to be connected to LUT1 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT1 _INP3_MUX,PLU LUT 1 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT1 _INP3 ,Selects the input source to be connected to LUT1 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT1 _INP4_MUX,PLU LUT 1 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT1 _INP4 ,Selects the input source to be connected to LUT1 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x13 "LUT2 " line.long 0x00 "LUT2 _INP0_MUX,PLU LUT 2 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT2 _INP0 ,Selects the input source to be connected to LUT2 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT2 _INP1_MUX,PLU LUT 2 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT2 _INP1 ,Selects the input source to be connected to LUT2 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT2 _INP2_MUX,PLU LUT 2 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT2 _INP2 ,Selects the input source to be connected to LUT2 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT2 _INP3_MUX,PLU LUT 2 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT2 _INP3 ,Selects the input source to be connected to LUT2 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT2 _INP4_MUX,PLU LUT 2 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT2 _INP4 ,Selects the input source to be connected to LUT2 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x13 "LUT3 " line.long 0x00 "LUT3 _INP0_MUX,PLU LUT 3 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT3 _INP0 ,Selects the input source to be connected to LUT3 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT3 _INP1_MUX,PLU LUT 3 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT3 _INP1 ,Selects the input source to be connected to LUT3 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT3 _INP2_MUX,PLU LUT 3 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT3 _INP2 ,Selects the input source to be connected to LUT3 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT3 _INP3_MUX,PLU LUT 3 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT3 _INP3 ,Selects the input source to be connected to LUT3 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT3 _INP4_MUX,PLU LUT 3 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT3 _INP4 ,Selects the input source to be connected to LUT3 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x80++0x13 "LUT4 " line.long 0x00 "LUT4 _INP0_MUX,PLU LUT 4 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT4 _INP0 ,Selects the input source to be connected to LUT4 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT4 _INP1_MUX,PLU LUT 4 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT4 _INP1 ,Selects the input source to be connected to LUT4 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT4 _INP2_MUX,PLU LUT 4 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT4 _INP2 ,Selects the input source to be connected to LUT4 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT4 _INP3_MUX,PLU LUT 4 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT4 _INP3 ,Selects the input source to be connected to LUT4 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT4 _INP4_MUX,PLU LUT 4 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT4 _INP4 ,Selects the input source to be connected to LUT4 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA0++0x13 "LUT5 " line.long 0x00 "LUT5 _INP0_MUX,PLU LUT 5 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT5 _INP0 ,Selects the input source to be connected to LUT5 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT5 _INP1_MUX,PLU LUT 5 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT5 _INP1 ,Selects the input source to be connected to LUT5 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT5 _INP2_MUX,PLU LUT 5 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT5 _INP2 ,Selects the input source to be connected to LUT5 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT5 _INP3_MUX,PLU LUT 5 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT5 _INP3 ,Selects the input source to be connected to LUT5 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT5 _INP4_MUX,PLU LUT 5 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT5 _INP4 ,Selects the input source to be connected to LUT5 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC0++0x13 "LUT6 " line.long 0x00 "LUT6 _INP0_MUX,PLU LUT 6 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT6 _INP0 ,Selects the input source to be connected to LUT6 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT6 _INP1_MUX,PLU LUT 6 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT6 _INP1 ,Selects the input source to be connected to LUT6 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT6 _INP2_MUX,PLU LUT 6 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT6 _INP2 ,Selects the input source to be connected to LUT6 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT6 _INP3_MUX,PLU LUT 6 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT6 _INP3 ,Selects the input source to be connected to LUT6 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT6 _INP4_MUX,PLU LUT 6 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT6 _INP4 ,Selects the input source to be connected to LUT6 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE0++0x13 "LUT7 " line.long 0x00 "LUT7 _INP0_MUX,PLU LUT 7 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT7 _INP0 ,Selects the input source to be connected to LUT7 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT7 _INP1_MUX,PLU LUT 7 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT7 _INP1 ,Selects the input source to be connected to LUT7 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT7 _INP2_MUX,PLU LUT 7 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT7 _INP2 ,Selects the input source to be connected to LUT7 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT7 _INP3_MUX,PLU LUT 7 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT7 _INP3 ,Selects the input source to be connected to LUT7 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT7 _INP4_MUX,PLU LUT 7 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT7 _INP4 ,Selects the input source to be connected to LUT7 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x100++0x13 "LUT8 " line.long 0x00 "LUT8 _INP0_MUX,PLU LUT 8 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT8 _INP0 ,Selects the input source to be connected to LUT8 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT8 _INP1_MUX,PLU LUT 8 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT8 _INP1 ,Selects the input source to be connected to LUT8 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT8 _INP2_MUX,PLU LUT 8 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT8 _INP2 ,Selects the input source to be connected to LUT8 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT8 _INP3_MUX,PLU LUT 8 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT8 _INP3 ,Selects the input source to be connected to LUT8 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT8 _INP4_MUX,PLU LUT 8 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT8 _INP4 ,Selects the input source to be connected to LUT8 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x120++0x13 "LUT9 " line.long 0x00 "LUT9 _INP0_MUX,PLU LUT 9 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT9 _INP0 ,Selects the input source to be connected to LUT9 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT9 _INP1_MUX,PLU LUT 9 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT9 _INP1 ,Selects the input source to be connected to LUT9 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT9 _INP2_MUX,PLU LUT 9 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT9 _INP2 ,Selects the input source to be connected to LUT9 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT9 _INP3_MUX,PLU LUT 9 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT9 _INP3 ,Selects the input source to be connected to LUT9 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT9 _INP4_MUX,PLU LUT 9 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT9 _INP4 ,Selects the input source to be connected to LUT9 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x13 "LUT10" line.long 0x00 "LUT10_INP0_MUX,PLU LUT 10 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT10_INP0 ,Selects the input source to be connected to LUT10 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT10_INP1_MUX,PLU LUT 10 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT10_INP1 ,Selects the input source to be connected to LUT10 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT10_INP2_MUX,PLU LUT 10 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT10_INP2 ,Selects the input source to be connected to LUT10 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT10_INP3_MUX,PLU LUT 10 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT10_INP3 ,Selects the input source to be connected to LUT10 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT10_INP4_MUX,PLU LUT 10 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT10_INP4 ,Selects the input source to be connected to LUT10 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x160++0x13 "LUT11" line.long 0x00 "LUT11_INP0_MUX,PLU LUT 11 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT11_INP0 ,Selects the input source to be connected to LUT11 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT11_INP1_MUX,PLU LUT 11 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT11_INP1 ,Selects the input source to be connected to LUT11 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT11_INP2_MUX,PLU LUT 11 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT11_INP2 ,Selects the input source to be connected to LUT11 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT11_INP3_MUX,PLU LUT 11 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT11_INP3 ,Selects the input source to be connected to LUT11 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT11_INP4_MUX,PLU LUT 11 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT11_INP4 ,Selects the input source to be connected to LUT11 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x180++0x13 "LUT12" line.long 0x00 "LUT12_INP0_MUX,PLU LUT 12 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT12_INP0 ,Selects the input source to be connected to LUT12 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT12_INP1_MUX,PLU LUT 12 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT12_INP1 ,Selects the input source to be connected to LUT12 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT12_INP2_MUX,PLU LUT 12 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT12_INP2 ,Selects the input source to be connected to LUT12 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT12_INP3_MUX,PLU LUT 12 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT12_INP3 ,Selects the input source to be connected to LUT12 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT12_INP4_MUX,PLU LUT 12 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT12_INP4 ,Selects the input source to be connected to LUT12 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1A0++0x13 "LUT13" line.long 0x00 "LUT13_INP0_MUX,PLU LUT 13 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT13_INP0 ,Selects the input source to be connected to LUT13 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT13_INP1_MUX,PLU LUT 13 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT13_INP1 ,Selects the input source to be connected to LUT13 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT13_INP2_MUX,PLU LUT 13 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT13_INP2 ,Selects the input source to be connected to LUT13 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT13_INP3_MUX,PLU LUT 13 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT13_INP3 ,Selects the input source to be connected to LUT13 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT13_INP4_MUX,PLU LUT 13 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT13_INP4 ,Selects the input source to be connected to LUT13 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C0++0x13 "LUT14" line.long 0x00 "LUT14_INP0_MUX,PLU LUT 14 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT14_INP0 ,Selects the input source to be connected to LUT14 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT14_INP1_MUX,PLU LUT 14 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT14_INP1 ,Selects the input source to be connected to LUT14 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT14_INP2_MUX,PLU LUT 14 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT14_INP2 ,Selects the input source to be connected to LUT14 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT14_INP3_MUX,PLU LUT 14 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT14_INP3 ,Selects the input source to be connected to LUT14 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT14_INP4_MUX,PLU LUT 14 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT14_INP4 ,Selects the input source to be connected to LUT14 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E0++0x13 "LUT15" line.long 0x00 "LUT15_INP0_MUX,PLU LUT 15 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT15_INP0 ,Selects the input source to be connected to LUT15 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT15_INP1_MUX,PLU LUT 15 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT15_INP1 ,Selects the input source to be connected to LUT15 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT15_INP2_MUX,PLU LUT 15 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT15_INP2 ,Selects the input source to be connected to LUT15 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT15_INP3_MUX,PLU LUT 15 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT15_INP3 ,Selects the input source to be connected to LUT15 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT15_INP4_MUX,PLU LUT 15 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT15_INP4 ,Selects the input source to be connected to LUT15 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x13 "LUT16" line.long 0x00 "LUT16_INP0_MUX,PLU LUT 16 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT16_INP0 ,Selects the input source to be connected to LUT16 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT16_INP1_MUX,PLU LUT 16 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT16_INP1 ,Selects the input source to be connected to LUT16 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT16_INP2_MUX,PLU LUT 16 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT16_INP2 ,Selects the input source to be connected to LUT16 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT16_INP3_MUX,PLU LUT 16 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT16_INP3 ,Selects the input source to be connected to LUT16 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT16_INP4_MUX,PLU LUT 16 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT16_INP4 ,Selects the input source to be connected to LUT16 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x220++0x13 "LUT17" line.long 0x00 "LUT17_INP0_MUX,PLU LUT 17 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT17_INP0 ,Selects the input source to be connected to LUT17 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT17_INP1_MUX,PLU LUT 17 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT17_INP1 ,Selects the input source to be connected to LUT17 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT17_INP2_MUX,PLU LUT 17 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT17_INP2 ,Selects the input source to be connected to LUT17 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT17_INP3_MUX,PLU LUT 17 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT17_INP3 ,Selects the input source to be connected to LUT17 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT17_INP4_MUX,PLU LUT 17 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT17_INP4 ,Selects the input source to be connected to LUT17 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x240++0x13 "LUT18" line.long 0x00 "LUT18_INP0_MUX,PLU LUT 18 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT18_INP0 ,Selects the input source to be connected to LUT18 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT18_INP1_MUX,PLU LUT 18 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT18_INP1 ,Selects the input source to be connected to LUT18 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT18_INP2_MUX,PLU LUT 18 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT18_INP2 ,Selects the input source to be connected to LUT18 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT18_INP3_MUX,PLU LUT 18 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT18_INP3 ,Selects the input source to be connected to LUT18 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT18_INP4_MUX,PLU LUT 18 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT18_INP4 ,Selects the input source to be connected to LUT18 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x260++0x13 "LUT19" line.long 0x00 "LUT19_INP0_MUX,PLU LUT 19 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT19_INP0 ,Selects the input source to be connected to LUT19 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT19_INP1_MUX,PLU LUT 19 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT19_INP1 ,Selects the input source to be connected to LUT19 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT19_INP2_MUX,PLU LUT 19 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT19_INP2 ,Selects the input source to be connected to LUT19 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT19_INP3_MUX,PLU LUT 19 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT19_INP3 ,Selects the input source to be connected to LUT19 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT19_INP4_MUX,PLU LUT 19 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT19_INP4 ,Selects the input source to be connected to LUT19 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x280++0x13 "LUT20" line.long 0x00 "LUT20_INP0_MUX,PLU LUT 20 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT20_INP0 ,Selects the input source to be connected to LUT20 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT20_INP1_MUX,PLU LUT 20 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT20_INP1 ,Selects the input source to be connected to LUT20 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT20_INP2_MUX,PLU LUT 20 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT20_INP2 ,Selects the input source to be connected to LUT20 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT20_INP3_MUX,PLU LUT 20 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT20_INP3 ,Selects the input source to be connected to LUT20 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT20_INP4_MUX,PLU LUT 20 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT20_INP4 ,Selects the input source to be connected to LUT20 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2A0++0x13 "LUT21" line.long 0x00 "LUT21_INP0_MUX,PLU LUT 21 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT21_INP0 ,Selects the input source to be connected to LUT21 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT21_INP1_MUX,PLU LUT 21 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT21_INP1 ,Selects the input source to be connected to LUT21 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT21_INP2_MUX,PLU LUT 21 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT21_INP2 ,Selects the input source to be connected to LUT21 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT21_INP3_MUX,PLU LUT 21 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT21_INP3 ,Selects the input source to be connected to LUT21 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT21_INP4_MUX,PLU LUT 21 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT21_INP4 ,Selects the input source to be connected to LUT21 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C0++0x13 "LUT22" line.long 0x00 "LUT22_INP0_MUX,PLU LUT 22 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT22_INP0 ,Selects the input source to be connected to LUT22 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT22_INP1_MUX,PLU LUT 22 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT22_INP1 ,Selects the input source to be connected to LUT22 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT22_INP2_MUX,PLU LUT 22 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT22_INP2 ,Selects the input source to be connected to LUT22 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT22_INP3_MUX,PLU LUT 22 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT22_INP3 ,Selects the input source to be connected to LUT22 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT22_INP4_MUX,PLU LUT 22 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT22_INP4 ,Selects the input source to be connected to LUT22 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2E0++0x13 "LUT23" line.long 0x00 "LUT23_INP0_MUX,PLU LUT 23 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT23_INP0 ,Selects the input source to be connected to LUT23 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT23_INP1_MUX,PLU LUT 23 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT23_INP1 ,Selects the input source to be connected to LUT23 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT23_INP2_MUX,PLU LUT 23 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT23_INP2 ,Selects the input source to be connected to LUT23 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT23_INP3_MUX,PLU LUT 23 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT23_INP3 ,Selects the input source to be connected to LUT23 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT23_INP4_MUX,PLU LUT 23 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT23_INP4 ,Selects the input source to be connected to LUT23 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x300++0x13 "LUT24" line.long 0x00 "LUT24_INP0_MUX,PLU LUT 24 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT24_INP0 ,Selects the input source to be connected to LUT24 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT24_INP1_MUX,PLU LUT 24 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT24_INP1 ,Selects the input source to be connected to LUT24 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT24_INP2_MUX,PLU LUT 24 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT24_INP2 ,Selects the input source to be connected to LUT24 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT24_INP3_MUX,PLU LUT 24 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT24_INP3 ,Selects the input source to be connected to LUT24 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT24_INP4_MUX,PLU LUT 24 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT24_INP4 ,Selects the input source to be connected to LUT24 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x320++0x13 "LUT25" line.long 0x00 "LUT25_INP0_MUX,PLU LUT 25 Input Mux 0 Register" bitfld.long 0x00 0.--5. " LUT25_INP0 ,Selects the input source to be connected to LUT25 Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LUT25_INP1_MUX,PLU LUT 25 Input Mux 1 Register" bitfld.long 0x04 0.--5. " LUT25_INP1 ,Selects the input source to be connected to LUT25 Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LUT25_INP2_MUX,PLU LUT 25 Input Mux 2 Register" bitfld.long 0x08 0.--5. " LUT25_INP2 ,Selects the input source to be connected to LUT25 Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "LUT25_INP3_MUX,PLU LUT 25 Input Mux 3 Register" bitfld.long 0x0C 0.--5. " LUT25_INP3 ,Selects the input source to be connected to LUT25 Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "LUT25_INP4_MUX,PLU LUT 25 Input Mux 4 Register" bitfld.long 0x10 0.--5. " LUT25_INP4 ,Selects the input source to be connected to LUT25 Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline group.long 0x800++0x03 line.long 0x00 "LUT0_TRUTH,PLU LUT 0x800 Truth Table Register" group.long 0x804++0x03 line.long 0x00 "LUT1_TRUTH,PLU LUT 0x804 Truth Table Register" group.long 0x808++0x03 line.long 0x00 "LUT2_TRUTH,PLU LUT 0x808 Truth Table Register" group.long 0x80C++0x03 line.long 0x00 "LUT3_TRUTH,PLU LUT 0x80C Truth Table Register" group.long 0x810++0x03 line.long 0x00 "LUT4_TRUTH,PLU LUT 0x810 Truth Table Register" group.long 0x814++0x03 line.long 0x00 "LUT5_TRUTH,PLU LUT 0x814 Truth Table Register" group.long 0x818++0x03 line.long 0x00 "LUT6_TRUTH,PLU LUT 0x818 Truth Table Register" group.long 0x81C++0x03 line.long 0x00 "LUT7_TRUTH,PLU LUT 0x81C Truth Table Register" group.long 0x820++0x03 line.long 0x00 "LUT8_TRUTH,PLU LUT 0x820 Truth Table Register" group.long 0x824++0x03 line.long 0x00 "LUT9_TRUTH,PLU LUT 0x824 Truth Table Register" group.long 0x828++0x03 line.long 0x00 "LUT10_TRUTH,PLU LUT 0x828 Truth Table Register" group.long 0x82C++0x03 line.long 0x00 "LUT11_TRUTH,PLU LUT 0x82C Truth Table Register" group.long 0x830++0x03 line.long 0x00 "LUT12_TRUTH,PLU LUT 0x830 Truth Table Register" group.long 0x834++0x03 line.long 0x00 "LUT13_TRUTH,PLU LUT 0x834 Truth Table Register" group.long 0x838++0x03 line.long 0x00 "LUT14_TRUTH,PLU LUT 0x838 Truth Table Register" group.long 0x83C++0x03 line.long 0x00 "LUT15_TRUTH,PLU LUT 0x83C Truth Table Register" group.long 0x840++0x03 line.long 0x00 "LUT16_TRUTH,PLU LUT 0x840 Truth Table Register" group.long 0x844++0x03 line.long 0x00 "LUT17_TRUTH,PLU LUT 0x844 Truth Table Register" group.long 0x848++0x03 line.long 0x00 "LUT18_TRUTH,PLU LUT 0x848 Truth Table Register" group.long 0x84C++0x03 line.long 0x00 "LUT19_TRUTH,PLU LUT 0x84C Truth Table Register" group.long 0x850++0x03 line.long 0x00 "LUT20_TRUTH,PLU LUT 0x850 Truth Table Register" group.long 0x854++0x03 line.long 0x00 "LUT21_TRUTH,PLU LUT 0x854 Truth Table Register" group.long 0x858++0x03 line.long 0x00 "LUT22_TRUTH,PLU LUT 0x858 Truth Table Register" group.long 0x85C++0x03 line.long 0x00 "LUT23_TRUTH,PLU LUT 0x85C Truth Table Register" group.long 0x860++0x03 line.long 0x00 "LUT24_TRUTH,PLU LUT 0x860 Truth Table Register" group.long 0x864++0x03 line.long 0x00 "LUT25_TRUTH,PLU LUT 0x864 Truth Table Register" group.long 0xC00++0x03 line.long 0x00 "OUTPUT0_MUX,PLU Output 0 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT0 ,Selects the source to be connected to PLU Output 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC04++0x03 line.long 0x00 "OUTPUT1_MUX,PLU Output 1 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT1 ,Selects the source to be connected to PLU Output 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC08++0x03 line.long 0x00 "OUTPUT2_MUX,PLU Output 2 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT2 ,Selects the source to be connected to PLU Output 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC0C++0x03 line.long 0x00 "OUTPUT3_MUX,PLU Output 3 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT3 ,Selects the source to be connected to PLU Output 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC10++0x03 line.long 0x00 "OUTPUT4_MUX,PLU Output 4 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT4 ,Selects the source to be connected to PLU Output 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC14++0x03 line.long 0x00 "OUTPUT5_MUX,PLU Output 5 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT5 ,Selects the source to be connected to PLU Output 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC18++0x03 line.long 0x00 "OUTPUT6_MUX,PLU Output 6 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT6 ,Selects the source to be connected to PLU Output 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC1C++0x03 line.long 0x00 "OUTPUT7_MUX,PLU Output 7 Mux Register" bitfld.long 0x00 0.--4. " OUTPUT7 ,Selects the source to be connected to PLU Output 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x900++0x03 line.long 0x00 "OUTPUTS,PLU Outputs Register" hexmask.long.byte 0x00 0.--7. 1. " OUTPUT ,Provides the current state of the 8 designated PLU outputs" width 0x0B tree.end endif sif !cpuis("LPC8N04") tree "CRC (Cyclic Redundancy Check)" base ad:0x50000000 width 9. group.long 0x00++0x07 line.long 0x00 "MODE,CRC Mode Register" bitfld.long 0x00 5. " CMPL_SUM ,Data 1's complement enable for CRC_SUM" "Disabled,Enabled" bitfld.long 0x00 4. " BIT_RVS_SUM ,Bit order for CRC_SUM" "Not reversed,Reversed" bitfld.long 0x00 3. " CMPL_WR ,Data 1's complement enable for CRC_WR_DATA" "Disabled,Enabled" newline bitfld.long 0x00 2. " BIT_RVS_WR ,Bit order for CRC_WR_DATA" "Not reversed,Reversed" bitfld.long 0x00 0.--1. " CRC_POLY ,CRC polynomial select" "CRC-CCITT,CRC-16,CRC-32,CRC-32" line.long 0x04 "SEED,CRC Seed Register" rgroup.long 0x08++0x03 line.long 0x00 "SUM,CRC Checksum Register" wgroup.long 0x08++0x03 line.long 0x00 "WR_DATA,CRC Data Register" width 0x0B tree.end endif sif !cpuis("LPC802*")&&!cpuis("LPC804*") sif cpuis("LPC8N04") tree "Flash Controller" base ad:0x4003C000 width 20. if (((per.l(ad:0x4003C000))&0x20000)==0x20000) if (((per.l(ad:0x4003C000))&0x80)==0x80) group.long 0x00++0x03 line.long 0x00 "FCTR,Flash Control Register" bitfld.long 0x00 19. " PDBG ,Band gap power-down mode enabled" "Disabled,Enabled" bitfld.long 0x00 18. " LPM ,Memory low-down mode enabled" "Disabled,Enabled" rbitfld.long 0x00 17. " INIT_WR ,Starts write initialization" "Not started,Started" bitfld.long 0x00 16. " REMAP ,Enable address remapping" "Disabled,Enabled" newline bitfld.long 0x00 15. " LOADREQ ,Triggers memory write operation" "Not triggered,Triggered" rbitfld.long 0x00 12. " PROGREQ ,Memory is busy doing program/erase" "Not busy,Busy" bitfld.long 0x00 11. " RLS ,Read sector latches instead of memory array" "Not read,Read" bitfld.long 0x00 10. " PDL ,Page register presetting" "No effect,Set" newline bitfld.long 0x00 9. " PD ,Force memory to power-down mode" "Not forced,Forced" bitfld.long 0x00 8. " ERSP ,Enable single page erase mode" "Disabled,Enabled" bitfld.long 0x00 7. " WPB ,Enable program\erase" "Disabled,Enabled" bitfld.long 0x00 6. " ISS ,Access index sector instead of main array" "Not accessed,Accessed" newline bitfld.long 0x00 5. " RLD ,Read the page register data-latches" "Not read,Read" bitfld.long 0x00 4. " DCR ,Select DC read mode" "Not selected,Selected" bitfld.long 0x00 2. " WEB ,Program/Erase start" "Started,Not started" newline bitfld.long 0x00 1. " WRE ,Erase or program" "Erase,Program" bitfld.long 0x00 0. " CS ,Standby mode disabled" "No,Yes" else group.long 0x00++0x03 line.long 0x00 "FCTR,Flash Control Register" bitfld.long 0x00 19. " PDBG ,Band gap power-down mode enabled" "Disabled,Enabled" bitfld.long 0x00 18. " LPM ,Memory low-down mode enabled" "Disabled,Enabled" rbitfld.long 0x00 17. " INIT_WR ,Starts write initialization" "Not started,Started" bitfld.long 0x00 16. " REMAP ,Enable address remapping" "Disabled,Enabled" newline bitfld.long 0x00 15. " LOADREQ ,Triggers memory write operation" "Not triggered,Triggered" rbitfld.long 0x00 12. " PROGREQ ,Memory is busy doing program/erase" "Not busy,Busy" bitfld.long 0x00 11. " RLS ,Read sector latches instead of memory array" "Not read,Read" bitfld.long 0x00 10. " PDL ,Page register presetting" "No effect,Set" newline bitfld.long 0x00 9. " PD ,Force memory to power-down mode" "Not forced,Forced" bitfld.long 0x00 8. " ERSP ,Enable single page erase mode" "Disabled,Enabled" bitfld.long 0x00 7. " WPB ,Enable program\erase" "Disabled,Enabled" bitfld.long 0x00 6. " ISS ,Access index sector instead of main array" "Not accessed,Accessed" newline bitfld.long 0x00 5. " RLD ,Read the page register data-latches" "Not read,Read" bitfld.long 0x00 4. " DCR ,Select DC read mode" "Not selected,Selected" bitfld.long 0x00 2. " WEB ,Program/Erase start" "Started,Not started" newline bitfld.long 0x00 1. " WRE ,Write or read" "Read,Write" bitfld.long 0x00 0. " CS ,Standby mode disabled" "No,Yes" endif else if (((per.l(ad:0x4003C000))&0x80)==0x80) group.long 0x00++0x03 line.long 0x00 "FCTR,Flash Control Register" bitfld.long 0x00 19. " PDBG ,Band gap power-down mode enabled" "Disabled,Enabled" bitfld.long 0x00 18. " LPM ,Memory low-down mode enabled" "Disabled,Enabled" bitfld.long 0x00 17. " INIT_WR ,Starts write initialization" "Not started,Started" bitfld.long 0x00 16. " REMAP ,Enable address remapping" "Disabled,Enabled" newline bitfld.long 0x00 15. " LOADREQ ,Triggers memory write operation" "Not triggered,Triggered" rbitfld.long 0x00 12. " PROGREQ ,Memory is busy doing program/erase" "Not busy,Busy" bitfld.long 0x00 11. " RLS ,Read sector latches instead of memory array" "Not read,Read" bitfld.long 0x00 10. " PDL ,Page register presetting" "No effect,Set" newline bitfld.long 0x00 9. " PD ,Force memory to power-down mode" "Not forced,Forced" bitfld.long 0x00 8. " ERSP ,Enable single page erase mode" "Disabled,Enabled" bitfld.long 0x00 7. " WPB ,Enable program\erase" "Disabled,Enabled" bitfld.long 0x00 6. " ISS ,Access index sector instead of main array" "Not accessed,Accessed" newline bitfld.long 0x00 5. " RLD ,Read the page register data-latches" "Not read,Read" bitfld.long 0x00 4. " DCR ,Select DC read mode" "Not selected,Selected" bitfld.long 0x00 2. " WEB ,Program/Erase start" "Started,Not started" newline bitfld.long 0x00 1. " WRE ,Erase or program" "Erase,Program" bitfld.long 0x00 0. " CS ,Standby mode disabled" "No,Yes" else group.long 0x00++0x03 line.long 0x00 "FCTR,Flash Control Register" bitfld.long 0x00 19. " PDBG ,Band gap power-down mode enabled" "Disabled,Enabled" bitfld.long 0x00 18. " LPM ,Memory low-down mode enabled" "Disabled,Enabled" bitfld.long 0x00 17. " INIT_WR ,Starts write initialization" "Not started,Started" bitfld.long 0x00 16. " REMAP ,Enable address remapping" "Disabled,Enabled" newline bitfld.long 0x00 15. " LOADREQ ,Triggers memory write operation" "Not triggered,Triggered" rbitfld.long 0x00 12. " PROGREQ ,Memory is busy doing program/erase" "Not busy,Busy" bitfld.long 0x00 11. " RLS ,Read sector latches instead of memory array" "Not read,Read" bitfld.long 0x00 10. " PDL ,Page register presetting" "No effect,Set" newline bitfld.long 0x00 9. " PD ,Force memory to power-down mode" "Not forced,Forced" bitfld.long 0x00 8. " ERSP ,Enable single page erase mode" "Disabled,Enabled" bitfld.long 0x00 7. " WPB ,Enable program\erase" "Disabled,Enabled" bitfld.long 0x00 6. " ISS ,Access index sector instead of main array" "Not accessed,Accessed" newline bitfld.long 0x00 5. " RLD ,Read the page register data-latches" "Not read,Read" bitfld.long 0x00 4. " DCR ,Select DC read mode" "Not selected,Selected" bitfld.long 0x00 2. " WEB ,Program/Erase start" "Started,Not started" newline bitfld.long 0x00 1. " WRE ,Write or read" "Read,Write" bitfld.long 0x00 0. " CS ,Standby mode disabled" "No,Yes" endif endif rgroup.long 0x04++0x03 line.long 0x00 "FSTAT,Flash Status Register" bitfld.long 0x00 8. " CORRECTED ,ECC detected a correctable error" "Not detected,Detected" bitfld.long 0x00 5.--7. " SL ,Sector latches" "Protected,Locked,Selected,?..." bitfld.long 0x00 2. " RY ,Flash busy status" "Busy,Not busy" group.long 0x10++0x03 line.long 0x00 "FBWST,Flash Wait State Register" bitfld.long 0x00 15. " CACHE2EN ,Cache enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPECALWAYS ,Speculative reading" "Single,Always" hexmask.long.byte 0x00 0.--7. 1. " WST ,Number of wait states" rgroup.long 0x08++0x03 line.long 0x00 "FPTR,Duration Of The Program/Erase Operation Register" hexmask.long.tbyte 0x00 11.--28. 1. " TR ,Duration of the program/erase pulse" hexmask.long.word 0x00 0.--11. 1. " EN_T ,Sets timer" group.long 0x1C++0x13 line.long 0x00 "FCRA,Frequency Of The Program/Erase Clock Register" hexmask.long.word 0x00 0.--11. 1. " FCRA ,Frequency of the program/erase clock" line.long 0x04 "FMSSTART,Flash Memory Signature Start Address" hexmask.long.tbyte 0x04 0.--16. 0x01 " STARTA ,Start address for signature generation" line.long 0x08 "FMSSTOP,Flash Memory Signature Stop Register" bitfld.long 0x08 31. " STRTBIS ,Starts signature generation" "Not started,Started" hexmask.long.tbyte 0x08 0.--16. 0x01 " STOPA ,Stop address for signature generation" line.long 0x0C "FMS16,Flash Parity Signature Register" hexmask.long.word 0x0C 0.--15. 1. " FMS16 ,Parity signature for the specified address range" line.long 0x10 "FMSW0,Flash Data Signature Register" rgroup.long 0x50++0x07 line.long 0x00 "ECCRSTERRCNT,ECC Status Information Register" bitfld.long 0x00 0. " ECCRSTERRCNT ,Clear the ECCERRCNT register" "Not cleared,Cleared" line.long 0x04 "ECCERRCNT,Invalid Flag And Error Corrected Counter Reset Register" hexmask.long.tbyte 0x04 5.--17. 0x20 " ERR_PAGE ,Page address of the last Location containing an ECC" bitfld.long 0x04 1.--4. " ERRCOUNTER ,ECC counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. " INVALID_FLAG ,Uncorrectable ECC error flag" "Not occurred,Occurred" newline group.long 0xFE8++0x07 line.long 0x00 "INT_CLR_STATUS,Clear Interrupt Status Bits Register" bitfld.long 0x00 31. " CLR_STATUS[31] ,Corresponding INT_STATUS bit 31 is cleared" "Not cleared,Cleared" bitfld.long 0x00 30. " [30] ,Corresponding INT_STATUS bit 30 is cleared" "Not cleared,Cleared" bitfld.long 0x00 29. " [29] ,Corresponding INT_STATUS bit 29 is cleared" "Not cleared,Cleared" bitfld.long 0x00 28. " [28] ,Corresponding INT_STATUS bit 28 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 27. " [27] ,Corresponding INT_STATUS bit 27 is cleared" "Not cleared,Cleared" bitfld.long 0x00 26. " [26] ,Corresponding INT_STATUS bit 26 is cleared" "Not cleared,Cleared" bitfld.long 0x00 25. " [25] ,Corresponding INT_STATUS bit 25 is cleared" "Not cleared,Cleared" bitfld.long 0x00 24. " [24] ,Corresponding INT_STATUS bit 24 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 23. " [23] ,Corresponding INT_STATUS bit 23 is cleared" "Not cleared,Cleared" bitfld.long 0x00 22. " [22] ,Corresponding INT_STATUS bit 22 is cleared" "Not cleared,Cleared" bitfld.long 0x00 21. " [21] ,Corresponding INT_STATUS bit 21 is cleared" "Not cleared,Cleared" bitfld.long 0x00 20. " [20] ,Corresponding INT_STATUS bit 20 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 19. " [19] ,Corresponding INT_STATUS bit 19 is cleared" "Not cleared,Cleared" bitfld.long 0x00 18. " [18] ,Corresponding INT_STATUS bit 18 is cleared" "Not cleared,Cleared" bitfld.long 0x00 17. " [17] ,Corresponding INT_STATUS bit 17 is cleared" "Not cleared,Cleared" bitfld.long 0x00 16. " [16] ,Corresponding INT_STATUS bit 16 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 15. " [15] ,Corresponding INT_STATUS bit 15 is cleared" "Not cleared,Cleared" bitfld.long 0x00 14. " [14] ,Corresponding INT_STATUS bit 14 is cleared" "Not cleared,Cleared" bitfld.long 0x00 13. " [13] ,Corresponding INT_STATUS bit 13 is cleared" "Not cleared,Cleared" bitfld.long 0x00 12. " [12] ,Corresponding INT_STATUS bit 12 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 11. " [11] ,Corresponding INT_STATUS bit 11 is cleared" "Not cleared,Cleared" bitfld.long 0x00 10. " [10] ,Corresponding INT_STATUS bit 10 is cleared" "Not cleared,Cleared" bitfld.long 0x00 9. " [9] ,Corresponding INT_STATUS bit 9 is cleared" "Not cleared,Cleared" bitfld.long 0x00 8. " [8] ,Corresponding INT_STATUS bit 8 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 7. " [7] ,Corresponding INT_STATUS bit 7 is cleared" "Not cleared,Cleared" bitfld.long 0x00 6. " [6] ,Corresponding INT_STATUS bit 6 is cleared" "Not cleared,Cleared" bitfld.long 0x00 5. " [5] ,Corresponding INT_STATUS bit 5 is cleared" "Not cleared,Cleared" bitfld.long 0x00 4. " [4] ,Corresponding INT_STATUS bit 4 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 3. " [3] ,Corresponding INT_STATUS bit 3 is cleared" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Corresponding INT_STATUS bit 2 is cleared" "Not cleared,Cleared" bitfld.long 0x00 1. " [1] ,Corresponding INT_STATUS bit 1 is cleared" "Not cleared,Cleared" bitfld.long 0x00 0. " [0] ,Corresponding INT_STATUS bit 0 is cleared" "Not cleared,Cleared" line.long 0x04 "INT_SET_STATUS,Interrupt Clear Status Register" bitfld.long 0x04 31. " CLR_STATUS[31] ,Corresponding INT_STATUS bit 31 is Set" "No effect,Set" bitfld.long 0x04 30. " [30] ,Corresponding INT_STATUS bit 30 is Set" "No effect,Set" bitfld.long 0x04 29. " [29] ,Corresponding INT_STATUS bit 29 is Set" "No effect,Set" bitfld.long 0x04 28. " [28] ,Corresponding INT_STATUS bit 28 is Set" "No effect,Set" newline bitfld.long 0x04 27. " [27] ,Corresponding INT_STATUS bit 27 is Set" "No effect,Set" bitfld.long 0x04 26. " [26] ,Corresponding INT_STATUS bit 26 is Set" "No effect,Set" bitfld.long 0x04 25. " [25] ,Corresponding INT_STATUS bit 25 is Set" "No effect,Set" bitfld.long 0x04 24. " [24] ,Corresponding INT_STATUS bit 24 is Set" "No effect,Set" newline bitfld.long 0x04 23. " [23] ,Corresponding INT_STATUS bit 23 is Set" "No effect,Set" bitfld.long 0x04 22. " [22] ,Corresponding INT_STATUS bit 22 is Set" "No effect,Set" bitfld.long 0x04 21. " [21] ,Corresponding INT_STATUS bit 21 is Set" "No effect,Set" bitfld.long 0x04 20. " [20] ,Corresponding INT_STATUS bit 20 is Set" "No effect,Set" newline bitfld.long 0x04 19. " [19] ,Corresponding INT_STATUS bit 19 is Set" "No effect,Set" bitfld.long 0x04 18. " [18] ,Corresponding INT_STATUS bit 18 is Set" "No effect,Set" bitfld.long 0x04 17. " [17] ,Corresponding INT_STATUS bit 17 is Set" "No effect,Set" bitfld.long 0x04 16. " [16] ,Corresponding INT_STATUS bit 16 is Set" "No effect,Set" newline bitfld.long 0x04 15. " [15] ,Corresponding INT_STATUS bit 15 is Set" "No effect,Set" bitfld.long 0x04 14. " [14] ,Corresponding INT_STATUS bit 14 is Set" "No effect,Set" bitfld.long 0x04 13. " [13] ,Corresponding INT_STATUS bit 13 is Set" "No effect,Set" bitfld.long 0x04 12. " [12] ,Corresponding INT_STATUS bit 12 is Set" "No effect,Set" newline bitfld.long 0x04 11. " [11] ,Corresponding INT_STATUS bit 11 is Set" "No effect,Set" bitfld.long 0x04 10. " [10] ,Corresponding INT_STATUS bit 10 is Set" "No effect,Set" bitfld.long 0x04 9. " [9] ,Corresponding INT_STATUS bit 9 is Set" "No effect,Set" bitfld.long 0x04 8. " [8] ,Corresponding INT_STATUS bit 8 is Set" "No effect,Set" newline bitfld.long 0x04 7. " [7] ,Corresponding INT_STATUS bit 7 is Set" "No effect,Set" bitfld.long 0x04 6. " [6] ,Corresponding INT_STATUS bit 6 is Set" "No effect,Set" bitfld.long 0x04 5. " [5] ,Corresponding INT_STATUS bit 5 is Set" "No effect,Set" bitfld.long 0x04 4. " [4] ,Corresponding INT_STATUS bit 4 is Set" "No effect,Set" newline bitfld.long 0x04 3. " [3] ,Corresponding INT_STATUS bit 3 is Set" "No effect,Set" bitfld.long 0x04 2. " [2] ,Corresponding INT_STATUS bit 2 is Set" "No effect,Set" bitfld.long 0x04 1. " [1] ,Corresponding INT_STATUS bit 1 is Set" "No effect,Set" bitfld.long 0x04 0. " [0] ,Corresponding INT_STATUS bit 0 is Set" "No effect,Set" group.long 0xFE0++0x07 line.long 0x00 "INT_ENABLE_SET/CLR,Interrupt Enable Bits Register" setclrfld.long 0x00 31. -0x04 31. -0x08 31. " INT_ENABLE[31] ,Bit 31 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Bit 30 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Bit 29 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Bit 28 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Bit 27 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Bit 26 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Bit 25 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Bit 24 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Bit 23 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Bit 22 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Bit 21 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Bit 20 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Bit 19 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Bit 18 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Bit 17 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Bit 16 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Bit 15 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Bit 14 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Bit 13 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Bit 12 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Bit 11 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Bit 10 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Bit 9 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Bit 8 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Bit 7 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Bit 6 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Bit 5 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Bit 4 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Bit 3 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Bit 2 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Bit 1 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Bit 0 interrupt status" "No interrupt,Interrupt" newline line.long 0x04 "INT_STATUS,Interrupt Status Bits Register" bitfld.long 0x04 3. " ECC_ERR ,Correctable or uncorrectable error" "Not occurred,Occurred" bitfld.long 0x04 2. " PROG_DONE ,High-voltage operation status" "Not done,Done" bitfld.long 0x04 1. " SIG_DONE ,Signature computation status" "Not done,Done" rgroup.long 0xFFC++0x03 line.long 0x00 "MODULE_ID,Controller Memory Module Identification Register" bitfld.long 0x00 12.--15. " CORRECTED ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,The size of the memory" width 0x0B tree.end else tree "Flash Controller" base ad:0x40040000 width 10. group.long 0x10++0x03 line.long 0x00 "FLASHCFG,Flash Configuration Register" bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 clock,2 clocks,?..." group.long 0x20++0x07 line.long 0x00 "FMSSTART,Flash Module Signature Start Register" hexmask.long.tbyte 0x00 0.--16. 0x1 " START ,Signature generation start address" line.long 0x04 "FMSSTOP,Flash Module Signature Stop Register" bitfld.long 0x04 31. " STRTBIST ,Signature generation start bit" "Not started/Finished,Started" hexmask.long.tbyte 0x04 0.--16. 0x1 " STOPA ,Signature generation stop address" rgroup.long 0x2C++0x03 line.long 0x00 "FMSW0,Flash Signature Generation Result" sif cpuis("LPC84*") rgroup.long 0xFE0++0x03 line.long 0x00 "FMSTAT,Flash Module Signature Status Register" bitfld.long 0x00 2. " SIG_DONE ,Signature status" "In progress,Done" wgroup.long 0xFE8++0x03 line.long 0x00 "FMSTATCLR,Flash Module Signature Status Clear Register" bitfld.long 0x00 2. " SIG_DONE_CLR ,Signature status clear" "Not clear,Clear" endif width 0x0B tree.end endif endif sif cpuis("LPC8N04") tree "TS (Temperature Sensor)" base ad:0x40060000 width 6. group.long 0x00++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 0. " START ,Sensor start bit" "Not started,Started" hgroup.long 0x04++0x03 hide.long 0x00 "DR,Data Register" in rgroup.long 0x08++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 8. " TOUTMODE ,Used output mode" "Raw,Calibrated" bitfld.long 0x00 5.--7. " TRESMODE ,Used resolution mode" ",,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit" bitfld.long 0x00 4. " TSUCC ,Conversion state" "Unsuccessful,Successful" bitfld.long 0x00 3. " TRANHIF ,Fine range" "Fine,Too large" newline bitfld.long 0x00 2. " TRANLOF ,Fine range" "Fine,Too low" bitfld.long 0x00 1. " TRANHIC ,Coarse range" "Fine,Too high" bitfld.long 0x00 0. " TRANLOC ,Coarse range" "Fine,Too low" group.long 0x0C++0x1B line.long 0x00 "SP0,Setup Register 0" bitfld.long 0x00 6. " TVCALEN ,Temperature sensor voltage calibration enable" "Disabled,Enabled" bitfld.long 0x00 1.--3. " TRESMODE ,Temperature sensor voltage calibration enable" ",,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit" bitfld.long 0x00 0. " TOUTMODE ,Temperature sensor output mode" "Raw,Calibrated" line.long 0x04 "SP1,Setup Register 1" hexmask.long.word 0x04 0.--15. 1. " A ,Calibration factor 'A' unsigned fixed point 2-complement" line.long 0x08 "SP2,Setup Register 2" hexmask.long.word 0x08 0.--15. 1. " B ,Calibration factor 'B' unsigned fixed point 2-complement" line.long 0x0C "SP3,Setup Register 3" hexmask.long.word 0x0C 0.--15. 1. " ALPHA ,Calibration factor 'alpha' unsigned fixed point 2-complement" line.long 0x10 "TLO,Low Temperature Threshold Register" hexmask.long.word 0x10 0.--15. 1. " TLO ,Low-temperature threshold value in signed fixed point 2-complement" line.long 0x14 "THI,High Temperature Threshold Register" hexmask.long.word 0x14 0.--15. 1. " THI ,High-temperature threshold value in signed fixed point 2-complement" line.long 0x18 "IMSC,Interrupt Mask Set/Clear Register" bitfld.long 0x18 2. " THIE ,High-temperature interrupt enable" "Disabled,Enabled" bitfld.long 0x18 1. " TLOE ,Low-temperature interrupt enable" "Disabled,Enabled" bitfld.long 0x18 0. " RDYI ,Temperature conversion interrupt enable" "Disabled,Enabled" rgroup.long 0x28++0x07 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 2. " HII ,Temperature conversion value exceeds THI value" "Not exceeded,Exceeded" bitfld.long 0x00 1. " LOI ,Temperature conversion is below TLO value" "Not below,Below" bitfld.long 0x00 0. " RDYI ,Temperature conversion has finished" "Not finished,Finished" line.long 0x04 "MIS,Masked Interrupt Status Register" bitfld.long 0x04 2. " HII ,Temperature conversion value exceeds THI and this interrupt is enabled" "No,Yes" bitfld.long 0x04 1. " LOI ,Temperature conversion is below TLO and this interrupt is enabled" "No,Yes" bitfld.long 0x04 0. " RDYI ,Temperature conversion has finished and this interrupt is enabled" "No,Yes" wgroup.long 0x30++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 2. " THIC ,High-temperature interrupt clear" "Not cleared,Cleared" bitfld.long 0x00 1. " TLOC ,Low-temperature interrupt clear" "Not cleared,Cleared" bitfld.long 0x00 0. " RDYC ,Temperature conversion interrupt clear" "Not cleared,Cleared" width 0x0B tree.end endif sif cpuis("LPC8N04") tree "RFID/NFC communication unit" base ad:0x40058000 width 19. group.long 0x00++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 0. " BYPASS ,Shared memory interface and registers state" "Activated,Deactivated" rgroup.long 0x04++0x03 line.long 0x00 "SR,Status Register" hexmask.long.byte 0x00 8.--15. 1. " RFID_CMD ,Opcode of last RFID command received" bitfld.long 0x00 6. " BYPASS ,RFID interface Bypass mode" "No,Yes" bitfld.long 0x00 5. " AUTH ,RFID password for access authenticated" "Not authenticated,Authenticated" bitfld.long 0x00 4. " SEL ,RFID selected" "Not selected,Selected" newline bitfld.long 0x00 3. " PLL ,RFID PLL locked" "Not locked,Locked" bitfld.long 0x00 2. " 1V5 ,Rectifier<1.5 V output warning" "Not detected,Detected" bitfld.long 0x00 1. " 1V2 ,Rectifier<1.2 V output warning" "Not detected,Detected" bitfld.long 0x00 0. " POR ,Power-on detected in the RFID analog core" "Not detected,Detected" newline hgroup.long 0x08++0x03 hide.long 0x00 "CMDIN,Incoming Command Register" in newline group.long 0x0C++0x07 line.long 0x00 "CMDOUT,Outgoing Data Register" line.long 0x04 "TARGET,Target Address Register" hexmask.long.byte 0x04 0.--7. 0x01 " PAGE ,Target page address" rgroup.long 0x14++0x03 line.long 0x00 "LAST_ACCESS,Last Accessed Address Register" bitfld.long 0x00 16. " DIR ,Direction of last accessed page" "Read,Write" hexmask.long.byte 0x00 8.--15. 0x01 " LAST_ACCESS_START ,Last accessed (RF) page address (start of range)" hexmask.long.byte 0x00 0.--7. 0x01 " LAST_ACCESS_END ,Last accessed (RF) page address (end of range)" group.long 0x18++0x03 line.long 0x00 "IMSC,Interrupt Mask Register" bitfld.long 0x00 8. " NFCOFF ,Set to enable interrupt when external reader powers down RFID/NFC front-end" "Disabled,Enabled" bitfld.long 0x00 7. " TARGETREAD ,Set to enable interrupt when reader reads from address specified in the TARGET register" "Disabled,Enabled" bitfld.long 0x00 6. " TARGETWRITE ,Set to enable interrupt when reader writes to address specified in the TARGET register" "Disabled,Enabled" bitfld.long 0x00 5. " CMDREAD ,Set to enable interrupt when reader reads the CMDOUT register" "Disabled,Enabled" newline bitfld.long 0x00 4. " CMDWRITE ,Set to enable interrupt when reader writes to CMDIN register" "Disabled,Enabled" bitfld.long 0x00 3. " MEMWRITE ,Set to enable interrupt when reader writes to shared memory" "Disabled,Enabled" bitfld.long 0x00 2. " MEMREAD ,Set to enable interrupt when reader reads from shared memory" "Disabled,Enabled" bitfld.long 0x00 1. " RFSELECT ,Set to enable interrupt when reader selects tag" "Disabled,Enabled" newline bitfld.long 0x00 0. " RFPOWER ,Set to enable interrupt when RFID power is detected" "Disabled,Enabled" rgroup.long 0x1C++0x03 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 8. " NFCOFF ,RFID/NFC front-end is not powered or clocked" "Not Occurred,Occurred" bitfld.long 0x00 7. " TARGETREAD ,Reader reads from address specified in the TARGET register" "Not Occurred,Occurred" bitfld.long 0x00 6. " TARGETWRITE ,Reader writes to address specified in the TARGET register" "Not Occurred,Occurred" bitfld.long 0x00 5. " CMDREAD ,Reader reads the CMDOUT register" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " CMDWRITE ,Reader writers to CMDIN register" "Not Occurred,Occurred" bitfld.long 0x00 3. " MEMWRITE ,Reader writes to shared memory" "Not Occurred,Occurred" bitfld.long 0x00 2. " MEMREAD ,Reader reads from shared memory" "Not Occurred,Occurred" bitfld.long 0x00 1. " RFSELECT ,Reader selects tag" "Not Occurred,Occurred" newline bitfld.long 0x00 0. " RFPOWER ,RFID power is detected" "Not Occurred,Occurred" wgroup.long 0x24++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 8. " NFCOFF ,Clear NFCOFF interrupt" "Not cleared,Cleared" bitfld.long 0x00 7. " TARGETREAD ,Clear TARGETREAD interrupt" "Not Occurred,Occurred" bitfld.long 0x00 6. " TARGETWRITE ,Clear TARGETWRITE interrupt" "Not Occurred,Occurred" bitfld.long 0x00 5. " CMDREAD ,Clear CMDREAD interrupt" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " CMDWRITE ,Clear CMDWRITE interrupt" "Not Occurred,Occurred" bitfld.long 0x00 3. " MEMWRITE ,Clear MEMWRITE interrupt" "Not Occurred,Occurred" bitfld.long 0x00 2. " MEMREAD ,Clear MEMREAD interrupt" "Not Occurred,Occurred" bitfld.long 0x00 1. " RFSELECT ,Clear RFSELECT interrupt" "Not Occurred,Occurred" newline bitfld.long 0x00 0. " RFPOWER ,Clear RFPOWER interrupt" "Not Occurred,Occurred" group.word 0x100++0x02 line.word 0x00 "SHARED_MEM,GPIO Data Register" BUTTON "Data" "Data.dump (ad:0x40058000+0x100)--(ad:0x40058000+0x2FC) /WORD" width 0x0B tree.end endif sif cpuis("LPC8N04") tree "RTC (Real-Time Clock)" base ad:0x40054000 width 9. group.long 0x00++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 2. " START ,Start countdown from SLEEPT value" "Not started,Started" bitfld.long 0x00 1. " AUTOSTART ,Automatic timer start" "Manual,Automatic" bitfld.long 0x00 0. " EN ,Enable the RTC timer" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 3. " RUN ,RTC timer state" "Idle,Running" bitfld.long 0x00 2. " FREEZE ,Freeze value in SLEEPT" "Not frozen,Frozen" bitfld.long 0x00 0. " EN ,RTC timer enable" "Disabled,Enabled" group.long 0x08++0x07 line.long 0x00 "CAL,Calibration Register" hexmask.long.word 0x00 0.--15. 1. " CALIB ,Number of TFRO clock pulses in one tick" line.long 0x04 "SLEEPT,Sleep Time Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPTIME ,Time to sleep in ticks" rgroup.long 0x10++0x03 line.long 0x00 "VAL,Current Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TIMEREMAIN ,Current value of the countdown timer" group.long 0x14++0x03 line.long 0x00 "IE,Interrupt Masek Set/Clear Register" bitfld.long 0x00 0. " IE ,Countdown finished interrupt enable" "Disabled,Enabled" rgroup.long 0x18++0x07 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 0. " RIS ,Countdown state" "Not finished,Finished" line.long 0x04 "MIS,Masked Interrupt Status Register" bitfld.long 0x04 0. " MIS ,Countdown has finished and this interrupt is enabled" "No,Yes" wgroup.long 0x20++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 0. " IC ,Countdown down interrupt clear" "Not cleared,Cleared" rgroup.long 0x24++0x03 line.long 0x00 "ACCSTAT,Timer Access Status Register" bitfld.long 0x00 0. " READY ,RTC access" "Not possible,Possible" group.long 0x30++0x03 line.long 0x00 "TIME,Time Register" width 0x0B tree.end endif sif cpuis("LPC8N04") tree "EEPROM (EEPROM Controller)" base ad:0x40034000 width 20. group.long 0x08++0x03 line.long 0x00 "RWSTATE,Read/Wait State Register" hexmask.long.byte 0x00 8.--15. 1. " RPHASE1 ,Duration of the EEPROM precharge phase" hexmask.long.byte 0x00 0.--7. 1. " RPHASE2 ,Duration of the EEPROM evaluation (read) phase" if (((per.l(ad:0x40034000+0x10))&0x80000000)==0x00) group.long 0x10++0x03 line.long 0x00 "WSTATE,Wait State Register" bitfld.long 0x00 31. " LOCK_PARWEP ,Lock all registers used for write/program timing configuration" "Not locked,Locked" hexmask.long.byte 0x00 16.--23. 1. " PHASE1 ,Setup of any input regarding write or program command" hexmask.long.byte 0x00 8.--15. 1. " PHASE2 ,Duration of the write or program command" hexmask.long.byte 0x00 0.--7. 1. " PHASE3 ,Hold of all signals regarding write or program command" group.long 0x0C++0x03 line.long 0x00 "PAUTOPROG,EEPROM Auto Programming Register" bitfld.long 0x00 0.--1. " AUTOPROG ,Set auto programming mode" "Switched off,After first word,After last word,?..." else group.long 0x10++0x03 line.long 0x00 "WSTATE,Wait State Register" rbitfld.long 0x00 31. " LOCK_PARWEP ,Lock all registers used for write/program timing configuration" "Not locked,Locked" hexmask.long.byte 0x00 16.--23. 1. " PHASE1 ,Setup of any input regarding write or program command" hexmask.long.byte 0x00 8.--15. 1. " PHASE2 ,Duration of the write or program command" hexmask.long.byte 0x00 0.--7. 1. " PHASE3 ,Hold of all signals regarding write or program command" rgroup.long 0x0C++0x03 line.long 0x00 "PAUTOPROG,EEPROM Auto Programming Register" bitfld.long 0x00 0.--1. " AUTOPROG ,Set auto programming mode" "Switched off,After first word,After last word,?..." endif rgroup.long 0x14++0x03 line.long 0x00 "CLKDIV,EEPROM Clock Divider Register" bitfld.long 0x00 30.--31. " CLKMOD ,Amount of clock modulation" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock division factor" rgroup.long 0x54++0x07 line.long 0x00 "CLKDIV1,EEPROM Clock Divider 1 Register" hexmask.long.word 0x00 0.--15. 1. " CLKDIV1 ,Clock division factor" line.long 0x04 "CLKDIV2,EEPROM Clock Divider 2 Register" hexmask.long.word 0x04 0.--15. 1. " CLKDIV2 ,Number of program clock cycles after which the clock division factor is decremented" rgroup.long 0x18++0x03 line.long 0x00 "PWRDWN,EEPROM Power Down Register" bitfld.long 0x00 0. " PWRDWN ,Power-down mode is in effect" "No effect,In mode" rgroup.long 0x20++0x03 line.long 0x00 "MSSTART,EEPROM Checksum Start Address Register" hexmask.long.word 0x00 0.--15. 0x01 " STARTA ,Start address for signature generation" group.long 0x24++0x03 line.long 0x00 "MSSTOP,EEPROM Checksum Stop Address Register" bitfld.long 0x00 31. " STRTBIST ,Signature generation starts" "Not started,Started" hexmask.long.word 0x00 0.--15. 0x01 " STOPA ,Stop address for signature generation" wgroup.long 0x28++0x07 line.long 0x00 "MSDATASIG,EEPROM Data Signature Register" line.long 0x04 "MSPARSIG,EEPROM Parity Signature Register" bitfld.long 0x04 0. " PARITY_SIG ,Contains the parity signature for the specified address range" "0,1" rgroup.long 0x34++0x07 line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 14. " VMPOK ,Margin pump level OK" "Not OK,OK" bitfld.long 0x00 13. " TMANALOG ,Analog test mode is in effect" "No effect,In effect" bitfld.long 0x00 12. " HVERR ,High-voltage error" "No error,Error" bitfld.long 0x00 11. " ALL0 ,All bits in the last memory word read are low" "Not all,All" newline bitfld.long 0x00 10. " ALL0 ,All bits in the last memory word read are high" "Not all,All" bitfld.long 0x00 9. " INVALID ,ECC detected an uncorrectable error" "Not detected,Detected" bitfld.long 0x00 8. " CORRECTED ,ECC detected a correctable error" "Not detected,Detected" newline bitfld.long 0x00 4.--7. " HVTRIM_P ,Trim value for the programming voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HVTRIM_E ,When bit is set Power-down mode is in effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ECCERRCNT,ECCERRCNT Register" hexmask.long.tbyte 0x04 5.--17. 0x20 " ERR_PAGE ,Page address of the last location containing an ECC" bitfld.long 0x04 1.--4. " ERRCOUNTER ,Incremented when an ECC correction occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. " INVALID_FLAG ,Set when an uncorrectable ECC error occurs" "Not occurred,Occurred" newline group.long 0xFE8++0x03 line.long 0x00 "INT_CLR_STATUS,Clear Interrupt Status Bits Register" bitfld.long 0x00 31. " CLR_STATUS[31] ,Corresponding INT_STATUS bit 31 is cleared" "Not cleared,Cleared" bitfld.long 0x00 30. " [30] ,Corresponding INT_STATUS bit 30 is cleared" "Not cleared,Cleared" bitfld.long 0x00 29. " [29] ,Corresponding INT_STATUS bit 29 is cleared" "Not cleared,Cleared" bitfld.long 0x00 28. " [28] ,Corresponding INT_STATUS bit 28 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 27. " [27] ,Corresponding INT_STATUS bit 27 is cleared" "Not cleared,Cleared" bitfld.long 0x00 26. " [26] ,Corresponding INT_STATUS bit 26 is cleared" "Not cleared,Cleared" bitfld.long 0x00 25. " [25] ,Corresponding INT_STATUS bit 25 is cleared" "Not cleared,Cleared" bitfld.long 0x00 24. " [24] ,Corresponding INT_STATUS bit 24 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 23. " [23] ,Corresponding INT_STATUS bit 23 is cleared" "Not cleared,Cleared" bitfld.long 0x00 22. " [22] ,Corresponding INT_STATUS bit 22 is cleared" "Not cleared,Cleared" bitfld.long 0x00 21. " [21] ,Corresponding INT_STATUS bit 21 is cleared" "Not cleared,Cleared" bitfld.long 0x00 20. " [20] ,Corresponding INT_STATUS bit 20 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 19. " [19] ,Corresponding INT_STATUS bit 19 is cleared" "Not cleared,Cleared" bitfld.long 0x00 18. " [18] ,Corresponding INT_STATUS bit 18 is cleared" "Not cleared,Cleared" bitfld.long 0x00 17. " [17] ,Corresponding INT_STATUS bit 17 is cleared" "Not cleared,Cleared" bitfld.long 0x00 16. " [16] ,Corresponding INT_STATUS bit 16 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 15. " [15] ,Corresponding INT_STATUS bit 15 is cleared" "Not cleared,Cleared" bitfld.long 0x00 14. " [14] ,Corresponding INT_STATUS bit 14 is cleared" "Not cleared,Cleared" bitfld.long 0x00 13. " [13] ,Corresponding INT_STATUS bit 13 is cleared" "Not cleared,Cleared" bitfld.long 0x00 12. " [12] ,Corresponding INT_STATUS bit 12 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 11. " [11] ,Corresponding INT_STATUS bit 11 is cleared" "Not cleared,Cleared" bitfld.long 0x00 10. " [10] ,Corresponding INT_STATUS bit 10 is cleared" "Not cleared,Cleared" bitfld.long 0x00 9. " [9] ,Corresponding INT_STATUS bit 9 is cleared" "Not cleared,Cleared" bitfld.long 0x00 8. " [8] ,Corresponding INT_STATUS bit 8 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 7. " [7] ,Corresponding INT_STATUS bit 7 is cleared" "Not cleared,Cleared" bitfld.long 0x00 6. " [6] ,Corresponding INT_STATUS bit 6 is cleared" "Not cleared,Cleared" bitfld.long 0x00 5. " [5] ,Corresponding INT_STATUS bit 5 is cleared" "Not cleared,Cleared" bitfld.long 0x00 4. " [4] ,Corresponding INT_STATUS bit 4 is cleared" "Not cleared,Cleared" newline bitfld.long 0x00 3. " [3] ,Corresponding INT_STATUS bit 3 is cleared" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Corresponding INT_STATUS bit 2 is cleared" "Not cleared,Cleared" bitfld.long 0x00 1. " [1] ,Corresponding INT_STATUS bit 1 is cleared" "Not cleared,Cleared" bitfld.long 0x00 0. " [0] ,Corresponding INT_STATUS bit 0 is cleared" "Not cleared,Cleared" group.long 0xFE0++0x07 line.long 0x00 "INT_ENABLE_SET/CLR,Interrupt Enable Bits Register" setclrfld.long 0x00 31. -0x04 31. -0x08 31. " INT_ENABLE[31] ,Bit 31 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Bit 30 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Bit 29 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Bit 28 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Bit 27 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Bit 26 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Bit 25 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Bit 24 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Bit 23 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Bit 22 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Bit 21 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Bit 20 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Bit 19 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Bit 18 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Bit 17 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Bit 16 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Bit 15 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Bit 14 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Bit 13 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Bit 12 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Bit 11 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Bit 10 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Bit 9 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Bit 8 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Bit 7 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Bit 6 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Bit 5 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Bit 4 interrupt status" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Bit 3 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Bit 2 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Bit 1 interrupt status" "No interrupt,Interrupt" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Bit 0 interrupt status" "No interrupt,Interrupt" newline line.long 0x04 "INT_STATUS,Interrupt Status Bits Register" bitfld.long 0x04 3. " ECC_ERR ,Detects a correctable or uncorrectable error" "No error,Error" bitfld.long 0x04 2. " PROG_DONE ,End of a high-voltage operation" "Not set,Set" bitfld.long 0x04 1. " SIG_DONE ,End of signature computation status" "Not done,Done" rgroup.long 0xFFC++0x03 line.long 0x00 "MODULE_ID,Module ID Register" hexmask.long.word 0x00 16.--31. 1. " ID_NUM ,Identification number" newline bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,The size of the memory encoded" width 0x0B tree.end endif textline ""